| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * wm8753.h -- audio driver for WM8753 |
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| 4 | * |
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| 5 | * Copyright 2003 Wolfson Microelectronics PLC. |
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| 6 | * Author: Liam Girdwood <lrg@slimlogic.co.uk> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _WM8753_H |
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| 10 | #define _WM8753_H |
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| 11 | |
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| 12 | /* WM8753 register space */ |
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| 13 | |
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| 14 | #define WM8753_DAC 0x01 |
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| 15 | #define WM8753_ADC 0x02 |
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| 16 | #define WM8753_PCM 0x03 |
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| 17 | #define WM8753_HIFI 0x04 |
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| 18 | #define WM8753_IOCTL 0x05 |
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| 19 | #define WM8753_SRATE1 0x06 |
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| 20 | #define WM8753_SRATE2 0x07 |
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| 21 | #define WM8753_LDAC 0x08 |
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| 22 | #define WM8753_RDAC 0x09 |
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| 23 | #define WM8753_BASS 0x0a |
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| 24 | #define WM8753_TREBLE 0x0b |
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| 25 | #define WM8753_ALC1 0x0c |
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| 26 | #define WM8753_ALC2 0x0d |
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| 27 | #define WM8753_ALC3 0x0e |
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| 28 | #define WM8753_NGATE 0x0f |
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| 29 | #define WM8753_LADC 0x10 |
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| 30 | #define WM8753_RADC 0x11 |
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| 31 | #define WM8753_ADCTL1 0x12 |
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| 32 | #define WM8753_3D 0x13 |
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| 33 | #define WM8753_PWR1 0x14 |
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| 34 | #define WM8753_PWR2 0x15 |
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| 35 | #define WM8753_PWR3 0x16 |
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| 36 | #define WM8753_PWR4 0x17 |
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| 37 | #define WM8753_ID 0x18 |
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| 38 | #define WM8753_INTPOL 0x19 |
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| 39 | #define WM8753_INTEN 0x1a |
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| 40 | #define WM8753_GPIO1 0x1b |
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| 41 | #define WM8753_GPIO2 0x1c |
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| 42 | #define WM8753_RESET 0x1f |
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| 43 | #define WM8753_RECMIX1 0x20 |
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| 44 | #define WM8753_RECMIX2 0x21 |
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| 45 | #define WM8753_LOUTM1 0x22 |
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| 46 | #define WM8753_LOUTM2 0x23 |
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| 47 | #define WM8753_ROUTM1 0x24 |
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| 48 | #define WM8753_ROUTM2 0x25 |
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| 49 | #define WM8753_MOUTM1 0x26 |
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| 50 | #define WM8753_MOUTM2 0x27 |
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| 51 | #define WM8753_LOUT1V 0x28 |
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| 52 | #define WM8753_ROUT1V 0x29 |
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| 53 | #define WM8753_LOUT2V 0x2a |
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| 54 | #define WM8753_ROUT2V 0x2b |
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| 55 | #define WM8753_MOUTV 0x2c |
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| 56 | #define WM8753_OUTCTL 0x2d |
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| 57 | #define WM8753_ADCIN 0x2e |
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| 58 | #define WM8753_INCTL1 0x2f |
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| 59 | #define WM8753_INCTL2 0x30 |
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| 60 | #define WM8753_LINVOL 0x31 |
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| 61 | #define WM8753_RINVOL 0x32 |
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| 62 | #define WM8753_MICBIAS 0x33 |
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| 63 | #define WM8753_CLOCK 0x34 |
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| 64 | #define WM8753_PLL1CTL1 0x35 |
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| 65 | #define WM8753_PLL1CTL2 0x36 |
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| 66 | #define WM8753_PLL1CTL3 0x37 |
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| 67 | #define WM8753_PLL1CTL4 0x38 |
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| 68 | #define WM8753_PLL2CTL1 0x39 |
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| 69 | #define WM8753_PLL2CTL2 0x3a |
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| 70 | #define WM8753_PLL2CTL3 0x3b |
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| 71 | #define WM8753_PLL2CTL4 0x3c |
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| 72 | #define WM8753_BIASCTL 0x3d |
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| 73 | #define WM8753_ADCTL2 0x3f |
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| 74 | |
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| 75 | #define WM8753_PLL1 0 |
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| 76 | #define WM8753_PLL2 1 |
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| 77 | |
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| 78 | /* clock inputs */ |
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| 79 | #define WM8753_MCLK 0 |
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| 80 | #define WM8753_PCMCLK 1 |
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| 81 | |
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| 82 | /* clock divider id's */ |
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| 83 | #define WM8753_PCMDIV 0 |
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| 84 | #define WM8753_BCLKDIV 1 |
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| 85 | #define WM8753_VXCLKDIV 2 |
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| 86 | |
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| 87 | /* PCM clock dividers */ |
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| 88 | #define WM8753_PCM_DIV_1 (0 << 6) |
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| 89 | #define WM8753_PCM_DIV_3 (2 << 6) |
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| 90 | #define WM8753_PCM_DIV_5_5 (3 << 6) |
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| 91 | #define WM8753_PCM_DIV_2 (4 << 6) |
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| 92 | #define WM8753_PCM_DIV_4 (5 << 6) |
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| 93 | #define WM8753_PCM_DIV_6 (6 << 6) |
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| 94 | #define WM8753_PCM_DIV_8 (7 << 6) |
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| 95 | |
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| 96 | /* BCLK clock dividers */ |
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| 97 | #define WM8753_BCLK_DIV_1 (0 << 3) |
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| 98 | #define WM8753_BCLK_DIV_2 (1 << 3) |
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| 99 | #define WM8753_BCLK_DIV_4 (2 << 3) |
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| 100 | #define WM8753_BCLK_DIV_8 (3 << 3) |
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| 101 | #define WM8753_BCLK_DIV_16 (4 << 3) |
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| 102 | |
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| 103 | /* VXCLK clock dividers */ |
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| 104 | #define WM8753_VXCLK_DIV_1 (0 << 6) |
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| 105 | #define WM8753_VXCLK_DIV_2 (1 << 6) |
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| 106 | #define WM8753_VXCLK_DIV_4 (2 << 6) |
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| 107 | #define WM8753_VXCLK_DIV_8 (3 << 6) |
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| 108 | #define WM8753_VXCLK_DIV_16 (4 << 6) |
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| 109 | |
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| 110 | #endif |
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| 111 | |
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