| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * wm8974.h -- WM8974 Soc Audio driver |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _WM8974_H |
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| 7 | #define _WM8974_H |
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| 8 | |
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| 9 | /* WM8974 register space */ |
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| 10 | |
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| 11 | #define WM8974_RESET 0x0 |
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| 12 | #define WM8974_POWER1 0x1 |
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| 13 | #define WM8974_POWER2 0x2 |
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| 14 | #define WM8974_POWER3 0x3 |
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| 15 | #define WM8974_IFACE 0x4 |
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| 16 | #define WM8974_COMP 0x5 |
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| 17 | #define WM8974_CLOCK 0x6 |
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| 18 | #define WM8974_ADD 0x7 |
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| 19 | #define WM8974_GPIO 0x8 |
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| 20 | #define WM8974_DAC 0xa |
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| 21 | #define WM8974_DACVOL 0xb |
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| 22 | #define WM8974_ADC 0xe |
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| 23 | #define WM8974_ADCVOL 0xf |
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| 24 | #define WM8974_EQ1 0x12 |
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| 25 | #define WM8974_EQ2 0x13 |
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| 26 | #define WM8974_EQ3 0x14 |
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| 27 | #define WM8974_EQ4 0x15 |
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| 28 | #define WM8974_EQ5 0x16 |
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| 29 | #define WM8974_DACLIM1 0x18 |
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| 30 | #define WM8974_DACLIM2 0x19 |
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| 31 | #define WM8974_NOTCH1 0x1b |
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| 32 | #define WM8974_NOTCH2 0x1c |
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| 33 | #define WM8974_NOTCH3 0x1d |
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| 34 | #define WM8974_NOTCH4 0x1e |
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| 35 | #define WM8974_ALC1 0x20 |
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| 36 | #define WM8974_ALC2 0x21 |
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| 37 | #define WM8974_ALC3 0x22 |
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| 38 | #define WM8974_NGATE 0x23 |
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| 39 | #define WM8974_PLLN 0x24 |
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| 40 | #define WM8974_PLLK1 0x25 |
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| 41 | #define WM8974_PLLK2 0x26 |
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| 42 | #define WM8974_PLLK3 0x27 |
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| 43 | #define WM8974_ATTEN 0x28 |
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| 44 | #define WM8974_INPUT 0x2c |
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| 45 | #define WM8974_INPPGA 0x2d |
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| 46 | #define WM8974_ADCBOOST 0x2f |
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| 47 | #define WM8974_OUTPUT 0x31 |
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| 48 | #define WM8974_SPKMIX 0x32 |
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| 49 | #define WM8974_SPKVOL 0x36 |
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| 50 | #define WM8974_MONOMIX 0x38 |
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| 51 | |
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| 52 | #define WM8974_CACHEREGNUM 57 |
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| 53 | |
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| 54 | /* Clock divider Id's */ |
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| 55 | #define WM8974_OPCLKDIV 0 |
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| 56 | #define WM8974_MCLKDIV 1 |
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| 57 | #define WM8974_BCLKDIV 2 |
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| 58 | |
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| 59 | /* PLL Out dividers */ |
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| 60 | #define WM8974_OPCLKDIV_1 (0 << 4) |
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| 61 | #define WM8974_OPCLKDIV_2 (1 << 4) |
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| 62 | #define WM8974_OPCLKDIV_3 (2 << 4) |
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| 63 | #define WM8974_OPCLKDIV_4 (3 << 4) |
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| 64 | |
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| 65 | /* BCLK clock dividers */ |
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| 66 | #define WM8974_BCLKDIV_1 (0 << 2) |
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| 67 | #define WM8974_BCLKDIV_2 (1 << 2) |
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| 68 | #define WM8974_BCLKDIV_4 (2 << 2) |
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| 69 | #define WM8974_BCLKDIV_8 (3 << 2) |
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| 70 | #define WM8974_BCLKDIV_16 (4 << 2) |
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| 71 | #define WM8974_BCLKDIV_32 (5 << 2) |
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| 72 | |
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| 73 | /* MCLK clock dividers */ |
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| 74 | #define WM8974_MCLKDIV_1 (0 << 5) |
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| 75 | #define WM8974_MCLKDIV_1_5 (1 << 5) |
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| 76 | #define WM8974_MCLKDIV_2 (2 << 5) |
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| 77 | #define WM8974_MCLKDIV_3 (3 << 5) |
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| 78 | #define WM8974_MCLKDIV_4 (4 << 5) |
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| 79 | #define WM8974_MCLKDIV_6 (5 << 5) |
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| 80 | #define WM8974_MCLKDIV_8 (6 << 5) |
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| 81 | #define WM8974_MCLKDIV_12 (7 << 5) |
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| 82 | |
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| 83 | #endif |
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| 84 | |
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