1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2015-2017, The Linux Foundation. |
3 | // Copyright (c) 2019, Linaro Limited |
4 | |
5 | #include <linux/bitops.h> |
6 | #include <linux/gpio.h> |
7 | #include <linux/gpio/consumer.h> |
8 | #include <linux/module.h> |
9 | #include <linux/regmap.h> |
10 | #include <linux/slab.h> |
11 | #include <linux/pm_runtime.h> |
12 | #include <linux/soundwire/sdw.h> |
13 | #include <linux/soundwire/sdw_registers.h> |
14 | #include <linux/soundwire/sdw_type.h> |
15 | #include <sound/soc.h> |
16 | #include <sound/tlv.h> |
17 | |
18 | #define WSA881X_DIGITAL_BASE 0x3000 |
19 | #define WSA881X_ANALOG_BASE 0x3100 |
20 | |
21 | /* Digital register address space */ |
22 | #define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000) |
23 | #define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001) |
24 | #define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002) |
25 | #define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003) |
26 | #define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004) |
27 | #define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005) |
28 | #define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006) |
29 | #define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007) |
30 | #define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008) |
31 | #define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009) |
32 | #define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A) |
33 | #define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B) |
34 | #define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C) |
35 | #define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F) |
36 | #define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010) |
37 | #define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011) |
38 | #define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012) |
39 | #define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013) |
40 | #define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014) |
41 | #define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015) |
42 | #define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016) |
43 | #define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017) |
44 | #define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018) |
45 | #define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019) |
46 | #define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A) |
47 | #define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B) |
48 | #define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C) |
49 | #define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D) |
50 | #define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E) |
51 | #define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F) |
52 | #define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020) |
53 | #define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021) |
54 | #define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022) |
55 | #define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023) |
56 | #define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024) |
57 | #define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025) |
58 | #define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026) |
59 | #define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030) |
60 | #define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031) |
61 | #define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032) |
62 | #define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033) |
63 | #define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034) |
64 | #define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035) |
65 | #define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037) |
66 | #define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038) |
67 | #define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039) |
68 | #define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B) |
69 | #define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C) |
70 | #define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D) |
71 | #define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E) |
72 | #define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F) |
73 | #define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044) |
74 | #define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045) |
75 | #define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050) |
76 | #define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051) |
77 | #define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052) |
78 | #define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080) |
79 | #define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081) |
80 | #define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082) |
81 | #define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083) |
82 | #define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084) |
83 | #define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085) |
84 | #define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086) |
85 | #define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087) |
86 | #define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088) |
87 | #define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089) |
88 | #define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A) |
89 | #define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B) |
90 | #define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C) |
91 | #define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D) |
92 | #define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E) |
93 | #define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F) |
94 | #define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090) |
95 | #define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091) |
96 | #define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092) |
97 | #define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093) |
98 | #define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094) |
99 | #define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095) |
100 | #define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096) |
101 | #define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097) |
102 | #define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098) |
103 | #define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099) |
104 | #define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A) |
105 | #define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B) |
106 | #define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C) |
107 | #define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D) |
108 | #define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E) |
109 | #define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F) |
110 | #define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF) |
111 | |
112 | /* Analog Register address space */ |
113 | #define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000) |
114 | #define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001) |
115 | #define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002) |
116 | #define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003) |
117 | #define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004) |
118 | #define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005) |
119 | #define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006) |
120 | #define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007) |
121 | #define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008) |
122 | #define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009) |
123 | #define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A) |
124 | #define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B) |
125 | #define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010) |
126 | #define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011) |
127 | #define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012) |
128 | #define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013) |
129 | #define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014) |
130 | #define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015) |
131 | #define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A) |
132 | #define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B) |
133 | #define WSA881X_PA_GAIN_SEL_MASK BIT(3) |
134 | #define WSA881X_PA_GAIN_SEL_REG BIT(3) |
135 | #define WSA881X_PA_GAIN_SEL_DRE 0 |
136 | #define WSA881X_SPKR_PAG_GAIN_MASK GENMASK(7, 4) |
137 | #define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C) |
138 | #define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D) |
139 | #define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E) |
140 | #define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F) |
141 | #define WSA881X_SPKR_OCP_MASK GENMASK(7, 6) |
142 | #define WSA881X_SPKR_OCP_EN BIT(7) |
143 | #define WSA881X_SPKR_OCP_HOLD BIT(6) |
144 | #define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020) |
145 | #define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021) |
146 | #define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022) |
147 | #define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023) |
148 | #define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024) |
149 | #define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025) |
150 | #define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026) |
151 | #define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027) |
152 | #define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028) |
153 | #define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029) |
154 | #define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A) |
155 | #define WSA881X_BOOST_EN_MASK BIT(7) |
156 | #define WSA881X_BOOST_EN BIT(7) |
157 | #define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B) |
158 | #define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C) |
159 | #define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D) |
160 | #define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E) |
161 | #define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F) |
162 | #define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030) |
163 | #define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031) |
164 | #define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032) |
165 | #define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033) |
166 | #define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034) |
167 | #define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035) |
168 | #define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036) |
169 | #define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037) |
170 | #define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038) |
171 | #define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039) |
172 | #define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A) |
173 | #define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B) |
174 | #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C) |
175 | #define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D) |
176 | #define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E) |
177 | #define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F) |
178 | #define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040) |
179 | #define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041) |
180 | #define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042) |
181 | #define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043) |
182 | #define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044) |
183 | #define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045) |
184 | |
185 | #define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m)) |
186 | #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m)) |
187 | #define SWR_SLV_MAX_REG_ADDR 0x390 |
188 | #define SWR_SLV_START_REG_ADDR 0x40 |
189 | #define SWR_SLV_MAX_BUF_LEN 20 |
190 | #define BYTES_PER_LINE 12 |
191 | #define SWR_SLV_RD_BUF_LEN 8 |
192 | #define SWR_SLV_WR_BUF_LEN 32 |
193 | #define SWR_SLV_MAX_DEVICES 2 |
194 | #define WSA881X_MAX_SWR_PORTS 4 |
195 | #define WSA881X_VERSION_ENTRY_SIZE 27 |
196 | #define WSA881X_OCP_CTL_TIMER_SEC 2 |
197 | #define WSA881X_OCP_CTL_TEMP_CELSIUS 25 |
198 | #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60 |
199 | #define WSA881X_PROBE_TIMEOUT 1000 |
200 | |
201 | #define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \ |
202 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
203 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ |
204 | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ |
205 | .tlv.p = (tlv_array), \ |
206 | .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ |
207 | .put = wsa881x_put_pa_gain, \ |
208 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } |
209 | |
210 | static struct reg_default wsa881x_defaults[] = { |
211 | { WSA881X_CHIP_ID0, 0x00 }, |
212 | { WSA881X_CHIP_ID1, 0x00 }, |
213 | { WSA881X_CHIP_ID2, 0x00 }, |
214 | { WSA881X_CHIP_ID3, 0x02 }, |
215 | { WSA881X_BUS_ID, 0x00 }, |
216 | { WSA881X_CDC_RST_CTL, 0x00 }, |
217 | { WSA881X_CDC_TOP_CLK_CTL, 0x03 }, |
218 | { WSA881X_CDC_ANA_CLK_CTL, 0x00 }, |
219 | { WSA881X_CDC_DIG_CLK_CTL, 0x00 }, |
220 | { WSA881X_CLOCK_CONFIG, 0x00 }, |
221 | { WSA881X_ANA_CTL, 0x08 }, |
222 | { WSA881X_SWR_RESET_EN, 0x00 }, |
223 | { WSA881X_TEMP_DETECT_CTL, 0x01 }, |
224 | { WSA881X_TEMP_MSB, 0x00 }, |
225 | { WSA881X_TEMP_LSB, 0x00 }, |
226 | { WSA881X_TEMP_CONFIG0, 0x00 }, |
227 | { WSA881X_TEMP_CONFIG1, 0x00 }, |
228 | { WSA881X_CDC_CLIP_CTL, 0x03 }, |
229 | { WSA881X_SDM_PDM9_LSB, 0x00 }, |
230 | { WSA881X_SDM_PDM9_MSB, 0x00 }, |
231 | { WSA881X_CDC_RX_CTL, 0x7E }, |
232 | { WSA881X_DEM_BYPASS_DATA0, 0x00 }, |
233 | { WSA881X_DEM_BYPASS_DATA1, 0x00 }, |
234 | { WSA881X_DEM_BYPASS_DATA2, 0x00 }, |
235 | { WSA881X_DEM_BYPASS_DATA3, 0x00 }, |
236 | { WSA881X_OTP_CTRL0, 0x00 }, |
237 | { WSA881X_OTP_CTRL1, 0x00 }, |
238 | { WSA881X_HDRIVE_CTL_GROUP1, 0x00 }, |
239 | { WSA881X_INTR_MODE, 0x00 }, |
240 | { WSA881X_INTR_STATUS, 0x00 }, |
241 | { WSA881X_INTR_CLEAR, 0x00 }, |
242 | { WSA881X_INTR_LEVEL, 0x00 }, |
243 | { WSA881X_INTR_SET, 0x00 }, |
244 | { WSA881X_INTR_TEST, 0x00 }, |
245 | { WSA881X_PDM_TEST_MODE, 0x00 }, |
246 | { WSA881X_ATE_TEST_MODE, 0x00 }, |
247 | { WSA881X_PIN_CTL_MODE, 0x00 }, |
248 | { WSA881X_PIN_CTL_OE, 0x00 }, |
249 | { WSA881X_PIN_WDATA_IOPAD, 0x00 }, |
250 | { WSA881X_PIN_STATUS, 0x00 }, |
251 | { WSA881X_DIG_DEBUG_MODE, 0x00 }, |
252 | { WSA881X_DIG_DEBUG_SEL, 0x00 }, |
253 | { WSA881X_DIG_DEBUG_EN, 0x00 }, |
254 | { WSA881X_SWR_HM_TEST1, 0x08 }, |
255 | { WSA881X_SWR_HM_TEST2, 0x00 }, |
256 | { WSA881X_TEMP_DETECT_DBG_CTL, 0x00 }, |
257 | { WSA881X_TEMP_DEBUG_MSB, 0x00 }, |
258 | { WSA881X_TEMP_DEBUG_LSB, 0x00 }, |
259 | { WSA881X_SAMPLE_EDGE_SEL, 0x0C }, |
260 | { WSA881X_SPARE_0, 0x00 }, |
261 | { WSA881X_SPARE_1, 0x00 }, |
262 | { WSA881X_SPARE_2, 0x00 }, |
263 | { WSA881X_OTP_REG_0, 0x01 }, |
264 | { WSA881X_OTP_REG_1, 0xFF }, |
265 | { WSA881X_OTP_REG_2, 0xC0 }, |
266 | { WSA881X_OTP_REG_3, 0xFF }, |
267 | { WSA881X_OTP_REG_4, 0xC0 }, |
268 | { WSA881X_OTP_REG_5, 0xFF }, |
269 | { WSA881X_OTP_REG_6, 0xFF }, |
270 | { WSA881X_OTP_REG_7, 0xFF }, |
271 | { WSA881X_OTP_REG_8, 0xFF }, |
272 | { WSA881X_OTP_REG_9, 0xFF }, |
273 | { WSA881X_OTP_REG_10, 0xFF }, |
274 | { WSA881X_OTP_REG_11, 0xFF }, |
275 | { WSA881X_OTP_REG_12, 0xFF }, |
276 | { WSA881X_OTP_REG_13, 0xFF }, |
277 | { WSA881X_OTP_REG_14, 0xFF }, |
278 | { WSA881X_OTP_REG_15, 0xFF }, |
279 | { WSA881X_OTP_REG_16, 0xFF }, |
280 | { WSA881X_OTP_REG_17, 0xFF }, |
281 | { WSA881X_OTP_REG_18, 0xFF }, |
282 | { WSA881X_OTP_REG_19, 0xFF }, |
283 | { WSA881X_OTP_REG_20, 0xFF }, |
284 | { WSA881X_OTP_REG_21, 0xFF }, |
285 | { WSA881X_OTP_REG_22, 0xFF }, |
286 | { WSA881X_OTP_REG_23, 0xFF }, |
287 | { WSA881X_OTP_REG_24, 0x03 }, |
288 | { WSA881X_OTP_REG_25, 0x01 }, |
289 | { WSA881X_OTP_REG_26, 0x03 }, |
290 | { WSA881X_OTP_REG_27, 0x11 }, |
291 | { WSA881X_OTP_REG_63, 0x40 }, |
292 | /* WSA881x Analog registers */ |
293 | { WSA881X_BIAS_REF_CTRL, 0x6C }, |
294 | { WSA881X_BIAS_TEST, 0x16 }, |
295 | { WSA881X_BIAS_BIAS, 0xF0 }, |
296 | { WSA881X_TEMP_OP, 0x00 }, |
297 | { WSA881X_TEMP_IREF_CTRL, 0x56 }, |
298 | { WSA881X_TEMP_ISENS_CTRL, 0x47 }, |
299 | { WSA881X_TEMP_CLK_CTRL, 0x87 }, |
300 | { WSA881X_TEMP_TEST, 0x00 }, |
301 | { WSA881X_TEMP_BIAS, 0x51 }, |
302 | { WSA881X_TEMP_DOUT_MSB, 0x00 }, |
303 | { WSA881X_TEMP_DOUT_LSB, 0x00 }, |
304 | { WSA881X_ADC_EN_MODU_V, 0x00 }, |
305 | { WSA881X_ADC_EN_MODU_I, 0x00 }, |
306 | { WSA881X_ADC_EN_DET_TEST_V, 0x00 }, |
307 | { WSA881X_ADC_EN_DET_TEST_I, 0x00 }, |
308 | { WSA881X_ADC_EN_SEL_IBAIS, 0x10 }, |
309 | { WSA881X_SPKR_DRV_EN, 0x74 }, |
310 | { WSA881X_SPKR_DRV_DBG, 0x15 }, |
311 | { WSA881X_SPKR_PWRSTG_DBG, 0x00 }, |
312 | { WSA881X_SPKR_OCP_CTL, 0xD4 }, |
313 | { WSA881X_SPKR_CLIP_CTL, 0x90 }, |
314 | { WSA881X_SPKR_PA_INT, 0x54 }, |
315 | { WSA881X_SPKR_BIAS_CAL, 0xAC }, |
316 | { WSA881X_SPKR_STATUS1, 0x00 }, |
317 | { WSA881X_SPKR_STATUS2, 0x00 }, |
318 | { WSA881X_BOOST_EN_CTL, 0x18 }, |
319 | { WSA881X_BOOST_CURRENT_LIMIT, 0x7A }, |
320 | { WSA881X_BOOST_PRESET_OUT2, 0x70 }, |
321 | { WSA881X_BOOST_FORCE_OUT, 0x0E }, |
322 | { WSA881X_BOOST_LDO_PROG, 0x16 }, |
323 | { WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71 }, |
324 | { WSA881X_BOOST_RON_CTL, 0x0F }, |
325 | { WSA881X_BOOST_ZX_CTL, 0x34 }, |
326 | { WSA881X_BOOST_START_CTL, 0x23 }, |
327 | { WSA881X_BOOST_MISC1_CTL, 0x80 }, |
328 | { WSA881X_BOOST_MISC2_CTL, 0x00 }, |
329 | { WSA881X_BOOST_MISC3_CTL, 0x00 }, |
330 | { WSA881X_BOOST_ATEST_CTL, 0x00 }, |
331 | { WSA881X_SPKR_PROT_FE_GAIN, 0x46 }, |
332 | { WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B }, |
333 | { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D }, |
334 | { WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D }, |
335 | { WSA881X_SPKR_PROT_ATEST1, 0x01 }, |
336 | { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D }, |
337 | { WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D }, |
338 | { WSA881X_SPKR_PROT_SAR, 0x00 }, |
339 | { WSA881X_SPKR_STATUS3, 0x00 }, |
340 | }; |
341 | |
342 | static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = { |
343 | { WSA881X_SPKR_DRV_GAIN, 0x41, 0 }, |
344 | { WSA881X_SPKR_MISC_CTL1, 0x87, 0 }, |
345 | }; |
346 | |
347 | static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = { |
348 | { WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0 }, |
349 | { WSA881X_SPKR_PROT_ATEST2, 0x0A, 0 }, |
350 | { WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0 }, |
351 | }; |
352 | |
353 | /* Default register reset values for WSA881x rev 2.0 */ |
354 | static struct reg_sequence wsa881x_rev_2_0[] = { |
355 | { WSA881X_RESET_CTL, 0x00, 0x00 }, |
356 | { WSA881X_TADC_VALUE_CTL, 0x01, 0x00 }, |
357 | { WSA881X_INTR_MASK, 0x1B, 0x00 }, |
358 | { WSA881X_IOPAD_CTL, 0x00, 0x00 }, |
359 | { WSA881X_OTP_REG_28, 0x3F, 0x00 }, |
360 | { WSA881X_OTP_REG_29, 0x3F, 0x00 }, |
361 | { WSA881X_OTP_REG_30, 0x01, 0x00 }, |
362 | { WSA881X_OTP_REG_31, 0x01, 0x00 }, |
363 | { WSA881X_TEMP_ADC_CTRL, 0x03, 0x00 }, |
364 | { WSA881X_ADC_SEL_IBIAS, 0x45, 0x00 }, |
365 | { WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00 }, |
366 | { WSA881X_SPKR_DAC_CTL, 0x42, 0x00 }, |
367 | { WSA881X_SPKR_BBM_CTL, 0x02, 0x00 }, |
368 | { WSA881X_SPKR_MISC_CTL1, 0x40, 0x00 }, |
369 | { WSA881X_SPKR_MISC_CTL2, 0x07, 0x00 }, |
370 | { WSA881X_SPKR_BIAS_INT, 0x5F, 0x00 }, |
371 | { WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00 }, |
372 | { WSA881X_BOOST_PS_CTL, 0xA0, 0x00 }, |
373 | { WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00 }, |
374 | { WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00 }, |
375 | { WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00 }, |
376 | { WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00 }, |
377 | { WSA881X_BONGO_RESRV_REG2, 0x07, 0x00 }, |
378 | }; |
379 | |
380 | enum wsa_port_ids { |
381 | WSA881X_PORT_DAC, |
382 | WSA881X_PORT_COMP, |
383 | WSA881X_PORT_BOOST, |
384 | WSA881X_PORT_VISENSE, |
385 | }; |
386 | |
387 | /* 4 ports */ |
388 | static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = { |
389 | { |
390 | /* DAC */ |
391 | .num = 1, |
392 | .type = SDW_DPN_SIMPLE, |
393 | .min_ch = 1, |
394 | .max_ch = 1, |
395 | .simple_ch_prep_sm = true, |
396 | .read_only_wordlength = true, |
397 | }, { |
398 | /* COMP */ |
399 | .num = 2, |
400 | .type = SDW_DPN_SIMPLE, |
401 | .min_ch = 1, |
402 | .max_ch = 1, |
403 | .simple_ch_prep_sm = true, |
404 | .read_only_wordlength = true, |
405 | }, { |
406 | /* BOOST */ |
407 | .num = 3, |
408 | .type = SDW_DPN_SIMPLE, |
409 | .min_ch = 1, |
410 | .max_ch = 1, |
411 | .simple_ch_prep_sm = true, |
412 | .read_only_wordlength = true, |
413 | }, { |
414 | /* VISENSE */ |
415 | .num = 4, |
416 | .type = SDW_DPN_SIMPLE, |
417 | .min_ch = 1, |
418 | .max_ch = 1, |
419 | .simple_ch_prep_sm = true, |
420 | .read_only_wordlength = true, |
421 | } |
422 | }; |
423 | |
424 | static const struct sdw_port_config wsa881x_pconfig[WSA881X_MAX_SWR_PORTS] = { |
425 | { |
426 | .num = 1, |
427 | .ch_mask = 0x1, |
428 | }, { |
429 | .num = 2, |
430 | .ch_mask = 0xf, |
431 | }, { |
432 | .num = 3, |
433 | .ch_mask = 0x3, |
434 | }, { /* IV feedback */ |
435 | .num = 4, |
436 | .ch_mask = 0x3, |
437 | }, |
438 | }; |
439 | |
440 | static bool wsa881x_readable_register(struct device *dev, unsigned int reg) |
441 | { |
442 | switch (reg) { |
443 | case WSA881X_CHIP_ID0: |
444 | case WSA881X_CHIP_ID1: |
445 | case WSA881X_CHIP_ID2: |
446 | case WSA881X_CHIP_ID3: |
447 | case WSA881X_BUS_ID: |
448 | case WSA881X_CDC_RST_CTL: |
449 | case WSA881X_CDC_TOP_CLK_CTL: |
450 | case WSA881X_CDC_ANA_CLK_CTL: |
451 | case WSA881X_CDC_DIG_CLK_CTL: |
452 | case WSA881X_CLOCK_CONFIG: |
453 | case WSA881X_ANA_CTL: |
454 | case WSA881X_SWR_RESET_EN: |
455 | case WSA881X_RESET_CTL: |
456 | case WSA881X_TADC_VALUE_CTL: |
457 | case WSA881X_TEMP_DETECT_CTL: |
458 | case WSA881X_TEMP_MSB: |
459 | case WSA881X_TEMP_LSB: |
460 | case WSA881X_TEMP_CONFIG0: |
461 | case WSA881X_TEMP_CONFIG1: |
462 | case WSA881X_CDC_CLIP_CTL: |
463 | case WSA881X_SDM_PDM9_LSB: |
464 | case WSA881X_SDM_PDM9_MSB: |
465 | case WSA881X_CDC_RX_CTL: |
466 | case WSA881X_DEM_BYPASS_DATA0: |
467 | case WSA881X_DEM_BYPASS_DATA1: |
468 | case WSA881X_DEM_BYPASS_DATA2: |
469 | case WSA881X_DEM_BYPASS_DATA3: |
470 | case WSA881X_OTP_CTRL0: |
471 | case WSA881X_OTP_CTRL1: |
472 | case WSA881X_HDRIVE_CTL_GROUP1: |
473 | case WSA881X_INTR_MODE: |
474 | case WSA881X_INTR_MASK: |
475 | case WSA881X_INTR_STATUS: |
476 | case WSA881X_INTR_CLEAR: |
477 | case WSA881X_INTR_LEVEL: |
478 | case WSA881X_INTR_SET: |
479 | case WSA881X_INTR_TEST: |
480 | case WSA881X_PDM_TEST_MODE: |
481 | case WSA881X_ATE_TEST_MODE: |
482 | case WSA881X_PIN_CTL_MODE: |
483 | case WSA881X_PIN_CTL_OE: |
484 | case WSA881X_PIN_WDATA_IOPAD: |
485 | case WSA881X_PIN_STATUS: |
486 | case WSA881X_DIG_DEBUG_MODE: |
487 | case WSA881X_DIG_DEBUG_SEL: |
488 | case WSA881X_DIG_DEBUG_EN: |
489 | case WSA881X_SWR_HM_TEST1: |
490 | case WSA881X_SWR_HM_TEST2: |
491 | case WSA881X_TEMP_DETECT_DBG_CTL: |
492 | case WSA881X_TEMP_DEBUG_MSB: |
493 | case WSA881X_TEMP_DEBUG_LSB: |
494 | case WSA881X_SAMPLE_EDGE_SEL: |
495 | case WSA881X_IOPAD_CTL: |
496 | case WSA881X_SPARE_0: |
497 | case WSA881X_SPARE_1: |
498 | case WSA881X_SPARE_2: |
499 | case WSA881X_OTP_REG_0: |
500 | case WSA881X_OTP_REG_1: |
501 | case WSA881X_OTP_REG_2: |
502 | case WSA881X_OTP_REG_3: |
503 | case WSA881X_OTP_REG_4: |
504 | case WSA881X_OTP_REG_5: |
505 | case WSA881X_OTP_REG_6: |
506 | case WSA881X_OTP_REG_7: |
507 | case WSA881X_OTP_REG_8: |
508 | case WSA881X_OTP_REG_9: |
509 | case WSA881X_OTP_REG_10: |
510 | case WSA881X_OTP_REG_11: |
511 | case WSA881X_OTP_REG_12: |
512 | case WSA881X_OTP_REG_13: |
513 | case WSA881X_OTP_REG_14: |
514 | case WSA881X_OTP_REG_15: |
515 | case WSA881X_OTP_REG_16: |
516 | case WSA881X_OTP_REG_17: |
517 | case WSA881X_OTP_REG_18: |
518 | case WSA881X_OTP_REG_19: |
519 | case WSA881X_OTP_REG_20: |
520 | case WSA881X_OTP_REG_21: |
521 | case WSA881X_OTP_REG_22: |
522 | case WSA881X_OTP_REG_23: |
523 | case WSA881X_OTP_REG_24: |
524 | case WSA881X_OTP_REG_25: |
525 | case WSA881X_OTP_REG_26: |
526 | case WSA881X_OTP_REG_27: |
527 | case WSA881X_OTP_REG_28: |
528 | case WSA881X_OTP_REG_29: |
529 | case WSA881X_OTP_REG_30: |
530 | case WSA881X_OTP_REG_31: |
531 | case WSA881X_OTP_REG_63: |
532 | case WSA881X_BIAS_REF_CTRL: |
533 | case WSA881X_BIAS_TEST: |
534 | case WSA881X_BIAS_BIAS: |
535 | case WSA881X_TEMP_OP: |
536 | case WSA881X_TEMP_IREF_CTRL: |
537 | case WSA881X_TEMP_ISENS_CTRL: |
538 | case WSA881X_TEMP_CLK_CTRL: |
539 | case WSA881X_TEMP_TEST: |
540 | case WSA881X_TEMP_BIAS: |
541 | case WSA881X_TEMP_ADC_CTRL: |
542 | case WSA881X_TEMP_DOUT_MSB: |
543 | case WSA881X_TEMP_DOUT_LSB: |
544 | case WSA881X_ADC_EN_MODU_V: |
545 | case WSA881X_ADC_EN_MODU_I: |
546 | case WSA881X_ADC_EN_DET_TEST_V: |
547 | case WSA881X_ADC_EN_DET_TEST_I: |
548 | case WSA881X_ADC_SEL_IBIAS: |
549 | case WSA881X_ADC_EN_SEL_IBAIS: |
550 | case WSA881X_SPKR_DRV_EN: |
551 | case WSA881X_SPKR_DRV_GAIN: |
552 | case WSA881X_SPKR_DAC_CTL: |
553 | case WSA881X_SPKR_DRV_DBG: |
554 | case WSA881X_SPKR_PWRSTG_DBG: |
555 | case WSA881X_SPKR_OCP_CTL: |
556 | case WSA881X_SPKR_CLIP_CTL: |
557 | case WSA881X_SPKR_BBM_CTL: |
558 | case WSA881X_SPKR_MISC_CTL1: |
559 | case WSA881X_SPKR_MISC_CTL2: |
560 | case WSA881X_SPKR_BIAS_INT: |
561 | case WSA881X_SPKR_PA_INT: |
562 | case WSA881X_SPKR_BIAS_CAL: |
563 | case WSA881X_SPKR_BIAS_PSRR: |
564 | case WSA881X_SPKR_STATUS1: |
565 | case WSA881X_SPKR_STATUS2: |
566 | case WSA881X_BOOST_EN_CTL: |
567 | case WSA881X_BOOST_CURRENT_LIMIT: |
568 | case WSA881X_BOOST_PS_CTL: |
569 | case WSA881X_BOOST_PRESET_OUT1: |
570 | case WSA881X_BOOST_PRESET_OUT2: |
571 | case WSA881X_BOOST_FORCE_OUT: |
572 | case WSA881X_BOOST_LDO_PROG: |
573 | case WSA881X_BOOST_SLOPE_COMP_ISENSE_FB: |
574 | case WSA881X_BOOST_RON_CTL: |
575 | case WSA881X_BOOST_LOOP_STABILITY: |
576 | case WSA881X_BOOST_ZX_CTL: |
577 | case WSA881X_BOOST_START_CTL: |
578 | case WSA881X_BOOST_MISC1_CTL: |
579 | case WSA881X_BOOST_MISC2_CTL: |
580 | case WSA881X_BOOST_MISC3_CTL: |
581 | case WSA881X_BOOST_ATEST_CTL: |
582 | case WSA881X_SPKR_PROT_FE_GAIN: |
583 | case WSA881X_SPKR_PROT_FE_CM_LDO_SET: |
584 | case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1: |
585 | case WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2: |
586 | case WSA881X_SPKR_PROT_ATEST1: |
587 | case WSA881X_SPKR_PROT_ATEST2: |
588 | case WSA881X_SPKR_PROT_FE_VSENSE_VCM: |
589 | case WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1: |
590 | case WSA881X_BONGO_RESRV_REG1: |
591 | case WSA881X_BONGO_RESRV_REG2: |
592 | case WSA881X_SPKR_PROT_SAR: |
593 | case WSA881X_SPKR_STATUS3: |
594 | return true; |
595 | default: |
596 | return false; |
597 | } |
598 | } |
599 | |
600 | static bool wsa881x_volatile_register(struct device *dev, unsigned int reg) |
601 | { |
602 | switch (reg) { |
603 | case WSA881X_CHIP_ID0: |
604 | case WSA881X_CHIP_ID1: |
605 | case WSA881X_CHIP_ID2: |
606 | case WSA881X_CHIP_ID3: |
607 | case WSA881X_BUS_ID: |
608 | case WSA881X_TEMP_MSB: |
609 | case WSA881X_TEMP_LSB: |
610 | case WSA881X_SDM_PDM9_LSB: |
611 | case WSA881X_SDM_PDM9_MSB: |
612 | case WSA881X_OTP_CTRL1: |
613 | case WSA881X_INTR_STATUS: |
614 | case WSA881X_ATE_TEST_MODE: |
615 | case WSA881X_PIN_STATUS: |
616 | case WSA881X_SWR_HM_TEST2: |
617 | case WSA881X_SPKR_STATUS1: |
618 | case WSA881X_SPKR_STATUS2: |
619 | case WSA881X_SPKR_STATUS3: |
620 | case WSA881X_OTP_REG_0: |
621 | case WSA881X_OTP_REG_1: |
622 | case WSA881X_OTP_REG_2: |
623 | case WSA881X_OTP_REG_3: |
624 | case WSA881X_OTP_REG_4: |
625 | case WSA881X_OTP_REG_5: |
626 | case WSA881X_OTP_REG_31: |
627 | case WSA881X_TEMP_DOUT_MSB: |
628 | case WSA881X_TEMP_DOUT_LSB: |
629 | case WSA881X_TEMP_OP: |
630 | case WSA881X_SPKR_PROT_SAR: |
631 | return true; |
632 | default: |
633 | return false; |
634 | } |
635 | } |
636 | |
637 | static struct regmap_config wsa881x_regmap_config = { |
638 | .reg_bits = 32, |
639 | .val_bits = 8, |
640 | .cache_type = REGCACHE_MAPLE, |
641 | .reg_defaults = wsa881x_defaults, |
642 | .max_register = WSA881X_SPKR_STATUS3, |
643 | .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults), |
644 | .volatile_reg = wsa881x_volatile_register, |
645 | .readable_reg = wsa881x_readable_register, |
646 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
647 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
648 | }; |
649 | |
650 | enum { |
651 | G_18DB = 0, |
652 | G_16P5DB, |
653 | G_15DB, |
654 | G_13P5DB, |
655 | G_12DB, |
656 | G_10P5DB, |
657 | G_9DB, |
658 | G_7P5DB, |
659 | G_6DB, |
660 | G_4P5DB, |
661 | G_3DB, |
662 | G_1P5DB, |
663 | G_0DB, |
664 | }; |
665 | |
666 | /* |
667 | * Private data Structure for wsa881x. All parameters related to |
668 | * WSA881X codec needs to be defined here. |
669 | */ |
670 | struct wsa881x_priv { |
671 | struct regmap *regmap; |
672 | struct device *dev; |
673 | struct sdw_slave *slave; |
674 | struct sdw_stream_config sconfig; |
675 | struct sdw_stream_runtime *sruntime; |
676 | struct sdw_port_config port_config[WSA881X_MAX_SWR_PORTS]; |
677 | struct gpio_desc *sd_n; |
678 | /* |
679 | * Logical state for SD_N GPIO: high for shutdown, low for enable. |
680 | * For backwards compatibility. |
681 | */ |
682 | unsigned int sd_n_val; |
683 | int version; |
684 | int active_ports; |
685 | bool port_prepared[WSA881X_MAX_SWR_PORTS]; |
686 | bool port_enable[WSA881X_MAX_SWR_PORTS]; |
687 | }; |
688 | |
689 | static void wsa881x_init(struct wsa881x_priv *wsa881x) |
690 | { |
691 | struct regmap *rm = wsa881x->regmap; |
692 | unsigned int val = 0; |
693 | |
694 | regmap_read(map: rm, WSA881X_CHIP_ID1, val: &wsa881x->version); |
695 | regmap_register_patch(map: wsa881x->regmap, regs: wsa881x_rev_2_0, |
696 | ARRAY_SIZE(wsa881x_rev_2_0)); |
697 | |
698 | /* Enable software reset output from soundwire slave */ |
699 | regmap_update_bits(map: rm, WSA881X_SWR_RESET_EN, mask: 0x07, val: 0x07); |
700 | |
701 | /* Bring out of analog reset */ |
702 | regmap_update_bits(map: rm, WSA881X_CDC_RST_CTL, mask: 0x02, val: 0x02); |
703 | |
704 | /* Bring out of digital reset */ |
705 | regmap_update_bits(map: rm, WSA881X_CDC_RST_CTL, mask: 0x01, val: 0x01); |
706 | regmap_update_bits(map: rm, WSA881X_CLOCK_CONFIG, mask: 0x10, val: 0x10); |
707 | regmap_update_bits(map: rm, WSA881X_SPKR_OCP_CTL, mask: 0x02, val: 0x02); |
708 | regmap_update_bits(map: rm, WSA881X_SPKR_MISC_CTL1, mask: 0xC0, val: 0x80); |
709 | regmap_update_bits(map: rm, WSA881X_SPKR_MISC_CTL1, mask: 0x06, val: 0x06); |
710 | regmap_update_bits(map: rm, WSA881X_SPKR_BIAS_INT, mask: 0xFF, val: 0x00); |
711 | regmap_update_bits(map: rm, WSA881X_SPKR_PA_INT, mask: 0xF0, val: 0x40); |
712 | regmap_update_bits(map: rm, WSA881X_SPKR_PA_INT, mask: 0x0E, val: 0x0E); |
713 | regmap_update_bits(map: rm, WSA881X_BOOST_LOOP_STABILITY, mask: 0x03, val: 0x03); |
714 | regmap_update_bits(map: rm, WSA881X_BOOST_MISC2_CTL, mask: 0xFF, val: 0x14); |
715 | regmap_update_bits(map: rm, WSA881X_BOOST_START_CTL, mask: 0x80, val: 0x80); |
716 | regmap_update_bits(map: rm, WSA881X_BOOST_START_CTL, mask: 0x03, val: 0x00); |
717 | regmap_update_bits(map: rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, mask: 0x0C, val: 0x04); |
718 | regmap_update_bits(map: rm, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, mask: 0x03, val: 0x00); |
719 | |
720 | regmap_read(map: rm, WSA881X_OTP_REG_0, val: &val); |
721 | if (val) |
722 | regmap_update_bits(map: rm, WSA881X_BOOST_PRESET_OUT1, mask: 0xF0, val: 0x70); |
723 | |
724 | regmap_update_bits(map: rm, WSA881X_BOOST_PRESET_OUT2, mask: 0xF0, val: 0x30); |
725 | regmap_update_bits(map: rm, WSA881X_SPKR_DRV_EN, mask: 0x08, val: 0x08); |
726 | regmap_update_bits(map: rm, WSA881X_BOOST_CURRENT_LIMIT, mask: 0x0F, val: 0x08); |
727 | regmap_update_bits(map: rm, WSA881X_SPKR_OCP_CTL, mask: 0x30, val: 0x30); |
728 | regmap_update_bits(map: rm, WSA881X_SPKR_OCP_CTL, mask: 0x0C, val: 0x00); |
729 | regmap_update_bits(map: rm, WSA881X_OTP_REG_28, mask: 0x3F, val: 0x3A); |
730 | regmap_update_bits(map: rm, WSA881X_BONGO_RESRV_REG1, mask: 0xFF, val: 0xB2); |
731 | regmap_update_bits(map: rm, WSA881X_BONGO_RESRV_REG2, mask: 0xFF, val: 0x05); |
732 | } |
733 | |
734 | static int wsa881x_component_probe(struct snd_soc_component *comp) |
735 | { |
736 | struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(c: comp); |
737 | |
738 | snd_soc_component_init_regmap(component: comp, regmap: wsa881x->regmap); |
739 | |
740 | return 0; |
741 | } |
742 | |
743 | static int wsa881x_put_pa_gain(struct snd_kcontrol *kc, |
744 | struct snd_ctl_elem_value *ucontrol) |
745 | { |
746 | struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol: kc); |
747 | struct soc_mixer_control *mc = |
748 | (struct soc_mixer_control *)kc->private_value; |
749 | int max = mc->max; |
750 | unsigned int mask = (1 << fls(x: max)) - 1; |
751 | int val, ret, min_gain, max_gain; |
752 | |
753 | ret = pm_runtime_resume_and_get(dev: comp->dev); |
754 | if (ret < 0 && ret != -EACCES) |
755 | return ret; |
756 | |
757 | max_gain = (max - ucontrol->value.integer.value[0]) & mask; |
758 | /* |
759 | * Gain has to set incrementally in 4 steps |
760 | * as per HW sequence |
761 | */ |
762 | if (max_gain > G_4P5DB) |
763 | min_gain = G_0DB; |
764 | else |
765 | min_gain = max_gain + 3; |
766 | /* |
767 | * 1ms delay is needed before change in gain |
768 | * as per HW requirement. |
769 | */ |
770 | usleep_range(min: 1000, max: 1010); |
771 | |
772 | for (val = min_gain; max_gain <= val; val--) { |
773 | ret = snd_soc_component_update_bits(component: comp, |
774 | WSA881X_SPKR_DRV_GAIN, |
775 | WSA881X_SPKR_PAG_GAIN_MASK, |
776 | val: val << 4); |
777 | if (ret < 0) |
778 | dev_err(comp->dev, "Failed to change PA gain" ); |
779 | |
780 | usleep_range(min: 1000, max: 1010); |
781 | } |
782 | |
783 | pm_runtime_mark_last_busy(dev: comp->dev); |
784 | pm_runtime_put_autosuspend(dev: comp->dev); |
785 | |
786 | return 1; |
787 | } |
788 | |
789 | static int wsa881x_get_port(struct snd_kcontrol *kcontrol, |
790 | struct snd_ctl_elem_value *ucontrol) |
791 | { |
792 | struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); |
793 | struct wsa881x_priv *data = snd_soc_component_get_drvdata(c: comp); |
794 | struct soc_mixer_control *mixer = |
795 | (struct soc_mixer_control *)kcontrol->private_value; |
796 | int portidx = mixer->reg; |
797 | |
798 | ucontrol->value.integer.value[0] = data->port_enable[portidx]; |
799 | |
800 | |
801 | return 0; |
802 | } |
803 | |
804 | static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable) |
805 | { |
806 | if (enable) |
807 | snd_soc_component_update_bits(component: comp, WSA881X_BOOST_EN_CTL, |
808 | WSA881X_BOOST_EN_MASK, |
809 | WSA881X_BOOST_EN); |
810 | else |
811 | snd_soc_component_update_bits(component: comp, WSA881X_BOOST_EN_CTL, |
812 | WSA881X_BOOST_EN_MASK, val: 0); |
813 | /* |
814 | * 1.5ms sleep is needed after boost enable/disable as per |
815 | * HW requirement |
816 | */ |
817 | usleep_range(min: 1500, max: 1510); |
818 | return 0; |
819 | } |
820 | |
821 | static int wsa881x_set_port(struct snd_kcontrol *kcontrol, |
822 | struct snd_ctl_elem_value *ucontrol) |
823 | { |
824 | struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); |
825 | struct wsa881x_priv *data = snd_soc_component_get_drvdata(c: comp); |
826 | struct soc_mixer_control *mixer = |
827 | (struct soc_mixer_control *)kcontrol->private_value; |
828 | int portidx = mixer->reg; |
829 | |
830 | if (ucontrol->value.integer.value[0]) { |
831 | if (data->port_enable[portidx]) |
832 | return 0; |
833 | |
834 | data->port_enable[portidx] = true; |
835 | } else { |
836 | if (!data->port_enable[portidx]) |
837 | return 0; |
838 | |
839 | data->port_enable[portidx] = false; |
840 | } |
841 | |
842 | if (portidx == WSA881X_PORT_BOOST) /* Boost Switch */ |
843 | wsa881x_boost_ctrl(comp, enable: data->port_enable[portidx]); |
844 | |
845 | return 1; |
846 | } |
847 | |
848 | static const char * const smart_boost_lvl_text[] = { |
849 | "6.625 V" , "6.750 V" , "6.875 V" , "7.000 V" , |
850 | "7.125 V" , "7.250 V" , "7.375 V" , "7.500 V" , |
851 | "7.625 V" , "7.750 V" , "7.875 V" , "8.000 V" , |
852 | "8.125 V" , "8.250 V" , "8.375 V" , "8.500 V" |
853 | }; |
854 | |
855 | static const struct soc_enum smart_boost_lvl_enum = |
856 | SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0, |
857 | ARRAY_SIZE(smart_boost_lvl_text), |
858 | smart_boost_lvl_text); |
859 | |
860 | static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0); |
861 | |
862 | static const struct snd_kcontrol_new wsa881x_snd_controls[] = { |
863 | SOC_ENUM("Smart Boost Level" , smart_boost_lvl_enum), |
864 | WSA881X_PA_GAIN_TLV("PA Volume" , WSA881X_SPKR_DRV_GAIN, |
865 | 4, 0xC, 1, pa_gain), |
866 | SOC_SINGLE_EXT("DAC Switch" , WSA881X_PORT_DAC, 0, 1, 0, |
867 | wsa881x_get_port, wsa881x_set_port), |
868 | SOC_SINGLE_EXT("COMP Switch" , WSA881X_PORT_COMP, 0, 1, 0, |
869 | wsa881x_get_port, wsa881x_set_port), |
870 | SOC_SINGLE_EXT("BOOST Switch" , WSA881X_PORT_BOOST, 0, 1, 0, |
871 | wsa881x_get_port, wsa881x_set_port), |
872 | SOC_SINGLE_EXT("VISENSE Switch" , WSA881X_PORT_VISENSE, 0, 1, 0, |
873 | wsa881x_get_port, wsa881x_set_port), |
874 | }; |
875 | |
876 | static const struct snd_soc_dapm_route wsa881x_audio_map[] = { |
877 | { "RDAC" , NULL, "IN" }, |
878 | { "RDAC" , NULL, "DCLK" }, |
879 | { "RDAC" , NULL, "ACLK" }, |
880 | { "RDAC" , NULL, "Bandgap" }, |
881 | { "SPKR PGA" , NULL, "RDAC" }, |
882 | { "SPKR" , NULL, "SPKR PGA" }, |
883 | }; |
884 | |
885 | static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp, |
886 | bool enable) |
887 | { |
888 | struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(c: comp); |
889 | |
890 | if (enable) { |
891 | regmap_multi_reg_write(map: wsa881x->regmap, regs: wsa881x_vi_txfe_en_2_0, |
892 | ARRAY_SIZE(wsa881x_vi_txfe_en_2_0)); |
893 | } else { |
894 | snd_soc_component_update_bits(component: comp, |
895 | WSA881X_SPKR_PROT_FE_VSENSE_VCM, |
896 | mask: 0x08, val: 0x08); |
897 | /* |
898 | * 200us sleep is needed after visense txfe disable as per |
899 | * HW requirement. |
900 | */ |
901 | usleep_range(min: 200, max: 210); |
902 | snd_soc_component_update_bits(component: comp, WSA881X_SPKR_PROT_FE_GAIN, |
903 | mask: 0x01, val: 0x00); |
904 | } |
905 | return 0; |
906 | } |
907 | |
908 | static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp, |
909 | bool enable) |
910 | { |
911 | snd_soc_component_update_bits(component: comp, WSA881X_ADC_EN_MODU_V, BIT(7), |
912 | val: (enable << 7)); |
913 | snd_soc_component_update_bits(component: comp, WSA881X_ADC_EN_MODU_I, BIT(7), |
914 | val: (enable << 7)); |
915 | return 0; |
916 | } |
917 | |
918 | static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w, |
919 | struct snd_kcontrol *kcontrol, int event) |
920 | { |
921 | struct snd_soc_component *comp = snd_soc_dapm_to_component(dapm: w->dapm); |
922 | struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(c: comp); |
923 | |
924 | switch (event) { |
925 | case SND_SOC_DAPM_PRE_PMU: |
926 | snd_soc_component_update_bits(component: comp, WSA881X_SPKR_OCP_CTL, |
927 | WSA881X_SPKR_OCP_MASK, |
928 | WSA881X_SPKR_OCP_EN); |
929 | regmap_multi_reg_write(map: wsa881x->regmap, regs: wsa881x_pre_pmu_pa_2_0, |
930 | ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0)); |
931 | |
932 | snd_soc_component_update_bits(component: comp, WSA881X_SPKR_DRV_GAIN, |
933 | WSA881X_PA_GAIN_SEL_MASK, |
934 | WSA881X_PA_GAIN_SEL_REG); |
935 | break; |
936 | case SND_SOC_DAPM_POST_PMU: |
937 | if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { |
938 | wsa881x_visense_txfe_ctrl(comp, enable: true); |
939 | snd_soc_component_update_bits(component: comp, |
940 | WSA881X_ADC_EN_SEL_IBAIS, |
941 | mask: 0x07, val: 0x01); |
942 | wsa881x_visense_adc_ctrl(comp, enable: true); |
943 | } |
944 | |
945 | break; |
946 | case SND_SOC_DAPM_POST_PMD: |
947 | if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) { |
948 | wsa881x_visense_adc_ctrl(comp, enable: false); |
949 | wsa881x_visense_txfe_ctrl(comp, enable: false); |
950 | } |
951 | |
952 | snd_soc_component_update_bits(component: comp, WSA881X_SPKR_OCP_CTL, |
953 | WSA881X_SPKR_OCP_MASK, |
954 | WSA881X_SPKR_OCP_EN | |
955 | WSA881X_SPKR_OCP_HOLD); |
956 | break; |
957 | } |
958 | return 0; |
959 | } |
960 | |
961 | static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = { |
962 | SND_SOC_DAPM_INPUT("IN" ), |
963 | SND_SOC_DAPM_DAC_E("RDAC" , NULL, WSA881X_SPKR_DAC_CTL, 7, 0, |
964 | NULL, |
965 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
966 | SND_SOC_DAPM_PGA_E("SPKR PGA" , SND_SOC_NOPM, 0, 0, NULL, 0, |
967 | wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU | |
968 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
969 | SND_SOC_DAPM_SUPPLY("DCLK" , WSA881X_CDC_DIG_CLK_CTL, 0, 0, NULL, |
970 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
971 | SND_SOC_DAPM_SUPPLY("ACLK" , WSA881X_CDC_ANA_CLK_CTL, 0, 0, NULL, |
972 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
973 | SND_SOC_DAPM_SUPPLY("Bandgap" , WSA881X_TEMP_OP, 3, 0, |
974 | NULL, |
975 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
976 | SND_SOC_DAPM_OUTPUT("SPKR" ), |
977 | }; |
978 | |
979 | static int wsa881x_hw_params(struct snd_pcm_substream *substream, |
980 | struct snd_pcm_hw_params *params, |
981 | struct snd_soc_dai *dai) |
982 | { |
983 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: dai->dev); |
984 | int i; |
985 | |
986 | wsa881x->active_ports = 0; |
987 | for (i = 0; i < WSA881X_MAX_SWR_PORTS; i++) { |
988 | if (!wsa881x->port_enable[i]) |
989 | continue; |
990 | |
991 | wsa881x->port_config[wsa881x->active_ports] = |
992 | wsa881x_pconfig[i]; |
993 | wsa881x->active_ports++; |
994 | } |
995 | |
996 | return sdw_stream_add_slave(slave: wsa881x->slave, stream_config: &wsa881x->sconfig, |
997 | port_config: wsa881x->port_config, num_ports: wsa881x->active_ports, |
998 | stream: wsa881x->sruntime); |
999 | } |
1000 | |
1001 | static int wsa881x_hw_free(struct snd_pcm_substream *substream, |
1002 | struct snd_soc_dai *dai) |
1003 | { |
1004 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: dai->dev); |
1005 | |
1006 | sdw_stream_remove_slave(slave: wsa881x->slave, stream: wsa881x->sruntime); |
1007 | |
1008 | return 0; |
1009 | } |
1010 | |
1011 | static int wsa881x_set_sdw_stream(struct snd_soc_dai *dai, |
1012 | void *stream, int direction) |
1013 | { |
1014 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: dai->dev); |
1015 | |
1016 | wsa881x->sruntime = stream; |
1017 | |
1018 | return 0; |
1019 | } |
1020 | |
1021 | static int wsa881x_digital_mute(struct snd_soc_dai *dai, int mute, int stream) |
1022 | { |
1023 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: dai->dev); |
1024 | |
1025 | if (mute) |
1026 | regmap_update_bits(map: wsa881x->regmap, WSA881X_SPKR_DRV_EN, mask: 0x80, |
1027 | val: 0x00); |
1028 | else |
1029 | regmap_update_bits(map: wsa881x->regmap, WSA881X_SPKR_DRV_EN, mask: 0x80, |
1030 | val: 0x80); |
1031 | |
1032 | return 0; |
1033 | } |
1034 | |
1035 | static const struct snd_soc_dai_ops wsa881x_dai_ops = { |
1036 | .hw_params = wsa881x_hw_params, |
1037 | .hw_free = wsa881x_hw_free, |
1038 | .mute_stream = wsa881x_digital_mute, |
1039 | .set_stream = wsa881x_set_sdw_stream, |
1040 | }; |
1041 | |
1042 | static struct snd_soc_dai_driver wsa881x_dais[] = { |
1043 | { |
1044 | .name = "SPKR" , |
1045 | .id = 0, |
1046 | .playback = { |
1047 | .stream_name = "SPKR Playback" , |
1048 | .rates = SNDRV_PCM_RATE_48000, |
1049 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
1050 | .rate_max = 48000, |
1051 | .rate_min = 48000, |
1052 | .channels_min = 1, |
1053 | .channels_max = 1, |
1054 | }, |
1055 | .ops = &wsa881x_dai_ops, |
1056 | }, |
1057 | }; |
1058 | |
1059 | static const struct snd_soc_component_driver wsa881x_component_drv = { |
1060 | .name = "WSA881x" , |
1061 | .probe = wsa881x_component_probe, |
1062 | .controls = wsa881x_snd_controls, |
1063 | .num_controls = ARRAY_SIZE(wsa881x_snd_controls), |
1064 | .dapm_widgets = wsa881x_dapm_widgets, |
1065 | .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets), |
1066 | .dapm_routes = wsa881x_audio_map, |
1067 | .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map), |
1068 | .endianness = 1, |
1069 | }; |
1070 | |
1071 | static int wsa881x_update_status(struct sdw_slave *slave, |
1072 | enum sdw_slave_status status) |
1073 | { |
1074 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: &slave->dev); |
1075 | |
1076 | if (status == SDW_SLAVE_ATTACHED && slave->dev_num > 0) |
1077 | wsa881x_init(wsa881x); |
1078 | |
1079 | return 0; |
1080 | } |
1081 | |
1082 | static int wsa881x_port_prep(struct sdw_slave *slave, |
1083 | struct sdw_prepare_ch *prepare_ch, |
1084 | enum sdw_port_prep_ops state) |
1085 | { |
1086 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev: &slave->dev); |
1087 | |
1088 | if (state == SDW_OPS_PORT_POST_PREP) |
1089 | wsa881x->port_prepared[prepare_ch->num - 1] = true; |
1090 | else |
1091 | wsa881x->port_prepared[prepare_ch->num - 1] = false; |
1092 | |
1093 | return 0; |
1094 | } |
1095 | |
1096 | static int wsa881x_bus_config(struct sdw_slave *slave, |
1097 | struct sdw_bus_params *params) |
1098 | { |
1099 | sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank), |
1100 | value: 0x01); |
1101 | |
1102 | return 0; |
1103 | } |
1104 | |
1105 | static const struct sdw_slave_ops wsa881x_slave_ops = { |
1106 | .update_status = wsa881x_update_status, |
1107 | .bus_config = wsa881x_bus_config, |
1108 | .port_prep = wsa881x_port_prep, |
1109 | }; |
1110 | |
1111 | static int wsa881x_probe(struct sdw_slave *pdev, |
1112 | const struct sdw_device_id *id) |
1113 | { |
1114 | struct wsa881x_priv *wsa881x; |
1115 | struct device *dev = &pdev->dev; |
1116 | |
1117 | wsa881x = devm_kzalloc(dev, size: sizeof(*wsa881x), GFP_KERNEL); |
1118 | if (!wsa881x) |
1119 | return -ENOMEM; |
1120 | |
1121 | wsa881x->sd_n = devm_gpiod_get_optional(dev, con_id: "powerdown" , |
1122 | GPIOD_FLAGS_BIT_NONEXCLUSIVE); |
1123 | if (IS_ERR(ptr: wsa881x->sd_n)) |
1124 | return dev_err_probe(dev, err: PTR_ERR(ptr: wsa881x->sd_n), |
1125 | fmt: "Shutdown Control GPIO not found\n" ); |
1126 | |
1127 | /* |
1128 | * Backwards compatibility work-around. |
1129 | * |
1130 | * The SD_N GPIO is active low, however upstream DTS used always active |
1131 | * high. Changing the flag in driver and DTS will break backwards |
1132 | * compatibility, so add a simple value inversion to work with both old |
1133 | * and new DTS. |
1134 | * |
1135 | * This won't work properly with DTS using the flags properly in cases: |
1136 | * 1. Old DTS with proper ACTIVE_LOW, however such case was broken |
1137 | * before as the driver required the active high. |
1138 | * 2. New DTS with proper ACTIVE_HIGH (intended), which is rare case |
1139 | * (not existing upstream) but possible. This is the price of |
1140 | * backwards compatibility, therefore this hack should be removed at |
1141 | * some point. |
1142 | */ |
1143 | wsa881x->sd_n_val = gpiod_is_active_low(desc: wsa881x->sd_n); |
1144 | if (!wsa881x->sd_n_val) |
1145 | dev_warn(dev, "Using ACTIVE_HIGH for shutdown GPIO. Your DTB might be outdated or you use unsupported configuration for the GPIO." ); |
1146 | |
1147 | dev_set_drvdata(dev, data: wsa881x); |
1148 | wsa881x->slave = pdev; |
1149 | wsa881x->dev = dev; |
1150 | wsa881x->sconfig.ch_count = 1; |
1151 | wsa881x->sconfig.bps = 1; |
1152 | wsa881x->sconfig.frame_rate = 48000; |
1153 | wsa881x->sconfig.direction = SDW_DATA_DIR_RX; |
1154 | wsa881x->sconfig.type = SDW_STREAM_PDM; |
1155 | pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0); |
1156 | pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop; |
1157 | pdev->prop.scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; |
1158 | gpiod_direction_output(desc: wsa881x->sd_n, value: !wsa881x->sd_n_val); |
1159 | |
1160 | wsa881x->regmap = devm_regmap_init_sdw(pdev, &wsa881x_regmap_config); |
1161 | if (IS_ERR(ptr: wsa881x->regmap)) |
1162 | return dev_err_probe(dev, err: PTR_ERR(ptr: wsa881x->regmap), fmt: "regmap_init failed\n" ); |
1163 | |
1164 | pm_runtime_set_autosuspend_delay(dev, delay: 3000); |
1165 | pm_runtime_use_autosuspend(dev); |
1166 | pm_runtime_mark_last_busy(dev); |
1167 | pm_runtime_set_active(dev); |
1168 | pm_runtime_enable(dev); |
1169 | |
1170 | return devm_snd_soc_register_component(dev, |
1171 | component_driver: &wsa881x_component_drv, |
1172 | dai_drv: wsa881x_dais, |
1173 | ARRAY_SIZE(wsa881x_dais)); |
1174 | } |
1175 | |
1176 | static int __maybe_unused wsa881x_runtime_suspend(struct device *dev) |
1177 | { |
1178 | struct regmap *regmap = dev_get_regmap(dev, NULL); |
1179 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev); |
1180 | |
1181 | gpiod_direction_output(desc: wsa881x->sd_n, value: wsa881x->sd_n_val); |
1182 | |
1183 | regcache_cache_only(map: regmap, enable: true); |
1184 | regcache_mark_dirty(map: regmap); |
1185 | |
1186 | return 0; |
1187 | } |
1188 | |
1189 | static int __maybe_unused wsa881x_runtime_resume(struct device *dev) |
1190 | { |
1191 | struct sdw_slave *slave = dev_to_sdw_dev(dev); |
1192 | struct regmap *regmap = dev_get_regmap(dev, NULL); |
1193 | struct wsa881x_priv *wsa881x = dev_get_drvdata(dev); |
1194 | unsigned long time; |
1195 | |
1196 | gpiod_direction_output(desc: wsa881x->sd_n, value: !wsa881x->sd_n_val); |
1197 | |
1198 | time = wait_for_completion_timeout(x: &slave->initialization_complete, |
1199 | timeout: msecs_to_jiffies(WSA881X_PROBE_TIMEOUT)); |
1200 | if (!time) { |
1201 | dev_err(dev, "Initialization not complete, timed out\n" ); |
1202 | gpiod_direction_output(desc: wsa881x->sd_n, value: wsa881x->sd_n_val); |
1203 | return -ETIMEDOUT; |
1204 | } |
1205 | |
1206 | regcache_cache_only(map: regmap, enable: false); |
1207 | regcache_sync(map: regmap); |
1208 | |
1209 | return 0; |
1210 | } |
1211 | |
1212 | static const struct dev_pm_ops wsa881x_pm_ops = { |
1213 | SET_RUNTIME_PM_OPS(wsa881x_runtime_suspend, wsa881x_runtime_resume, NULL) |
1214 | }; |
1215 | |
1216 | static const struct sdw_device_id wsa881x_slave_id[] = { |
1217 | SDW_SLAVE_ENTRY(0x0217, 0x2010, 0), |
1218 | SDW_SLAVE_ENTRY(0x0217, 0x2110, 0), |
1219 | {}, |
1220 | }; |
1221 | MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id); |
1222 | |
1223 | static struct sdw_driver wsa881x_codec_driver = { |
1224 | .probe = wsa881x_probe, |
1225 | .ops = &wsa881x_slave_ops, |
1226 | .id_table = wsa881x_slave_id, |
1227 | .driver = { |
1228 | .name = "wsa881x-codec" , |
1229 | .pm = &wsa881x_pm_ops, |
1230 | } |
1231 | }; |
1232 | module_sdw_driver(wsa881x_codec_driver); |
1233 | |
1234 | MODULE_DESCRIPTION("WSA881x codec driver" ); |
1235 | MODULE_LICENSE("GPL v2" ); |
1236 | |