1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2019 NXP
4 */
5
6#ifndef _FSL_EASRC_H
7#define _FSL_EASRC_H
8
9#include <sound/asound.h>
10#include <linux/dma/imx-dma.h>
11
12#include "fsl_asrc_common.h"
13
14/* EASRC Register Map */
15
16/* ASRC Input Write FIFO */
17#define REG_EASRC_WRFIFO(ctx) (0x000 + 4 * (ctx))
18/* ASRC Output Read FIFO */
19#define REG_EASRC_RDFIFO(ctx) (0x010 + 4 * (ctx))
20/* ASRC Context Control */
21#define REG_EASRC_CC(ctx) (0x020 + 4 * (ctx))
22/* ASRC Context Control Extended 1 */
23#define REG_EASRC_CCE1(ctx) (0x030 + 4 * (ctx))
24/* ASRC Context Control Extended 2 */
25#define REG_EASRC_CCE2(ctx) (0x040 + 4 * (ctx))
26/* ASRC Control Input Access */
27#define REG_EASRC_CIA(ctx) (0x050 + 4 * (ctx))
28/* ASRC Datapath Processor Control Slot0 */
29#define REG_EASRC_DPCS0R0(ctx) (0x060 + 4 * (ctx))
30#define REG_EASRC_DPCS0R1(ctx) (0x070 + 4 * (ctx))
31#define REG_EASRC_DPCS0R2(ctx) (0x080 + 4 * (ctx))
32#define REG_EASRC_DPCS0R3(ctx) (0x090 + 4 * (ctx))
33/* ASRC Datapath Processor Control Slot1 */
34#define REG_EASRC_DPCS1R0(ctx) (0x0A0 + 4 * (ctx))
35#define REG_EASRC_DPCS1R1(ctx) (0x0B0 + 4 * (ctx))
36#define REG_EASRC_DPCS1R2(ctx) (0x0C0 + 4 * (ctx))
37#define REG_EASRC_DPCS1R3(ctx) (0x0D0 + 4 * (ctx))
38/* ASRC Context Output Control */
39#define REG_EASRC_COC(ctx) (0x0E0 + 4 * (ctx))
40/* ASRC Control Output Access */
41#define REG_EASRC_COA(ctx) (0x0F0 + 4 * (ctx))
42/* ASRC Sample FIFO Status */
43#define REG_EASRC_SFS(ctx) (0x100 + 4 * (ctx))
44/* ASRC Resampling Ratio Low */
45#define REG_EASRC_RRL(ctx) (0x110 + 8 * (ctx))
46/* ASRC Resampling Ratio High */
47#define REG_EASRC_RRH(ctx) (0x114 + 8 * (ctx))
48/* ASRC Resampling Ratio Update Control */
49#define REG_EASRC_RUC(ctx) (0x130 + 4 * (ctx))
50/* ASRC Resampling Ratio Update Rate */
51#define REG_EASRC_RUR(ctx) (0x140 + 4 * (ctx))
52/* ASRC Resampling Center Tap Coefficient Low */
53#define REG_EASRC_RCTCL (0x150)
54/* ASRC Resampling Center Tap Coefficient High */
55#define REG_EASRC_RCTCH (0x154)
56/* ASRC Prefilter Coefficient FIFO */
57#define REG_EASRC_PCF(ctx) (0x160 + 4 * (ctx))
58/* ASRC Context Resampling Coefficient Memory */
59#define REG_EASRC_CRCM 0x170
60/* ASRC Context Resampling Coefficient Control*/
61#define REG_EASRC_CRCC 0x174
62/* ASRC Interrupt Control */
63#define REG_EASRC_IRQC 0x178
64/* ASRC Interrupt Status Flags */
65#define REG_EASRC_IRQF 0x17C
66/* ASRC Channel Status 0 */
67#define REG_EASRC_CS0(ctx) (0x180 + 4 * (ctx))
68/* ASRC Channel Status 1 */
69#define REG_EASRC_CS1(ctx) (0x190 + 4 * (ctx))
70/* ASRC Channel Status 2 */
71#define REG_EASRC_CS2(ctx) (0x1A0 + 4 * (ctx))
72/* ASRC Channel Status 3 */
73#define REG_EASRC_CS3(ctx) (0x1B0 + 4 * (ctx))
74/* ASRC Channel Status 4 */
75#define REG_EASRC_CS4(ctx) (0x1C0 + 4 * (ctx))
76/* ASRC Channel Status 5 */
77#define REG_EASRC_CS5(ctx) (0x1D0 + 4 * (ctx))
78/* ASRC Debug Control Register */
79#define REG_EASRC_DBGC 0x1E0
80/* ASRC Debug Status Register */
81#define REG_EASRC_DBGS 0x1E4
82
83#define REG_EASRC_FIFO(x, ctx) (x == IN ? REG_EASRC_WRFIFO(ctx) \
84 : REG_EASRC_RDFIFO(ctx))
85
86/* ASRC Context Control (CC) */
87#define EASRC_CC_EN_SHIFT 31
88#define EASRC_CC_EN_MASK BIT(EASRC_CC_EN_SHIFT)
89#define EASRC_CC_EN BIT(EASRC_CC_EN_SHIFT)
90#define EASRC_CC_STOP_SHIFT 29
91#define EASRC_CC_STOP_MASK BIT(EASRC_CC_STOP_SHIFT)
92#define EASRC_CC_STOP BIT(EASRC_CC_STOP_SHIFT)
93#define EASRC_CC_FWMDE_SHIFT 28
94#define EASRC_CC_FWMDE_MASK BIT(EASRC_CC_FWMDE_SHIFT)
95#define EASRC_CC_FWMDE BIT(EASRC_CC_FWMDE_SHIFT)
96#define EASRC_CC_FIFO_WTMK_SHIFT 16
97#define EASRC_CC_FIFO_WTMK_WIDTH 7
98#define EASRC_CC_FIFO_WTMK_MASK ((BIT(EASRC_CC_FIFO_WTMK_WIDTH) - 1) \
99 << EASRC_CC_FIFO_WTMK_SHIFT)
100#define EASRC_CC_FIFO_WTMK(v) (((v) << EASRC_CC_FIFO_WTMK_SHIFT) \
101 & EASRC_CC_FIFO_WTMK_MASK)
102#define EASRC_CC_SAMPLE_POS_SHIFT 11
103#define EASRC_CC_SAMPLE_POS_WIDTH 5
104#define EASRC_CC_SAMPLE_POS_MASK ((BIT(EASRC_CC_SAMPLE_POS_WIDTH) - 1) \
105 << EASRC_CC_SAMPLE_POS_SHIFT)
106#define EASRC_CC_SAMPLE_POS(v) (((v) << EASRC_CC_SAMPLE_POS_SHIFT) \
107 & EASRC_CC_SAMPLE_POS_MASK)
108#define EASRC_CC_ENDIANNESS_SHIFT 10
109#define EASRC_CC_ENDIANNESS_MASK BIT(EASRC_CC_ENDIANNESS_SHIFT)
110#define EASRC_CC_ENDIANNESS BIT(EASRC_CC_ENDIANNESS_SHIFT)
111#define EASRC_CC_BPS_SHIFT 8
112#define EASRC_CC_BPS_WIDTH 2
113#define EASRC_CC_BPS_MASK ((BIT(EASRC_CC_BPS_WIDTH) - 1) \
114 << EASRC_CC_BPS_SHIFT)
115#define EASRC_CC_BPS(v) (((v) << EASRC_CC_BPS_SHIFT) \
116 & EASRC_CC_BPS_MASK)
117#define EASRC_CC_FMT_SHIFT 7
118#define EASRC_CC_FMT_MASK BIT(EASRC_CC_FMT_SHIFT)
119#define EASRC_CC_FMT BIT(EASRC_CC_FMT_SHIFT)
120#define EASRC_CC_INSIGN_SHIFT 6
121#define EASRC_CC_INSIGN_MASK BIT(EASRC_CC_INSIGN_SHIFT)
122#define EASRC_CC_INSIGN BIT(EASRC_CC_INSIGN_SHIFT)
123#define EASRC_CC_CHEN_SHIFT 0
124#define EASRC_CC_CHEN_WIDTH 5
125#define EASRC_CC_CHEN_MASK ((BIT(EASRC_CC_CHEN_WIDTH) - 1) \
126 << EASRC_CC_CHEN_SHIFT)
127#define EASRC_CC_CHEN(v) (((v) << EASRC_CC_CHEN_SHIFT) \
128 & EASRC_CC_CHEN_MASK)
129
130/* ASRC Context Control Extended 1 (CCE1) */
131#define EASRC_CCE1_COEF_WS_SHIFT 25
132#define EASRC_CCE1_COEF_WS_MASK BIT(EASRC_CCE1_COEF_WS_SHIFT)
133#define EASRC_CCE1_COEF_WS BIT(EASRC_CCE1_COEF_WS_SHIFT)
134#define EASRC_CCE1_COEF_MEM_RST_SHIFT 24
135#define EASRC_CCE1_COEF_MEM_RST_MASK BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
136#define EASRC_CCE1_COEF_MEM_RST BIT(EASRC_CCE1_COEF_MEM_RST_SHIFT)
137#define EASRC_CCE1_PF_EXP_SHIFT 16
138#define EASRC_CCE1_PF_EXP_WIDTH 8
139#define EASRC_CCE1_PF_EXP_MASK ((BIT(EASRC_CCE1_PF_EXP_WIDTH) - 1) \
140 << EASRC_CCE1_PF_EXP_SHIFT)
141#define EASRC_CCE1_PF_EXP(v) (((v) << EASRC_CCE1_PF_EXP_SHIFT) \
142 & EASRC_CCE1_PF_EXP_MASK)
143#define EASRC_CCE1_PF_ST1_WBFP_SHIFT 9
144#define EASRC_CCE1_PF_ST1_WBFP_MASK BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
145#define EASRC_CCE1_PF_ST1_WBFP BIT(EASRC_CCE1_PF_ST1_WBFP_SHIFT)
146#define EASRC_CCE1_PF_TSEN_SHIFT 8
147#define EASRC_CCE1_PF_TSEN_MASK BIT(EASRC_CCE1_PF_TSEN_SHIFT)
148#define EASRC_CCE1_PF_TSEN BIT(EASRC_CCE1_PF_TSEN_SHIFT)
149#define EASRC_CCE1_RS_BYPASS_SHIFT 7
150#define EASRC_CCE1_RS_BYPASS_MASK BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
151#define EASRC_CCE1_RS_BYPASS BIT(EASRC_CCE1_RS_BYPASS_SHIFT)
152#define EASRC_CCE1_PF_BYPASS_SHIFT 6
153#define EASRC_CCE1_PF_BYPASS_MASK BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
154#define EASRC_CCE1_PF_BYPASS BIT(EASRC_CCE1_PF_BYPASS_SHIFT)
155#define EASRC_CCE1_RS_STOP_SHIFT 5
156#define EASRC_CCE1_RS_STOP_MASK BIT(EASRC_CCE1_RS_STOP_SHIFT)
157#define EASRC_CCE1_RS_STOP BIT(EASRC_CCE1_RS_STOP_SHIFT)
158#define EASRC_CCE1_PF_STOP_SHIFT 4
159#define EASRC_CCE1_PF_STOP_MASK BIT(EASRC_CCE1_PF_STOP_SHIFT)
160#define EASRC_CCE1_PF_STOP BIT(EASRC_CCE1_PF_STOP_SHIFT)
161#define EASRC_CCE1_RS_INIT_SHIFT 2
162#define EASRC_CCE1_RS_INIT_WIDTH 2
163#define EASRC_CCE1_RS_INIT_MASK ((BIT(EASRC_CCE1_RS_INIT_WIDTH) - 1) \
164 << EASRC_CCE1_RS_INIT_SHIFT)
165#define EASRC_CCE1_RS_INIT(v) (((v) << EASRC_CCE1_RS_INIT_SHIFT) \
166 & EASRC_CCE1_RS_INIT_MASK)
167#define EASRC_CCE1_PF_INIT_SHIFT 0
168#define EASRC_CCE1_PF_INIT_WIDTH 2
169#define EASRC_CCE1_PF_INIT_MASK ((BIT(EASRC_CCE1_PF_INIT_WIDTH) - 1) \
170 << EASRC_CCE1_PF_INIT_SHIFT)
171#define EASRC_CCE1_PF_INIT(v) (((v) << EASRC_CCE1_PF_INIT_SHIFT) \
172 & EASRC_CCE1_PF_INIT_MASK)
173
174/* ASRC Context Control Extended 2 (CCE2) */
175#define EASRC_CCE2_ST2_TAPS_SHIFT 16
176#define EASRC_CCE2_ST2_TAPS_WIDTH 9
177#define EASRC_CCE2_ST2_TAPS_MASK ((BIT(EASRC_CCE2_ST2_TAPS_WIDTH) - 1) \
178 << EASRC_CCE2_ST2_TAPS_SHIFT)
179#define EASRC_CCE2_ST2_TAPS(v) (((v) << EASRC_CCE2_ST2_TAPS_SHIFT) \
180 & EASRC_CCE2_ST2_TAPS_MASK)
181#define EASRC_CCE2_ST1_TAPS_SHIFT 0
182#define EASRC_CCE2_ST1_TAPS_WIDTH 9
183#define EASRC_CCE2_ST1_TAPS_MASK ((BIT(EASRC_CCE2_ST1_TAPS_WIDTH) - 1) \
184 << EASRC_CCE2_ST1_TAPS_SHIFT)
185#define EASRC_CCE2_ST1_TAPS(v) (((v) << EASRC_CCE2_ST1_TAPS_SHIFT) \
186 & EASRC_CCE2_ST1_TAPS_MASK)
187
188/* ASRC Control Input Access (CIA) */
189#define EASRC_CIA_ITER_SHIFT 16
190#define EASRC_CIA_ITER_WIDTH 6
191#define EASRC_CIA_ITER_MASK ((BIT(EASRC_CIA_ITER_WIDTH) - 1) \
192 << EASRC_CIA_ITER_SHIFT)
193#define EASRC_CIA_ITER(v) (((v) << EASRC_CIA_ITER_SHIFT) \
194 & EASRC_CIA_ITER_MASK)
195#define EASRC_CIA_GRLEN_SHIFT 8
196#define EASRC_CIA_GRLEN_WIDTH 6
197#define EASRC_CIA_GRLEN_MASK ((BIT(EASRC_CIA_GRLEN_WIDTH) - 1) \
198 << EASRC_CIA_GRLEN_SHIFT)
199#define EASRC_CIA_GRLEN(v) (((v) << EASRC_CIA_GRLEN_SHIFT) \
200 & EASRC_CIA_GRLEN_MASK)
201#define EASRC_CIA_ACCLEN_SHIFT 0
202#define EASRC_CIA_ACCLEN_WIDTH 6
203#define EASRC_CIA_ACCLEN_MASK ((BIT(EASRC_CIA_ACCLEN_WIDTH) - 1) \
204 << EASRC_CIA_ACCLEN_SHIFT)
205#define EASRC_CIA_ACCLEN(v) (((v) << EASRC_CIA_ACCLEN_SHIFT) \
206 & EASRC_CIA_ACCLEN_MASK)
207
208/* ASRC Datapath Processor Control Slot0 Register0 (DPCS0R0) */
209#define EASRC_DPCS0R0_MAXCH_SHIFT 24
210#define EASRC_DPCS0R0_MAXCH_WIDTH 5
211#define EASRC_DPCS0R0_MAXCH_MASK ((BIT(EASRC_DPCS0R0_MAXCH_WIDTH) - 1) \
212 << EASRC_DPCS0R0_MAXCH_SHIFT)
213#define EASRC_DPCS0R0_MAXCH(v) (((v) << EASRC_DPCS0R0_MAXCH_SHIFT) \
214 & EASRC_DPCS0R0_MAXCH_MASK)
215#define EASRC_DPCS0R0_MINCH_SHIFT 16
216#define EASRC_DPCS0R0_MINCH_WIDTH 5
217#define EASRC_DPCS0R0_MINCH_MASK ((BIT(EASRC_DPCS0R0_MINCH_WIDTH) - 1) \
218 << EASRC_DPCS0R0_MINCH_SHIFT)
219#define EASRC_DPCS0R0_MINCH(v) (((v) << EASRC_DPCS0R0_MINCH_SHIFT) \
220 & EASRC_DPCS0R0_MINCH_MASK)
221#define EASRC_DPCS0R0_NUMCH_SHIFT 8
222#define EASRC_DPCS0R0_NUMCH_WIDTH 5
223#define EASRC_DPCS0R0_NUMCH_MASK ((BIT(EASRC_DPCS0R0_NUMCH_WIDTH) - 1) \
224 << EASRC_DPCS0R0_NUMCH_SHIFT)
225#define EASRC_DPCS0R0_NUMCH(v) (((v) << EASRC_DPCS0R0_NUMCH_SHIFT) \
226 & EASRC_DPCS0R0_NUMCH_MASK)
227#define EASRC_DPCS0R0_CTXNUM_SHIFT 1
228#define EASRC_DPCS0R0_CTXNUM_WIDTH 2
229#define EASRC_DPCS0R0_CTXNUM_MASK ((BIT(EASRC_DPCS0R0_CTXNUM_WIDTH) - 1) \
230 << EASRC_DPCS0R0_CTXNUM_SHIFT)
231#define EASRC_DPCS0R0_CTXNUM(v) (((v) << EASRC_DPCS0R0_CTXNUM_SHIFT) \
232 & EASRC_DPCS0R0_CTXNUM_MASK)
233#define EASRC_DPCS0R0_EN_SHIFT 0
234#define EASRC_DPCS0R0_EN_MASK BIT(EASRC_DPCS0R0_EN_SHIFT)
235#define EASRC_DPCS0R0_EN BIT(EASRC_DPCS0R0_EN_SHIFT)
236
237/* ASRC Datapath Processor Control Slot0 Register1 (DPCS0R1) */
238#define EASRC_DPCS0R1_ST1_EXP_SHIFT 0
239#define EASRC_DPCS0R1_ST1_EXP_WIDTH 13
240#define EASRC_DPCS0R1_ST1_EXP_MASK ((BIT(EASRC_DPCS0R1_ST1_EXP_WIDTH) - 1) \
241 << EASRC_DPCS0R1_ST1_EXP_SHIFT)
242#define EASRC_DPCS0R1_ST1_EXP(v) (((v) << EASRC_DPCS0R1_ST1_EXP_SHIFT) \
243 & EASRC_DPCS0R1_ST1_EXP_MASK)
244
245/* ASRC Datapath Processor Control Slot0 Register2 (DPCS0R2) */
246#define EASRC_DPCS0R2_ST1_MA_SHIFT 16
247#define EASRC_DPCS0R2_ST1_MA_WIDTH 13
248#define EASRC_DPCS0R2_ST1_MA_MASK ((BIT(EASRC_DPCS0R2_ST1_MA_WIDTH) - 1) \
249 << EASRC_DPCS0R2_ST1_MA_SHIFT)
250#define EASRC_DPCS0R2_ST1_MA(v) (((v) << EASRC_DPCS0R2_ST1_MA_SHIFT) \
251 & EASRC_DPCS0R2_ST1_MA_MASK)
252#define EASRC_DPCS0R2_ST1_SA_SHIFT 0
253#define EASRC_DPCS0R2_ST1_SA_WIDTH 13
254#define EASRC_DPCS0R2_ST1_SA_MASK ((BIT(EASRC_DPCS0R2_ST1_SA_WIDTH) - 1) \
255 << EASRC_DPCS0R2_ST1_SA_SHIFT)
256#define EASRC_DPCS0R2_ST1_SA(v) (((v) << EASRC_DPCS0R2_ST1_SA_SHIFT) \
257 & EASRC_DPCS0R2_ST1_SA_MASK)
258
259/* ASRC Datapath Processor Control Slot0 Register3 (DPCS0R3) */
260#define EASRC_DPCS0R3_ST2_MA_SHIFT 16
261#define EASRC_DPCS0R3_ST2_MA_WIDTH 13
262#define EASRC_DPCS0R3_ST2_MA_MASK ((BIT(EASRC_DPCS0R3_ST2_MA_WIDTH) - 1) \
263 << EASRC_DPCS0R3_ST2_MA_SHIFT)
264#define EASRC_DPCS0R3_ST2_MA(v) (((v) << EASRC_DPCS0R3_ST2_MA_SHIFT) \
265 & EASRC_DPCS0R3_ST2_MA_MASK)
266#define EASRC_DPCS0R3_ST2_SA_SHIFT 0
267#define EASRC_DPCS0R3_ST2_SA_WIDTH 13
268#define EASRC_DPCS0R3_ST2_SA_MASK ((BIT(EASRC_DPCS0R3_ST2_SA_WIDTH) - 1) \
269 << EASRC_DPCS0R3_ST2_SA_SHIFT)
270#define EASRC_DPCS0R3_ST2_SA(v) (((v) << EASRC_DPCS0R3_ST2_SA_SHIFT) \
271 & EASRC_DPCS0R3_ST2_SA_MASK)
272
273/* ASRC Context Output Control (COC) */
274#define EASRC_COC_FWMDE_SHIFT 28
275#define EASRC_COC_FWMDE_MASK BIT(EASRC_COC_FWMDE_SHIFT)
276#define EASRC_COC_FWMDE BIT(EASRC_COC_FWMDE_SHIFT)
277#define EASRC_COC_FIFO_WTMK_SHIFT 16
278#define EASRC_COC_FIFO_WTMK_WIDTH 7
279#define EASRC_COC_FIFO_WTMK_MASK ((BIT(EASRC_COC_FIFO_WTMK_WIDTH) - 1) \
280 << EASRC_COC_FIFO_WTMK_SHIFT)
281#define EASRC_COC_FIFO_WTMK(v) (((v) << EASRC_COC_FIFO_WTMK_SHIFT) \
282 & EASRC_COC_FIFO_WTMK_MASK)
283#define EASRC_COC_SAMPLE_POS_SHIFT 11
284#define EASRC_COC_SAMPLE_POS_WIDTH 5
285#define EASRC_COC_SAMPLE_POS_MASK ((BIT(EASRC_COC_SAMPLE_POS_WIDTH) - 1) \
286 << EASRC_COC_SAMPLE_POS_SHIFT)
287#define EASRC_COC_SAMPLE_POS(v) (((v) << EASRC_COC_SAMPLE_POS_SHIFT) \
288 & EASRC_COC_SAMPLE_POS_MASK)
289#define EASRC_COC_ENDIANNESS_SHIFT 10
290#define EASRC_COC_ENDIANNESS_MASK BIT(EASRC_COC_ENDIANNESS_SHIFT)
291#define EASRC_COC_ENDIANNESS BIT(EASRC_COC_ENDIANNESS_SHIFT)
292#define EASRC_COC_BPS_SHIFT 8
293#define EASRC_COC_BPS_WIDTH 2
294#define EASRC_COC_BPS_MASK ((BIT(EASRC_COC_BPS_WIDTH) - 1) \
295 << EASRC_COC_BPS_SHIFT)
296#define EASRC_COC_BPS(v) (((v) << EASRC_COC_BPS_SHIFT) \
297 & EASRC_COC_BPS_MASK)
298#define EASRC_COC_FMT_SHIFT 7
299#define EASRC_COC_FMT_MASK BIT(EASRC_COC_FMT_SHIFT)
300#define EASRC_COC_FMT BIT(EASRC_COC_FMT_SHIFT)
301#define EASRC_COC_OUTSIGN_SHIFT 6
302#define EASRC_COC_OUTSIGN_MASK BIT(EASRC_COC_OUTSIGN_SHIFT)
303#define EASRC_COC_OUTSIGN_OUT BIT(EASRC_COC_OUTSIGN_SHIFT)
304#define EASRC_COC_IEC_VDATA_SHIFT 2
305#define EASRC_COC_IEC_VDATA_MASK BIT(EASRC_COC_IEC_VDATA_SHIFT)
306#define EASRC_COC_IEC_VDATA BIT(EASRC_COC_IEC_VDATA_SHIFT)
307#define EASRC_COC_IEC_EN_SHIFT 1
308#define EASRC_COC_IEC_EN_MASK BIT(EASRC_COC_IEC_EN_SHIFT)
309#define EASRC_COC_IEC_EN BIT(EASRC_COC_IEC_EN_SHIFT)
310#define EASRC_COC_DITHER_EN_SHIFT 0
311#define EASRC_COC_DITHER_EN_MASK BIT(EASRC_COC_DITHER_EN_SHIFT)
312#define EASRC_COC_DITHER_EN BIT(EASRC_COC_DITHER_EN_SHIFT)
313
314/* ASRC Control Output Access (COA) */
315#define EASRC_COA_ITER_SHIFT 16
316#define EASRC_COA_ITER_WIDTH 6
317#define EASRC_COA_ITER_MASK ((BIT(EASRC_COA_ITER_WIDTH) - 1) \
318 << EASRC_COA_ITER_SHIFT)
319#define EASRC_COA_ITER(v) (((v) << EASRC_COA_ITER_SHIFT) \
320 & EASRC_COA_ITER_MASK)
321#define EASRC_COA_GRLEN_SHIFT 8
322#define EASRC_COA_GRLEN_WIDTH 6
323#define EASRC_COA_GRLEN_MASK ((BIT(EASRC_COA_GRLEN_WIDTH) - 1) \
324 << EASRC_COA_GRLEN_SHIFT)
325#define EASRC_COA_GRLEN(v) (((v) << EASRC_COA_GRLEN_SHIFT) \
326 & EASRC_COA_GRLEN_MASK)
327#define EASRC_COA_ACCLEN_SHIFT 0
328#define EASRC_COA_ACCLEN_WIDTH 6
329#define EASRC_COA_ACCLEN_MASK ((BIT(EASRC_COA_ACCLEN_WIDTH) - 1) \
330 << EASRC_COA_ACCLEN_SHIFT)
331#define EASRC_COA_ACCLEN(v) (((v) << EASRC_COA_ACCLEN_SHIFT) \
332 & EASRC_COA_ACCLEN_MASK)
333
334/* ASRC Sample FIFO Status (SFS) */
335#define EASRC_SFS_IWTMK_SHIFT 23
336#define EASRC_SFS_IWTMK_MASK BIT(EASRC_SFS_IWTMK_SHIFT)
337#define EASRC_SFS_IWTMK BIT(EASRC_SFS_IWTMK_SHIFT)
338#define EASRC_SFS_NSGI_SHIFT 16
339#define EASRC_SFS_NSGI_WIDTH 7
340#define EASRC_SFS_NSGI_MASK ((BIT(EASRC_SFS_NSGI_WIDTH) - 1) \
341 << EASRC_SFS_NSGI_SHIFT)
342#define EASRC_SFS_NSGI(v) (((v) << EASRC_SFS_NSGI_SHIFT) \
343 & EASRC_SFS_NSGI_MASK)
344#define EASRC_SFS_OWTMK_SHIFT 7
345#define EASRC_SFS_OWTMK_MASK BIT(EASRC_SFS_OWTMK_SHIFT)
346#define EASRC_SFS_OWTMK BIT(EASRC_SFS_OWTMK_SHIFT)
347#define EASRC_SFS_NSGO_SHIFT 0
348#define EASRC_SFS_NSGO_WIDTH 7
349#define EASRC_SFS_NSGO_MASK ((BIT(EASRC_SFS_NSGO_WIDTH) - 1) \
350 << EASRC_SFS_NSGO_SHIFT)
351#define EASRC_SFS_NSGO(v) (((v) << EASRC_SFS_NSGO_SHIFT) \
352 & EASRC_SFS_NSGO_MASK)
353
354/* ASRC Resampling Ratio Low (RRL) */
355#define EASRC_RRL_RS_RL_SHIFT 0
356#define EASRC_RRL_RS_RL_WIDTH 32
357#define EASRC_RRL_RS_RL(v) ((v) << EASRC_RRL_RS_RL_SHIFT)
358
359/* ASRC Resampling Ratio High (RRH) */
360#define EASRC_RRH_RS_VLD_SHIFT 31
361#define EASRC_RRH_RS_VLD_MASK BIT(EASRC_RRH_RS_VLD_SHIFT)
362#define EASRC_RRH_RS_VLD BIT(EASRC_RRH_RS_VLD_SHIFT)
363#define EASRC_RRH_RS_RH_SHIFT 0
364#define EASRC_RRH_RS_RH_WIDTH 12
365#define EASRC_RRH_RS_RH_MASK ((BIT(EASRC_RRH_RS_RH_WIDTH) - 1) \
366 << EASRC_RRH_RS_RH_SHIFT)
367#define EASRC_RRH_RS_RH(v) (((v) << EASRC_RRH_RS_RH_SHIFT) \
368 & EASRC_RRH_RS_RH_MASK)
369
370/* ASRC Resampling Ratio Update Control (RSUC) */
371#define EASRC_RSUC_RS_RM_SHIFT 0
372#define EASRC_RSUC_RS_RM_WIDTH 32
373#define EASRC_RSUC_RS_RM(v) ((v) << EASRC_RSUC_RS_RM_SHIFT)
374
375/* ASRC Resampling Ratio Update Rate (RRUR) */
376#define EASRC_RRUR_RRR_SHIFT 0
377#define EASRC_RRUR_RRR_WIDTH 31
378#define EASRC_RRUR_RRR_MASK ((BIT(EASRC_RRUR_RRR_WIDTH) - 1) \
379 << EASRC_RRUR_RRR_SHIFT)
380#define EASRC_RRUR_RRR(v) (((v) << EASRC_RRUR_RRR_SHIFT) \
381 & EASRC_RRUR_RRR_MASK)
382
383/* ASRC Resampling Center Tap Coefficient Low (RCTCL) */
384#define EASRC_RCTCL_RS_CL_SHIFT 0
385#define EASRC_RCTCL_RS_CL_WIDTH 32
386#define EASRC_RCTCL_RS_CL(v) ((v) << EASRC_RCTCL_RS_CL_SHIFT)
387
388/* ASRC Resampling Center Tap Coefficient High (RCTCH) */
389#define EASRC_RCTCH_RS_CH_SHIFT 0
390#define EASRC_RCTCH_RS_CH_WIDTH 32
391#define EASRC_RCTCH_RS_CH(v) ((v) << EASRC_RCTCH_RS_CH_SHIFT)
392
393/* ASRC Prefilter Coefficient FIFO (PCF) */
394#define EASRC_PCF_CD_SHIFT 0
395#define EASRC_PCF_CD_WIDTH 32
396#define EASRC_PCF_CD(v) ((v) << EASRC_PCF_CD_SHIFT)
397
398/* ASRC Context Resampling Coefficient Memory (CRCM) */
399#define EASRC_CRCM_RS_CWD_SHIFT 0
400#define EASRC_CRCM_RS_CWD_WIDTH 32
401#define EASRC_CRCM_RS_CWD(v) ((v) << EASRC_CRCM_RS_CWD_SHIFT)
402
403/* ASRC Context Resampling Coefficient Control (CRCC) */
404#define EASRC_CRCC_RS_CA_SHIFT 16
405#define EASRC_CRCC_RS_CA_WIDTH 11
406#define EASRC_CRCC_RS_CA_MASK ((BIT(EASRC_CRCC_RS_CA_WIDTH) - 1) \
407 << EASRC_CRCC_RS_CA_SHIFT)
408#define EASRC_CRCC_RS_CA(v) (((v) << EASRC_CRCC_RS_CA_SHIFT) \
409 & EASRC_CRCC_RS_CA_MASK)
410#define EASRC_CRCC_RS_TAPS_SHIFT 1
411#define EASRC_CRCC_RS_TAPS_WIDTH 2
412#define EASRC_CRCC_RS_TAPS_MASK ((BIT(EASRC_CRCC_RS_TAPS_WIDTH) - 1) \
413 << EASRC_CRCC_RS_TAPS_SHIFT)
414#define EASRC_CRCC_RS_TAPS(v) (((v) << EASRC_CRCC_RS_TAPS_SHIFT) \
415 & EASRC_CRCC_RS_TAPS_MASK)
416#define EASRC_CRCC_RS_CPR_SHIFT 0
417#define EASRC_CRCC_RS_CPR_MASK BIT(EASRC_CRCC_RS_CPR_SHIFT)
418#define EASRC_CRCC_RS_CPR BIT(EASRC_CRCC_RS_CPR_SHIFT)
419
420/* ASRC Interrupt_Control (IC) */
421#define EASRC_IRQC_RSDM_SHIFT 8
422#define EASRC_IRQC_RSDM_WIDTH 4
423#define EASRC_IRQC_RSDM_MASK ((BIT(EASRC_IRQC_RSDM_WIDTH) - 1) \
424 << EASRC_IRQC_RSDM_SHIFT)
425#define EASRC_IRQC_RSDM(v) (((v) << EASRC_IRQC_RSDM_SHIFT) \
426 & EASRC_IRQC_RSDM_MASK)
427#define EASRC_IRQC_OERM_SHIFT 4
428#define EASRC_IRQC_OERM_WIDTH 4
429#define EASRC_IRQC_OERM_MASK ((BIT(EASRC_IRQC_OERM_WIDTH) - 1) \
430 << EASRC_IRQC_OERM_SHIFT)
431#define EASRC_IRQC_OERM(v) (((v) << EASRC_IRQC_OERM_SHIFT) \
432 & EASRC_IEQC_OERM_MASK)
433#define EASRC_IRQC_IOM_SHIFT 0
434#define EASRC_IRQC_IOM_WIDTH 4
435#define EASRC_IRQC_IOM_MASK ((BIT(EASRC_IRQC_IOM_WIDTH) - 1) \
436 << EASRC_IRQC_IOM_SHIFT)
437#define EASRC_IRQC_IOM(v) (((v) << EASRC_IRQC_IOM_SHIFT) \
438 & EASRC_IRQC_IOM_MASK)
439
440/* ASRC Interrupt Status Flags (ISF) */
441#define EASRC_IRQF_RSD_SHIFT 8
442#define EASRC_IRQF_RSD_WIDTH 4
443#define EASRC_IRQF_RSD_MASK ((BIT(EASRC_IRQF_RSD_WIDTH) - 1) \
444 << EASRC_IRQF_RSD_SHIFT)
445#define EASRC_IRQF_RSD(v) (((v) << EASRC_IRQF_RSD_SHIFT) \
446 & EASRC_IRQF_RSD_MASK)
447#define EASRC_IRQF_OER_SHIFT 4
448#define EASRC_IRQF_OER_WIDTH 4
449#define EASRC_IRQF_OER_MASK ((BIT(EASRC_IRQF_OER_WIDTH) - 1) \
450 << EASRC_IRQF_OER_SHIFT)
451#define EASRC_IRQF_OER(v) (((v) << EASRC_IRQF_OER_SHIFT) \
452 & EASRC_IRQF_OER_MASK)
453#define EASRC_IRQF_IFO_SHIFT 0
454#define EASRC_IRQF_IFO_WIDTH 4
455#define EASRC_IRQF_IFO_MASK ((BIT(EASRC_IRQF_IFO_WIDTH) - 1) \
456 << EASRC_IRQF_IFO_SHIFT)
457#define EASRC_IRQF_IFO(v) (((v) << EASRC_IRQF_IFO_SHIFT) \
458 & EASRC_IRQF_IFO_MASK)
459
460/* ASRC Context Channel STAT */
461#define EASRC_CSx_CSx_SHIFT 0
462#define EASRC_CSx_CSx_WIDTH 32
463#define EASRC_CSx_CSx(v) ((v) << EASRC_CSx_CSx_SHIFT)
464
465/* ASRC Debug Control Register */
466#define EASRC_DBGC_DMS_SHIFT 0
467#define EASRC_DBGC_DMS_WIDTH 6
468#define EASRC_DBGC_DMS_MASK ((BIT(EASRC_DBGC_DMS_WIDTH) - 1) \
469 << EASRC_DBGC_DMS_SHIFT)
470#define EASRC_DBGC_DMS(v) (((v) << EASRC_DBGC_DMS_SHIFT) \
471 & EASRC_DBGC_DMS_MASK)
472
473/* ASRC Debug Status Register */
474#define EASRC_DBGS_DS_SHIFT 0
475#define EASRC_DBGS_DS_WIDTH 32
476#define EASRC_DBGS_DS(v) ((v) << EASRC_DBGS_DS_SHIFT)
477
478/* General Constants */
479#define EASRC_CTX_MAX_NUM 4
480#define EASRC_RS_COEFF_MEM 0
481#define EASRC_PF_COEFF_MEM 1
482
483/* Prefilter constants */
484#define EASRC_PF_ST1_ONLY 0
485#define EASRC_PF_TWO_STAGE_MODE 1
486#define EASRC_PF_ST1_COEFF_WR 0
487#define EASRC_PF_ST2_COEFF_WR 1
488#define EASRC_MAX_PF_TAPS 384
489
490/* Resampling constants */
491#define EASRC_RS_32_TAPS 0
492#define EASRC_RS_64_TAPS 1
493#define EASRC_RS_128_TAPS 2
494
495/* Initialization mode */
496#define EASRC_INIT_MODE_SW_CONTROL 0
497#define EASRC_INIT_MODE_REPLICATE 1
498#define EASRC_INIT_MODE_ZERO_FILL 2
499
500/* FIFO watermarks */
501#define FSL_EASRC_INPUTFIFO_WML 0x4
502#define FSL_EASRC_OUTPUTFIFO_WML 0x1
503
504#define EASRC_INPUTFIFO_THRESHOLD_MIN 0
505#define EASRC_INPUTFIFO_THRESHOLD_MAX 127
506#define EASRC_OUTPUTFIFO_THRESHOLD_MIN 0
507#define EASRC_OUTPUTFIFO_THRESHOLD_MAX 63
508
509#define EASRC_DMA_BUFFER_SIZE (1024 * 48 * 9)
510#define EASRC_MAX_BUFFER_SIZE (1024 * 48)
511
512#define FIRMWARE_MAGIC 0xDEAD
513#define FIRMWARE_VERSION 1
514
515#define PREFILTER_MEM_LEN 0x1800
516
517enum easrc_word_width {
518 EASRC_WIDTH_16_BIT = 0,
519 EASRC_WIDTH_20_BIT = 1,
520 EASRC_WIDTH_24_BIT = 2,
521 EASRC_WIDTH_32_BIT = 3,
522};
523
524struct __attribute__((__packed__)) asrc_firmware_hdr {
525 u32 magic;
526 u32 interp_scen;
527 u32 prefil_scen;
528 u32 firmware_version;
529};
530
531struct __attribute__((__packed__)) interp_params {
532 u32 magic;
533 u32 num_taps;
534 u32 num_phases;
535 u64 center_tap;
536 u64 coeff[8192];
537};
538
539struct __attribute__((__packed__)) prefil_params {
540 u32 magic;
541 u32 insr;
542 u32 outsr;
543 u32 st1_taps;
544 u32 st2_taps;
545 u32 st1_exp;
546 u64 coeff[256];
547};
548
549struct dma_block {
550 void *dma_vaddr;
551 unsigned int length;
552 unsigned int max_buf_size;
553};
554
555struct fsl_easrc_data_fmt {
556 unsigned int width : 2;
557 unsigned int endianness : 1;
558 unsigned int unsign : 1;
559 unsigned int floating_point : 1;
560 unsigned int iec958: 1;
561 unsigned int sample_pos: 5;
562 unsigned int addexp;
563};
564
565struct fsl_easrc_io_params {
566 struct fsl_easrc_data_fmt fmt;
567 unsigned int group_len;
568 unsigned int iterations;
569 unsigned int access_len;
570 unsigned int fifo_wtmk;
571 unsigned int sample_rate;
572 snd_pcm_format_t sample_format;
573 unsigned int norm_rate;
574};
575
576struct fsl_easrc_slot {
577 bool busy;
578 int ctx_index;
579 int slot_index;
580 int num_channel; /* maximum is 8 */
581 int min_channel;
582 int max_channel;
583 int pf_mem_used;
584};
585
586/**
587 * fsl_easrc_ctx_priv: EASRC context private data
588 *
589 * @in_params: input parameter
590 * @out_params: output parameter
591 * @st1_num_taps: tap number of stage 1
592 * @st2_num_taps: tap number of stage 2
593 * @st1_num_exp: exponent number of stage 1
594 * @pf_init_mode: prefilter init mode
595 * @rs_init_mode: resample filter init mode
596 * @ctx_streams: stream flag of ctx
597 * @rs_ratio: resampler ratio
598 * @st1_coeff: pointer of stage 1 coeff
599 * @st2_coeff: pointer of stage 2 coeff
600 * @in_filled_sample: input filled sample
601 * @out_missed_sample: sample missed in output
602 * @st1_addexp: exponent added for stage1
603 * @st2_addexp: exponent added for stage2
604 */
605struct fsl_easrc_ctx_priv {
606 struct fsl_easrc_io_params in_params;
607 struct fsl_easrc_io_params out_params;
608 unsigned int st1_num_taps;
609 unsigned int st2_num_taps;
610 unsigned int st1_num_exp;
611 unsigned int pf_init_mode;
612 unsigned int rs_init_mode;
613 unsigned int ctx_streams;
614 u64 rs_ratio;
615 u64 *st1_coeff;
616 u64 *st2_coeff;
617 int in_filled_sample;
618 int out_missed_sample;
619 int st1_addexp;
620 int st2_addexp;
621};
622
623/**
624 * fsl_easrc_priv: EASRC private data
625 *
626 * @slot: slot setting
627 * @firmware_hdr: the header of firmware
628 * @interp: pointer to interpolation filter coeff
629 * @prefil: pointer to prefilter coeff
630 * @fw: firmware of coeff table
631 * @fw_name: firmware name
632 * @rs_num_taps: resample filter taps, 32, 64, or 128
633 * @bps_iec958: bits per sample of iec958
634 * @rs_coeff: resampler coefficient
635 * @const_coeff: one tap prefilter coefficient
636 * @firmware_loaded: firmware is loaded
637 */
638struct fsl_easrc_priv {
639 struct fsl_easrc_slot slot[EASRC_CTX_MAX_NUM][2];
640 struct asrc_firmware_hdr *firmware_hdr;
641 struct interp_params *interp;
642 struct prefil_params *prefil;
643 const struct firmware *fw;
644 const char *fw_name;
645 unsigned int rs_num_taps;
646 unsigned int bps_iec958[EASRC_CTX_MAX_NUM];
647 u64 *rs_coeff;
648 u64 const_coeff;
649 int firmware_loaded;
650};
651#endif /* _FSL_EASRC_H */
652

source code of linux/sound/soc/fsl/fsl_easrc.h