1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
2 | /* |
3 | * PDM Microphone Interface for the NXP i.MX SoC |
4 | * Copyright 2018 NXP |
5 | */ |
6 | |
7 | #ifndef _FSL_MICFIL_H |
8 | #define _FSL_MICFIL_H |
9 | |
10 | /* MICFIL Register Map */ |
11 | #define REG_MICFIL_CTRL1 0x00 |
12 | #define REG_MICFIL_CTRL2 0x04 |
13 | #define REG_MICFIL_STAT 0x08 |
14 | #define REG_MICFIL_FIFO_CTRL 0x10 |
15 | #define REG_MICFIL_FIFO_STAT 0x14 |
16 | #define REG_MICFIL_DATACH0 0x24 |
17 | #define REG_MICFIL_DATACH1 0x28 |
18 | #define REG_MICFIL_DATACH2 0x2C |
19 | #define REG_MICFIL_DATACH3 0x30 |
20 | #define REG_MICFIL_DATACH4 0x34 |
21 | #define REG_MICFIL_DATACH5 0x38 |
22 | #define REG_MICFIL_DATACH6 0x3C |
23 | #define REG_MICFIL_DATACH7 0x40 |
24 | #define REG_MICFIL_DC_CTRL 0x64 |
25 | #define REG_MICFIL_OUT_CTRL 0x74 |
26 | #define REG_MICFIL_OUT_STAT 0x7C |
27 | #define REG_MICFIL_FSYNC_CTRL 0x80 |
28 | #define REG_MICFIL_VERID 0x84 |
29 | #define REG_MICFIL_PARAM 0x88 |
30 | #define REG_MICFIL_VAD0_CTRL1 0x90 |
31 | #define REG_MICFIL_VAD0_CTRL2 0x94 |
32 | #define REG_MICFIL_VAD0_STAT 0x98 |
33 | #define REG_MICFIL_VAD0_SCONFIG 0x9C |
34 | #define REG_MICFIL_VAD0_NCONFIG 0xA0 |
35 | #define REG_MICFIL_VAD0_NDATA 0xA4 |
36 | #define REG_MICFIL_VAD0_ZCD 0xA8 |
37 | |
38 | /* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */ |
39 | #define MICFIL_CTRL1_MDIS BIT(31) |
40 | #define MICFIL_CTRL1_DOZEN BIT(30) |
41 | #define MICFIL_CTRL1_PDMIEN BIT(29) |
42 | #define MICFIL_CTRL1_DBG BIT(28) |
43 | #define MICFIL_CTRL1_SRES BIT(27) |
44 | #define MICFIL_CTRL1_DBGE BIT(26) |
45 | #define MICFIL_CTRL1_DECFILS BIT(20) |
46 | #define MICFIL_CTRL1_FSYNCEN BIT(16) |
47 | |
48 | #define MICFIL_CTRL1_DISEL_DISABLE 0 |
49 | #define MICFIL_CTRL1_DISEL_DMA 1 |
50 | #define MICFIL_CTRL1_DISEL_IRQ 2 |
51 | #define MICFIL_CTRL1_DISEL GENMASK(25, 24) |
52 | #define MICFIL_CTRL1_ERREN BIT(23) |
53 | #define MICFIL_CTRL1_CHEN(ch) BIT(ch) |
54 | |
55 | /* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */ |
56 | #define MICFIL_CTRL2_QSEL_SHIFT 25 |
57 | #define MICFIL_CTRL2_QSEL GENMASK(27, 25) |
58 | #define MICFIL_QSEL_MEDIUM_QUALITY 0 |
59 | #define MICFIL_QSEL_HIGH_QUALITY 1 |
60 | #define MICFIL_QSEL_LOW_QUALITY 7 |
61 | #define MICFIL_QSEL_VLOW0_QUALITY 6 |
62 | #define MICFIL_QSEL_VLOW1_QUALITY 5 |
63 | #define MICFIL_QSEL_VLOW2_QUALITY 4 |
64 | |
65 | #define MICFIL_CTRL2_CICOSR GENMASK(19, 16) |
66 | #define MICFIL_CTRL2_CLKDIV GENMASK(7, 0) |
67 | |
68 | /* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */ |
69 | #define MICFIL_STAT_BSY_FIL BIT(31) |
70 | #define MICFIL_STAT_FIR_RDY BIT(30) |
71 | #define MICFIL_STAT_LOWFREQF BIT(29) |
72 | #define MICFIL_STAT_CHXF(ch) BIT(ch) |
73 | |
74 | /* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */ |
75 | #define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0) |
76 | |
77 | /* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */ |
78 | #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch) |
79 | #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) |
80 | |
81 | /* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */ |
82 | #define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0) |
83 | #define MICFIL_DC_CHX_SHIFT(ch) ((ch) << 1) |
84 | #define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) << 1)) |
85 | #define MICFIL_DC_CUTOFF_21HZ 0 |
86 | #define MICFIL_DC_CUTOFF_83HZ 1 |
87 | #define MICFIL_DC_CUTOFF_152Hz 2 |
88 | #define MICFIL_DC_BYPASS 3 |
89 | |
90 | /* MICFIL VERID Register -- REG_MICFIL_VERID */ |
91 | #define MICFIL_VERID_MAJOR_SHIFT 24 |
92 | #define MICFIL_VERID_MAJOR_MASK GENMASK(31, 24) |
93 | #define MICFIL_VERID_MINOR_SHIFT 16 |
94 | #define MICFIL_VERID_MINOR_MASK GENMASK(23, 16) |
95 | #define MICFIL_VERID_FEATURE_SHIFT 0 |
96 | #define MICFIL_VERID_FEATURE_MASK GENMASK(15, 0) |
97 | |
98 | /* MICFIL PARAM Register -- REG_MICFIL_PARAM */ |
99 | #define MICFIL_PARAM_NUM_HWVAD_SHIFT 24 |
100 | #define MICFIL_PARAM_NUM_HWVAD_MASK GENMASK(27, 24) |
101 | #define MICFIL_PARAM_HWVAD_ZCD BIT(19) |
102 | #define MICFIL_PARAM_HWVAD_ENERGY_MODE BIT(17) |
103 | #define MICFIL_PARAM_HWVAD BIT(16) |
104 | #define MICFIL_PARAM_DC_OUT_BYPASS BIT(11) |
105 | #define MICFIL_PARAM_DC_IN_BYPASS BIT(10) |
106 | #define MICFIL_PARAM_LOW_POWER BIT(9) |
107 | #define MICFIL_PARAM_FIL_OUT_WIDTH BIT(8) |
108 | #define MICFIL_PARAM_FIFO_PTRWID_SHIFT 4 |
109 | #define MICFIL_PARAM_FIFO_PTRWID_MASK GENMASK(7, 4) |
110 | #define MICFIL_PARAM_NPAIR_SHIFT 0 |
111 | #define MICFIL_PARAM_NPAIR_MASK GENMASK(3, 0) |
112 | |
113 | /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ |
114 | #define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24) |
115 | #define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16) |
116 | #define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8) |
117 | #define MICFIL_VAD0_CTRL1_ST10 BIT(4) |
118 | #define MICFIL_VAD0_CTRL1_ERIE BIT(3) |
119 | #define MICFIL_VAD0_CTRL1_IE BIT(2) |
120 | #define MICFIL_VAD0_CTRL1_RST BIT(1) |
121 | #define MICFIL_VAD0_CTRL1_EN BIT(0) |
122 | |
123 | /* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/ |
124 | #define MICFIL_VAD0_CTRL2_FRENDIS BIT(31) |
125 | #define MICFIL_VAD0_CTRL2_PREFEN BIT(30) |
126 | #define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28) |
127 | #define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16) |
128 | #define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8) |
129 | #define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0) |
130 | |
131 | /* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */ |
132 | #define MICFIL_VAD0_SCONFIG_SFILEN BIT(31) |
133 | #define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30) |
134 | #define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0) |
135 | |
136 | /* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */ |
137 | #define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31) |
138 | #define MICFIL_VAD0_NCONFIG_NMINEN BIT(30) |
139 | #define MICFIL_VAD0_NCONFIG_NDECEN BIT(29) |
140 | #define MICFIL_VAD0_NCONFIG_NOREN BIT(28) |
141 | #define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8) |
142 | #define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0) |
143 | |
144 | /* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */ |
145 | #define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16) |
146 | #define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8) |
147 | #define MICFIL_VAD0_ZCD_ZCDAND BIT(4) |
148 | #define MICFIL_VAD0_ZCD_ZCDAUT BIT(2) |
149 | #define MICFIL_VAD0_ZCD_ZCDEN BIT(0) |
150 | |
151 | /* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */ |
152 | #define MICFIL_VAD0_STAT_INITF BIT(31) |
153 | #define MICFIL_VAD0_STAT_INSATF BIT(16) |
154 | #define MICFIL_VAD0_STAT_EF BIT(15) |
155 | #define MICFIL_VAD0_STAT_IF BIT(0) |
156 | |
157 | /* MICFIL Output Control Register */ |
158 | #define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v)) |
159 | |
160 | /* Constants */ |
161 | #define MICFIL_OUTPUT_CHANNELS 8 |
162 | #define MICFIL_FIFO_NUM 8 |
163 | |
164 | #define FIFO_PTRWID 3 |
165 | #define FIFO_LEN BIT(FIFO_PTRWID) |
166 | |
167 | #define MICFIL_IRQ_LINES 4 |
168 | #define MICFIL_MAX_RETRY 25 |
169 | #define MICFIL_SLEEP_MIN 90000 /* in us */ |
170 | #define MICFIL_SLEEP_MAX 100000 /* in us */ |
171 | #define MICFIL_DMA_MAXBURST_RX 6 |
172 | |
173 | /* HWVAD Constants */ |
174 | #define MICFIL_HWVAD_ENVELOPE_MODE 0 |
175 | #define MICFIL_HWVAD_ENERGY_MODE 1 |
176 | |
177 | /** |
178 | * struct fsl_micfil_verid - version id data |
179 | * @version: version number |
180 | * @feature: feature specification number |
181 | */ |
182 | struct fsl_micfil_verid { |
183 | u32 version; |
184 | u32 feature; |
185 | }; |
186 | |
187 | /** |
188 | * struct fsl_micfil_param - parameter data |
189 | * @hwvad_num: the number of HWVADs |
190 | * @hwvad_zcd: HWVAD zero-cross detector is active |
191 | * @hwvad_energy_mode: HWVAD energy mode is active |
192 | * @hwvad: HWVAD is active |
193 | * @dc_out_bypass: points out if the output DC remover is disabled |
194 | * @dc_in_bypass: points out if the input DC remover is disabled |
195 | * @low_power: low power decimation filter |
196 | * @fil_out_width: filter output width |
197 | * @fifo_ptrwid: FIFO pointer width |
198 | * @npair: number of microphone pairs |
199 | */ |
200 | struct fsl_micfil_param { |
201 | u32 hwvad_num; |
202 | bool hwvad_zcd; |
203 | bool hwvad_energy_mode; |
204 | bool hwvad; |
205 | bool dc_out_bypass; |
206 | bool dc_in_bypass; |
207 | bool low_power; |
208 | bool fil_out_width; |
209 | u32 fifo_ptrwid; |
210 | u32 npair; |
211 | }; |
212 | |
213 | #endif /* _FSL_MICFIL_H */ |
214 | |