1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright(c) 2021-2024 Intel Corporation. All rights reserved. |
4 | // |
5 | // Authors: Cezary Rojewski <cezary.rojewski@intel.com> |
6 | // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com> |
7 | // |
8 | |
9 | #include "avs.h" |
10 | |
11 | static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power) |
12 | { |
13 | core_mask &= AVS_MAIN_CORE_MASK; |
14 | |
15 | if (!core_mask) |
16 | return 0; |
17 | return avs_dsp_core_power(adev, core_mask, power); |
18 | } |
19 | |
20 | static int avs_tgl_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset) |
21 | { |
22 | core_mask &= AVS_MAIN_CORE_MASK; |
23 | |
24 | if (!core_mask) |
25 | return 0; |
26 | return avs_dsp_core_reset(adev, core_mask, reset); |
27 | } |
28 | |
29 | static int avs_tgl_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall) |
30 | { |
31 | core_mask &= AVS_MAIN_CORE_MASK; |
32 | |
33 | if (!core_mask) |
34 | return 0; |
35 | return avs_dsp_core_stall(adev, core_mask, stall); |
36 | } |
37 | |
38 | const struct avs_dsp_ops avs_tgl_dsp_ops = { |
39 | .power = avs_tgl_dsp_core_power, |
40 | .reset = avs_tgl_dsp_core_reset, |
41 | .stall = avs_tgl_dsp_core_stall, |
42 | .irq_handler = avs_irq_handler, |
43 | .irq_thread = avs_cnl_irq_thread, |
44 | .int_control = avs_dsp_interrupt_control, |
45 | .load_basefw = avs_icl_load_basefw, |
46 | .load_lib = avs_hda_load_library, |
47 | .transfer_mods = avs_hda_transfer_modules, |
48 | .log_buffer_offset = avs_icl_log_buffer_offset, |
49 | .log_buffer_status = avs_apl_log_buffer_status, |
50 | .coredump = avs_apl_coredump, |
51 | .d0ix_toggle = avs_icl_d0ix_toggle, |
52 | .set_d0ix = avs_icl_set_d0ix, |
53 | AVS_SET_ENABLE_LOGS_OP(icl) |
54 | }; |
55 | |