| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2018 BayLibre, SAS. |
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| 4 | * Author: Jerome Brunet <jbrunet@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef _MESON_AIU_H |
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| 8 | #define _MESON_AIU_H |
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| 9 | |
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| 10 | struct clk; |
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| 11 | struct clk_bulk_data; |
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| 12 | struct device; |
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| 13 | struct of_phandle_args; |
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| 14 | struct snd_soc_dai; |
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| 15 | struct snd_soc_dai_ops; |
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| 16 | |
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| 17 | enum aiu_clk_ids { |
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| 18 | PCLK = 0, |
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| 19 | AOCLK, |
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| 20 | MCLK, |
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| 21 | MIXER |
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| 22 | }; |
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| 23 | |
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| 24 | struct aiu_interface { |
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| 25 | struct clk_bulk_data *clks; |
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| 26 | unsigned int clk_num; |
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| 27 | int irq; |
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| 28 | }; |
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| 29 | |
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| 30 | struct aiu_platform_data { |
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| 31 | bool has_acodec; |
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| 32 | bool has_clk_ctrl_more_i2s_div; |
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| 33 | }; |
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| 34 | |
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| 35 | struct aiu { |
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| 36 | struct clk *spdif_mclk; |
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| 37 | struct aiu_interface i2s; |
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| 38 | struct aiu_interface spdif; |
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| 39 | const struct aiu_platform_data *platform; |
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| 40 | }; |
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| 41 | |
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| 42 | #define AIU_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ |
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| 43 | SNDRV_PCM_FMTBIT_S20_LE | \ |
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| 44 | SNDRV_PCM_FMTBIT_S24_LE) |
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| 45 | |
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| 46 | int aiu_of_xlate_dai_name(struct snd_soc_component *component, |
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| 47 | const struct of_phandle_args *args, |
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| 48 | const char **dai_name, |
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| 49 | unsigned int component_id); |
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| 50 | |
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| 51 | int aiu_hdmi_ctrl_register_component(struct device *dev); |
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| 52 | int aiu_acodec_ctrl_register_component(struct device *dev); |
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| 53 | |
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| 54 | int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai); |
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| 55 | int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai); |
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| 56 | |
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| 57 | extern const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops; |
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| 58 | extern const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops; |
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| 59 | extern const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops; |
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| 60 | extern const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops; |
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| 61 | |
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| 62 | #define AIU_IEC958_BPF 0x000 |
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| 63 | #define AIU_958_MISC 0x010 |
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| 64 | #define AIU_IEC958_DCU_FF_CTRL 0x01c |
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| 65 | #define AIU_958_CHSTAT_L0 0x020 |
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| 66 | #define AIU_958_CHSTAT_L1 0x024 |
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| 67 | #define AIU_958_CTRL 0x028 |
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| 68 | #define AIU_I2S_SOURCE_DESC 0x034 |
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| 69 | #define AIU_I2S_DAC_CFG 0x040 |
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| 70 | #define AIU_I2S_SYNC 0x044 |
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| 71 | #define AIU_I2S_MISC 0x048 |
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| 72 | #define AIU_RST_SOFT 0x054 |
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| 73 | #define AIU_CLK_CTRL 0x058 |
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| 74 | #define AIU_CLK_CTRL_MORE 0x064 |
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| 75 | #define AIU_CODEC_DAC_LRCLK_CTRL 0x0a0 |
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| 76 | #define AIU_HDMI_CLK_DATA_CTRL 0x0a8 |
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| 77 | #define AIU_ACODEC_CTRL 0x0b0 |
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| 78 | #define AIU_958_CHSTAT_R0 0x0c0 |
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| 79 | #define AIU_958_CHSTAT_R1 0x0c4 |
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| 80 | #define AIU_MEM_I2S_START 0x180 |
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| 81 | #define AIU_MEM_I2S_MASKS 0x18c |
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| 82 | #define AIU_MEM_I2S_CONTROL 0x190 |
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| 83 | #define AIU_MEM_IEC958_START 0x194 |
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| 84 | #define AIU_MEM_IEC958_CONTROL 0x1a4 |
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| 85 | #define AIU_MEM_I2S_BUF_CNTL 0x1d8 |
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| 86 | #define AIU_MEM_IEC958_BUF_CNTL 0x1fc |
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| 87 | |
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| 88 | #endif /* _MESON_AIU_H */ |
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| 89 | |
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