| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * linux/sound/soc/pxa/mmp-sspa.h |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Marvell International Ltd. |
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| 6 | */ |
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| 7 | #ifndef _MMP_SSPA_H |
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| 8 | #define _MMP_SSPA_H |
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| 9 | |
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| 10 | /* |
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| 11 | * SSPA Registers |
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| 12 | */ |
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| 13 | #define SSPA_D (0x00) |
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| 14 | #define SSPA_ID (0x04) |
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| 15 | #define SSPA_CTL (0x08) |
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| 16 | #define SSPA_SP (0x0c) |
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| 17 | #define SSPA_FIFO_UL (0x10) |
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| 18 | #define SSPA_INT_MASK (0x14) |
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| 19 | #define SSPA_C (0x18) |
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| 20 | #define SSPA_FIFO_NOFS (0x1c) |
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| 21 | #define SSPA_FIFO_SIZE (0x20) |
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| 22 | |
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| 23 | /* SSPA Control Register */ |
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| 24 | #define SSPA_CTL_XPH (1 << 31) /* Read Phase */ |
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| 25 | #define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */ |
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| 26 | #define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */ |
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| 27 | #define SSPA_CTL_XFRLEN2_MASK (7 << 24) |
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| 28 | #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ |
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| 29 | #define SSPA_CTL_XWDLEN2_MASK (7 << 21) |
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| 30 | #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ |
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| 31 | #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */ |
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| 32 | #define SSPA_CTL_XSSZ2_MASK (7 << 16) |
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| 33 | #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ |
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| 34 | #define SSPA_CTL_XFRLEN1_MASK (7 << 8) |
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| 35 | #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ |
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| 36 | #define SSPA_CTL_XWDLEN1_MASK (7 << 5) |
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| 37 | #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ |
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| 38 | #define SSPA_CTL_XSSZ1_MASK (7 << 0) |
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| 39 | #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ |
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| 40 | |
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| 41 | #define SSPA_CTL_8_BITS (0x0) /* Sample Size */ |
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| 42 | #define SSPA_CTL_12_BITS (0x1) |
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| 43 | #define SSPA_CTL_16_BITS (0x2) |
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| 44 | #define SSPA_CTL_20_BITS (0x3) |
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| 45 | #define SSPA_CTL_24_BITS (0x4) |
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| 46 | #define SSPA_CTL_32_BITS (0x5) |
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| 47 | |
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| 48 | /* SSPA Serial Port Register */ |
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| 49 | #define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */ |
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| 50 | #define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */ |
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| 51 | #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */ |
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| 52 | #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */ |
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| 53 | #define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */ |
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| 54 | #define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */ |
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| 55 | #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */ |
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| 56 | #define SSPA_SP_FWID_MASK (0x3f << 20) |
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| 57 | #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ |
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| 58 | #define SSPA_TXSP_FPER_MASK (0x3f << 4) |
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| 59 | #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ |
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| 60 | |
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| 61 | /* sspa clock sources */ |
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| 62 | #define MMP_SSPA_CLK_PLL 0 |
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| 63 | #define MMP_SSPA_CLK_VCXO 1 |
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| 64 | #define MMP_SSPA_CLK_AUDIO 3 |
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| 65 | |
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| 66 | /* sspa pll id */ |
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| 67 | #define MMP_SYSCLK 0 |
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| 68 | #define MMP_SSPA_CLK 1 |
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| 69 | |
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| 70 | #endif /* _MMP_SSPA_H */ |
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| 71 | |
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