| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * sound/soc/rockchip/rockchip_i2s.h |
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| 4 | * |
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| 5 | * ALSA SoC Audio Layer - Rockchip I2S Controller driver |
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| 6 | * |
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| 7 | * Copyright (c) 2014 Rockchip Electronics Co. Ltd. |
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| 8 | * Author: Jianqun xu <jay.xu@rock-chips.com> |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _ROCKCHIP_IIS_H |
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| 12 | #define _ROCKCHIP_IIS_H |
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| 13 | |
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| 14 | /* |
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| 15 | * TXCR |
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| 16 | * transmit operation control register |
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| 17 | */ |
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| 18 | #define I2S_TXCR_RCNT_SHIFT 17 |
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| 19 | #define I2S_TXCR_RCNT_MASK (0x3f << I2S_TXCR_RCNT_SHIFT) |
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| 20 | #define I2S_TXCR_CSR_SHIFT 15 |
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| 21 | #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) |
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| 22 | #define I2S_TXCR_CSR_MASK (3 << I2S_TXCR_CSR_SHIFT) |
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| 23 | #define I2S_TXCR_HWT BIT(14) |
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| 24 | #define I2S_TXCR_SJM_SHIFT 12 |
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| 25 | #define I2S_TXCR_SJM_R (0 << I2S_TXCR_SJM_SHIFT) |
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| 26 | #define I2S_TXCR_SJM_L (1 << I2S_TXCR_SJM_SHIFT) |
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| 27 | #define I2S_TXCR_FBM_SHIFT 11 |
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| 28 | #define I2S_TXCR_FBM_MSB (0 << I2S_TXCR_FBM_SHIFT) |
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| 29 | #define I2S_TXCR_FBM_LSB (1 << I2S_TXCR_FBM_SHIFT) |
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| 30 | #define I2S_TXCR_IBM_SHIFT 9 |
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| 31 | #define I2S_TXCR_IBM_NORMAL (0 << I2S_TXCR_IBM_SHIFT) |
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| 32 | #define I2S_TXCR_IBM_LSJM (1 << I2S_TXCR_IBM_SHIFT) |
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| 33 | #define I2S_TXCR_IBM_RSJM (2 << I2S_TXCR_IBM_SHIFT) |
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| 34 | #define I2S_TXCR_IBM_MASK (3 << I2S_TXCR_IBM_SHIFT) |
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| 35 | #define I2S_TXCR_PBM_SHIFT 7 |
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| 36 | #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) |
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| 37 | #define I2S_TXCR_PBM_MASK (3 << I2S_TXCR_PBM_SHIFT) |
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| 38 | #define I2S_TXCR_TFS_SHIFT 5 |
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| 39 | #define I2S_TXCR_TFS_I2S (0 << I2S_TXCR_TFS_SHIFT) |
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| 40 | #define I2S_TXCR_TFS_PCM (1 << I2S_TXCR_TFS_SHIFT) |
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| 41 | #define I2S_TXCR_TFS_MASK (1 << I2S_TXCR_TFS_SHIFT) |
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| 42 | #define I2S_TXCR_VDW_SHIFT 0 |
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| 43 | #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) |
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| 44 | #define I2S_TXCR_VDW_MASK (0x1f << I2S_TXCR_VDW_SHIFT) |
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| 45 | |
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| 46 | /* |
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| 47 | * RXCR |
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| 48 | * receive operation control register |
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| 49 | */ |
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| 50 | #define I2S_RXCR_CSR_SHIFT 15 |
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| 51 | #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) |
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| 52 | #define I2S_RXCR_CSR_MASK (3 << I2S_RXCR_CSR_SHIFT) |
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| 53 | #define I2S_RXCR_HWT BIT(14) |
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| 54 | #define I2S_RXCR_SJM_SHIFT 12 |
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| 55 | #define I2S_RXCR_SJM_R (0 << I2S_RXCR_SJM_SHIFT) |
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| 56 | #define I2S_RXCR_SJM_L (1 << I2S_RXCR_SJM_SHIFT) |
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| 57 | #define I2S_RXCR_FBM_SHIFT 11 |
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| 58 | #define I2S_RXCR_FBM_MSB (0 << I2S_RXCR_FBM_SHIFT) |
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| 59 | #define I2S_RXCR_FBM_LSB (1 << I2S_RXCR_FBM_SHIFT) |
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| 60 | #define I2S_RXCR_IBM_SHIFT 9 |
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| 61 | #define I2S_RXCR_IBM_NORMAL (0 << I2S_RXCR_IBM_SHIFT) |
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| 62 | #define I2S_RXCR_IBM_LSJM (1 << I2S_RXCR_IBM_SHIFT) |
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| 63 | #define I2S_RXCR_IBM_RSJM (2 << I2S_RXCR_IBM_SHIFT) |
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| 64 | #define I2S_RXCR_IBM_MASK (3 << I2S_RXCR_IBM_SHIFT) |
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| 65 | #define I2S_RXCR_PBM_SHIFT 7 |
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| 66 | #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) |
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| 67 | #define I2S_RXCR_PBM_MASK (3 << I2S_RXCR_PBM_SHIFT) |
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| 68 | #define I2S_RXCR_TFS_SHIFT 5 |
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| 69 | #define I2S_RXCR_TFS_I2S (0 << I2S_RXCR_TFS_SHIFT) |
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| 70 | #define I2S_RXCR_TFS_PCM (1 << I2S_RXCR_TFS_SHIFT) |
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| 71 | #define I2S_RXCR_TFS_MASK (1 << I2S_RXCR_TFS_SHIFT) |
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| 72 | #define I2S_RXCR_VDW_SHIFT 0 |
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| 73 | #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) |
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| 74 | #define I2S_RXCR_VDW_MASK (0x1f << I2S_RXCR_VDW_SHIFT) |
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| 75 | |
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| 76 | /* |
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| 77 | * CKR |
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| 78 | * clock generation register |
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| 79 | */ |
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| 80 | #define I2S_CKR_TRCM_SHIFT 28 |
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| 81 | #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) |
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| 82 | #define I2S_CKR_TRCM_TXRX (0 << I2S_CKR_TRCM_SHIFT) |
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| 83 | #define I2S_CKR_TRCM_TXONLY (1 << I2S_CKR_TRCM_SHIFT) |
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| 84 | #define I2S_CKR_TRCM_RXONLY (2 << I2S_CKR_TRCM_SHIFT) |
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| 85 | #define I2S_CKR_TRCM_MASK (3 << I2S_CKR_TRCM_SHIFT) |
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| 86 | #define I2S_CKR_MSS_SHIFT 27 |
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| 87 | #define I2S_CKR_MSS_MASTER (0 << I2S_CKR_MSS_SHIFT) |
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| 88 | #define I2S_CKR_MSS_SLAVE (1 << I2S_CKR_MSS_SHIFT) |
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| 89 | #define I2S_CKR_MSS_MASK (1 << I2S_CKR_MSS_SHIFT) |
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| 90 | #define I2S_CKR_CKP_SHIFT 26 |
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| 91 | #define I2S_CKR_CKP_NORMAL (0 << I2S_CKR_CKP_SHIFT) |
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| 92 | #define I2S_CKR_CKP_INVERTED (1 << I2S_CKR_CKP_SHIFT) |
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| 93 | #define I2S_CKR_CKP_MASK (1 << I2S_CKR_CKP_SHIFT) |
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| 94 | #define I2S_CKR_RLP_SHIFT 25 |
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| 95 | #define I2S_CKR_RLP_NORMAL (0 << I2S_CKR_RLP_SHIFT) |
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| 96 | #define I2S_CKR_RLP_INVERTED (1 << I2S_CKR_RLP_SHIFT) |
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| 97 | #define I2S_CKR_RLP_MASK (1 << I2S_CKR_RLP_SHIFT) |
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| 98 | #define I2S_CKR_TLP_SHIFT 24 |
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| 99 | #define I2S_CKR_TLP_NORMAL (0 << I2S_CKR_TLP_SHIFT) |
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| 100 | #define I2S_CKR_TLP_INVERTED (1 << I2S_CKR_TLP_SHIFT) |
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| 101 | #define I2S_CKR_TLP_MASK (1 << I2S_CKR_TLP_SHIFT) |
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| 102 | #define I2S_CKR_MDIV_SHIFT 16 |
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| 103 | #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) |
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| 104 | #define I2S_CKR_MDIV_MASK (0xff << I2S_CKR_MDIV_SHIFT) |
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| 105 | #define I2S_CKR_RSD_SHIFT 8 |
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| 106 | #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) |
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| 107 | #define I2S_CKR_RSD_MASK (0xff << I2S_CKR_RSD_SHIFT) |
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| 108 | #define I2S_CKR_TSD_SHIFT 0 |
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| 109 | #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) |
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| 110 | #define I2S_CKR_TSD_MASK (0xff << I2S_CKR_TSD_SHIFT) |
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| 111 | |
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| 112 | /* |
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| 113 | * FIFOLR |
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| 114 | * FIFO level register |
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| 115 | */ |
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| 116 | #define I2S_FIFOLR_RFL_SHIFT 24 |
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| 117 | #define I2S_FIFOLR_RFL_MASK (0x3f << I2S_FIFOLR_RFL_SHIFT) |
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| 118 | #define I2S_FIFOLR_TFL3_SHIFT 18 |
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| 119 | #define I2S_FIFOLR_TFL3_MASK (0x3f << I2S_FIFOLR_TFL3_SHIFT) |
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| 120 | #define I2S_FIFOLR_TFL2_SHIFT 12 |
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| 121 | #define I2S_FIFOLR_TFL2_MASK (0x3f << I2S_FIFOLR_TFL2_SHIFT) |
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| 122 | #define I2S_FIFOLR_TFL1_SHIFT 6 |
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| 123 | #define I2S_FIFOLR_TFL1_MASK (0x3f << I2S_FIFOLR_TFL1_SHIFT) |
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| 124 | #define I2S_FIFOLR_TFL0_SHIFT 0 |
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| 125 | #define I2S_FIFOLR_TFL0_MASK (0x3f << I2S_FIFOLR_TFL0_SHIFT) |
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| 126 | |
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| 127 | /* |
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| 128 | * DMACR |
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| 129 | * DMA control register |
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| 130 | */ |
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| 131 | #define I2S_DMACR_RDE_SHIFT 24 |
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| 132 | #define I2S_DMACR_RDE_DISABLE (0 << I2S_DMACR_RDE_SHIFT) |
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| 133 | #define I2S_DMACR_RDE_ENABLE (1 << I2S_DMACR_RDE_SHIFT) |
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| 134 | #define I2S_DMACR_RDL_SHIFT 16 |
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| 135 | #define I2S_DMACR_RDL(x) ((x - 1) << I2S_DMACR_RDL_SHIFT) |
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| 136 | #define I2S_DMACR_RDL_MASK (0x1f << I2S_DMACR_RDL_SHIFT) |
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| 137 | #define I2S_DMACR_TDE_SHIFT 8 |
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| 138 | #define I2S_DMACR_TDE_DISABLE (0 << I2S_DMACR_TDE_SHIFT) |
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| 139 | #define I2S_DMACR_TDE_ENABLE (1 << I2S_DMACR_TDE_SHIFT) |
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| 140 | #define I2S_DMACR_TDL_SHIFT 0 |
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| 141 | #define I2S_DMACR_TDL(x) ((x) << I2S_DMACR_TDL_SHIFT) |
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| 142 | #define I2S_DMACR_TDL_MASK (0x1f << I2S_DMACR_TDL_SHIFT) |
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| 143 | |
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| 144 | /* |
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| 145 | * INTCR |
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| 146 | * interrupt control register |
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| 147 | */ |
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| 148 | #define I2S_INTCR_RFT_SHIFT 20 |
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| 149 | #define I2S_INTCR_RFT(x) ((x - 1) << I2S_INTCR_RFT_SHIFT) |
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| 150 | #define I2S_INTCR_RXOIC BIT(18) |
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| 151 | #define I2S_INTCR_RXOIE_SHIFT 17 |
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| 152 | #define I2S_INTCR_RXOIE_DISABLE (0 << I2S_INTCR_RXOIE_SHIFT) |
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| 153 | #define I2S_INTCR_RXOIE_ENABLE (1 << I2S_INTCR_RXOIE_SHIFT) |
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| 154 | #define I2S_INTCR_RXFIE_SHIFT 16 |
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| 155 | #define I2S_INTCR_RXFIE_DISABLE (0 << I2S_INTCR_RXFIE_SHIFT) |
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| 156 | #define I2S_INTCR_RXFIE_ENABLE (1 << I2S_INTCR_RXFIE_SHIFT) |
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| 157 | #define I2S_INTCR_TFT_SHIFT 4 |
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| 158 | #define I2S_INTCR_TFT(x) ((x - 1) << I2S_INTCR_TFT_SHIFT) |
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| 159 | #define I2S_INTCR_TFT_MASK (0x1f << I2S_INTCR_TFT_SHIFT) |
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| 160 | #define I2S_INTCR_TXUIC BIT(2) |
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| 161 | #define I2S_INTCR_TXUIE_SHIFT 1 |
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| 162 | #define I2S_INTCR_TXUIE_DISABLE (0 << I2S_INTCR_TXUIE_SHIFT) |
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| 163 | #define I2S_INTCR_TXUIE_ENABLE (1 << I2S_INTCR_TXUIE_SHIFT) |
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| 164 | |
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| 165 | /* |
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| 166 | * INTSR |
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| 167 | * interrupt status register |
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| 168 | */ |
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| 169 | #define I2S_INTSR_TXEIE_SHIFT 0 |
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| 170 | #define I2S_INTSR_TXEIE_DISABLE (0 << I2S_INTSR_TXEIE_SHIFT) |
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| 171 | #define I2S_INTSR_TXEIE_ENABLE (1 << I2S_INTSR_TXEIE_SHIFT) |
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| 172 | #define I2S_INTSR_RXOI_SHIFT 17 |
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| 173 | #define I2S_INTSR_RXOI_INA (0 << I2S_INTSR_RXOI_SHIFT) |
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| 174 | #define I2S_INTSR_RXOI_ACT (1 << I2S_INTSR_RXOI_SHIFT) |
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| 175 | #define I2S_INTSR_RXFI_SHIFT 16 |
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| 176 | #define I2S_INTSR_RXFI_INA (0 << I2S_INTSR_RXFI_SHIFT) |
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| 177 | #define I2S_INTSR_RXFI_ACT (1 << I2S_INTSR_RXFI_SHIFT) |
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| 178 | #define I2S_INTSR_TXUI_SHIFT 1 |
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| 179 | #define I2S_INTSR_TXUI_INA (0 << I2S_INTSR_TXUI_SHIFT) |
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| 180 | #define I2S_INTSR_TXUI_ACT (1 << I2S_INTSR_TXUI_SHIFT) |
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| 181 | #define I2S_INTSR_TXEI_SHIFT 0 |
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| 182 | #define I2S_INTSR_TXEI_INA (0 << I2S_INTSR_TXEI_SHIFT) |
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| 183 | #define I2S_INTSR_TXEI_ACT (1 << I2S_INTSR_TXEI_SHIFT) |
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| 184 | |
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| 185 | /* |
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| 186 | * XFER |
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| 187 | * Transfer start register |
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| 188 | */ |
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| 189 | #define I2S_XFER_RXS_SHIFT 1 |
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| 190 | #define I2S_XFER_RXS_STOP (0 << I2S_XFER_RXS_SHIFT) |
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| 191 | #define I2S_XFER_RXS_START (1 << I2S_XFER_RXS_SHIFT) |
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| 192 | #define I2S_XFER_TXS_SHIFT 0 |
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| 193 | #define I2S_XFER_TXS_STOP (0 << I2S_XFER_TXS_SHIFT) |
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| 194 | #define I2S_XFER_TXS_START (1 << I2S_XFER_TXS_SHIFT) |
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| 195 | |
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| 196 | /* |
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| 197 | * CLR |
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| 198 | * clear SCLK domain logic register |
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| 199 | */ |
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| 200 | #define I2S_CLR_RXC BIT(1) |
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| 201 | #define I2S_CLR_TXC BIT(0) |
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| 202 | |
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| 203 | /* |
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| 204 | * TXDR |
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| 205 | * Transimt FIFO data register, write only. |
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| 206 | */ |
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| 207 | #define I2S_TXDR_MASK (0xff) |
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| 208 | |
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| 209 | /* |
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| 210 | * RXDR |
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| 211 | * Receive FIFO data register, write only. |
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| 212 | */ |
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| 213 | #define I2S_RXDR_MASK (0xff) |
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| 214 | |
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| 215 | /* Clock divider id */ |
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| 216 | enum { |
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| 217 | ROCKCHIP_DIV_MCLK = 0, |
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| 218 | ROCKCHIP_DIV_BCLK, |
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| 219 | }; |
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| 220 | |
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| 221 | /* channel select */ |
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| 222 | #define I2S_CSR_SHIFT 15 |
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| 223 | #define I2S_CHN_2 (0 << I2S_CSR_SHIFT) |
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| 224 | #define I2S_CHN_4 (1 << I2S_CSR_SHIFT) |
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| 225 | #define I2S_CHN_6 (2 << I2S_CSR_SHIFT) |
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| 226 | #define I2S_CHN_8 (3 << I2S_CSR_SHIFT) |
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| 227 | |
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| 228 | /* I2S REGS */ |
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| 229 | #define I2S_TXCR (0x0000) |
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| 230 | #define I2S_RXCR (0x0004) |
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| 231 | #define I2S_CKR (0x0008) |
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| 232 | #define I2S_FIFOLR (0x000c) |
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| 233 | #define I2S_DMACR (0x0010) |
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| 234 | #define I2S_INTCR (0x0014) |
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| 235 | #define I2S_INTSR (0x0018) |
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| 236 | #define I2S_XFER (0x001c) |
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| 237 | #define I2S_CLR (0x0020) |
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| 238 | #define I2S_TXDR (0x0024) |
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| 239 | #define I2S_RXDR (0x0028) |
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| 240 | |
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| 241 | /* io direction cfg register */ |
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| 242 | #define I2S_IO_DIRECTION_MASK (7) |
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| 243 | #define I2S_IO_8CH_OUT_2CH_IN (0) |
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| 244 | #define I2S_IO_6CH_OUT_4CH_IN (4) |
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| 245 | #define I2S_IO_4CH_OUT_6CH_IN (6) |
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| 246 | #define I2S_IO_2CH_OUT_8CH_IN (7) |
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| 247 | |
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| 248 | #endif /* _ROCKCHIP_IIS_H */ |
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| 249 | |
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