| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Rockchip PDM ALSA SoC Digital Audio Interface(DAI) driver |
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| 4 | * |
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| 5 | * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef _ROCKCHIP_PDM_H |
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| 9 | #define _ROCKCHIP_PDM_H |
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| 10 | |
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| 11 | /* PDM REGS */ |
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| 12 | #define PDM_SYSCONFIG (0x0000) |
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| 13 | #define PDM_CTRL0 (0x0004) |
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| 14 | #define PDM_CTRL1 (0x0008) |
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| 15 | #define PDM_CLK_CTRL (0x000c) |
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| 16 | #define PDM_HPF_CTRL (0x0010) |
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| 17 | #define PDM_FIFO_CTRL (0x0014) |
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| 18 | #define PDM_DMA_CTRL (0x0018) |
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| 19 | #define PDM_INT_EN (0x001c) |
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| 20 | #define PDM_INT_CLR (0x0020) |
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| 21 | #define PDM_INT_ST (0x0024) |
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| 22 | #define PDM_RXFIFO_DATA (0x0030) |
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| 23 | #define PDM_DATA_VALID (0x0054) |
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| 24 | #define PDM_VERSION (0x0058) |
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| 25 | |
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| 26 | /* PDM_SYSCONFIG */ |
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| 27 | #define PDM_RX_MASK (0x1 << 2) |
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| 28 | #define PDM_RX_START (0x1 << 2) |
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| 29 | #define PDM_RX_STOP (0x0 << 2) |
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| 30 | #define PDM_RX_CLR_MASK (0x1 << 0) |
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| 31 | #define PDM_RX_CLR_WR (0x1 << 0) |
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| 32 | #define PDM_RX_CLR_DONE (0x0 << 0) |
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| 33 | |
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| 34 | /* PDM CTRL0 */ |
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| 35 | #define PDM_PATH_MSK (0xf << 27) |
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| 36 | #define PDM_MODE_MSK BIT(31) |
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| 37 | #define PDM_MODE_RJ 0 |
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| 38 | #define PDM_MODE_LJ BIT(31) |
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| 39 | #define PDM_PATH3_EN BIT(30) |
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| 40 | #define PDM_PATH2_EN BIT(29) |
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| 41 | #define PDM_PATH1_EN BIT(28) |
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| 42 | #define PDM_PATH0_EN BIT(27) |
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| 43 | #define PDM_HWT_EN BIT(26) |
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| 44 | #define PDM_SAMPLERATE_MSK GENMASK(7, 5) |
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| 45 | #define PDM_SAMPLERATE(x) ((x) << 5) |
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| 46 | #define PDM_VDW_MSK (0x1f << 0) |
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| 47 | #define PDM_VDW(X) ((X - 1) << 0) |
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| 48 | |
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| 49 | /* PDM CTRL1 */ |
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| 50 | #define PDM_FD_NUMERATOR_SFT 16 |
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| 51 | #define PDM_FD_NUMERATOR_MSK GENMASK(31, 16) |
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| 52 | #define PDM_FD_DENOMINATOR_SFT 0 |
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| 53 | #define PDM_FD_DENOMINATOR_MSK GENMASK(15, 0) |
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| 54 | |
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| 55 | /* PDM CLK CTRL */ |
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| 56 | #define PDM_PATH_SHIFT(x) (8 + (x) * 2) |
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| 57 | #define PDM_PATH_MASK(x) (0x3 << PDM_PATH_SHIFT(x)) |
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| 58 | #define PDM_PATH(x, v) ((v) << PDM_PATH_SHIFT(x)) |
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| 59 | #define PDM_CLK_FD_RATIO_MSK BIT(6) |
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| 60 | #define PDM_CLK_FD_RATIO_40 (0X0 << 6) |
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| 61 | #define PDM_CLK_FD_RATIO_35 BIT(6) |
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| 62 | #define PDM_CLK_MSK BIT(5) |
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| 63 | #define PDM_CLK_EN BIT(5) |
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| 64 | #define PDM_CLK_DIS (0x0 << 5) |
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| 65 | #define PDM_CKP_MSK BIT(3) |
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| 66 | #define PDM_CKP_NORMAL (0x0 << 3) |
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| 67 | #define PDM_CKP_INVERTED BIT(3) |
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| 68 | #define PDM_DS_RATIO_MSK (0x7 << 0) |
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| 69 | #define PDM_CLK_320FS (0x0 << 0) |
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| 70 | #define PDM_CLK_640FS (0x1 << 0) |
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| 71 | #define PDM_CLK_1280FS (0x2 << 0) |
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| 72 | #define PDM_CLK_2560FS (0x3 << 0) |
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| 73 | #define PDM_CLK_5120FS (0x4 << 0) |
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| 74 | #define PDM_CIC_RATIO_MSK (0x3 << 0) |
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| 75 | |
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| 76 | /* PDM HPF CTRL */ |
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| 77 | #define PDM_HPF_LE BIT(3) |
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| 78 | #define PDM_HPF_RE BIT(2) |
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| 79 | #define PDM_HPF_CF_MSK (0x3 << 0) |
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| 80 | #define PDM_HPF_3P79HZ (0x0 << 0) |
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| 81 | #define PDM_HPF_60HZ (0x1 << 0) |
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| 82 | #define PDM_HPF_243HZ (0x2 << 0) |
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| 83 | #define PDM_HPF_493HZ (0x3 << 0) |
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| 84 | |
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| 85 | /* PDM DMA CTRL */ |
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| 86 | #define PDM_DMA_RD_MSK BIT(8) |
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| 87 | #define PDM_DMA_RD_EN BIT(8) |
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| 88 | #define PDM_DMA_RD_DIS (0x0 << 8) |
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| 89 | #define PDM_DMA_RDL_MSK (0x7f << 0) |
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| 90 | #define PDM_DMA_RDL(X) ((X - 1) << 0) |
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| 91 | |
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| 92 | #endif /* _ROCKCHIP_PDM_H */ |
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| 93 | |
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