1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * tegra20_das.c - Tegra20 DAS driver |
4 | * |
5 | * Author: Stephen Warren <swarren@nvidia.com> |
6 | * Copyright (C) 2010 - NVIDIA, Inc. |
7 | */ |
8 | |
9 | #include <linux/device.h> |
10 | #include <linux/io.h> |
11 | #include <linux/module.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/regmap.h> |
14 | #include <linux/slab.h> |
15 | #include <sound/soc.h> |
16 | |
17 | #define DRV_NAME "tegra20-das" |
18 | |
19 | /* Register TEGRA20_DAS_DAP_CTRL_SEL */ |
20 | #define TEGRA20_DAS_DAP_CTRL_SEL 0x00 |
21 | #define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5 |
22 | #define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4 |
23 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31 |
24 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1 |
25 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30 |
26 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1 |
27 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29 |
28 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1 |
29 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0 |
30 | #define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5 |
31 | |
32 | /* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */ |
33 | #define TEGRA20_DAS_DAP_SEL_DAC1 0 |
34 | #define TEGRA20_DAS_DAP_SEL_DAC2 1 |
35 | #define TEGRA20_DAS_DAP_SEL_DAC3 2 |
36 | #define TEGRA20_DAS_DAP_SEL_DAP1 16 |
37 | #define TEGRA20_DAS_DAP_SEL_DAP2 17 |
38 | #define TEGRA20_DAS_DAP_SEL_DAP3 18 |
39 | #define TEGRA20_DAS_DAP_SEL_DAP4 19 |
40 | #define TEGRA20_DAS_DAP_SEL_DAP5 20 |
41 | |
42 | /* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */ |
43 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40 |
44 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3 |
45 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4 |
46 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28 |
47 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4 |
48 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24 |
49 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4 |
50 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0 |
51 | #define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4 |
52 | |
53 | /* |
54 | * Values for: |
55 | * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL |
56 | * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL |
57 | * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL |
58 | */ |
59 | #define TEGRA20_DAS_DAC_SEL_DAP1 0 |
60 | #define TEGRA20_DAS_DAC_SEL_DAP2 1 |
61 | #define TEGRA20_DAS_DAC_SEL_DAP3 2 |
62 | #define TEGRA20_DAS_DAC_SEL_DAP4 3 |
63 | #define TEGRA20_DAS_DAC_SEL_DAP5 4 |
64 | |
65 | /* |
66 | * Names/IDs of the DACs/DAPs. |
67 | */ |
68 | |
69 | #define TEGRA20_DAS_DAP_ID_1 0 |
70 | #define TEGRA20_DAS_DAP_ID_2 1 |
71 | #define TEGRA20_DAS_DAP_ID_3 2 |
72 | #define TEGRA20_DAS_DAP_ID_4 3 |
73 | #define TEGRA20_DAS_DAP_ID_5 4 |
74 | |
75 | #define TEGRA20_DAS_DAC_ID_1 0 |
76 | #define TEGRA20_DAS_DAC_ID_2 1 |
77 | #define TEGRA20_DAS_DAC_ID_3 2 |
78 | |
79 | struct tegra20_das { |
80 | struct regmap *regmap; |
81 | }; |
82 | |
83 | /* |
84 | * Terminology: |
85 | * DAS: Digital audio switch (HW module controlled by this driver) |
86 | * DAP: Digital audio port (port/pins on Tegra device) |
87 | * DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere) |
88 | * |
89 | * The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific |
90 | * DAC, or another DAP. When DAPs are connected, one must be the master and |
91 | * one the slave. Each DAC allows selection of a specific DAP for input, to |
92 | * cater for the case where N DAPs are connected to 1 DAC for broadcast |
93 | * output. |
94 | * |
95 | * This driver is dumb; no attempt is made to ensure that a valid routing |
96 | * configuration is programmed. |
97 | */ |
98 | |
99 | static inline void tegra20_das_write(struct tegra20_das *das, u32 reg, u32 val) |
100 | { |
101 | regmap_write(map: das->regmap, reg, val); |
102 | } |
103 | |
104 | static void tegra20_das_connect_dap_to_dac(struct tegra20_das *das, int dap, int dac) |
105 | { |
106 | u32 addr; |
107 | u32 reg; |
108 | |
109 | addr = TEGRA20_DAS_DAP_CTRL_SEL + |
110 | (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE); |
111 | reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P; |
112 | |
113 | tegra20_das_write(das, reg: addr, val: reg); |
114 | } |
115 | |
116 | static void tegra20_das_connect_dac_to_dap(struct tegra20_das *das, int dac, int dap) |
117 | { |
118 | u32 addr; |
119 | u32 reg; |
120 | |
121 | addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL + |
122 | (dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE); |
123 | reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P | |
124 | dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P | |
125 | dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P; |
126 | |
127 | tegra20_das_write(das, reg: addr, val: reg); |
128 | } |
129 | |
130 | #define LAST_REG(name) \ |
131 | (TEGRA20_DAS_##name + \ |
132 | (TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1))) |
133 | |
134 | static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg) |
135 | { |
136 | if (reg <= LAST_REG(DAP_CTRL_SEL)) |
137 | return true; |
138 | if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) && |
139 | (reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL))) |
140 | return true; |
141 | |
142 | return false; |
143 | } |
144 | |
145 | static const struct regmap_config tegra20_das_regmap_config = { |
146 | .reg_bits = 32, |
147 | .reg_stride = 4, |
148 | .val_bits = 32, |
149 | .max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL), |
150 | .writeable_reg = tegra20_das_wr_rd_reg, |
151 | .readable_reg = tegra20_das_wr_rd_reg, |
152 | .cache_type = REGCACHE_FLAT, |
153 | }; |
154 | |
155 | static int tegra20_das_probe(struct platform_device *pdev) |
156 | { |
157 | void __iomem *regs; |
158 | struct tegra20_das *das; |
159 | |
160 | das = devm_kzalloc(dev: &pdev->dev, size: sizeof(struct tegra20_das), GFP_KERNEL); |
161 | if (!das) |
162 | return -ENOMEM; |
163 | |
164 | regs = devm_platform_ioremap_resource(pdev, index: 0); |
165 | if (IS_ERR(ptr: regs)) |
166 | return PTR_ERR(ptr: regs); |
167 | |
168 | das->regmap = devm_regmap_init_mmio(&pdev->dev, regs, |
169 | &tegra20_das_regmap_config); |
170 | if (IS_ERR(ptr: das->regmap)) { |
171 | dev_err(&pdev->dev, "regmap init failed\n" ); |
172 | return PTR_ERR(ptr: das->regmap); |
173 | } |
174 | |
175 | tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_1, |
176 | TEGRA20_DAS_DAP_SEL_DAC1); |
177 | tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_1, |
178 | TEGRA20_DAS_DAC_SEL_DAP1); |
179 | tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_3, |
180 | TEGRA20_DAS_DAP_SEL_DAC3); |
181 | tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_3, |
182 | TEGRA20_DAS_DAC_SEL_DAP3); |
183 | |
184 | return 0; |
185 | } |
186 | |
187 | static const struct of_device_id tegra20_das_of_match[] = { |
188 | { .compatible = "nvidia,tegra20-das" , }, |
189 | {}, |
190 | }; |
191 | |
192 | static struct platform_driver tegra20_das_driver = { |
193 | .probe = tegra20_das_probe, |
194 | .driver = { |
195 | .name = DRV_NAME, |
196 | .of_match_table = tegra20_das_of_match, |
197 | }, |
198 | }; |
199 | module_platform_driver(tegra20_das_driver); |
200 | |
201 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>" ); |
202 | MODULE_DESCRIPTION("Tegra20 DAS driver" ); |
203 | MODULE_LICENSE("GPL" ); |
204 | MODULE_ALIAS("platform:" DRV_NAME); |
205 | MODULE_DEVICE_TABLE(of, tegra20_das_of_match); |
206 | |