1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * tegra20_spdif.h - Definitions for Tegra20 SPDIF driver |
4 | * |
5 | * Author: Stephen Warren <swarren@nvidia.com> |
6 | * Copyright (C) 2011 - NVIDIA, Inc. |
7 | * |
8 | * Based on code copyright/by: |
9 | * Copyright (c) 2008-2009, NVIDIA Corporation |
10 | */ |
11 | |
12 | #ifndef __TEGRA20_SPDIF_H__ |
13 | #define __TEGRA20_SPDIF_H__ |
14 | |
15 | #include "tegra_pcm.h" |
16 | |
17 | /* Offsets from TEGRA20_SPDIF_BASE */ |
18 | |
19 | #define TEGRA20_SPDIF_CTRL 0x0 |
20 | #define TEGRA20_SPDIF_STATUS 0x4 |
21 | #define TEGRA20_SPDIF_STROBE_CTRL 0x8 |
22 | #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C |
23 | #define TEGRA20_SPDIF_DATA_OUT 0x40 |
24 | #define TEGRA20_SPDIF_DATA_IN 0x80 |
25 | #define TEGRA20_SPDIF_CH_STA_RX_A 0x100 |
26 | #define TEGRA20_SPDIF_CH_STA_RX_B 0x104 |
27 | #define TEGRA20_SPDIF_CH_STA_RX_C 0x108 |
28 | #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C |
29 | #define TEGRA20_SPDIF_CH_STA_RX_E 0x110 |
30 | #define TEGRA20_SPDIF_CH_STA_RX_F 0x114 |
31 | #define TEGRA20_SPDIF_CH_STA_TX_A 0x140 |
32 | #define TEGRA20_SPDIF_CH_STA_TX_B 0x144 |
33 | #define TEGRA20_SPDIF_CH_STA_TX_C 0x148 |
34 | #define TEGRA20_SPDIF_CH_STA_TX_D 0x14C |
35 | #define TEGRA20_SPDIF_CH_STA_TX_E 0x150 |
36 | #define TEGRA20_SPDIF_CH_STA_TX_F 0x154 |
37 | #define TEGRA20_SPDIF_USR_STA_RX_A 0x180 |
38 | #define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0 |
39 | |
40 | /* Fields in TEGRA20_SPDIF_CTRL */ |
41 | |
42 | /* Start capturing from 0=right, 1=left channel */ |
43 | #define TEGRA20_SPDIF_CTRL_CAP_LC (1 << 30) |
44 | |
45 | /* SPDIF receiver(RX) enable */ |
46 | #define TEGRA20_SPDIF_CTRL_RX_EN (1 << 29) |
47 | |
48 | /* SPDIF Transmitter(TX) enable */ |
49 | #define TEGRA20_SPDIF_CTRL_TX_EN (1 << 28) |
50 | |
51 | /* Transmit Channel status */ |
52 | #define TEGRA20_SPDIF_CTRL_TC_EN (1 << 27) |
53 | |
54 | /* Transmit user Data */ |
55 | #define TEGRA20_SPDIF_CTRL_TU_EN (1 << 26) |
56 | |
57 | /* Interrupt on transmit error */ |
58 | #define TEGRA20_SPDIF_CTRL_IE_TXE (1 << 25) |
59 | |
60 | /* Interrupt on receive error */ |
61 | #define TEGRA20_SPDIF_CTRL_IE_RXE (1 << 24) |
62 | |
63 | /* Interrupt on invalid preamble */ |
64 | #define TEGRA20_SPDIF_CTRL_IE_P (1 << 23) |
65 | |
66 | /* Interrupt on "B" preamble */ |
67 | #define TEGRA20_SPDIF_CTRL_IE_B (1 << 22) |
68 | |
69 | /* Interrupt when block of channel status received */ |
70 | #define TEGRA20_SPDIF_CTRL_IE_C (1 << 21) |
71 | |
72 | /* Interrupt when a valid information unit (IU) is received */ |
73 | #define TEGRA20_SPDIF_CTRL_IE_U (1 << 20) |
74 | |
75 | /* Interrupt when RX user FIFO attention level is reached */ |
76 | #define TEGRA20_SPDIF_CTRL_QE_RU (1 << 19) |
77 | |
78 | /* Interrupt when TX user FIFO attention level is reached */ |
79 | #define TEGRA20_SPDIF_CTRL_QE_TU (1 << 18) |
80 | |
81 | /* Interrupt when RX data FIFO attention level is reached */ |
82 | #define TEGRA20_SPDIF_CTRL_QE_RX (1 << 17) |
83 | |
84 | /* Interrupt when TX data FIFO attention level is reached */ |
85 | #define TEGRA20_SPDIF_CTRL_QE_TX (1 << 16) |
86 | |
87 | /* Loopback test mode enable */ |
88 | #define TEGRA20_SPDIF_CTRL_LBK_EN (1 << 15) |
89 | |
90 | /* |
91 | * Pack data mode: |
92 | * 0 = Single data (16 bit needs to be padded to match the |
93 | * interface data bit size). |
94 | * 1 = Packeted left/right channel data into a single word. |
95 | */ |
96 | #define TEGRA20_SPDIF_CTRL_PACK (1 << 14) |
97 | |
98 | /* |
99 | * 00 = 16bit data |
100 | * 01 = 20bit data |
101 | * 10 = 24bit data |
102 | * 11 = raw data |
103 | */ |
104 | #define TEGRA20_SPDIF_BIT_MODE_16BIT 0 |
105 | #define TEGRA20_SPDIF_BIT_MODE_20BIT 1 |
106 | #define TEGRA20_SPDIF_BIT_MODE_24BIT 2 |
107 | #define TEGRA20_SPDIF_BIT_MODE_RAW 3 |
108 | |
109 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT 12 |
110 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) |
111 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA20_SPDIF_BIT_MODE_16BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) |
112 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA20_SPDIF_BIT_MODE_20BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) |
113 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA20_SPDIF_BIT_MODE_24BIT << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) |
114 | #define TEGRA20_SPDIF_CTRL_BIT_MODE_RAW (TEGRA20_SPDIF_BIT_MODE_RAW << TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT) |
115 | |
116 | /* Fields in TEGRA20_SPDIF_STATUS */ |
117 | |
118 | /* |
119 | * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must |
120 | * write a 1 to the corresponding bit location to clear the status. |
121 | */ |
122 | |
123 | /* |
124 | * Receiver(RX) shifter is busy receiving data. |
125 | * This bit is asserted when the receiver first locked onto the |
126 | * preamble of the data stream after RX_EN is asserted. This bit is |
127 | * deasserted when either, |
128 | * (a) the end of a frame is reached after RX_EN is deeasserted, or |
129 | * (b) the SPDIF data stream becomes inactive. |
130 | */ |
131 | #define TEGRA20_SPDIF_STATUS_RX_BSY (1 << 29) |
132 | |
133 | /* |
134 | * Transmitter(TX) shifter is busy transmitting data. |
135 | * This bit is asserted when TX_EN is asserted. |
136 | * This bit is deasserted when the end of a frame is reached after |
137 | * TX_EN is deasserted. |
138 | */ |
139 | #define TEGRA20_SPDIF_STATUS_TX_BSY (1 << 28) |
140 | |
141 | /* |
142 | * TX is busy shifting out channel status. |
143 | * This bit is asserted when both TX_EN and TC_EN are asserted and |
144 | * data from CH_STA_TX_A register is loaded into the internal shifter. |
145 | * This bit is deasserted when either, |
146 | * (a) the end of a frame is reached after TX_EN is deasserted, or |
147 | * (b) CH_STA_TX_F register is loaded into the internal shifter. |
148 | */ |
149 | #define TEGRA20_SPDIF_STATUS_TC_BSY (1 << 27) |
150 | |
151 | /* |
152 | * TX User data FIFO busy. |
153 | * This bit is asserted when TX_EN and TXU_EN are asserted and |
154 | * there's data in the TX user FIFO. This bit is deassert when either, |
155 | * (a) the end of a frame is reached after TX_EN is deasserted, or |
156 | * (b) there's no data left in the TX user FIFO. |
157 | */ |
158 | #define TEGRA20_SPDIF_STATUS_TU_BSY (1 << 26) |
159 | |
160 | /* TX FIFO Underrun error status */ |
161 | #define TEGRA20_SPDIF_STATUS_TX_ERR (1 << 25) |
162 | |
163 | /* RX FIFO Overrun error status */ |
164 | #define TEGRA20_SPDIF_STATUS_RX_ERR (1 << 24) |
165 | |
166 | /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */ |
167 | #define TEGRA20_SPDIF_STATUS_IS_P (1 << 23) |
168 | |
169 | /* B-preamble detection status: 0=not detected, 1=B-preamble detected */ |
170 | #define TEGRA20_SPDIF_STATUS_IS_B (1 << 22) |
171 | |
172 | /* |
173 | * RX channel block data receive status: |
174 | * 0=entire block not recieved yet. |
175 | * 1=received entire block of channel status, |
176 | */ |
177 | #define TEGRA20_SPDIF_STATUS_IS_C (1 << 21) |
178 | |
179 | /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */ |
180 | #define TEGRA20_SPDIF_STATUS_IS_U (1 << 20) |
181 | |
182 | /* |
183 | * RX User FIFO Status: |
184 | * 1=attention level reached, 0=attention level not reached. |
185 | */ |
186 | #define TEGRA20_SPDIF_STATUS_QS_RU (1 << 19) |
187 | |
188 | /* |
189 | * TX User FIFO Status: |
190 | * 1=attention level reached, 0=attention level not reached. |
191 | */ |
192 | #define TEGRA20_SPDIF_STATUS_QS_TU (1 << 18) |
193 | |
194 | /* |
195 | * RX Data FIFO Status: |
196 | * 1=attention level reached, 0=attention level not reached. |
197 | */ |
198 | #define TEGRA20_SPDIF_STATUS_QS_RX (1 << 17) |
199 | |
200 | /* |
201 | * TX Data FIFO Status: |
202 | * 1=attention level reached, 0=attention level not reached. |
203 | */ |
204 | #define TEGRA20_SPDIF_STATUS_QS_TX (1 << 16) |
205 | |
206 | /* Fields in TEGRA20_SPDIF_STROBE_CTRL */ |
207 | |
208 | /* |
209 | * Indicates the approximate number of detected SPDIFIN clocks within a |
210 | * bi-phase period. |
211 | */ |
212 | #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16 |
213 | #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT) |
214 | |
215 | /* Data strobe mode: 0=Auto-locked 1=Manual locked */ |
216 | #define TEGRA20_SPDIF_STROBE_CTRL_STROBE (1 << 15) |
217 | |
218 | /* |
219 | * Manual data strobe time within the bi-phase clock period (in terms of |
220 | * the number of over-sampling clocks). |
221 | */ |
222 | #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8 |
223 | #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT) |
224 | |
225 | /* |
226 | * Manual SPDIFIN bi-phase clock period (in terms of the number of |
227 | * over-sampling clocks). |
228 | */ |
229 | #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0 |
230 | #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT) |
231 | |
232 | /* Fields in SPDIF_DATA_FIFO_CSR */ |
233 | |
234 | /* Clear Receiver User FIFO (RX USR.FIFO) */ |
235 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31) |
236 | |
237 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0 |
238 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1 |
239 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2 |
240 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3 |
241 | |
242 | /* RU FIFO attention level */ |
243 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29 |
244 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \ |
245 | (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) |
246 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \ |
247 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) |
248 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \ |
249 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) |
250 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \ |
251 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) |
252 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \ |
253 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT) |
254 | |
255 | /* Number of RX USR.FIFO levels with valid data. */ |
256 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24 |
257 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT) |
258 | |
259 | /* Clear Transmitter User FIFO (TX USR.FIFO) */ |
260 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23) |
261 | |
262 | /* TU FIFO attention level */ |
263 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21 |
264 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \ |
265 | (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) |
266 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \ |
267 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) |
268 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \ |
269 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) |
270 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \ |
271 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) |
272 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \ |
273 | (TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT) |
274 | |
275 | /* Number of TX USR.FIFO levels that could be filled. */ |
276 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16 |
277 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT) |
278 | |
279 | /* Clear Receiver Data FIFO (RX DATA.FIFO) */ |
280 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15) |
281 | |
282 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0 |
283 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1 |
284 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2 |
285 | #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3 |
286 | |
287 | /* RU FIFO attention level */ |
288 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13 |
289 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \ |
290 | (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) |
291 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \ |
292 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) |
293 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \ |
294 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) |
295 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \ |
296 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) |
297 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \ |
298 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT) |
299 | |
300 | /* Number of RX DATA.FIFO levels with valid data. */ |
301 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8 |
302 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT) |
303 | |
304 | /* Clear Transmitter Data FIFO (TX DATA.FIFO) */ |
305 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7) |
306 | |
307 | /* TU FIFO attention level */ |
308 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5 |
309 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \ |
310 | (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) |
311 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \ |
312 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) |
313 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \ |
314 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) |
315 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \ |
316 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) |
317 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \ |
318 | (TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT) |
319 | |
320 | /* Number of TX DATA.FIFO levels that could be filled. */ |
321 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0 |
322 | #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT) |
323 | |
324 | /* Fields in TEGRA20_SPDIF_DATA_OUT */ |
325 | |
326 | /* |
327 | * This register has 5 different formats: |
328 | * 16-bit (BIT_MODE=00, PACK=0) |
329 | * 20-bit (BIT_MODE=01, PACK=0) |
330 | * 24-bit (BIT_MODE=10, PACK=0) |
331 | * raw (BIT_MODE=11, PACK=0) |
332 | * 16-bit packed (BIT_MODE=00, PACK=1) |
333 | */ |
334 | |
335 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0 |
336 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT) |
337 | |
338 | #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0 |
339 | #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT) |
340 | |
341 | #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0 |
342 | #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT) |
343 | |
344 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31) |
345 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30) |
346 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29) |
347 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28) |
348 | |
349 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8 |
350 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT) |
351 | |
352 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4 |
353 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT) |
354 | |
355 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0 |
356 | #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT) |
357 | |
358 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16 |
359 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT) |
360 | |
361 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0 |
362 | #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT) |
363 | |
364 | /* Fields in TEGRA20_SPDIF_DATA_IN */ |
365 | |
366 | /* |
367 | * This register has 5 different formats: |
368 | * 16-bit (BIT_MODE=00, PACK=0) |
369 | * 20-bit (BIT_MODE=01, PACK=0) |
370 | * 24-bit (BIT_MODE=10, PACK=0) |
371 | * raw (BIT_MODE=11, PACK=0) |
372 | * 16-bit packed (BIT_MODE=00, PACK=1) |
373 | * |
374 | * Bits 31:24 are common to all modes except 16-bit packed |
375 | */ |
376 | |
377 | #define TEGRA20_SPDIF_DATA_IN_DATA_P (1 << 31) |
378 | #define TEGRA20_SPDIF_DATA_IN_DATA_C (1 << 30) |
379 | #define TEGRA20_SPDIF_DATA_IN_DATA_U (1 << 29) |
380 | #define TEGRA20_SPDIF_DATA_IN_DATA_V (1 << 28) |
381 | |
382 | #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24 |
383 | #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT) |
384 | |
385 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0 |
386 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT) |
387 | |
388 | #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0 |
389 | #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT) |
390 | |
391 | #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0 |
392 | #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT) |
393 | |
394 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8 |
395 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT) |
396 | |
397 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4 |
398 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT) |
399 | |
400 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0 |
401 | #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT) |
402 | |
403 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16 |
404 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT) |
405 | |
406 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0 |
407 | #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT) |
408 | |
409 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_A */ |
410 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_B */ |
411 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_C */ |
412 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_D */ |
413 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_E */ |
414 | /* Fields in TEGRA20_SPDIF_CH_STA_RX_F */ |
415 | |
416 | /* |
417 | * The 6-word receive channel data page buffer holds a block (192 frames) of |
418 | * channel status information. The order of receive is from LSB to MSB |
419 | * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A. |
420 | */ |
421 | |
422 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_A */ |
423 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_B */ |
424 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_C */ |
425 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_D */ |
426 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_E */ |
427 | /* Fields in TEGRA20_SPDIF_CH_STA_TX_F */ |
428 | |
429 | /* |
430 | * The 6-word transmit channel data page buffer holds a block (192 frames) of |
431 | * channel status information. The order of transmission is from LSB to MSB |
432 | * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A. |
433 | */ |
434 | |
435 | /* Fields in TEGRA20_SPDIF_USR_STA_RX_A */ |
436 | |
437 | /* |
438 | * This 4-word deep FIFO receives user FIFO field information. The order of |
439 | * receive is from LSB to MSB bit. |
440 | */ |
441 | |
442 | /* Fields in TEGRA20_SPDIF_USR_DAT_TX_A */ |
443 | |
444 | /* |
445 | * This 4-word deep FIFO transmits user FIFO field information. The order of |
446 | * transmission is from LSB to MSB bit. |
447 | */ |
448 | |
449 | struct tegra20_spdif { |
450 | struct clk *clk_spdif_out; |
451 | struct snd_dmaengine_dai_dma_data capture_dma_data; |
452 | struct snd_dmaengine_dai_dma_data playback_dma_data; |
453 | struct regmap *regmap; |
454 | struct reset_control *reset; |
455 | }; |
456 | |
457 | #endif |
458 | |