| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tegra210_adx.h - Definitions for Tegra210 ADX driver |
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| 4 | * |
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| 5 | * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __TEGRA210_ADX_H__ |
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| 10 | #define __TEGRA210_ADX_H__ |
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| 11 | |
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| 12 | /* Register offsets from TEGRA210_ADX*_BASE */ |
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| 13 | #define TEGRA210_ADX_RX_STATUS 0x0c |
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| 14 | #define TEGRA210_ADX_RX_INT_STATUS 0x10 |
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| 15 | #define TEGRA210_ADX_RX_INT_MASK 0x14 |
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| 16 | #define TEGRA210_ADX_RX_INT_SET 0x18 |
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| 17 | #define TEGRA210_ADX_RX_INT_CLEAR 0x1c |
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| 18 | #define TEGRA210_ADX_RX_CIF_CTRL 0x20 |
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| 19 | #define TEGRA210_ADX_TX_STATUS 0x4c |
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| 20 | #define TEGRA210_ADX_TX_INT_STATUS 0x50 |
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| 21 | #define TEGRA210_ADX_TX_INT_MASK 0x54 |
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| 22 | #define TEGRA210_ADX_TX_INT_SET 0x58 |
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| 23 | #define TEGRA210_ADX_TX_INT_CLEAR 0x5c |
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| 24 | #define TEGRA210_ADX_TX1_CIF_CTRL 0x60 |
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| 25 | #define TEGRA210_ADX_TX2_CIF_CTRL 0x64 |
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| 26 | #define TEGRA210_ADX_TX3_CIF_CTRL 0x68 |
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| 27 | #define TEGRA210_ADX_TX4_CIF_CTRL 0x6c |
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| 28 | #define TEGRA210_ADX_ENABLE 0x80 |
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| 29 | #define TEGRA210_ADX_SOFT_RESET 0x84 |
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| 30 | #define TEGRA210_ADX_CG 0x88 |
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| 31 | #define TEGRA210_ADX_STATUS 0x8c |
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| 32 | #define TEGRA210_ADX_INT_STATUS 0x90 |
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| 33 | #define TEGRA210_ADX_CTRL 0xa4 |
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| 34 | #define TEGRA210_ADX_IN_BYTE_EN0 0xa8 |
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| 35 | #define TEGRA210_ADX_IN_BYTE_EN1 0xac |
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| 36 | #define TEGRA210_ADX_CFG_RAM_CTRL 0xb8 |
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| 37 | #define TEGRA210_ADX_CFG_RAM_DATA 0xbc |
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| 38 | |
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| 39 | /* Fields in TEGRA210_ADX_ENABLE */ |
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| 40 | #define TEGRA210_ADX_ENABLE_SHIFT 0 |
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| 41 | |
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| 42 | /* Fields in TEGRA210_ADX_CFG_RAM_CTRL */ |
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| 43 | #define TEGRA210_ADX_CFG_RAM_CTRL_RAM_ADDR_SHIFT 0 |
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| 44 | |
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| 45 | #define TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT 14 |
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| 46 | #define TEGRA210_ADX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_ADX_CFG_RAM_CTRL_RW_SHIFT) |
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| 47 | |
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| 48 | #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 |
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| 49 | #define TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) |
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| 50 | |
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| 51 | #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 |
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| 52 | #define TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_ADX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) |
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| 53 | |
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| 54 | /* Fields in TEGRA210_ADX_SOFT_RESET */ |
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| 55 | #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT 0 |
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| 56 | #define TEGRA210_ADX_SOFT_RESET_SOFT_RESET_MASK (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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| 57 | #define TEGRA210_ADX_SOFT_RESET_SOFT_EN (1 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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| 58 | #define TEGRA210_ADX_SOFT_RESET_SOFT_DEFAULT (0 << TEGRA210_ADX_SOFT_RESET_SOFT_RESET_SHIFT) |
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| 59 | |
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| 60 | #define TEGRA210_ADX_AUDIOCIF_CH_STRIDE 4 |
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| 61 | #define TEGRA210_ADX_RAM_DEPTH 16 |
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| 62 | #define TEGRA210_ADX_MAP_STREAM_NUMBER_SHIFT 6 |
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| 63 | #define TEGRA210_ADX_MAP_WORD_NUMBER_SHIFT 2 |
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| 64 | #define TEGRA210_ADX_MAP_BYTE_NUMBER_SHIFT 0 |
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| 65 | |
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| 66 | struct tegra210_adx { |
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| 67 | struct regmap *regmap; |
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| 68 | unsigned int map[TEGRA210_ADX_RAM_DEPTH]; |
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| 69 | unsigned int byte_mask[2]; |
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| 70 | }; |
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| 71 | |
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| 72 | #endif |
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| 73 | |
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