1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * tegra210_ahub.h - TEGRA210 AHUB |
4 | * |
5 | * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. |
6 | * |
7 | */ |
8 | |
9 | #ifndef __TEGRA210_AHUB__H__ |
10 | #define __TEGRA210_AHUB__H__ |
11 | |
12 | /* Tegra210 specific */ |
13 | #define TEGRA210_XBAR_PART1_RX 0x200 |
14 | #define TEGRA210_XBAR_PART2_RX 0x400 |
15 | #define TEGRA210_XBAR_RX_STRIDE 0x4 |
16 | #define TEGRA210_XBAR_AUDIO_RX_COUNT 90 |
17 | #define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff |
18 | #define TEGRA210_XBAR_REG_MASK_1 0x3f30031f |
19 | #define TEGRA210_XBAR_REG_MASK_2 0xff1cf313 |
20 | #define TEGRA210_XBAR_REG_MASK_3 0x0 |
21 | #define TEGRA210_XBAR_UPDATE_MAX_REG 3 |
22 | /* Tegra186 specific */ |
23 | #define TEGRA186_XBAR_PART3_RX 0x600 |
24 | #define TEGRA186_XBAR_AUDIO_RX_COUNT 115 |
25 | #define TEGRA186_XBAR_REG_MASK_0 0xf3fffff |
26 | #define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f |
27 | #define TEGRA186_XBAR_REG_MASK_2 0xff3cf311 |
28 | #define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff |
29 | #define TEGRA186_XBAR_UPDATE_MAX_REG 4 |
30 | |
31 | #define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA186_XBAR_UPDATE_MAX_REG) |
32 | |
33 | #define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \ |
34 | (TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1))) |
35 | |
36 | #define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \ |
37 | (TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1))) |
38 | |
39 | #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id)) |
40 | |
41 | #define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32) |
42 | |
43 | #define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \ |
44 | { \ |
45 | .reg = xreg, \ |
46 | .shift_l = shift, \ |
47 | .shift_r = shift, \ |
48 | .items = xmax, \ |
49 | .texts = xtexts, \ |
50 | .values = xvalues, \ |
51 | .mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \ |
52 | } |
53 | |
54 | #define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \ |
55 | static struct soc_enum name = \ |
56 | SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \ |
57 | xtexts, xvalues) |
58 | |
59 | #define MUX_ENUM_CTRL_DECL(ename, id) \ |
60 | SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \ |
61 | tegra210_ahub_mux_texts, \ |
62 | tegra210_ahub_mux_values); \ |
63 | static const struct snd_kcontrol_new ename##_control = \ |
64 | SOC_DAPM_ENUM_EXT("Route", ename##_enum, \ |
65 | tegra_ahub_get_value_enum, \ |
66 | tegra_ahub_put_value_enum) |
67 | |
68 | #define MUX_ENUM_CTRL_DECL_186(ename, id) \ |
69 | SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \ |
70 | tegra186_ahub_mux_texts, \ |
71 | tegra186_ahub_mux_values); \ |
72 | static const struct snd_kcontrol_new ename##_control = \ |
73 | SOC_DAPM_ENUM_EXT("Route", ename##_enum, \ |
74 | tegra_ahub_get_value_enum, \ |
75 | tegra_ahub_put_value_enum) |
76 | |
77 | #define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id) |
78 | |
79 | #define WIDGETS(sname, ename) \ |
80 | SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ |
81 | SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \ |
82 | SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \ |
83 | &ename##_control) |
84 | |
85 | #define TX_WIDGETS(sname) \ |
86 | SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \ |
87 | SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0) |
88 | |
89 | #define DAI(sname) \ |
90 | { \ |
91 | .name = "XBAR-" #sname, \ |
92 | .playback = { \ |
93 | .stream_name = #sname " XBAR-Playback", \ |
94 | .channels_min = 1, \ |
95 | .channels_max = 16, \ |
96 | .rates = SNDRV_PCM_RATE_8000_192000, \ |
97 | .formats = SNDRV_PCM_FMTBIT_S8 | \ |
98 | SNDRV_PCM_FMTBIT_S16_LE | \ |
99 | SNDRV_PCM_FMTBIT_S24_LE | \ |
100 | SNDRV_PCM_FMTBIT_S32_LE, \ |
101 | }, \ |
102 | .capture = { \ |
103 | .stream_name = #sname " XBAR-Capture", \ |
104 | .channels_min = 1, \ |
105 | .channels_max = 16, \ |
106 | .rates = SNDRV_PCM_RATE_8000_192000, \ |
107 | .formats = SNDRV_PCM_FMTBIT_S8 | \ |
108 | SNDRV_PCM_FMTBIT_S16_LE | \ |
109 | SNDRV_PCM_FMTBIT_S24_LE | \ |
110 | SNDRV_PCM_FMTBIT_S32_LE, \ |
111 | }, \ |
112 | } |
113 | |
114 | struct tegra_ahub_soc_data { |
115 | const struct regmap_config *regmap_config; |
116 | const struct snd_soc_component_driver *cmpnt_drv; |
117 | struct snd_soc_dai_driver *dai_drv; |
118 | unsigned int mask[4]; |
119 | unsigned int reg_count; |
120 | unsigned int num_dais; |
121 | }; |
122 | |
123 | struct tegra_ahub { |
124 | const struct tegra_ahub_soc_data *soc_data; |
125 | struct regmap *regmap; |
126 | struct clk *clk; |
127 | }; |
128 | |
129 | #endif |
130 | |