| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tegra210_sfc.h - Definitions for Tegra210 SFC driver |
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| 4 | * |
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| 5 | * Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved. |
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| 6 | * |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef __TEGRA210_SFC_H__ |
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| 10 | #define __TEGRA210_SFC_H__ |
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| 11 | |
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| 12 | /* |
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| 13 | * SFC_RX registers are with respect to XBAR. |
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| 14 | * The data comes from XBAR to SFC. |
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| 15 | */ |
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| 16 | #define TEGRA210_SFC_RX_STATUS 0x0c |
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| 17 | #define TEGRA210_SFC_RX_INT_STATUS 0x10 |
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| 18 | #define TEGRA210_SFC_RX_INT_MASK 0x14 |
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| 19 | #define TEGRA210_SFC_RX_INT_SET 0x18 |
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| 20 | #define TEGRA210_SFC_RX_INT_CLEAR 0x1c |
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| 21 | #define TEGRA210_SFC_RX_CIF_CTRL 0x20 |
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| 22 | #define TEGRA210_SFC_RX_FREQ 0x24 |
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| 23 | |
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| 24 | /* |
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| 25 | * SFC_TX registers are with respect to XBAR. |
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| 26 | * The data goes out of SFC. |
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| 27 | */ |
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| 28 | #define TEGRA210_SFC_TX_STATUS 0x4c |
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| 29 | #define TEGRA210_SFC_TX_INT_STATUS 0x50 |
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| 30 | #define TEGRA210_SFC_TX_INT_MASK 0x54 |
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| 31 | #define TEGRA210_SFC_TX_INT_SET 0x58 |
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| 32 | #define TEGRA210_SFC_TX_INT_CLEAR 0x5c |
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| 33 | #define TEGRA210_SFC_TX_CIF_CTRL 0x60 |
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| 34 | #define TEGRA210_SFC_TX_FREQ 0x64 |
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| 35 | |
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| 36 | /* Register offsets from TEGRA210_SFC*_BASE */ |
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| 37 | #define TEGRA210_SFC_ENABLE 0x80 |
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| 38 | #define TEGRA210_SFC_SOFT_RESET 0x84 |
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| 39 | #define TEGRA210_SFC_CG 0x88 |
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| 40 | #define TEGRA210_SFC_STATUS 0x8c |
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| 41 | #define TEGRA210_SFC_INT_STATUS 0x90 |
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| 42 | #define TEGRA210_SFC_COEF_RAM 0xbc |
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| 43 | #define TEGRA210_SFC_CFG_RAM_CTRL 0xc0 |
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| 44 | #define TEGRA210_SFC_CFG_RAM_DATA 0xc4 |
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| 45 | |
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| 46 | /* Fields in TEGRA210_SFC_ENABLE */ |
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| 47 | #define TEGRA210_SFC_EN_SHIFT 0 |
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| 48 | #define TEGRA210_SFC_EN (1 << TEGRA210_SFC_EN_SHIFT) |
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| 49 | |
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| 50 | #define TEGRA210_SFC_NUM_RATES 13 |
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| 51 | |
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| 52 | /* Fields in TEGRA210_SFC_COEF_RAM */ |
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| 53 | #define TEGRA210_SFC_COEF_RAM_EN BIT(0) |
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| 54 | |
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| 55 | #define TEGRA210_SFC_SOFT_RESET_EN BIT(0) |
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| 56 | |
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| 57 | /* Coefficients */ |
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| 58 | #define TEGRA210_SFC_COEF_RAM_DEPTH 64 |
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| 59 | #define TEGRA210_SFC_RAM_CTRL_RW_WRITE (1 << 14) |
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| 60 | #define TEGRA210_SFC_RAM_CTRL_ADDR_INIT_EN (1 << 13) |
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| 61 | #define TEGRA210_SFC_RAM_CTRL_SEQ_ACCESS_EN (1 << 12) |
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| 62 | |
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| 63 | |
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| 64 | enum tegra210_sfc_path { |
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| 65 | SFC_RX_PATH, |
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| 66 | SFC_TX_PATH, |
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| 67 | SFC_PATHS, |
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| 68 | }; |
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| 69 | |
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| 70 | struct tegra210_sfc { |
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| 71 | unsigned int mono_to_stereo[SFC_PATHS]; |
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| 72 | unsigned int stereo_to_mono[SFC_PATHS]; |
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| 73 | unsigned int srate_out; |
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| 74 | unsigned int srate_in; |
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| 75 | struct regmap *regmap; |
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| 76 | }; |
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| 77 | |
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| 78 | #endif |
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| 79 | |
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