| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * tegra30_ahub.h - Definitions for Tegra30 AHUB driver |
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| 4 | * |
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| 5 | * Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved. |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __TEGRA30_AHUB_H__ |
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| 9 | #define __TEGRA30_AHUB_H__ |
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| 10 | |
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| 11 | /* Fields in *_CIF_RX/TX_CTRL; used by AHUB FIFOs, and all other audio modules */ |
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| 12 | |
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| 13 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 28 |
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| 14 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0xf |
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| 15 | #define TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
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| 16 | |
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| 17 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT 24 |
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| 18 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US 0x3f |
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| 19 | #define TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK (TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US << TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
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| 20 | |
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| 21 | /* Channel count minus 1 */ |
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| 22 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 24 |
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| 23 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 7 |
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| 24 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
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| 25 | |
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| 26 | /* Channel count minus 1 */ |
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| 27 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT 20 |
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| 28 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US 0xf |
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| 29 | #define TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK (TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US << TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
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| 30 | |
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| 31 | /* Channel count minus 1 */ |
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| 32 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 |
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| 33 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 7 |
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| 34 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
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| 35 | |
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| 36 | /* Channel count minus 1 */ |
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| 37 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT 16 |
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| 38 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US 0xf |
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| 39 | #define TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK (TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
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| 40 | |
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| 41 | #define TEGRA30_AUDIOCIF_BITS_4 0 |
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| 42 | #define TEGRA30_AUDIOCIF_BITS_8 1 |
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| 43 | #define TEGRA30_AUDIOCIF_BITS_12 2 |
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| 44 | #define TEGRA30_AUDIOCIF_BITS_16 3 |
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| 45 | #define TEGRA30_AUDIOCIF_BITS_20 4 |
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| 46 | #define TEGRA30_AUDIOCIF_BITS_24 5 |
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| 47 | #define TEGRA30_AUDIOCIF_BITS_28 6 |
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| 48 | #define TEGRA30_AUDIOCIF_BITS_32 7 |
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| 49 | |
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| 50 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT 12 |
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| 51 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 52 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 53 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 54 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 55 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 56 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 57 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 58 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 59 | #define TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT) |
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| 60 | |
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| 61 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT 8 |
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| 62 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK (7 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 63 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4 (TEGRA30_AUDIOCIF_BITS_4 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 64 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8 (TEGRA30_AUDIOCIF_BITS_8 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 65 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12 (TEGRA30_AUDIOCIF_BITS_12 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 66 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16 (TEGRA30_AUDIOCIF_BITS_16 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 67 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20 (TEGRA30_AUDIOCIF_BITS_20 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 68 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24 (TEGRA30_AUDIOCIF_BITS_24 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 69 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28 (TEGRA30_AUDIOCIF_BITS_28 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 70 | #define TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32 (TEGRA30_AUDIOCIF_BITS_32 << TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT) |
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| 71 | |
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| 72 | #define TEGRA30_AUDIOCIF_EXPAND_ZERO 0 |
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| 73 | #define TEGRA30_AUDIOCIF_EXPAND_ONE 1 |
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| 74 | #define TEGRA30_AUDIOCIF_EXPAND_LFSR 2 |
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| 75 | |
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| 76 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT 6 |
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| 77 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK (3 << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
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| 78 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO (TEGRA30_AUDIOCIF_EXPAND_ZERO << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
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| 79 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE (TEGRA30_AUDIOCIF_EXPAND_ONE << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
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| 80 | #define TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR (TEGRA30_AUDIOCIF_EXPAND_LFSR << TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT) |
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| 81 | |
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| 82 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH0 0 |
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| 83 | #define TEGRA30_AUDIOCIF_STEREO_CONV_CH1 1 |
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| 84 | #define TEGRA30_AUDIOCIF_STEREO_CONV_AVG 2 |
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| 85 | |
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| 86 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT 4 |
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| 87 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK (3 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
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| 88 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0 (TEGRA30_AUDIOCIF_STEREO_CONV_CH0 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
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| 89 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1 (TEGRA30_AUDIOCIF_STEREO_CONV_CH1 << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
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| 90 | #define TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG (TEGRA30_AUDIOCIF_STEREO_CONV_AVG << TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT) |
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| 91 | |
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| 92 | #define TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT 3 |
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| 93 | |
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| 94 | #define TEGRA30_AUDIOCIF_DIRECTION_TX 0 |
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| 95 | #define TEGRA30_AUDIOCIF_DIRECTION_RX 1 |
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| 96 | |
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| 97 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT 2 |
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| 98 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK (1 << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
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| 99 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX (TEGRA30_AUDIOCIF_DIRECTION_TX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
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| 100 | #define TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX (TEGRA30_AUDIOCIF_DIRECTION_RX << TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT) |
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| 101 | |
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| 102 | #define TEGRA30_AUDIOCIF_TRUNCATE_ROUND 0 |
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| 103 | #define TEGRA30_AUDIOCIF_TRUNCATE_CHOP 1 |
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| 104 | |
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| 105 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT 1 |
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| 106 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK (1 << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
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| 107 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND (TEGRA30_AUDIOCIF_TRUNCATE_ROUND << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
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| 108 | #define TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP (TEGRA30_AUDIOCIF_TRUNCATE_CHOP << TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT) |
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| 109 | |
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| 110 | #define TEGRA30_AUDIOCIF_MONO_CONV_ZERO 0 |
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| 111 | #define TEGRA30_AUDIOCIF_MONO_CONV_COPY 1 |
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| 112 | |
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| 113 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT 0 |
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| 114 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK (1 << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
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| 115 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO (TEGRA30_AUDIOCIF_MONO_CONV_ZERO << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
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| 116 | #define TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY (TEGRA30_AUDIOCIF_MONO_CONV_COPY << TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT) |
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| 117 | |
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| 118 | /* Registers within TEGRA30_AUDIO_CLUSTER_BASE */ |
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| 119 | |
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| 120 | /* TEGRA30_AHUB_CHANNEL_CTRL */ |
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| 121 | |
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| 122 | #define TEGRA30_AHUB_CHANNEL_CTRL 0x0 |
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| 123 | #define TEGRA30_AHUB_CHANNEL_CTRL_STRIDE 0x20 |
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| 124 | #define TEGRA30_AHUB_CHANNEL_CTRL_COUNT 4 |
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| 125 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_EN (1 << 31) |
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| 126 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_EN (1 << 30) |
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| 127 | #define TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK (1 << 29) |
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| 128 | |
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| 129 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT 16 |
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| 130 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US 0xff |
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| 131 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT) |
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| 132 | |
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| 133 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT 8 |
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| 134 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US 0xff |
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| 135 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT) |
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| 136 | |
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| 137 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN (1 << 6) |
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| 138 | |
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| 139 | #define TEGRA30_PACK_8_4 2 |
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| 140 | #define TEGRA30_PACK_16 3 |
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| 141 | |
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| 142 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT 4 |
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| 143 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US 3 |
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| 144 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
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| 145 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
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| 146 | #define TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT) |
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| 147 | |
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| 148 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN (1 << 2) |
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| 149 | |
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| 150 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT 0 |
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| 151 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US 3 |
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| 152 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK (TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
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| 153 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4 (TEGRA30_PACK_8_4 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
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| 154 | #define TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16 (TEGRA30_PACK_16 << TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT) |
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| 155 | |
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| 156 | /* TEGRA30_AHUB_CHANNEL_CLEAR */ |
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| 157 | |
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| 158 | #define TEGRA30_AHUB_CHANNEL_CLEAR 0x4 |
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| 159 | #define TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE 0x20 |
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| 160 | #define TEGRA30_AHUB_CHANNEL_CLEAR_COUNT 4 |
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| 161 | #define TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET (1 << 31) |
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| 162 | #define TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET (1 << 30) |
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| 163 | |
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| 164 | /* TEGRA30_AHUB_CHANNEL_STATUS */ |
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| 165 | |
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| 166 | #define TEGRA30_AHUB_CHANNEL_STATUS 0x8 |
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| 167 | #define TEGRA30_AHUB_CHANNEL_STATUS_STRIDE 0x20 |
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| 168 | #define TEGRA30_AHUB_CHANNEL_STATUS_COUNT 4 |
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| 169 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT 24 |
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| 170 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US 0xff |
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| 171 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT) |
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| 172 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT 16 |
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| 173 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US 0xff |
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| 174 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK (TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US << TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT) |
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| 175 | #define TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG (1 << 1) |
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| 176 | #define TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG (1 << 0) |
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| 177 | |
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| 178 | /* TEGRA30_AHUB_CHANNEL_TXFIFO */ |
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| 179 | |
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| 180 | #define TEGRA30_AHUB_CHANNEL_TXFIFO 0xc |
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| 181 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE 0x20 |
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| 182 | #define TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT 4 |
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| 183 | |
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| 184 | /* TEGRA30_AHUB_CHANNEL_RXFIFO */ |
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| 185 | |
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| 186 | #define TEGRA30_AHUB_CHANNEL_RXFIFO 0x10 |
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| 187 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE 0x20 |
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| 188 | #define TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT 4 |
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| 189 | |
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| 190 | /* TEGRA30_AHUB_CIF_TX_CTRL */ |
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| 191 | |
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| 192 | #define TEGRA30_AHUB_CIF_TX_CTRL 0x14 |
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| 193 | #define TEGRA30_AHUB_CIF_TX_CTRL_STRIDE 0x20 |
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| 194 | #define TEGRA30_AHUB_CIF_TX_CTRL_COUNT 4 |
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| 195 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ |
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| 196 | |
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| 197 | /* TEGRA30_AHUB_CIF_RX_CTRL */ |
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| 198 | |
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| 199 | #define TEGRA30_AHUB_CIF_RX_CTRL 0x18 |
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| 200 | #define TEGRA30_AHUB_CIF_RX_CTRL_STRIDE 0x20 |
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| 201 | #define TEGRA30_AHUB_CIF_RX_CTRL_COUNT 4 |
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| 202 | /* Uses field from TEGRA30_AUDIOCIF_CTRL_* */ |
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| 203 | |
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| 204 | /* TEGRA30_AHUB_CONFIG_LINK_CTRL */ |
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| 205 | |
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| 206 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL 0x80 |
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| 207 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT 28 |
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| 208 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US 0xf |
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| 209 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT) |
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| 210 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT 16 |
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| 211 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US 0xfff |
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| 212 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT) |
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| 213 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT 4 |
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| 214 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US 0xfff |
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| 215 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK (TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US << TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT) |
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| 216 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN (1 << 2) |
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| 217 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR (1 << 1) |
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| 218 | #define TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET (1 << 0) |
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| 219 | |
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| 220 | /* TEGRA30_AHUB_MISC_CTRL */ |
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| 221 | |
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| 222 | #define TEGRA30_AHUB_MISC_CTRL 0x84 |
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| 223 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE (1 << 31) |
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| 224 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN (1 << 8) |
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| 225 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT 0 |
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| 226 | #define TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK (0x1f << TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT) |
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| 227 | |
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| 228 | /* TEGRA30_AHUB_APBDMA_LIVE_STATUS */ |
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| 229 | |
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| 230 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS 0x88 |
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| 231 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL (1 << 31) |
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| 232 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL (1 << 30) |
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| 233 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL (1 << 29) |
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| 234 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL (1 << 28) |
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| 235 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL (1 << 27) |
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| 236 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL (1 << 26) |
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| 237 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL (1 << 25) |
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| 238 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL (1 << 24) |
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| 239 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY (1 << 23) |
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| 240 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY (1 << 22) |
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| 241 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY (1 << 21) |
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| 242 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY (1 << 20) |
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| 243 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY (1 << 19) |
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| 244 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY (1 << 18) |
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| 245 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY (1 << 17) |
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| 246 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY (1 << 16) |
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| 247 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL (1 << 15) |
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| 248 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL (1 << 14) |
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| 249 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL (1 << 13) |
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| 250 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL (1 << 12) |
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| 251 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL (1 << 11) |
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| 252 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL (1 << 10) |
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| 253 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL (1 << 9) |
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| 254 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL (1 << 8) |
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| 255 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY (1 << 7) |
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| 256 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY (1 << 6) |
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| 257 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY (1 << 5) |
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| 258 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY (1 << 4) |
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| 259 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY (1 << 3) |
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| 260 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY (1 << 2) |
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| 261 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY (1 << 1) |
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| 262 | #define TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY (1 << 0) |
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| 263 | |
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| 264 | /* TEGRA30_AHUB_I2S_LIVE_STATUS */ |
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| 265 | |
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| 266 | #define TEGRA30_AHUB_I2S_LIVE_STATUS 0x8c |
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| 267 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL (1 << 29) |
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| 268 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL (1 << 28) |
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| 269 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL (1 << 27) |
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| 270 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL (1 << 26) |
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| 271 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL (1 << 25) |
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| 272 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL (1 << 24) |
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| 273 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL (1 << 23) |
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| 274 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL (1 << 22) |
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| 275 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL (1 << 21) |
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| 276 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL (1 << 20) |
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| 277 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED (1 << 19) |
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| 278 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED (1 << 18) |
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| 279 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED (1 << 17) |
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| 280 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED (1 << 16) |
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| 281 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED (1 << 15) |
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| 282 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED (1 << 14) |
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| 283 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED (1 << 13) |
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| 284 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED (1 << 12) |
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| 285 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED (1 << 11) |
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| 286 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED (1 << 10) |
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| 287 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY (1 << 9) |
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| 288 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY (1 << 8) |
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| 289 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY (1 << 7) |
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| 290 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY (1 << 6) |
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| 291 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY (1 << 5) |
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| 292 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY (1 << 4) |
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| 293 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY (1 << 3) |
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| 294 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY (1 << 2) |
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| 295 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY (1 << 1) |
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| 296 | #define TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY (1 << 0) |
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| 297 | |
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| 298 | /* TEGRA30_AHUB_DAM0_LIVE_STATUS */ |
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| 299 | |
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| 300 | #define TEGRA30_AHUB_DAM_LIVE_STATUS 0x90 |
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| 301 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE 0x8 |
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| 302 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT 3 |
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| 303 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED (1 << 26) |
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| 304 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED (1 << 25) |
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| 305 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED (1 << 24) |
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| 306 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL (1 << 15) |
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| 307 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL (1 << 9) |
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| 308 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL (1 << 8) |
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| 309 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY (1 << 7) |
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| 310 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY (1 << 1) |
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| 311 | #define TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY (1 << 0) |
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| 312 | |
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| 313 | /* TEGRA30_AHUB_SPDIF_LIVE_STATUS */ |
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| 314 | |
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| 315 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS 0xa8 |
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| 316 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED (1 << 11) |
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| 317 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED (1 << 10) |
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| 318 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED (1 << 9) |
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| 319 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED (1 << 8) |
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| 320 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL (1 << 7) |
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| 321 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL (1 << 6) |
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| 322 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL (1 << 5) |
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| 323 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL (1 << 4) |
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| 324 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY (1 << 3) |
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| 325 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY (1 << 2) |
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| 326 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY (1 << 1) |
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| 327 | #define TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY (1 << 0) |
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| 328 | |
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| 329 | /* TEGRA30_AHUB_I2S_INT_MASK */ |
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| 330 | |
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| 331 | #define TEGRA30_AHUB_I2S_INT_MASK 0xb0 |
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| 332 | |
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| 333 | /* TEGRA30_AHUB_DAM_INT_MASK */ |
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| 334 | |
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| 335 | #define TEGRA30_AHUB_DAM_INT_MASK 0xb4 |
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| 336 | |
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| 337 | /* TEGRA30_AHUB_SPDIF_INT_MASK */ |
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| 338 | |
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| 339 | #define TEGRA30_AHUB_SPDIF_INT_MASK 0xbc |
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| 340 | |
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| 341 | /* TEGRA30_AHUB_APBIF_INT_MASK */ |
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| 342 | |
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| 343 | #define TEGRA30_AHUB_APBIF_INT_MASK 0xc0 |
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| 344 | |
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| 345 | /* TEGRA30_AHUB_I2S_INT_STATUS */ |
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| 346 | |
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| 347 | #define TEGRA30_AHUB_I2S_INT_STATUS 0xc8 |
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| 348 | |
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| 349 | /* TEGRA30_AHUB_DAM_INT_STATUS */ |
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| 350 | |
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| 351 | #define TEGRA30_AHUB_DAM_INT_STATUS 0xcc |
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| 352 | |
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| 353 | /* TEGRA30_AHUB_SPDIF_INT_STATUS */ |
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| 354 | |
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| 355 | #define TEGRA30_AHUB_SPDIF_INT_STATUS 0xd4 |
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| 356 | |
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| 357 | /* TEGRA30_AHUB_APBIF_INT_STATUS */ |
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| 358 | |
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| 359 | #define TEGRA30_AHUB_APBIF_INT_STATUS 0xd8 |
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| 360 | |
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| 361 | /* TEGRA30_AHUB_I2S_INT_SOURCE */ |
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| 362 | |
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| 363 | #define TEGRA30_AHUB_I2S_INT_SOURCE 0xe0 |
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| 364 | |
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| 365 | /* TEGRA30_AHUB_DAM_INT_SOURCE */ |
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| 366 | |
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| 367 | #define TEGRA30_AHUB_DAM_INT_SOURCE 0xe4 |
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| 368 | |
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| 369 | /* TEGRA30_AHUB_SPDIF_INT_SOURCE */ |
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| 370 | |
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| 371 | #define TEGRA30_AHUB_SPDIF_INT_SOURCE 0xec |
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| 372 | |
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| 373 | /* TEGRA30_AHUB_APBIF_INT_SOURCE */ |
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| 374 | |
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| 375 | #define TEGRA30_AHUB_APBIF_INT_SOURCE 0xf0 |
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| 376 | |
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| 377 | /* TEGRA30_AHUB_I2S_INT_SET */ |
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| 378 | |
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| 379 | #define TEGRA30_AHUB_I2S_INT_SET 0xf8 |
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| 380 | |
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| 381 | /* TEGRA30_AHUB_DAM_INT_SET */ |
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| 382 | |
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| 383 | #define TEGRA30_AHUB_DAM_INT_SET 0xfc |
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| 384 | |
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| 385 | /* TEGRA30_AHUB_SPDIF_INT_SET */ |
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| 386 | |
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| 387 | #define TEGRA30_AHUB_SPDIF_INT_SET 0x100 |
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| 388 | |
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| 389 | /* TEGRA30_AHUB_APBIF_INT_SET */ |
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| 390 | |
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| 391 | #define TEGRA30_AHUB_APBIF_INT_SET 0x104 |
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| 392 | |
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| 393 | /* Registers within TEGRA30_AHUB_BASE */ |
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| 394 | |
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| 395 | #define TEGRA30_AHUB_AUDIO_RX 0x0 |
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| 396 | #define TEGRA30_AHUB_AUDIO_RX_STRIDE 0x4 |
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| 397 | #define TEGRA30_AHUB_AUDIO_RX_COUNT 17 |
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| 398 | /* This register repeats once for each entry in enum tegra30_ahub_rxcif */ |
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| 399 | /* The fields in this register are 1 bit per entry in tegra30_ahub_txcif */ |
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| 400 | |
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| 401 | /* |
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| 402 | * Terminology: |
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| 403 | * AHUB: Audio Hub; a cross-bar switch between the audio devices: DMA FIFOs, |
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| 404 | * I2S controllers, SPDIF controllers, and DAMs. |
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| 405 | * XBAR: The core cross-bar component of the AHUB. |
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| 406 | * CIF: Client Interface; the HW module connecting an audio device to the |
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| 407 | * XBAR. |
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| 408 | * DAM: Digital Audio Mixer: A HW module that mixes multiple audio streams, |
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| 409 | * possibly including sample-rate conversion. |
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| 410 | * |
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| 411 | * Each TX CIF transmits data into the XBAR. Each RX CIF can receive audio |
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| 412 | * transmitted by a particular TX CIF. |
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| 413 | * |
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| 414 | * This driver is currently very simplistic; many HW features are not |
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| 415 | * exposed; DAMs are not supported, only 16-bit stereo audio is supported, |
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| 416 | * etc. |
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| 417 | */ |
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| 418 | |
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| 419 | enum tegra30_ahub_txcif { |
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| 420 | TEGRA30_AHUB_TXCIF_APBIF_TX0, |
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| 421 | TEGRA30_AHUB_TXCIF_APBIF_TX1, |
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| 422 | TEGRA30_AHUB_TXCIF_APBIF_TX2, |
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| 423 | TEGRA30_AHUB_TXCIF_APBIF_TX3, |
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| 424 | TEGRA30_AHUB_TXCIF_I2S0_TX0, |
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| 425 | TEGRA30_AHUB_TXCIF_I2S1_TX0, |
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| 426 | TEGRA30_AHUB_TXCIF_I2S2_TX0, |
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| 427 | TEGRA30_AHUB_TXCIF_I2S3_TX0, |
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| 428 | TEGRA30_AHUB_TXCIF_I2S4_TX0, |
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| 429 | TEGRA30_AHUB_TXCIF_DAM0_TX0, |
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| 430 | TEGRA30_AHUB_TXCIF_DAM1_TX0, |
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| 431 | TEGRA30_AHUB_TXCIF_DAM2_TX0, |
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| 432 | TEGRA30_AHUB_TXCIF_SPDIF_TX0, |
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| 433 | TEGRA30_AHUB_TXCIF_SPDIF_TX1, |
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| 434 | }; |
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| 435 | |
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| 436 | enum tegra30_ahub_rxcif { |
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| 437 | TEGRA30_AHUB_RXCIF_APBIF_RX0, |
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| 438 | TEGRA30_AHUB_RXCIF_APBIF_RX1, |
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| 439 | TEGRA30_AHUB_RXcIF_APBIF_RX2, |
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| 440 | TEGRA30_AHUB_RXCIF_APBIF_RX3, |
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| 441 | TEGRA30_AHUB_RXCIF_I2S0_RX0, |
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| 442 | TEGRA30_AHUB_RXCIF_I2S1_RX0, |
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| 443 | TEGRA30_AHUB_RXCIF_I2S2_RX0, |
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| 444 | TEGRA30_AHUB_RXCIF_I2S3_RX0, |
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| 445 | TEGRA30_AHUB_RXCIF_I2S4_RX0, |
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| 446 | TEGRA30_AHUB_RXCIF_DAM0_RX0, |
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| 447 | TEGRA30_AHUB_RXCIF_DAM0_RX1, |
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| 448 | TEGRA30_AHUB_RXCIF_DAM1_RX0, |
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| 449 | TEGRA30_AHUB_RXCIF_DAM2_RX1, |
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| 450 | TEGRA30_AHUB_RXCIF_DAM3_RX0, |
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| 451 | TEGRA30_AHUB_RXCIF_DAM3_RX1, |
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| 452 | TEGRA30_AHUB_RXCIF_SPDIF_RX0, |
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| 453 | TEGRA30_AHUB_RXCIF_SPDIF_RX1, |
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| 454 | }; |
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| 455 | |
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| 456 | extern int tegra30_ahub_allocate_rx_fifo(enum tegra30_ahub_rxcif *rxcif, |
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| 457 | char *dmachan, int dmachan_len, |
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| 458 | dma_addr_t *fiforeg); |
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| 459 | extern int tegra30_ahub_enable_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
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| 460 | extern int tegra30_ahub_disable_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
|---|
| 461 | extern int tegra30_ahub_free_rx_fifo(enum tegra30_ahub_rxcif rxcif); |
|---|
| 462 | |
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| 463 | extern int tegra30_ahub_allocate_tx_fifo(enum tegra30_ahub_txcif *txcif, |
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| 464 | char *dmachan, int dmachan_len, |
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| 465 | dma_addr_t *fiforeg); |
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| 466 | extern int tegra30_ahub_enable_tx_fifo(enum tegra30_ahub_txcif txcif); |
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| 467 | extern int tegra30_ahub_disable_tx_fifo(enum tegra30_ahub_txcif txcif); |
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| 468 | extern int tegra30_ahub_free_tx_fifo(enum tegra30_ahub_txcif txcif); |
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| 469 | |
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| 470 | extern int tegra30_ahub_set_rx_cif_source(enum tegra30_ahub_rxcif rxcif, |
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| 471 | enum tegra30_ahub_txcif txcif); |
|---|
| 472 | extern int tegra30_ahub_unset_rx_cif_source(enum tegra30_ahub_rxcif rxcif); |
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| 473 | |
|---|
| 474 | struct tegra30_ahub_cif_conf { |
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| 475 | unsigned int threshold; |
|---|
| 476 | unsigned int audio_channels; |
|---|
| 477 | unsigned int client_channels; |
|---|
| 478 | unsigned int audio_bits; |
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| 479 | unsigned int client_bits; |
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| 480 | unsigned int expand; |
|---|
| 481 | unsigned int stereo_conv; |
|---|
| 482 | unsigned int replicate; |
|---|
| 483 | unsigned int direction; |
|---|
| 484 | unsigned int truncate; |
|---|
| 485 | unsigned int mono_conv; |
|---|
| 486 | }; |
|---|
| 487 | |
|---|
| 488 | void tegra30_ahub_set_cif(struct regmap *regmap, unsigned int reg, |
|---|
| 489 | struct tegra30_ahub_cif_conf *conf); |
|---|
| 490 | void tegra124_ahub_set_cif(struct regmap *regmap, unsigned int reg, |
|---|
| 491 | struct tegra30_ahub_cif_conf *conf); |
|---|
| 492 | |
|---|
| 493 | struct tegra30_ahub_soc_data { |
|---|
| 494 | unsigned int num_resets; |
|---|
| 495 | void (*set_audio_cif)(struct regmap *regmap, |
|---|
| 496 | unsigned int reg, |
|---|
| 497 | struct tegra30_ahub_cif_conf *conf); |
|---|
| 498 | /* |
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| 499 | * FIXME: There are many more differences in HW, such as: |
|---|
| 500 | * - More APBIF channels. |
|---|
| 501 | * - Extra separate chunks of register address space to represent |
|---|
| 502 | * the extra APBIF channels. |
|---|
| 503 | * - More units connected to the AHUB, so that tegra30_ahub_[rt]xcif |
|---|
| 504 | * need expansion, coupled with there being more defined bits in |
|---|
| 505 | * the AHUB routing registers. |
|---|
| 506 | * However, the driver doesn't support those new features yet, so we |
|---|
| 507 | * don't represent them here yet. |
|---|
| 508 | */ |
|---|
| 509 | }; |
|---|
| 510 | |
|---|
| 511 | struct tegra30_ahub { |
|---|
| 512 | const struct tegra30_ahub_soc_data *soc_data; |
|---|
| 513 | struct device *dev; |
|---|
| 514 | struct reset_control_bulk_data resets[21]; |
|---|
| 515 | unsigned int nresets; |
|---|
| 516 | struct clk_bulk_data clocks[2]; |
|---|
| 517 | unsigned int nclocks; |
|---|
| 518 | resource_size_t apbif_addr; |
|---|
| 519 | struct regmap *regmap_apbif; |
|---|
| 520 | struct regmap *regmap_ahub; |
|---|
| 521 | DECLARE_BITMAP(rx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
|---|
| 522 | DECLARE_BITMAP(tx_usage, TEGRA30_AHUB_CHANNEL_CTRL_COUNT); |
|---|
| 523 | }; |
|---|
| 524 | |
|---|
| 525 | #endif |
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| 526 | |
|---|
