1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright 2022, Kajol Jain, IBM Corp. |
4 | */ |
5 | |
6 | #include <stdio.h> |
7 | #include <stdlib.h> |
8 | |
9 | #include "../event.h" |
10 | #include "utils.h" |
11 | #include "../sampling_tests/misc.h" |
12 | |
13 | /* |
14 | * Load Missed L1, for power9 its pointing to PM_LD_MISS_L1_FIN (0x2c04e) and |
15 | * for power10 its pointing to PM_LD_MISS_L1 (0x3e054) |
16 | * |
17 | * Hardware cache level : PERF_COUNT_HW_CACHE_L1D |
18 | * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_READ |
19 | * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_MISS |
20 | */ |
21 | #define EventCode_1 0x10000 |
22 | /* |
23 | * Hardware cache level : PERF_COUNT_HW_CACHE_L1D |
24 | * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_WRITE |
25 | * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_ACCESS |
26 | */ |
27 | #define EventCode_2 0x0100 |
28 | /* |
29 | * Hardware cache level : PERF_COUNT_HW_CACHE_DTLB |
30 | * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_WRITE |
31 | * Hardware cache event result type : PERF_COUNT_HW_CACHE_RESULT_ACCESS |
32 | */ |
33 | #define EventCode_3 0x0103 |
34 | /* |
35 | * Hardware cache level : PERF_COUNT_HW_CACHE_L1D |
36 | * Hardware cache event operation type : PERF_COUNT_HW_CACHE_OP_READ |
37 | * Hardware cache event result type : Invalid ( > PERF_COUNT_HW_CACHE_RESULT_MAX) |
38 | */ |
39 | #define EventCode_4 0x030000 |
40 | |
41 | /* |
42 | * A perf test to check valid hardware cache events. |
43 | */ |
44 | static int hw_cache_event_type_test(void) |
45 | { |
46 | struct event event; |
47 | |
48 | /* Check for platform support for the test */ |
49 | SKIP_IF(platform_check_for_tests()); |
50 | |
51 | /* Skip for Generic compat PMU */ |
52 | SKIP_IF(check_for_generic_compat_pmu()); |
53 | |
54 | /* Init the event to test hardware cache event */ |
55 | event_init_opts(e: &event, EventCode_1, type: PERF_TYPE_HW_CACHE, name: "event" ); |
56 | |
57 | /* Expected to success as its pointing to L1 load miss */ |
58 | FAIL_IF(event_open(e: &event)); |
59 | event_close(e: &event); |
60 | |
61 | /* Init the event to test hardware cache event */ |
62 | event_init_opts(e: &event, EventCode_2, type: PERF_TYPE_HW_CACHE, name: "event" ); |
63 | |
64 | /* Expected to fail as the corresponding cache event entry have 0 in that index */ |
65 | FAIL_IF(!event_open(e: &event)); |
66 | event_close(e: &event); |
67 | |
68 | /* Init the event to test hardware cache event */ |
69 | event_init_opts(e: &event, EventCode_3, type: PERF_TYPE_HW_CACHE, name: "event" ); |
70 | |
71 | /* Expected to fail as the corresponding cache event entry have -1 in that index */ |
72 | FAIL_IF(!event_open(e: &event)); |
73 | event_close(e: &event); |
74 | |
75 | /* Init the event to test hardware cache event */ |
76 | event_init_opts(e: &event, EventCode_4, type: PERF_TYPE_HW_CACHE, name: "event" ); |
77 | |
78 | /* Expected to fail as hardware cache event result type is Invalid */ |
79 | FAIL_IF(!event_open(e: &event)); |
80 | event_close(e: &event); |
81 | |
82 | return 0; |
83 | } |
84 | |
85 | int main(void) |
86 | { |
87 | return test_harness(hw_cache_event_type_test, "hw_cache_event_type_test" ); |
88 | } |
89 | |