1//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "RISCV.h"
10#include "../Clang.h"
11#include "ToolChains/CommonArgs.h"
12#include "clang/Basic/CharInfo.h"
13#include "clang/Driver/Driver.h"
14#include "clang/Driver/DriverDiagnostic.h"
15#include "clang/Driver/Options.h"
16#include "llvm/Option/ArgList.h"
17#include "llvm/Support/Error.h"
18#include "llvm/Support/RISCVISAInfo.h"
19#include "llvm/Support/raw_ostream.h"
20#include "llvm/TargetParser/Host.h"
21#include "llvm/TargetParser/RISCVTargetParser.h"
22
23using namespace clang::driver;
24using namespace clang::driver::tools;
25using namespace clang;
26using namespace llvm::opt;
27
28// Returns false if an error is diagnosed.
29static bool getArchFeatures(const Driver &D, StringRef Arch,
30 std::vector<StringRef> &Features,
31 const ArgList &Args) {
32 bool EnableExperimentalExtensions =
33 Args.hasArg(options::OPT_menable_experimental_extensions);
34 auto ISAInfo =
35 llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtension: EnableExperimentalExtensions);
36 if (!ISAInfo) {
37 handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
38 D.Diag(diag::DiagID: err_drv_invalid_riscv_arch_name)
39 << Arch << ErrMsg.getMessage();
40 });
41
42 return false;
43 }
44
45 for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
46 /*IgnoreUnknown=*/false))
47 Features.push_back(Args.MakeArgString(Str));
48
49 if (EnableExperimentalExtensions)
50 Features.push_back(x: Args.MakeArgString(Str: "+experimental"));
51
52 return true;
53}
54
55// Get features except standard extension feature
56static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
57 const llvm::Triple &Triple,
58 StringRef Mcpu,
59 std::vector<StringRef> &Features) {
60 bool Is64Bit = Triple.isRISCV64();
61 if (!llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: Is64Bit)) {
62 // Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
63 if (llvm::RISCV::parseCPU(CPU: Mcpu, IsRV64: !Is64Bit))
64 D.Diag(clang::diag::DiagID: err_drv_invalid_riscv_cpu_name_for_target)
65 << Mcpu << Is64Bit;
66 else
67 D.Diag(clang::diag::DiagID: err_drv_unsupported_option_argument)
68 << A->getSpelling() << Mcpu;
69 }
70
71 if (llvm::RISCV::hasFastUnalignedAccess(CPU: Mcpu))
72 Features.push_back(x: "+fast-unaligned-access");
73}
74
75void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
76 const ArgList &Args,
77 std::vector<StringRef> &Features) {
78 StringRef MArch = getRISCVArch(Args, Triple);
79
80 if (!getArchFeatures(D, Arch: MArch, Features, Args))
81 return;
82
83 // If users give march and mcpu, get std extension feature from MArch
84 // and other features (ex. mirco architecture feature) from mcpu
85 if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
86 StringRef CPU = A->getValue();
87 if (CPU == "native")
88 CPU = llvm::sys::getHostCPUName();
89
90 getRISCFeaturesFromMcpu(D, A, Triple, Mcpu: CPU, Features);
91 }
92
93 // Handle features corresponding to "-ffixed-X" options
94 if (Args.hasArg(options::OPT_ffixed_x1))
95 Features.push_back(x: "+reserve-x1");
96 if (Args.hasArg(options::OPT_ffixed_x2))
97 Features.push_back(x: "+reserve-x2");
98 if (Args.hasArg(options::OPT_ffixed_x3))
99 Features.push_back(x: "+reserve-x3");
100 if (Args.hasArg(options::OPT_ffixed_x4))
101 Features.push_back(x: "+reserve-x4");
102 if (Args.hasArg(options::OPT_ffixed_x5))
103 Features.push_back(x: "+reserve-x5");
104 if (Args.hasArg(options::OPT_ffixed_x6))
105 Features.push_back(x: "+reserve-x6");
106 if (Args.hasArg(options::OPT_ffixed_x7))
107 Features.push_back(x: "+reserve-x7");
108 if (Args.hasArg(options::OPT_ffixed_x8))
109 Features.push_back(x: "+reserve-x8");
110 if (Args.hasArg(options::OPT_ffixed_x9))
111 Features.push_back(x: "+reserve-x9");
112 if (Args.hasArg(options::OPT_ffixed_x10))
113 Features.push_back(x: "+reserve-x10");
114 if (Args.hasArg(options::OPT_ffixed_x11))
115 Features.push_back(x: "+reserve-x11");
116 if (Args.hasArg(options::OPT_ffixed_x12))
117 Features.push_back(x: "+reserve-x12");
118 if (Args.hasArg(options::OPT_ffixed_x13))
119 Features.push_back(x: "+reserve-x13");
120 if (Args.hasArg(options::OPT_ffixed_x14))
121 Features.push_back(x: "+reserve-x14");
122 if (Args.hasArg(options::OPT_ffixed_x15))
123 Features.push_back(x: "+reserve-x15");
124 if (Args.hasArg(options::OPT_ffixed_x16))
125 Features.push_back(x: "+reserve-x16");
126 if (Args.hasArg(options::OPT_ffixed_x17))
127 Features.push_back(x: "+reserve-x17");
128 if (Args.hasArg(options::OPT_ffixed_x18))
129 Features.push_back(x: "+reserve-x18");
130 if (Args.hasArg(options::OPT_ffixed_x19))
131 Features.push_back(x: "+reserve-x19");
132 if (Args.hasArg(options::OPT_ffixed_x20))
133 Features.push_back(x: "+reserve-x20");
134 if (Args.hasArg(options::OPT_ffixed_x21))
135 Features.push_back(x: "+reserve-x21");
136 if (Args.hasArg(options::OPT_ffixed_x22))
137 Features.push_back(x: "+reserve-x22");
138 if (Args.hasArg(options::OPT_ffixed_x23))
139 Features.push_back(x: "+reserve-x23");
140 if (Args.hasArg(options::OPT_ffixed_x24))
141 Features.push_back(x: "+reserve-x24");
142 if (Args.hasArg(options::OPT_ffixed_x25))
143 Features.push_back(x: "+reserve-x25");
144 if (Args.hasArg(options::OPT_ffixed_x26))
145 Features.push_back(x: "+reserve-x26");
146 if (Args.hasArg(options::OPT_ffixed_x27))
147 Features.push_back(x: "+reserve-x27");
148 if (Args.hasArg(options::OPT_ffixed_x28))
149 Features.push_back(x: "+reserve-x28");
150 if (Args.hasArg(options::OPT_ffixed_x29))
151 Features.push_back(x: "+reserve-x29");
152 if (Args.hasArg(options::OPT_ffixed_x30))
153 Features.push_back(x: "+reserve-x30");
154 if (Args.hasArg(options::OPT_ffixed_x31))
155 Features.push_back(x: "+reserve-x31");
156
157 // -mrelax is default, unless -mno-relax is specified.
158 if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {
159 Features.push_back(x: "+relax");
160 // -gsplit-dwarf -mrelax requires DW_AT_high_pc/DW_AT_ranges/... indexing
161 // into .debug_addr, which is currently not implemented.
162 Arg *A;
163 if (getDebugFissionKind(D, Args, Arg&: A) != DwarfFissionKind::None)
164 D.Diag(clang::diag::DiagID: err_drv_riscv_unsupported_with_linker_relaxation)
165 << A->getAsString(Args);
166 } else {
167 Features.push_back(x: "-relax");
168 }
169
170 // -mno-unaligned-access is default, unless -munaligned-access is specified.
171 AddTargetFeature(Args, Features, options::OPT_munaligned_access,
172 options::OPT_mno_unaligned_access, "fast-unaligned-access");
173
174 // Now add any that the user explicitly requested on the command line,
175 // which may override the defaults.
176 handleTargetFeaturesGroup(D, Triple, Args, Features,
177 options::OPT_m_riscv_Features_Group);
178}
179
180StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
181 assert(Triple.isRISCV() && "Unexpected triple");
182
183 // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
184 // configured using `--with-abi=`, then the logic for the default choice is
185 // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
186 //
187 // The logic used in GCC 9.2.0 is the following, in order:
188 // 1. Explicit choices using `--with-abi=`
189 // 2. A default based on `--with-arch=`, if provided
190 // 3. A default based on the target triple's arch
191 //
192 // The logic in config.gcc is a little circular but it is not inconsistent.
193 //
194 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
195 // and `-mabi=` respectively instead.
196 //
197 // In order to make chosing logic more clear, Clang uses the following logic,
198 // in order:
199 // 1. Explicit choices using `-mabi=`
200 // 2. A default based on the architecture as determined by getRISCVArch
201 // 3. Choose a default based on the triple
202
203 // 1. If `-mabi=` is specified, use it.
204 if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
205 return A->getValue();
206
207 // 2. Choose a default based on the target architecture.
208 //
209 // rv32g | rv32*d -> ilp32d
210 // rv32e -> ilp32e
211 // rv32* -> ilp32
212 // rv64g | rv64*d -> lp64d
213 // rv64e -> lp64e
214 // rv64* -> lp64
215 StringRef Arch = getRISCVArch(Args, Triple);
216
217 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
218 Arch, /* EnableExperimentalExtension */ true);
219 // Ignore parsing error, just go 3rd step.
220 if (!llvm::errorToBool(Err: ParseResult.takeError()))
221 return (*ParseResult)->computeDefaultABI();
222
223 // 3. Choose a default based on the triple
224 //
225 // We deviate from GCC's defaults here:
226 // - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
227 // - On all other OSs we use the double floating point calling convention.
228 if (Triple.isRISCV32()) {
229 if (Triple.getOS() == llvm::Triple::UnknownOS)
230 return "ilp32";
231 else
232 return "ilp32d";
233 } else {
234 if (Triple.getOS() == llvm::Triple::UnknownOS)
235 return "lp64";
236 else
237 return "lp64d";
238 }
239}
240
241StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
242 const llvm::Triple &Triple) {
243 assert(Triple.isRISCV() && "Unexpected triple");
244
245 // GCC's logic around choosing a default `-march=` is complex. If GCC is not
246 // configured using `--with-arch=`, then the logic for the default choice is
247 // defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
248 // deviate from GCC's default on additional `-mcpu` option (GCC does not
249 // support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
250 // nor `-mabi` is specified.
251 //
252 // The logic used in GCC 9.2.0 is the following, in order:
253 // 1. Explicit choices using `--with-arch=`
254 // 2. A default based on `--with-abi=`, if provided
255 // 3. A default based on the target triple's arch
256 //
257 // The logic in config.gcc is a little circular but it is not inconsistent.
258 //
259 // Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
260 // and `-mabi=` respectively instead.
261 //
262 // Clang uses the following logic, in order:
263 // 1. Explicit choices using `-march=`
264 // 2. Based on `-mcpu` if the target CPU has a default ISA string
265 // 3. A default based on `-mabi`, if provided
266 // 4. A default based on the target triple's arch
267 //
268 // Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
269 // instead of `rv{XLEN}gc` though they are (currently) equivalent.
270
271 // 1. If `-march=` is specified, use it.
272 if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
273 return A->getValue();
274
275 // 2. Get march (isa string) based on `-mcpu=`
276 if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
277 StringRef CPU = A->getValue();
278 if (CPU == "native")
279 CPU = llvm::sys::getHostCPUName();
280 StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
281 // Bypass if target cpu's default march is empty.
282 if (MArch != "")
283 return MArch;
284 }
285
286 // 3. Choose a default based on `-mabi=`
287 //
288 // ilp32e -> rv32e
289 // lp64e -> rv64e
290 // ilp32 | ilp32f | ilp32d -> rv32imafdc
291 // lp64 | lp64f | lp64d -> rv64imafdc
292 if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
293 StringRef MABI = A->getValue();
294
295 if (MABI.equals_insensitive(RHS: "ilp32e"))
296 return "rv32e";
297 else if (MABI.equals_insensitive(RHS: "lp64e"))
298 return "rv64e";
299 else if (MABI.starts_with_insensitive(Prefix: "ilp32"))
300 return "rv32imafdc";
301 else if (MABI.starts_with_insensitive(Prefix: "lp64")) {
302 if (Triple.isAndroid())
303 return "rv64imafdcv_zba_zbb_zbs";
304
305 return "rv64imafdc";
306 }
307 }
308
309 // 4. Choose a default based on the triple
310 //
311 // We deviate from GCC's defaults here:
312 // - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
313 // - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
314 if (Triple.isRISCV32()) {
315 if (Triple.getOS() == llvm::Triple::UnknownOS)
316 return "rv32imac";
317 else
318 return "rv32imafdc";
319 } else {
320 if (Triple.getOS() == llvm::Triple::UnknownOS)
321 return "rv64imac";
322 else if (Triple.isAndroid())
323 return "rv64imafdcv_zba_zbb_zbs";
324 else
325 return "rv64imafdc";
326 }
327}
328
329std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
330 const llvm::Triple &Triple) {
331 std::string CPU;
332 // If we have -mcpu, use that.
333 if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
334 CPU = A->getValue();
335
336 // Handle CPU name is 'native'.
337 if (CPU == "native")
338 CPU = llvm::sys::getHostCPUName();
339
340 if (!CPU.empty())
341 return CPU;
342
343 return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
344}
345

source code of clang/lib/Driver/ToolChains/Arch/RISCV.cpp