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1 | //===----------------------------------------------------------------------===// |
---|---|
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // Automatically generated file, do not edit! |
9 | //===----------------------------------------------------------------------===// |
10 | |
11 | |
12 | |
13 | #ifndef __HEXAGON_PROTOS_H_ |
14 | #define __HEXAGON_PROTOS_H_ 1 |
15 | |
16 | /* ========================================================================== |
17 | Assembly Syntax: Rd32=abs(Rs32) |
18 | C Intrinsic Prototype: Word32 Q6_R_abs_R(Word32 Rs) |
19 | Instruction Type: S_2op |
20 | Execution Slots: SLOT23 |
21 | ========================================================================== */ |
22 | |
23 | #define Q6_R_abs_R __builtin_HEXAGON_A2_abs |
24 | |
25 | /* ========================================================================== |
26 | Assembly Syntax: Rdd32=abs(Rss32) |
27 | C Intrinsic Prototype: Word64 Q6_P_abs_P(Word64 Rss) |
28 | Instruction Type: S_2op |
29 | Execution Slots: SLOT23 |
30 | ========================================================================== */ |
31 | |
32 | #define Q6_P_abs_P __builtin_HEXAGON_A2_absp |
33 | |
34 | /* ========================================================================== |
35 | Assembly Syntax: Rd32=abs(Rs32):sat |
36 | C Intrinsic Prototype: Word32 Q6_R_abs_R_sat(Word32 Rs) |
37 | Instruction Type: S_2op |
38 | Execution Slots: SLOT23 |
39 | ========================================================================== */ |
40 | |
41 | #define Q6_R_abs_R_sat __builtin_HEXAGON_A2_abssat |
42 | |
43 | /* ========================================================================== |
44 | Assembly Syntax: Rd32=add(Rs32,Rt32) |
45 | C Intrinsic Prototype: Word32 Q6_R_add_RR(Word32 Rs, Word32 Rt) |
46 | Instruction Type: ALU32_3op |
47 | Execution Slots: SLOT0123 |
48 | ========================================================================== */ |
49 | |
50 | #define Q6_R_add_RR __builtin_HEXAGON_A2_add |
51 | |
52 | /* ========================================================================== |
53 | Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):<<16 |
54 | C Intrinsic Prototype: Word32 Q6_R_add_RhRh_s16(Word32 Rt, Word32 Rs) |
55 | Instruction Type: ALU64 |
56 | Execution Slots: SLOT23 |
57 | ========================================================================== */ |
58 | |
59 | #define Q6_R_add_RhRh_s16 __builtin_HEXAGON_A2_addh_h16_hh |
60 | |
61 | /* ========================================================================== |
62 | Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):<<16 |
63 | C Intrinsic Prototype: Word32 Q6_R_add_RhRl_s16(Word32 Rt, Word32 Rs) |
64 | Instruction Type: ALU64 |
65 | Execution Slots: SLOT23 |
66 | ========================================================================== */ |
67 | |
68 | #define Q6_R_add_RhRl_s16 __builtin_HEXAGON_A2_addh_h16_hl |
69 | |
70 | /* ========================================================================== |
71 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):<<16 |
72 | C Intrinsic Prototype: Word32 Q6_R_add_RlRh_s16(Word32 Rt, Word32 Rs) |
73 | Instruction Type: ALU64 |
74 | Execution Slots: SLOT23 |
75 | ========================================================================== */ |
76 | |
77 | #define Q6_R_add_RlRh_s16 __builtin_HEXAGON_A2_addh_h16_lh |
78 | |
79 | /* ========================================================================== |
80 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):<<16 |
81 | C Intrinsic Prototype: Word32 Q6_R_add_RlRl_s16(Word32 Rt, Word32 Rs) |
82 | Instruction Type: ALU64 |
83 | Execution Slots: SLOT23 |
84 | ========================================================================== */ |
85 | |
86 | #define Q6_R_add_RlRl_s16 __builtin_HEXAGON_A2_addh_h16_ll |
87 | |
88 | /* ========================================================================== |
89 | Assembly Syntax: Rd32=add(Rt32.h,Rs32.h):sat:<<16 |
90 | C Intrinsic Prototype: Word32 Q6_R_add_RhRh_sat_s16(Word32 Rt, Word32 Rs) |
91 | Instruction Type: ALU64 |
92 | Execution Slots: SLOT23 |
93 | ========================================================================== */ |
94 | |
95 | #define Q6_R_add_RhRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hh |
96 | |
97 | /* ========================================================================== |
98 | Assembly Syntax: Rd32=add(Rt32.h,Rs32.l):sat:<<16 |
99 | C Intrinsic Prototype: Word32 Q6_R_add_RhRl_sat_s16(Word32 Rt, Word32 Rs) |
100 | Instruction Type: ALU64 |
101 | Execution Slots: SLOT23 |
102 | ========================================================================== */ |
103 | |
104 | #define Q6_R_add_RhRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_hl |
105 | |
106 | /* ========================================================================== |
107 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat:<<16 |
108 | C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat_s16(Word32 Rt, Word32 Rs) |
109 | Instruction Type: ALU64 |
110 | Execution Slots: SLOT23 |
111 | ========================================================================== */ |
112 | |
113 | #define Q6_R_add_RlRh_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_lh |
114 | |
115 | /* ========================================================================== |
116 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat:<<16 |
117 | C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat_s16(Word32 Rt, Word32 Rs) |
118 | Instruction Type: ALU64 |
119 | Execution Slots: SLOT23 |
120 | ========================================================================== */ |
121 | |
122 | #define Q6_R_add_RlRl_sat_s16 __builtin_HEXAGON_A2_addh_h16_sat_ll |
123 | |
124 | /* ========================================================================== |
125 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.h) |
126 | C Intrinsic Prototype: Word32 Q6_R_add_RlRh(Word32 Rt, Word32 Rs) |
127 | Instruction Type: ALU64 |
128 | Execution Slots: SLOT23 |
129 | ========================================================================== */ |
130 | |
131 | #define Q6_R_add_RlRh __builtin_HEXAGON_A2_addh_l16_hl |
132 | |
133 | /* ========================================================================== |
134 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.l) |
135 | C Intrinsic Prototype: Word32 Q6_R_add_RlRl(Word32 Rt, Word32 Rs) |
136 | Instruction Type: ALU64 |
137 | Execution Slots: SLOT23 |
138 | ========================================================================== */ |
139 | |
140 | #define Q6_R_add_RlRl __builtin_HEXAGON_A2_addh_l16_ll |
141 | |
142 | /* ========================================================================== |
143 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.h):sat |
144 | C Intrinsic Prototype: Word32 Q6_R_add_RlRh_sat(Word32 Rt, Word32 Rs) |
145 | Instruction Type: ALU64 |
146 | Execution Slots: SLOT23 |
147 | ========================================================================== */ |
148 | |
149 | #define Q6_R_add_RlRh_sat __builtin_HEXAGON_A2_addh_l16_sat_hl |
150 | |
151 | /* ========================================================================== |
152 | Assembly Syntax: Rd32=add(Rt32.l,Rs32.l):sat |
153 | C Intrinsic Prototype: Word32 Q6_R_add_RlRl_sat(Word32 Rt, Word32 Rs) |
154 | Instruction Type: ALU64 |
155 | Execution Slots: SLOT23 |
156 | ========================================================================== */ |
157 | |
158 | #define Q6_R_add_RlRl_sat __builtin_HEXAGON_A2_addh_l16_sat_ll |
159 | |
160 | /* ========================================================================== |
161 | Assembly Syntax: Rd32=add(Rs32,#s16) |
162 | C Intrinsic Prototype: Word32 Q6_R_add_RI(Word32 Rs, Word32 Is16) |
163 | Instruction Type: ALU32_ADDI |
164 | Execution Slots: SLOT0123 |
165 | ========================================================================== */ |
166 | |
167 | #define Q6_R_add_RI __builtin_HEXAGON_A2_addi |
168 | |
169 | /* ========================================================================== |
170 | Assembly Syntax: Rdd32=add(Rss32,Rtt32) |
171 | C Intrinsic Prototype: Word64 Q6_P_add_PP(Word64 Rss, Word64 Rtt) |
172 | Instruction Type: ALU64 |
173 | Execution Slots: SLOT23 |
174 | ========================================================================== */ |
175 | |
176 | #define Q6_P_add_PP __builtin_HEXAGON_A2_addp |
177 | |
178 | /* ========================================================================== |
179 | Assembly Syntax: Rdd32=add(Rss32,Rtt32):sat |
180 | C Intrinsic Prototype: Word64 Q6_P_add_PP_sat(Word64 Rss, Word64 Rtt) |
181 | Instruction Type: ALU64 |
182 | Execution Slots: SLOT23 |
183 | ========================================================================== */ |
184 | |
185 | #define Q6_P_add_PP_sat __builtin_HEXAGON_A2_addpsat |
186 | |
187 | /* ========================================================================== |
188 | Assembly Syntax: Rd32=add(Rs32,Rt32):sat |
189 | C Intrinsic Prototype: Word32 Q6_R_add_RR_sat(Word32 Rs, Word32 Rt) |
190 | Instruction Type: ALU32_3op |
191 | Execution Slots: SLOT0123 |
192 | ========================================================================== */ |
193 | |
194 | #define Q6_R_add_RR_sat __builtin_HEXAGON_A2_addsat |
195 | |
196 | /* ========================================================================== |
197 | Assembly Syntax: Rdd32=add(Rs32,Rtt32) |
198 | C Intrinsic Prototype: Word64 Q6_P_add_RP(Word32 Rs, Word64 Rtt) |
199 | Instruction Type: ALU64 |
200 | Execution Slots: SLOT0123 |
201 | ========================================================================== */ |
202 | |
203 | #define Q6_P_add_RP __builtin_HEXAGON_A2_addsp |
204 | |
205 | /* ========================================================================== |
206 | Assembly Syntax: Rd32=and(Rs32,Rt32) |
207 | C Intrinsic Prototype: Word32 Q6_R_and_RR(Word32 Rs, Word32 Rt) |
208 | Instruction Type: ALU32_3op |
209 | Execution Slots: SLOT0123 |
210 | ========================================================================== */ |
211 | |
212 | #define Q6_R_and_RR __builtin_HEXAGON_A2_and |
213 | |
214 | /* ========================================================================== |
215 | Assembly Syntax: Rd32=and(Rs32,#s10) |
216 | C Intrinsic Prototype: Word32 Q6_R_and_RI(Word32 Rs, Word32 Is10) |
217 | Instruction Type: ALU32_2op |
218 | Execution Slots: SLOT0123 |
219 | ========================================================================== */ |
220 | |
221 | #define Q6_R_and_RI __builtin_HEXAGON_A2_andir |
222 | |
223 | /* ========================================================================== |
224 | Assembly Syntax: Rdd32=and(Rss32,Rtt32) |
225 | C Intrinsic Prototype: Word64 Q6_P_and_PP(Word64 Rss, Word64 Rtt) |
226 | Instruction Type: ALU64 |
227 | Execution Slots: SLOT23 |
228 | ========================================================================== */ |
229 | |
230 | #define Q6_P_and_PP __builtin_HEXAGON_A2_andp |
231 | |
232 | /* ========================================================================== |
233 | Assembly Syntax: Rd32=aslh(Rs32) |
234 | C Intrinsic Prototype: Word32 Q6_R_aslh_R(Word32 Rs) |
235 | Instruction Type: ALU32_2op |
236 | Execution Slots: SLOT0123 |
237 | ========================================================================== */ |
238 | |
239 | #define Q6_R_aslh_R __builtin_HEXAGON_A2_aslh |
240 | |
241 | /* ========================================================================== |
242 | Assembly Syntax: Rd32=asrh(Rs32) |
243 | C Intrinsic Prototype: Word32 Q6_R_asrh_R(Word32 Rs) |
244 | Instruction Type: ALU32_2op |
245 | Execution Slots: SLOT0123 |
246 | ========================================================================== */ |
247 | |
248 | #define Q6_R_asrh_R __builtin_HEXAGON_A2_asrh |
249 | |
250 | /* ========================================================================== |
251 | Assembly Syntax: Rd32=combine(Rt32.h,Rs32.h) |
252 | C Intrinsic Prototype: Word32 Q6_R_combine_RhRh(Word32 Rt, Word32 Rs) |
253 | Instruction Type: ALU32_3op |
254 | Execution Slots: SLOT0123 |
255 | ========================================================================== */ |
256 | |
257 | #define Q6_R_combine_RhRh __builtin_HEXAGON_A2_combine_hh |
258 | |
259 | /* ========================================================================== |
260 | Assembly Syntax: Rd32=combine(Rt32.h,Rs32.l) |
261 | C Intrinsic Prototype: Word32 Q6_R_combine_RhRl(Word32 Rt, Word32 Rs) |
262 | Instruction Type: ALU32_3op |
263 | Execution Slots: SLOT0123 |
264 | ========================================================================== */ |
265 | |
266 | #define Q6_R_combine_RhRl __builtin_HEXAGON_A2_combine_hl |
267 | |
268 | /* ========================================================================== |
269 | Assembly Syntax: Rd32=combine(Rt32.l,Rs32.h) |
270 | C Intrinsic Prototype: Word32 Q6_R_combine_RlRh(Word32 Rt, Word32 Rs) |
271 | Instruction Type: ALU32_3op |
272 | Execution Slots: SLOT0123 |
273 | ========================================================================== */ |
274 | |
275 | #define Q6_R_combine_RlRh __builtin_HEXAGON_A2_combine_lh |
276 | |
277 | /* ========================================================================== |
278 | Assembly Syntax: Rd32=combine(Rt32.l,Rs32.l) |
279 | C Intrinsic Prototype: Word32 Q6_R_combine_RlRl(Word32 Rt, Word32 Rs) |
280 | Instruction Type: ALU32_3op |
281 | Execution Slots: SLOT0123 |
282 | ========================================================================== */ |
283 | |
284 | #define Q6_R_combine_RlRl __builtin_HEXAGON_A2_combine_ll |
285 | |
286 | /* ========================================================================== |
287 | Assembly Syntax: Rdd32=combine(#s8,#S8) |
288 | C Intrinsic Prototype: Word64 Q6_P_combine_II(Word32 Is8, Word32 IS8) |
289 | Instruction Type: ALU32_2op |
290 | Execution Slots: SLOT0123 |
291 | ========================================================================== */ |
292 | |
293 | #define Q6_P_combine_II __builtin_HEXAGON_A2_combineii |
294 | |
295 | /* ========================================================================== |
296 | Assembly Syntax: Rdd32=combine(Rs32,Rt32) |
297 | C Intrinsic Prototype: Word64 Q6_P_combine_RR(Word32 Rs, Word32 Rt) |
298 | Instruction Type: ALU32_3op |
299 | Execution Slots: SLOT0123 |
300 | ========================================================================== */ |
301 | |
302 | #define Q6_P_combine_RR __builtin_HEXAGON_A2_combinew |
303 | |
304 | /* ========================================================================== |
305 | Assembly Syntax: Rd32=max(Rs32,Rt32) |
306 | C Intrinsic Prototype: Word32 Q6_R_max_RR(Word32 Rs, Word32 Rt) |
307 | Instruction Type: ALU64 |
308 | Execution Slots: SLOT23 |
309 | ========================================================================== */ |
310 | |
311 | #define Q6_R_max_RR __builtin_HEXAGON_A2_max |
312 | |
313 | /* ========================================================================== |
314 | Assembly Syntax: Rdd32=max(Rss32,Rtt32) |
315 | C Intrinsic Prototype: Word64 Q6_P_max_PP(Word64 Rss, Word64 Rtt) |
316 | Instruction Type: ALU64 |
317 | Execution Slots: SLOT23 |
318 | ========================================================================== */ |
319 | |
320 | #define Q6_P_max_PP __builtin_HEXAGON_A2_maxp |
321 | |
322 | /* ========================================================================== |
323 | Assembly Syntax: Rd32=maxu(Rs32,Rt32) |
324 | C Intrinsic Prototype: UWord32 Q6_R_maxu_RR(Word32 Rs, Word32 Rt) |
325 | Instruction Type: ALU64 |
326 | Execution Slots: SLOT23 |
327 | ========================================================================== */ |
328 | |
329 | #define Q6_R_maxu_RR __builtin_HEXAGON_A2_maxu |
330 | |
331 | /* ========================================================================== |
332 | Assembly Syntax: Rdd32=maxu(Rss32,Rtt32) |
333 | C Intrinsic Prototype: UWord64 Q6_P_maxu_PP(Word64 Rss, Word64 Rtt) |
334 | Instruction Type: ALU64 |
335 | Execution Slots: SLOT23 |
336 | ========================================================================== */ |
337 | |
338 | #define Q6_P_maxu_PP __builtin_HEXAGON_A2_maxup |
339 | |
340 | /* ========================================================================== |
341 | Assembly Syntax: Rd32=min(Rt32,Rs32) |
342 | C Intrinsic Prototype: Word32 Q6_R_min_RR(Word32 Rt, Word32 Rs) |
343 | Instruction Type: ALU64 |
344 | Execution Slots: SLOT23 |
345 | ========================================================================== */ |
346 | |
347 | #define Q6_R_min_RR __builtin_HEXAGON_A2_min |
348 | |
349 | /* ========================================================================== |
350 | Assembly Syntax: Rdd32=min(Rtt32,Rss32) |
351 | C Intrinsic Prototype: Word64 Q6_P_min_PP(Word64 Rtt, Word64 Rss) |
352 | Instruction Type: ALU64 |
353 | Execution Slots: SLOT23 |
354 | ========================================================================== */ |
355 | |
356 | #define Q6_P_min_PP __builtin_HEXAGON_A2_minp |
357 | |
358 | /* ========================================================================== |
359 | Assembly Syntax: Rd32=minu(Rt32,Rs32) |
360 | C Intrinsic Prototype: UWord32 Q6_R_minu_RR(Word32 Rt, Word32 Rs) |
361 | Instruction Type: ALU64 |
362 | Execution Slots: SLOT23 |
363 | ========================================================================== */ |
364 | |
365 | #define Q6_R_minu_RR __builtin_HEXAGON_A2_minu |
366 | |
367 | /* ========================================================================== |
368 | Assembly Syntax: Rdd32=minu(Rtt32,Rss32) |
369 | C Intrinsic Prototype: UWord64 Q6_P_minu_PP(Word64 Rtt, Word64 Rss) |
370 | Instruction Type: ALU64 |
371 | Execution Slots: SLOT23 |
372 | ========================================================================== */ |
373 | |
374 | #define Q6_P_minu_PP __builtin_HEXAGON_A2_minup |
375 | |
376 | /* ========================================================================== |
377 | Assembly Syntax: Rd32=neg(Rs32) |
378 | C Intrinsic Prototype: Word32 Q6_R_neg_R(Word32 Rs) |
379 | Instruction Type: ALU32_2op |
380 | Execution Slots: SLOT0123 |
381 | ========================================================================== */ |
382 | |
383 | #define Q6_R_neg_R __builtin_HEXAGON_A2_neg |
384 | |
385 | /* ========================================================================== |
386 | Assembly Syntax: Rdd32=neg(Rss32) |
387 | C Intrinsic Prototype: Word64 Q6_P_neg_P(Word64 Rss) |
388 | Instruction Type: S_2op |
389 | Execution Slots: SLOT23 |
390 | ========================================================================== */ |
391 | |
392 | #define Q6_P_neg_P __builtin_HEXAGON_A2_negp |
393 | |
394 | /* ========================================================================== |
395 | Assembly Syntax: Rd32=neg(Rs32):sat |
396 | C Intrinsic Prototype: Word32 Q6_R_neg_R_sat(Word32 Rs) |
397 | Instruction Type: S_2op |
398 | Execution Slots: SLOT23 |
399 | ========================================================================== */ |
400 | |
401 | #define Q6_R_neg_R_sat __builtin_HEXAGON_A2_negsat |
402 | |
403 | /* ========================================================================== |
404 | Assembly Syntax: Rd32=not(Rs32) |
405 | C Intrinsic Prototype: Word32 Q6_R_not_R(Word32 Rs) |
406 | Instruction Type: ALU32_2op |
407 | Execution Slots: SLOT0123 |
408 | ========================================================================== */ |
409 | |
410 | #define Q6_R_not_R __builtin_HEXAGON_A2_not |
411 | |
412 | /* ========================================================================== |
413 | Assembly Syntax: Rdd32=not(Rss32) |
414 | C Intrinsic Prototype: Word64 Q6_P_not_P(Word64 Rss) |
415 | Instruction Type: S_2op |
416 | Execution Slots: SLOT23 |
417 | ========================================================================== */ |
418 | |
419 | #define Q6_P_not_P __builtin_HEXAGON_A2_notp |
420 | |
421 | /* ========================================================================== |
422 | Assembly Syntax: Rd32=or(Rs32,Rt32) |
423 | C Intrinsic Prototype: Word32 Q6_R_or_RR(Word32 Rs, Word32 Rt) |
424 | Instruction Type: ALU32_3op |
425 | Execution Slots: SLOT0123 |
426 | ========================================================================== */ |
427 | |
428 | #define Q6_R_or_RR __builtin_HEXAGON_A2_or |
429 | |
430 | /* ========================================================================== |
431 | Assembly Syntax: Rd32=or(Rs32,#s10) |
432 | C Intrinsic Prototype: Word32 Q6_R_or_RI(Word32 Rs, Word32 Is10) |
433 | Instruction Type: ALU32_2op |
434 | Execution Slots: SLOT0123 |
435 | ========================================================================== */ |
436 | |
437 | #define Q6_R_or_RI __builtin_HEXAGON_A2_orir |
438 | |
439 | /* ========================================================================== |
440 | Assembly Syntax: Rdd32=or(Rss32,Rtt32) |
441 | C Intrinsic Prototype: Word64 Q6_P_or_PP(Word64 Rss, Word64 Rtt) |
442 | Instruction Type: ALU64 |
443 | Execution Slots: SLOT23 |
444 | ========================================================================== */ |
445 | |
446 | #define Q6_P_or_PP __builtin_HEXAGON_A2_orp |
447 | |
448 | /* ========================================================================== |
449 | Assembly Syntax: Rd32=round(Rss32):sat |
450 | C Intrinsic Prototype: Word32 Q6_R_round_P_sat(Word64 Rss) |
451 | Instruction Type: S_2op |
452 | Execution Slots: SLOT23 |
453 | ========================================================================== */ |
454 | |
455 | #define Q6_R_round_P_sat __builtin_HEXAGON_A2_roundsat |
456 | |
457 | /* ========================================================================== |
458 | Assembly Syntax: Rd32=sat(Rss32) |
459 | C Intrinsic Prototype: Word32 Q6_R_sat_P(Word64 Rss) |
460 | Instruction Type: S_2op |
461 | Execution Slots: SLOT23 |
462 | ========================================================================== */ |
463 | |
464 | #define Q6_R_sat_P __builtin_HEXAGON_A2_sat |
465 | |
466 | /* ========================================================================== |
467 | Assembly Syntax: Rd32=satb(Rs32) |
468 | C Intrinsic Prototype: Word32 Q6_R_satb_R(Word32 Rs) |
469 | Instruction Type: S_2op |
470 | Execution Slots: SLOT23 |
471 | ========================================================================== */ |
472 | |
473 | #define Q6_R_satb_R __builtin_HEXAGON_A2_satb |
474 | |
475 | /* ========================================================================== |
476 | Assembly Syntax: Rd32=sath(Rs32) |
477 | C Intrinsic Prototype: Word32 Q6_R_sath_R(Word32 Rs) |
478 | Instruction Type: S_2op |
479 | Execution Slots: SLOT23 |
480 | ========================================================================== */ |
481 | |
482 | #define Q6_R_sath_R __builtin_HEXAGON_A2_sath |
483 | |
484 | /* ========================================================================== |
485 | Assembly Syntax: Rd32=satub(Rs32) |
486 | C Intrinsic Prototype: Word32 Q6_R_satub_R(Word32 Rs) |
487 | Instruction Type: S_2op |
488 | Execution Slots: SLOT23 |
489 | ========================================================================== */ |
490 | |
491 | #define Q6_R_satub_R __builtin_HEXAGON_A2_satub |
492 | |
493 | /* ========================================================================== |
494 | Assembly Syntax: Rd32=satuh(Rs32) |
495 | C Intrinsic Prototype: Word32 Q6_R_satuh_R(Word32 Rs) |
496 | Instruction Type: S_2op |
497 | Execution Slots: SLOT23 |
498 | ========================================================================== */ |
499 | |
500 | #define Q6_R_satuh_R __builtin_HEXAGON_A2_satuh |
501 | |
502 | /* ========================================================================== |
503 | Assembly Syntax: Rd32=sub(Rt32,Rs32) |
504 | C Intrinsic Prototype: Word32 Q6_R_sub_RR(Word32 Rt, Word32 Rs) |
505 | Instruction Type: ALU32_3op |
506 | Execution Slots: SLOT0123 |
507 | ========================================================================== */ |
508 | |
509 | #define Q6_R_sub_RR __builtin_HEXAGON_A2_sub |
510 | |
511 | /* ========================================================================== |
512 | Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):<<16 |
513 | C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_s16(Word32 Rt, Word32 Rs) |
514 | Instruction Type: ALU64 |
515 | Execution Slots: SLOT23 |
516 | ========================================================================== */ |
517 | |
518 | #define Q6_R_sub_RhRh_s16 __builtin_HEXAGON_A2_subh_h16_hh |
519 | |
520 | /* ========================================================================== |
521 | Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):<<16 |
522 | C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_s16(Word32 Rt, Word32 Rs) |
523 | Instruction Type: ALU64 |
524 | Execution Slots: SLOT23 |
525 | ========================================================================== */ |
526 | |
527 | #define Q6_R_sub_RhRl_s16 __builtin_HEXAGON_A2_subh_h16_hl |
528 | |
529 | /* ========================================================================== |
530 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):<<16 |
531 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_s16(Word32 Rt, Word32 Rs) |
532 | Instruction Type: ALU64 |
533 | Execution Slots: SLOT23 |
534 | ========================================================================== */ |
535 | |
536 | #define Q6_R_sub_RlRh_s16 __builtin_HEXAGON_A2_subh_h16_lh |
537 | |
538 | /* ========================================================================== |
539 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):<<16 |
540 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_s16(Word32 Rt, Word32 Rs) |
541 | Instruction Type: ALU64 |
542 | Execution Slots: SLOT23 |
543 | ========================================================================== */ |
544 | |
545 | #define Q6_R_sub_RlRl_s16 __builtin_HEXAGON_A2_subh_h16_ll |
546 | |
547 | /* ========================================================================== |
548 | Assembly Syntax: Rd32=sub(Rt32.h,Rs32.h):sat:<<16 |
549 | C Intrinsic Prototype: Word32 Q6_R_sub_RhRh_sat_s16(Word32 Rt, Word32 Rs) |
550 | Instruction Type: ALU64 |
551 | Execution Slots: SLOT23 |
552 | ========================================================================== */ |
553 | |
554 | #define Q6_R_sub_RhRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hh |
555 | |
556 | /* ========================================================================== |
557 | Assembly Syntax: Rd32=sub(Rt32.h,Rs32.l):sat:<<16 |
558 | C Intrinsic Prototype: Word32 Q6_R_sub_RhRl_sat_s16(Word32 Rt, Word32 Rs) |
559 | Instruction Type: ALU64 |
560 | Execution Slots: SLOT23 |
561 | ========================================================================== */ |
562 | |
563 | #define Q6_R_sub_RhRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_hl |
564 | |
565 | /* ========================================================================== |
566 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat:<<16 |
567 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat_s16(Word32 Rt, Word32 Rs) |
568 | Instruction Type: ALU64 |
569 | Execution Slots: SLOT23 |
570 | ========================================================================== */ |
571 | |
572 | #define Q6_R_sub_RlRh_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_lh |
573 | |
574 | /* ========================================================================== |
575 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat:<<16 |
576 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat_s16(Word32 Rt, Word32 Rs) |
577 | Instruction Type: ALU64 |
578 | Execution Slots: SLOT23 |
579 | ========================================================================== */ |
580 | |
581 | #define Q6_R_sub_RlRl_sat_s16 __builtin_HEXAGON_A2_subh_h16_sat_ll |
582 | |
583 | /* ========================================================================== |
584 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h) |
585 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRh(Word32 Rt, Word32 Rs) |
586 | Instruction Type: ALU64 |
587 | Execution Slots: SLOT23 |
588 | ========================================================================== */ |
589 | |
590 | #define Q6_R_sub_RlRh __builtin_HEXAGON_A2_subh_l16_hl |
591 | |
592 | /* ========================================================================== |
593 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l) |
594 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRl(Word32 Rt, Word32 Rs) |
595 | Instruction Type: ALU64 |
596 | Execution Slots: SLOT23 |
597 | ========================================================================== */ |
598 | |
599 | #define Q6_R_sub_RlRl __builtin_HEXAGON_A2_subh_l16_ll |
600 | |
601 | /* ========================================================================== |
602 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.h):sat |
603 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRh_sat(Word32 Rt, Word32 Rs) |
604 | Instruction Type: ALU64 |
605 | Execution Slots: SLOT23 |
606 | ========================================================================== */ |
607 | |
608 | #define Q6_R_sub_RlRh_sat __builtin_HEXAGON_A2_subh_l16_sat_hl |
609 | |
610 | /* ========================================================================== |
611 | Assembly Syntax: Rd32=sub(Rt32.l,Rs32.l):sat |
612 | C Intrinsic Prototype: Word32 Q6_R_sub_RlRl_sat(Word32 Rt, Word32 Rs) |
613 | Instruction Type: ALU64 |
614 | Execution Slots: SLOT23 |
615 | ========================================================================== */ |
616 | |
617 | #define Q6_R_sub_RlRl_sat __builtin_HEXAGON_A2_subh_l16_sat_ll |
618 | |
619 | /* ========================================================================== |
620 | Assembly Syntax: Rdd32=sub(Rtt32,Rss32) |
621 | C Intrinsic Prototype: Word64 Q6_P_sub_PP(Word64 Rtt, Word64 Rss) |
622 | Instruction Type: ALU64 |
623 | Execution Slots: SLOT23 |
624 | ========================================================================== */ |
625 | |
626 | #define Q6_P_sub_PP __builtin_HEXAGON_A2_subp |
627 | |
628 | /* ========================================================================== |
629 | Assembly Syntax: Rd32=sub(#s10,Rs32) |
630 | C Intrinsic Prototype: Word32 Q6_R_sub_IR(Word32 Is10, Word32 Rs) |
631 | Instruction Type: ALU32_2op |
632 | Execution Slots: SLOT0123 |
633 | ========================================================================== */ |
634 | |
635 | #define Q6_R_sub_IR __builtin_HEXAGON_A2_subri |
636 | |
637 | /* ========================================================================== |
638 | Assembly Syntax: Rd32=sub(Rt32,Rs32):sat |
639 | C Intrinsic Prototype: Word32 Q6_R_sub_RR_sat(Word32 Rt, Word32 Rs) |
640 | Instruction Type: ALU32_3op |
641 | Execution Slots: SLOT0123 |
642 | ========================================================================== */ |
643 | |
644 | #define Q6_R_sub_RR_sat __builtin_HEXAGON_A2_subsat |
645 | |
646 | /* ========================================================================== |
647 | Assembly Syntax: Rd32=vaddh(Rs32,Rt32) |
648 | C Intrinsic Prototype: Word32 Q6_R_vaddh_RR(Word32 Rs, Word32 Rt) |
649 | Instruction Type: ALU32_3op |
650 | Execution Slots: SLOT0123 |
651 | ========================================================================== */ |
652 | |
653 | #define Q6_R_vaddh_RR __builtin_HEXAGON_A2_svaddh |
654 | |
655 | /* ========================================================================== |
656 | Assembly Syntax: Rd32=vaddh(Rs32,Rt32):sat |
657 | C Intrinsic Prototype: Word32 Q6_R_vaddh_RR_sat(Word32 Rs, Word32 Rt) |
658 | Instruction Type: ALU32_3op |
659 | Execution Slots: SLOT0123 |
660 | ========================================================================== */ |
661 | |
662 | #define Q6_R_vaddh_RR_sat __builtin_HEXAGON_A2_svaddhs |
663 | |
664 | /* ========================================================================== |
665 | Assembly Syntax: Rd32=vadduh(Rs32,Rt32):sat |
666 | C Intrinsic Prototype: Word32 Q6_R_vadduh_RR_sat(Word32 Rs, Word32 Rt) |
667 | Instruction Type: ALU32_3op |
668 | Execution Slots: SLOT0123 |
669 | ========================================================================== */ |
670 | |
671 | #define Q6_R_vadduh_RR_sat __builtin_HEXAGON_A2_svadduhs |
672 | |
673 | /* ========================================================================== |
674 | Assembly Syntax: Rd32=vavgh(Rs32,Rt32) |
675 | C Intrinsic Prototype: Word32 Q6_R_vavgh_RR(Word32 Rs, Word32 Rt) |
676 | Instruction Type: ALU32_3op |
677 | Execution Slots: SLOT0123 |
678 | ========================================================================== */ |
679 | |
680 | #define Q6_R_vavgh_RR __builtin_HEXAGON_A2_svavgh |
681 | |
682 | /* ========================================================================== |
683 | Assembly Syntax: Rd32=vavgh(Rs32,Rt32):rnd |
684 | C Intrinsic Prototype: Word32 Q6_R_vavgh_RR_rnd(Word32 Rs, Word32 Rt) |
685 | Instruction Type: ALU32_3op |
686 | Execution Slots: SLOT0123 |
687 | ========================================================================== */ |
688 | |
689 | #define Q6_R_vavgh_RR_rnd __builtin_HEXAGON_A2_svavghs |
690 | |
691 | /* ========================================================================== |
692 | Assembly Syntax: Rd32=vnavgh(Rt32,Rs32) |
693 | C Intrinsic Prototype: Word32 Q6_R_vnavgh_RR(Word32 Rt, Word32 Rs) |
694 | Instruction Type: ALU32_3op |
695 | Execution Slots: SLOT0123 |
696 | ========================================================================== */ |
697 | |
698 | #define Q6_R_vnavgh_RR __builtin_HEXAGON_A2_svnavgh |
699 | |
700 | /* ========================================================================== |
701 | Assembly Syntax: Rd32=vsubh(Rt32,Rs32) |
702 | C Intrinsic Prototype: Word32 Q6_R_vsubh_RR(Word32 Rt, Word32 Rs) |
703 | Instruction Type: ALU32_3op |
704 | Execution Slots: SLOT0123 |
705 | ========================================================================== */ |
706 | |
707 | #define Q6_R_vsubh_RR __builtin_HEXAGON_A2_svsubh |
708 | |
709 | /* ========================================================================== |
710 | Assembly Syntax: Rd32=vsubh(Rt32,Rs32):sat |
711 | C Intrinsic Prototype: Word32 Q6_R_vsubh_RR_sat(Word32 Rt, Word32 Rs) |
712 | Instruction Type: ALU32_3op |
713 | Execution Slots: SLOT0123 |
714 | ========================================================================== */ |
715 | |
716 | #define Q6_R_vsubh_RR_sat __builtin_HEXAGON_A2_svsubhs |
717 | |
718 | /* ========================================================================== |
719 | Assembly Syntax: Rd32=vsubuh(Rt32,Rs32):sat |
720 | C Intrinsic Prototype: Word32 Q6_R_vsubuh_RR_sat(Word32 Rt, Word32 Rs) |
721 | Instruction Type: ALU32_3op |
722 | Execution Slots: SLOT0123 |
723 | ========================================================================== */ |
724 | |
725 | #define Q6_R_vsubuh_RR_sat __builtin_HEXAGON_A2_svsubuhs |
726 | |
727 | /* ========================================================================== |
728 | Assembly Syntax: Rd32=swiz(Rs32) |
729 | C Intrinsic Prototype: Word32 Q6_R_swiz_R(Word32 Rs) |
730 | Instruction Type: S_2op |
731 | Execution Slots: SLOT23 |
732 | ========================================================================== */ |
733 | |
734 | #define Q6_R_swiz_R __builtin_HEXAGON_A2_swiz |
735 | |
736 | /* ========================================================================== |
737 | Assembly Syntax: Rd32=sxtb(Rs32) |
738 | C Intrinsic Prototype: Word32 Q6_R_sxtb_R(Word32 Rs) |
739 | Instruction Type: ALU32_2op |
740 | Execution Slots: SLOT0123 |
741 | ========================================================================== */ |
742 | |
743 | #define Q6_R_sxtb_R __builtin_HEXAGON_A2_sxtb |
744 | |
745 | /* ========================================================================== |
746 | Assembly Syntax: Rd32=sxth(Rs32) |
747 | C Intrinsic Prototype: Word32 Q6_R_sxth_R(Word32 Rs) |
748 | Instruction Type: ALU32_2op |
749 | Execution Slots: SLOT0123 |
750 | ========================================================================== */ |
751 | |
752 | #define Q6_R_sxth_R __builtin_HEXAGON_A2_sxth |
753 | |
754 | /* ========================================================================== |
755 | Assembly Syntax: Rdd32=sxtw(Rs32) |
756 | C Intrinsic Prototype: Word64 Q6_P_sxtw_R(Word32 Rs) |
757 | Instruction Type: S_2op |
758 | Execution Slots: SLOT23 |
759 | ========================================================================== */ |
760 | |
761 | #define Q6_P_sxtw_R __builtin_HEXAGON_A2_sxtw |
762 | |
763 | /* ========================================================================== |
764 | Assembly Syntax: Rd32=Rs32 |
765 | C Intrinsic Prototype: Word32 Q6_R_equals_R(Word32 Rs) |
766 | Instruction Type: ALU32_2op |
767 | Execution Slots: SLOT0123 |
768 | ========================================================================== */ |
769 | |
770 | #define Q6_R_equals_R __builtin_HEXAGON_A2_tfr |
771 | |
772 | /* ========================================================================== |
773 | Assembly Syntax: Rx32.h=#u16 |
774 | C Intrinsic Prototype: Word32 Q6_Rh_equals_I(Word32 Rx, Word32 Iu16) |
775 | Instruction Type: ALU32_2op |
776 | Execution Slots: SLOT0123 |
777 | ========================================================================== */ |
778 | |
779 | #define Q6_Rh_equals_I __builtin_HEXAGON_A2_tfrih |
780 | |
781 | /* ========================================================================== |
782 | Assembly Syntax: Rx32.l=#u16 |
783 | C Intrinsic Prototype: Word32 Q6_Rl_equals_I(Word32 Rx, Word32 Iu16) |
784 | Instruction Type: ALU32_2op |
785 | Execution Slots: SLOT0123 |
786 | ========================================================================== */ |
787 | |
788 | #define Q6_Rl_equals_I __builtin_HEXAGON_A2_tfril |
789 | |
790 | /* ========================================================================== |
791 | Assembly Syntax: Rdd32=Rss32 |
792 | C Intrinsic Prototype: Word64 Q6_P_equals_P(Word64 Rss) |
793 | Instruction Type: ALU32_2op |
794 | Execution Slots: SLOT0123 |
795 | ========================================================================== */ |
796 | |
797 | #define Q6_P_equals_P __builtin_HEXAGON_A2_tfrp |
798 | |
799 | /* ========================================================================== |
800 | Assembly Syntax: Rdd32=#s8 |
801 | C Intrinsic Prototype: Word64 Q6_P_equals_I(Word32 Is8) |
802 | Instruction Type: ALU64 |
803 | Execution Slots: SLOT0123 |
804 | ========================================================================== */ |
805 | |
806 | #define Q6_P_equals_I __builtin_HEXAGON_A2_tfrpi |
807 | |
808 | /* ========================================================================== |
809 | Assembly Syntax: Rd32=#s16 |
810 | C Intrinsic Prototype: Word32 Q6_R_equals_I(Word32 Is16) |
811 | Instruction Type: ALU32_2op |
812 | Execution Slots: SLOT0123 |
813 | ========================================================================== */ |
814 | |
815 | #define Q6_R_equals_I __builtin_HEXAGON_A2_tfrsi |
816 | |
817 | /* ========================================================================== |
818 | Assembly Syntax: Rdd32=vabsh(Rss32) |
819 | C Intrinsic Prototype: Word64 Q6_P_vabsh_P(Word64 Rss) |
820 | Instruction Type: S_2op |
821 | Execution Slots: SLOT23 |
822 | ========================================================================== */ |
823 | |
824 | #define Q6_P_vabsh_P __builtin_HEXAGON_A2_vabsh |
825 | |
826 | /* ========================================================================== |
827 | Assembly Syntax: Rdd32=vabsh(Rss32):sat |
828 | C Intrinsic Prototype: Word64 Q6_P_vabsh_P_sat(Word64 Rss) |
829 | Instruction Type: S_2op |
830 | Execution Slots: SLOT23 |
831 | ========================================================================== */ |
832 | |
833 | #define Q6_P_vabsh_P_sat __builtin_HEXAGON_A2_vabshsat |
834 | |
835 | /* ========================================================================== |
836 | Assembly Syntax: Rdd32=vabsw(Rss32) |
837 | C Intrinsic Prototype: Word64 Q6_P_vabsw_P(Word64 Rss) |
838 | Instruction Type: S_2op |
839 | Execution Slots: SLOT23 |
840 | ========================================================================== */ |
841 | |
842 | #define Q6_P_vabsw_P __builtin_HEXAGON_A2_vabsw |
843 | |
844 | /* ========================================================================== |
845 | Assembly Syntax: Rdd32=vabsw(Rss32):sat |
846 | C Intrinsic Prototype: Word64 Q6_P_vabsw_P_sat(Word64 Rss) |
847 | Instruction Type: S_2op |
848 | Execution Slots: SLOT23 |
849 | ========================================================================== */ |
850 | |
851 | #define Q6_P_vabsw_P_sat __builtin_HEXAGON_A2_vabswsat |
852 | |
853 | /* ========================================================================== |
854 | Assembly Syntax: Rdd32=vaddb(Rss32,Rtt32) |
855 | C Intrinsic Prototype: Word64 Q6_P_vaddb_PP(Word64 Rss, Word64 Rtt) |
856 | Instruction Type: MAPPING |
857 | Execution Slots: SLOT0123 |
858 | ========================================================================== */ |
859 | |
860 | #define Q6_P_vaddb_PP __builtin_HEXAGON_A2_vaddb_map |
861 | |
862 | /* ========================================================================== |
863 | Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32) |
864 | C Intrinsic Prototype: Word64 Q6_P_vaddh_PP(Word64 Rss, Word64 Rtt) |
865 | Instruction Type: ALU64 |
866 | Execution Slots: SLOT23 |
867 | ========================================================================== */ |
868 | |
869 | #define Q6_P_vaddh_PP __builtin_HEXAGON_A2_vaddh |
870 | |
871 | /* ========================================================================== |
872 | Assembly Syntax: Rdd32=vaddh(Rss32,Rtt32):sat |
873 | C Intrinsic Prototype: Word64 Q6_P_vaddh_PP_sat(Word64 Rss, Word64 Rtt) |
874 | Instruction Type: ALU64 |
875 | Execution Slots: SLOT23 |
876 | ========================================================================== */ |
877 | |
878 | #define Q6_P_vaddh_PP_sat __builtin_HEXAGON_A2_vaddhs |
879 | |
880 | /* ========================================================================== |
881 | Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32) |
882 | C Intrinsic Prototype: Word64 Q6_P_vaddub_PP(Word64 Rss, Word64 Rtt) |
883 | Instruction Type: ALU64 |
884 | Execution Slots: SLOT23 |
885 | ========================================================================== */ |
886 | |
887 | #define Q6_P_vaddub_PP __builtin_HEXAGON_A2_vaddub |
888 | |
889 | /* ========================================================================== |
890 | Assembly Syntax: Rdd32=vaddub(Rss32,Rtt32):sat |
891 | C Intrinsic Prototype: Word64 Q6_P_vaddub_PP_sat(Word64 Rss, Word64 Rtt) |
892 | Instruction Type: ALU64 |
893 | Execution Slots: SLOT23 |
894 | ========================================================================== */ |
895 | |
896 | #define Q6_P_vaddub_PP_sat __builtin_HEXAGON_A2_vaddubs |
897 | |
898 | /* ========================================================================== |
899 | Assembly Syntax: Rdd32=vadduh(Rss32,Rtt32):sat |
900 | C Intrinsic Prototype: Word64 Q6_P_vadduh_PP_sat(Word64 Rss, Word64 Rtt) |
901 | Instruction Type: ALU64 |
902 | Execution Slots: SLOT23 |
903 | ========================================================================== */ |
904 | |
905 | #define Q6_P_vadduh_PP_sat __builtin_HEXAGON_A2_vadduhs |
906 | |
907 | /* ========================================================================== |
908 | Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32) |
909 | C Intrinsic Prototype: Word64 Q6_P_vaddw_PP(Word64 Rss, Word64 Rtt) |
910 | Instruction Type: ALU64 |
911 | Execution Slots: SLOT23 |
912 | ========================================================================== */ |
913 | |
914 | #define Q6_P_vaddw_PP __builtin_HEXAGON_A2_vaddw |
915 | |
916 | /* ========================================================================== |
917 | Assembly Syntax: Rdd32=vaddw(Rss32,Rtt32):sat |
918 | C Intrinsic Prototype: Word64 Q6_P_vaddw_PP_sat(Word64 Rss, Word64 Rtt) |
919 | Instruction Type: ALU64 |
920 | Execution Slots: SLOT23 |
921 | ========================================================================== */ |
922 | |
923 | #define Q6_P_vaddw_PP_sat __builtin_HEXAGON_A2_vaddws |
924 | |
925 | /* ========================================================================== |
926 | Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32) |
927 | C Intrinsic Prototype: Word64 Q6_P_vavgh_PP(Word64 Rss, Word64 Rtt) |
928 | Instruction Type: ALU64 |
929 | Execution Slots: SLOT23 |
930 | ========================================================================== */ |
931 | |
932 | #define Q6_P_vavgh_PP __builtin_HEXAGON_A2_vavgh |
933 | |
934 | /* ========================================================================== |
935 | Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):crnd |
936 | C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_crnd(Word64 Rss, Word64 Rtt) |
937 | Instruction Type: ALU64 |
938 | Execution Slots: SLOT23 |
939 | ========================================================================== */ |
940 | |
941 | #define Q6_P_vavgh_PP_crnd __builtin_HEXAGON_A2_vavghcr |
942 | |
943 | /* ========================================================================== |
944 | Assembly Syntax: Rdd32=vavgh(Rss32,Rtt32):rnd |
945 | C Intrinsic Prototype: Word64 Q6_P_vavgh_PP_rnd(Word64 Rss, Word64 Rtt) |
946 | Instruction Type: ALU64 |
947 | Execution Slots: SLOT23 |
948 | ========================================================================== */ |
949 | |
950 | #define Q6_P_vavgh_PP_rnd __builtin_HEXAGON_A2_vavghr |
951 | |
952 | /* ========================================================================== |
953 | Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32) |
954 | C Intrinsic Prototype: Word64 Q6_P_vavgub_PP(Word64 Rss, Word64 Rtt) |
955 | Instruction Type: ALU64 |
956 | Execution Slots: SLOT23 |
957 | ========================================================================== */ |
958 | |
959 | #define Q6_P_vavgub_PP __builtin_HEXAGON_A2_vavgub |
960 | |
961 | /* ========================================================================== |
962 | Assembly Syntax: Rdd32=vavgub(Rss32,Rtt32):rnd |
963 | C Intrinsic Prototype: Word64 Q6_P_vavgub_PP_rnd(Word64 Rss, Word64 Rtt) |
964 | Instruction Type: ALU64 |
965 | Execution Slots: SLOT23 |
966 | ========================================================================== */ |
967 | |
968 | #define Q6_P_vavgub_PP_rnd __builtin_HEXAGON_A2_vavgubr |
969 | |
970 | /* ========================================================================== |
971 | Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32) |
972 | C Intrinsic Prototype: Word64 Q6_P_vavguh_PP(Word64 Rss, Word64 Rtt) |
973 | Instruction Type: ALU64 |
974 | Execution Slots: SLOT23 |
975 | ========================================================================== */ |
976 | |
977 | #define Q6_P_vavguh_PP __builtin_HEXAGON_A2_vavguh |
978 | |
979 | /* ========================================================================== |
980 | Assembly Syntax: Rdd32=vavguh(Rss32,Rtt32):rnd |
981 | C Intrinsic Prototype: Word64 Q6_P_vavguh_PP_rnd(Word64 Rss, Word64 Rtt) |
982 | Instruction Type: ALU64 |
983 | Execution Slots: SLOT23 |
984 | ========================================================================== */ |
985 | |
986 | #define Q6_P_vavguh_PP_rnd __builtin_HEXAGON_A2_vavguhr |
987 | |
988 | /* ========================================================================== |
989 | Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32) |
990 | C Intrinsic Prototype: Word64 Q6_P_vavguw_PP(Word64 Rss, Word64 Rtt) |
991 | Instruction Type: ALU64 |
992 | Execution Slots: SLOT23 |
993 | ========================================================================== */ |
994 | |
995 | #define Q6_P_vavguw_PP __builtin_HEXAGON_A2_vavguw |
996 | |
997 | /* ========================================================================== |
998 | Assembly Syntax: Rdd32=vavguw(Rss32,Rtt32):rnd |
999 | C Intrinsic Prototype: Word64 Q6_P_vavguw_PP_rnd(Word64 Rss, Word64 Rtt) |
1000 | Instruction Type: ALU64 |
1001 | Execution Slots: SLOT23 |
1002 | ========================================================================== */ |
1003 | |
1004 | #define Q6_P_vavguw_PP_rnd __builtin_HEXAGON_A2_vavguwr |
1005 | |
1006 | /* ========================================================================== |
1007 | Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32) |
1008 | C Intrinsic Prototype: Word64 Q6_P_vavgw_PP(Word64 Rss, Word64 Rtt) |
1009 | Instruction Type: ALU64 |
1010 | Execution Slots: SLOT23 |
1011 | ========================================================================== */ |
1012 | |
1013 | #define Q6_P_vavgw_PP __builtin_HEXAGON_A2_vavgw |
1014 | |
1015 | /* ========================================================================== |
1016 | Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):crnd |
1017 | C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_crnd(Word64 Rss, Word64 Rtt) |
1018 | Instruction Type: ALU64 |
1019 | Execution Slots: SLOT23 |
1020 | ========================================================================== */ |
1021 | |
1022 | #define Q6_P_vavgw_PP_crnd __builtin_HEXAGON_A2_vavgwcr |
1023 | |
1024 | /* ========================================================================== |
1025 | Assembly Syntax: Rdd32=vavgw(Rss32,Rtt32):rnd |
1026 | C Intrinsic Prototype: Word64 Q6_P_vavgw_PP_rnd(Word64 Rss, Word64 Rtt) |
1027 | Instruction Type: ALU64 |
1028 | Execution Slots: SLOT23 |
1029 | ========================================================================== */ |
1030 | |
1031 | #define Q6_P_vavgw_PP_rnd __builtin_HEXAGON_A2_vavgwr |
1032 | |
1033 | /* ========================================================================== |
1034 | Assembly Syntax: Pd4=vcmpb.eq(Rss32,Rtt32) |
1035 | C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) |
1036 | Instruction Type: ALU64 |
1037 | Execution Slots: SLOT23 |
1038 | ========================================================================== */ |
1039 | |
1040 | #define Q6_p_vcmpb_eq_PP __builtin_HEXAGON_A2_vcmpbeq |
1041 | |
1042 | /* ========================================================================== |
1043 | Assembly Syntax: Pd4=vcmpb.gtu(Rss32,Rtt32) |
1044 | C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PP(Word64 Rss, Word64 Rtt) |
1045 | Instruction Type: ALU64 |
1046 | Execution Slots: SLOT23 |
1047 | ========================================================================== */ |
1048 | |
1049 | #define Q6_p_vcmpb_gtu_PP __builtin_HEXAGON_A2_vcmpbgtu |
1050 | |
1051 | /* ========================================================================== |
1052 | Assembly Syntax: Pd4=vcmph.eq(Rss32,Rtt32) |
1053 | C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PP(Word64 Rss, Word64 Rtt) |
1054 | Instruction Type: ALU64 |
1055 | Execution Slots: SLOT23 |
1056 | ========================================================================== */ |
1057 | |
1058 | #define Q6_p_vcmph_eq_PP __builtin_HEXAGON_A2_vcmpheq |
1059 | |
1060 | /* ========================================================================== |
1061 | Assembly Syntax: Pd4=vcmph.gt(Rss32,Rtt32) |
1062 | C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PP(Word64 Rss, Word64 Rtt) |
1063 | Instruction Type: ALU64 |
1064 | Execution Slots: SLOT23 |
1065 | ========================================================================== */ |
1066 | |
1067 | #define Q6_p_vcmph_gt_PP __builtin_HEXAGON_A2_vcmphgt |
1068 | |
1069 | /* ========================================================================== |
1070 | Assembly Syntax: Pd4=vcmph.gtu(Rss32,Rtt32) |
1071 | C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PP(Word64 Rss, Word64 Rtt) |
1072 | Instruction Type: ALU64 |
1073 | Execution Slots: SLOT23 |
1074 | ========================================================================== */ |
1075 | |
1076 | #define Q6_p_vcmph_gtu_PP __builtin_HEXAGON_A2_vcmphgtu |
1077 | |
1078 | /* ========================================================================== |
1079 | Assembly Syntax: Pd4=vcmpw.eq(Rss32,Rtt32) |
1080 | C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PP(Word64 Rss, Word64 Rtt) |
1081 | Instruction Type: ALU64 |
1082 | Execution Slots: SLOT23 |
1083 | ========================================================================== */ |
1084 | |
1085 | #define Q6_p_vcmpw_eq_PP __builtin_HEXAGON_A2_vcmpweq |
1086 | |
1087 | /* ========================================================================== |
1088 | Assembly Syntax: Pd4=vcmpw.gt(Rss32,Rtt32) |
1089 | C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PP(Word64 Rss, Word64 Rtt) |
1090 | Instruction Type: ALU64 |
1091 | Execution Slots: SLOT23 |
1092 | ========================================================================== */ |
1093 | |
1094 | #define Q6_p_vcmpw_gt_PP __builtin_HEXAGON_A2_vcmpwgt |
1095 | |
1096 | /* ========================================================================== |
1097 | Assembly Syntax: Pd4=vcmpw.gtu(Rss32,Rtt32) |
1098 | C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PP(Word64 Rss, Word64 Rtt) |
1099 | Instruction Type: ALU64 |
1100 | Execution Slots: SLOT23 |
1101 | ========================================================================== */ |
1102 | |
1103 | #define Q6_p_vcmpw_gtu_PP __builtin_HEXAGON_A2_vcmpwgtu |
1104 | |
1105 | /* ========================================================================== |
1106 | Assembly Syntax: Rdd32=vconj(Rss32):sat |
1107 | C Intrinsic Prototype: Word64 Q6_P_vconj_P_sat(Word64 Rss) |
1108 | Instruction Type: S_2op |
1109 | Execution Slots: SLOT23 |
1110 | ========================================================================== */ |
1111 | |
1112 | #define Q6_P_vconj_P_sat __builtin_HEXAGON_A2_vconj |
1113 | |
1114 | /* ========================================================================== |
1115 | Assembly Syntax: Rdd32=vmaxb(Rtt32,Rss32) |
1116 | C Intrinsic Prototype: Word64 Q6_P_vmaxb_PP(Word64 Rtt, Word64 Rss) |
1117 | Instruction Type: ALU64 |
1118 | Execution Slots: SLOT23 |
1119 | ========================================================================== */ |
1120 | |
1121 | #define Q6_P_vmaxb_PP __builtin_HEXAGON_A2_vmaxb |
1122 | |
1123 | /* ========================================================================== |
1124 | Assembly Syntax: Rdd32=vmaxh(Rtt32,Rss32) |
1125 | C Intrinsic Prototype: Word64 Q6_P_vmaxh_PP(Word64 Rtt, Word64 Rss) |
1126 | Instruction Type: ALU64 |
1127 | Execution Slots: SLOT23 |
1128 | ========================================================================== */ |
1129 | |
1130 | #define Q6_P_vmaxh_PP __builtin_HEXAGON_A2_vmaxh |
1131 | |
1132 | /* ========================================================================== |
1133 | Assembly Syntax: Rdd32=vmaxub(Rtt32,Rss32) |
1134 | C Intrinsic Prototype: Word64 Q6_P_vmaxub_PP(Word64 Rtt, Word64 Rss) |
1135 | Instruction Type: ALU64 |
1136 | Execution Slots: SLOT23 |
1137 | ========================================================================== */ |
1138 | |
1139 | #define Q6_P_vmaxub_PP __builtin_HEXAGON_A2_vmaxub |
1140 | |
1141 | /* ========================================================================== |
1142 | Assembly Syntax: Rdd32=vmaxuh(Rtt32,Rss32) |
1143 | C Intrinsic Prototype: Word64 Q6_P_vmaxuh_PP(Word64 Rtt, Word64 Rss) |
1144 | Instruction Type: ALU64 |
1145 | Execution Slots: SLOT23 |
1146 | ========================================================================== */ |
1147 | |
1148 | #define Q6_P_vmaxuh_PP __builtin_HEXAGON_A2_vmaxuh |
1149 | |
1150 | /* ========================================================================== |
1151 | Assembly Syntax: Rdd32=vmaxuw(Rtt32,Rss32) |
1152 | C Intrinsic Prototype: Word64 Q6_P_vmaxuw_PP(Word64 Rtt, Word64 Rss) |
1153 | Instruction Type: ALU64 |
1154 | Execution Slots: SLOT23 |
1155 | ========================================================================== */ |
1156 | |
1157 | #define Q6_P_vmaxuw_PP __builtin_HEXAGON_A2_vmaxuw |
1158 | |
1159 | /* ========================================================================== |
1160 | Assembly Syntax: Rdd32=vmaxw(Rtt32,Rss32) |
1161 | C Intrinsic Prototype: Word64 Q6_P_vmaxw_PP(Word64 Rtt, Word64 Rss) |
1162 | Instruction Type: ALU64 |
1163 | Execution Slots: SLOT23 |
1164 | ========================================================================== */ |
1165 | |
1166 | #define Q6_P_vmaxw_PP __builtin_HEXAGON_A2_vmaxw |
1167 | |
1168 | /* ========================================================================== |
1169 | Assembly Syntax: Rdd32=vminb(Rtt32,Rss32) |
1170 | C Intrinsic Prototype: Word64 Q6_P_vminb_PP(Word64 Rtt, Word64 Rss) |
1171 | Instruction Type: ALU64 |
1172 | Execution Slots: SLOT23 |
1173 | ========================================================================== */ |
1174 | |
1175 | #define Q6_P_vminb_PP __builtin_HEXAGON_A2_vminb |
1176 | |
1177 | /* ========================================================================== |
1178 | Assembly Syntax: Rdd32=vminh(Rtt32,Rss32) |
1179 | C Intrinsic Prototype: Word64 Q6_P_vminh_PP(Word64 Rtt, Word64 Rss) |
1180 | Instruction Type: ALU64 |
1181 | Execution Slots: SLOT23 |
1182 | ========================================================================== */ |
1183 | |
1184 | #define Q6_P_vminh_PP __builtin_HEXAGON_A2_vminh |
1185 | |
1186 | /* ========================================================================== |
1187 | Assembly Syntax: Rdd32=vminub(Rtt32,Rss32) |
1188 | C Intrinsic Prototype: Word64 Q6_P_vminub_PP(Word64 Rtt, Word64 Rss) |
1189 | Instruction Type: ALU64 |
1190 | Execution Slots: SLOT23 |
1191 | ========================================================================== */ |
1192 | |
1193 | #define Q6_P_vminub_PP __builtin_HEXAGON_A2_vminub |
1194 | |
1195 | /* ========================================================================== |
1196 | Assembly Syntax: Rdd32=vminuh(Rtt32,Rss32) |
1197 | C Intrinsic Prototype: Word64 Q6_P_vminuh_PP(Word64 Rtt, Word64 Rss) |
1198 | Instruction Type: ALU64 |
1199 | Execution Slots: SLOT23 |
1200 | ========================================================================== */ |
1201 | |
1202 | #define Q6_P_vminuh_PP __builtin_HEXAGON_A2_vminuh |
1203 | |
1204 | /* ========================================================================== |
1205 | Assembly Syntax: Rdd32=vminuw(Rtt32,Rss32) |
1206 | C Intrinsic Prototype: Word64 Q6_P_vminuw_PP(Word64 Rtt, Word64 Rss) |
1207 | Instruction Type: ALU64 |
1208 | Execution Slots: SLOT23 |
1209 | ========================================================================== */ |
1210 | |
1211 | #define Q6_P_vminuw_PP __builtin_HEXAGON_A2_vminuw |
1212 | |
1213 | /* ========================================================================== |
1214 | Assembly Syntax: Rdd32=vminw(Rtt32,Rss32) |
1215 | C Intrinsic Prototype: Word64 Q6_P_vminw_PP(Word64 Rtt, Word64 Rss) |
1216 | Instruction Type: ALU64 |
1217 | Execution Slots: SLOT23 |
1218 | ========================================================================== */ |
1219 | |
1220 | #define Q6_P_vminw_PP __builtin_HEXAGON_A2_vminw |
1221 | |
1222 | /* ========================================================================== |
1223 | Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32) |
1224 | C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP(Word64 Rtt, Word64 Rss) |
1225 | Instruction Type: ALU64 |
1226 | Execution Slots: SLOT23 |
1227 | ========================================================================== */ |
1228 | |
1229 | #define Q6_P_vnavgh_PP __builtin_HEXAGON_A2_vnavgh |
1230 | |
1231 | /* ========================================================================== |
1232 | Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):crnd:sat |
1233 | C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_crnd_sat(Word64 Rtt, Word64 Rss) |
1234 | Instruction Type: ALU64 |
1235 | Execution Slots: SLOT23 |
1236 | ========================================================================== */ |
1237 | |
1238 | #define Q6_P_vnavgh_PP_crnd_sat __builtin_HEXAGON_A2_vnavghcr |
1239 | |
1240 | /* ========================================================================== |
1241 | Assembly Syntax: Rdd32=vnavgh(Rtt32,Rss32):rnd:sat |
1242 | C Intrinsic Prototype: Word64 Q6_P_vnavgh_PP_rnd_sat(Word64 Rtt, Word64 Rss) |
1243 | Instruction Type: ALU64 |
1244 | Execution Slots: SLOT23 |
1245 | ========================================================================== */ |
1246 | |
1247 | #define Q6_P_vnavgh_PP_rnd_sat __builtin_HEXAGON_A2_vnavghr |
1248 | |
1249 | /* ========================================================================== |
1250 | Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32) |
1251 | C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP(Word64 Rtt, Word64 Rss) |
1252 | Instruction Type: ALU64 |
1253 | Execution Slots: SLOT23 |
1254 | ========================================================================== */ |
1255 | |
1256 | #define Q6_P_vnavgw_PP __builtin_HEXAGON_A2_vnavgw |
1257 | |
1258 | /* ========================================================================== |
1259 | Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):crnd:sat |
1260 | C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_crnd_sat(Word64 Rtt, Word64 Rss) |
1261 | Instruction Type: ALU64 |
1262 | Execution Slots: SLOT23 |
1263 | ========================================================================== */ |
1264 | |
1265 | #define Q6_P_vnavgw_PP_crnd_sat __builtin_HEXAGON_A2_vnavgwcr |
1266 | |
1267 | /* ========================================================================== |
1268 | Assembly Syntax: Rdd32=vnavgw(Rtt32,Rss32):rnd:sat |
1269 | C Intrinsic Prototype: Word64 Q6_P_vnavgw_PP_rnd_sat(Word64 Rtt, Word64 Rss) |
1270 | Instruction Type: ALU64 |
1271 | Execution Slots: SLOT23 |
1272 | ========================================================================== */ |
1273 | |
1274 | #define Q6_P_vnavgw_PP_rnd_sat __builtin_HEXAGON_A2_vnavgwr |
1275 | |
1276 | /* ========================================================================== |
1277 | Assembly Syntax: Rdd32=vraddub(Rss32,Rtt32) |
1278 | C Intrinsic Prototype: Word64 Q6_P_vraddub_PP(Word64 Rss, Word64 Rtt) |
1279 | Instruction Type: M |
1280 | Execution Slots: SLOT23 |
1281 | ========================================================================== */ |
1282 | |
1283 | #define Q6_P_vraddub_PP __builtin_HEXAGON_A2_vraddub |
1284 | |
1285 | /* ========================================================================== |
1286 | Assembly Syntax: Rxx32+=vraddub(Rss32,Rtt32) |
1287 | C Intrinsic Prototype: Word64 Q6_P_vraddubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
1288 | Instruction Type: M |
1289 | Execution Slots: SLOT23 |
1290 | ========================================================================== */ |
1291 | |
1292 | #define Q6_P_vraddubacc_PP __builtin_HEXAGON_A2_vraddub_acc |
1293 | |
1294 | /* ========================================================================== |
1295 | Assembly Syntax: Rdd32=vrsadub(Rss32,Rtt32) |
1296 | C Intrinsic Prototype: Word64 Q6_P_vrsadub_PP(Word64 Rss, Word64 Rtt) |
1297 | Instruction Type: M |
1298 | Execution Slots: SLOT23 |
1299 | ========================================================================== */ |
1300 | |
1301 | #define Q6_P_vrsadub_PP __builtin_HEXAGON_A2_vrsadub |
1302 | |
1303 | /* ========================================================================== |
1304 | Assembly Syntax: Rxx32+=vrsadub(Rss32,Rtt32) |
1305 | C Intrinsic Prototype: Word64 Q6_P_vrsadubacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
1306 | Instruction Type: M |
1307 | Execution Slots: SLOT23 |
1308 | ========================================================================== */ |
1309 | |
1310 | #define Q6_P_vrsadubacc_PP __builtin_HEXAGON_A2_vrsadub_acc |
1311 | |
1312 | /* ========================================================================== |
1313 | Assembly Syntax: Rdd32=vsubb(Rss32,Rtt32) |
1314 | C Intrinsic Prototype: Word64 Q6_P_vsubb_PP(Word64 Rss, Word64 Rtt) |
1315 | Instruction Type: MAPPING |
1316 | Execution Slots: SLOT0123 |
1317 | ========================================================================== */ |
1318 | |
1319 | #define Q6_P_vsubb_PP __builtin_HEXAGON_A2_vsubb_map |
1320 | |
1321 | /* ========================================================================== |
1322 | Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32) |
1323 | C Intrinsic Prototype: Word64 Q6_P_vsubh_PP(Word64 Rtt, Word64 Rss) |
1324 | Instruction Type: ALU64 |
1325 | Execution Slots: SLOT23 |
1326 | ========================================================================== */ |
1327 | |
1328 | #define Q6_P_vsubh_PP __builtin_HEXAGON_A2_vsubh |
1329 | |
1330 | /* ========================================================================== |
1331 | Assembly Syntax: Rdd32=vsubh(Rtt32,Rss32):sat |
1332 | C Intrinsic Prototype: Word64 Q6_P_vsubh_PP_sat(Word64 Rtt, Word64 Rss) |
1333 | Instruction Type: ALU64 |
1334 | Execution Slots: SLOT23 |
1335 | ========================================================================== */ |
1336 | |
1337 | #define Q6_P_vsubh_PP_sat __builtin_HEXAGON_A2_vsubhs |
1338 | |
1339 | /* ========================================================================== |
1340 | Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32) |
1341 | C Intrinsic Prototype: Word64 Q6_P_vsubub_PP(Word64 Rtt, Word64 Rss) |
1342 | Instruction Type: ALU64 |
1343 | Execution Slots: SLOT23 |
1344 | ========================================================================== */ |
1345 | |
1346 | #define Q6_P_vsubub_PP __builtin_HEXAGON_A2_vsubub |
1347 | |
1348 | /* ========================================================================== |
1349 | Assembly Syntax: Rdd32=vsubub(Rtt32,Rss32):sat |
1350 | C Intrinsic Prototype: Word64 Q6_P_vsubub_PP_sat(Word64 Rtt, Word64 Rss) |
1351 | Instruction Type: ALU64 |
1352 | Execution Slots: SLOT23 |
1353 | ========================================================================== */ |
1354 | |
1355 | #define Q6_P_vsubub_PP_sat __builtin_HEXAGON_A2_vsububs |
1356 | |
1357 | /* ========================================================================== |
1358 | Assembly Syntax: Rdd32=vsubuh(Rtt32,Rss32):sat |
1359 | C Intrinsic Prototype: Word64 Q6_P_vsubuh_PP_sat(Word64 Rtt, Word64 Rss) |
1360 | Instruction Type: ALU64 |
1361 | Execution Slots: SLOT23 |
1362 | ========================================================================== */ |
1363 | |
1364 | #define Q6_P_vsubuh_PP_sat __builtin_HEXAGON_A2_vsubuhs |
1365 | |
1366 | /* ========================================================================== |
1367 | Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32) |
1368 | C Intrinsic Prototype: Word64 Q6_P_vsubw_PP(Word64 Rtt, Word64 Rss) |
1369 | Instruction Type: ALU64 |
1370 | Execution Slots: SLOT23 |
1371 | ========================================================================== */ |
1372 | |
1373 | #define Q6_P_vsubw_PP __builtin_HEXAGON_A2_vsubw |
1374 | |
1375 | /* ========================================================================== |
1376 | Assembly Syntax: Rdd32=vsubw(Rtt32,Rss32):sat |
1377 | C Intrinsic Prototype: Word64 Q6_P_vsubw_PP_sat(Word64 Rtt, Word64 Rss) |
1378 | Instruction Type: ALU64 |
1379 | Execution Slots: SLOT23 |
1380 | ========================================================================== */ |
1381 | |
1382 | #define Q6_P_vsubw_PP_sat __builtin_HEXAGON_A2_vsubws |
1383 | |
1384 | /* ========================================================================== |
1385 | Assembly Syntax: Rd32=xor(Rs32,Rt32) |
1386 | C Intrinsic Prototype: Word32 Q6_R_xor_RR(Word32 Rs, Word32 Rt) |
1387 | Instruction Type: ALU32_3op |
1388 | Execution Slots: SLOT0123 |
1389 | ========================================================================== */ |
1390 | |
1391 | #define Q6_R_xor_RR __builtin_HEXAGON_A2_xor |
1392 | |
1393 | /* ========================================================================== |
1394 | Assembly Syntax: Rdd32=xor(Rss32,Rtt32) |
1395 | C Intrinsic Prototype: Word64 Q6_P_xor_PP(Word64 Rss, Word64 Rtt) |
1396 | Instruction Type: ALU64 |
1397 | Execution Slots: SLOT23 |
1398 | ========================================================================== */ |
1399 | |
1400 | #define Q6_P_xor_PP __builtin_HEXAGON_A2_xorp |
1401 | |
1402 | /* ========================================================================== |
1403 | Assembly Syntax: Rd32=zxtb(Rs32) |
1404 | C Intrinsic Prototype: Word32 Q6_R_zxtb_R(Word32 Rs) |
1405 | Instruction Type: ALU32_2op |
1406 | Execution Slots: SLOT0123 |
1407 | ========================================================================== */ |
1408 | |
1409 | #define Q6_R_zxtb_R __builtin_HEXAGON_A2_zxtb |
1410 | |
1411 | /* ========================================================================== |
1412 | Assembly Syntax: Rd32=zxth(Rs32) |
1413 | C Intrinsic Prototype: Word32 Q6_R_zxth_R(Word32 Rs) |
1414 | Instruction Type: ALU32_2op |
1415 | Execution Slots: SLOT0123 |
1416 | ========================================================================== */ |
1417 | |
1418 | #define Q6_R_zxth_R __builtin_HEXAGON_A2_zxth |
1419 | |
1420 | /* ========================================================================== |
1421 | Assembly Syntax: Rd32=and(Rt32,~Rs32) |
1422 | C Intrinsic Prototype: Word32 Q6_R_and_RnR(Word32 Rt, Word32 Rs) |
1423 | Instruction Type: ALU32_3op |
1424 | Execution Slots: SLOT0123 |
1425 | ========================================================================== */ |
1426 | |
1427 | #define Q6_R_and_RnR __builtin_HEXAGON_A4_andn |
1428 | |
1429 | /* ========================================================================== |
1430 | Assembly Syntax: Rdd32=and(Rtt32,~Rss32) |
1431 | C Intrinsic Prototype: Word64 Q6_P_and_PnP(Word64 Rtt, Word64 Rss) |
1432 | Instruction Type: ALU64 |
1433 | Execution Slots: SLOT23 |
1434 | ========================================================================== */ |
1435 | |
1436 | #define Q6_P_and_PnP __builtin_HEXAGON_A4_andnp |
1437 | |
1438 | /* ========================================================================== |
1439 | Assembly Syntax: Rdd32=bitsplit(Rs32,Rt32) |
1440 | C Intrinsic Prototype: Word64 Q6_P_bitsplit_RR(Word32 Rs, Word32 Rt) |
1441 | Instruction Type: ALU64 |
1442 | Execution Slots: SLOT23 |
1443 | ========================================================================== */ |
1444 | |
1445 | #define Q6_P_bitsplit_RR __builtin_HEXAGON_A4_bitsplit |
1446 | |
1447 | /* ========================================================================== |
1448 | Assembly Syntax: Rdd32=bitsplit(Rs32,#u5) |
1449 | C Intrinsic Prototype: Word64 Q6_P_bitsplit_RI(Word32 Rs, Word32 Iu5) |
1450 | Instruction Type: S_2op |
1451 | Execution Slots: SLOT23 |
1452 | ========================================================================== */ |
1453 | |
1454 | #define Q6_P_bitsplit_RI __builtin_HEXAGON_A4_bitspliti |
1455 | |
1456 | /* ========================================================================== |
1457 | Assembly Syntax: Pd4=boundscheck(Rs32,Rtt32) |
1458 | C Intrinsic Prototype: Byte Q6_p_boundscheck_RP(Word32 Rs, Word64 Rtt) |
1459 | Instruction Type: ALU64 |
1460 | Execution Slots: SLOT0123 |
1461 | ========================================================================== */ |
1462 | |
1463 | #define Q6_p_boundscheck_RP __builtin_HEXAGON_A4_boundscheck |
1464 | |
1465 | /* ========================================================================== |
1466 | Assembly Syntax: Pd4=cmpb.eq(Rs32,Rt32) |
1467 | C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RR(Word32 Rs, Word32 Rt) |
1468 | Instruction Type: S_3op |
1469 | Execution Slots: SLOT23 |
1470 | ========================================================================== */ |
1471 | |
1472 | #define Q6_p_cmpb_eq_RR __builtin_HEXAGON_A4_cmpbeq |
1473 | |
1474 | /* ========================================================================== |
1475 | Assembly Syntax: Pd4=cmpb.eq(Rs32,#u8) |
1476 | C Intrinsic Prototype: Byte Q6_p_cmpb_eq_RI(Word32 Rs, Word32 Iu8) |
1477 | Instruction Type: ALU64 |
1478 | Execution Slots: SLOT23 |
1479 | ========================================================================== */ |
1480 | |
1481 | #define Q6_p_cmpb_eq_RI __builtin_HEXAGON_A4_cmpbeqi |
1482 | |
1483 | /* ========================================================================== |
1484 | Assembly Syntax: Pd4=cmpb.gt(Rs32,Rt32) |
1485 | C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RR(Word32 Rs, Word32 Rt) |
1486 | Instruction Type: S_3op |
1487 | Execution Slots: SLOT23 |
1488 | ========================================================================== */ |
1489 | |
1490 | #define Q6_p_cmpb_gt_RR __builtin_HEXAGON_A4_cmpbgt |
1491 | |
1492 | /* ========================================================================== |
1493 | Assembly Syntax: Pd4=cmpb.gt(Rs32,#s8) |
1494 | C Intrinsic Prototype: Byte Q6_p_cmpb_gt_RI(Word32 Rs, Word32 Is8) |
1495 | Instruction Type: ALU64 |
1496 | Execution Slots: SLOT23 |
1497 | ========================================================================== */ |
1498 | |
1499 | #define Q6_p_cmpb_gt_RI __builtin_HEXAGON_A4_cmpbgti |
1500 | |
1501 | /* ========================================================================== |
1502 | Assembly Syntax: Pd4=cmpb.gtu(Rs32,Rt32) |
1503 | C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RR(Word32 Rs, Word32 Rt) |
1504 | Instruction Type: S_3op |
1505 | Execution Slots: SLOT23 |
1506 | ========================================================================== */ |
1507 | |
1508 | #define Q6_p_cmpb_gtu_RR __builtin_HEXAGON_A4_cmpbgtu |
1509 | |
1510 | /* ========================================================================== |
1511 | Assembly Syntax: Pd4=cmpb.gtu(Rs32,#u7) |
1512 | C Intrinsic Prototype: Byte Q6_p_cmpb_gtu_RI(Word32 Rs, Word32 Iu7) |
1513 | Instruction Type: ALU64 |
1514 | Execution Slots: SLOT23 |
1515 | ========================================================================== */ |
1516 | |
1517 | #define Q6_p_cmpb_gtu_RI __builtin_HEXAGON_A4_cmpbgtui |
1518 | |
1519 | /* ========================================================================== |
1520 | Assembly Syntax: Pd4=cmph.eq(Rs32,Rt32) |
1521 | C Intrinsic Prototype: Byte Q6_p_cmph_eq_RR(Word32 Rs, Word32 Rt) |
1522 | Instruction Type: S_3op |
1523 | Execution Slots: SLOT23 |
1524 | ========================================================================== */ |
1525 | |
1526 | #define Q6_p_cmph_eq_RR __builtin_HEXAGON_A4_cmpheq |
1527 | |
1528 | /* ========================================================================== |
1529 | Assembly Syntax: Pd4=cmph.eq(Rs32,#s8) |
1530 | C Intrinsic Prototype: Byte Q6_p_cmph_eq_RI(Word32 Rs, Word32 Is8) |
1531 | Instruction Type: ALU64 |
1532 | Execution Slots: SLOT23 |
1533 | ========================================================================== */ |
1534 | |
1535 | #define Q6_p_cmph_eq_RI __builtin_HEXAGON_A4_cmpheqi |
1536 | |
1537 | /* ========================================================================== |
1538 | Assembly Syntax: Pd4=cmph.gt(Rs32,Rt32) |
1539 | C Intrinsic Prototype: Byte Q6_p_cmph_gt_RR(Word32 Rs, Word32 Rt) |
1540 | Instruction Type: S_3op |
1541 | Execution Slots: SLOT23 |
1542 | ========================================================================== */ |
1543 | |
1544 | #define Q6_p_cmph_gt_RR __builtin_HEXAGON_A4_cmphgt |
1545 | |
1546 | /* ========================================================================== |
1547 | Assembly Syntax: Pd4=cmph.gt(Rs32,#s8) |
1548 | C Intrinsic Prototype: Byte Q6_p_cmph_gt_RI(Word32 Rs, Word32 Is8) |
1549 | Instruction Type: ALU64 |
1550 | Execution Slots: SLOT23 |
1551 | ========================================================================== */ |
1552 | |
1553 | #define Q6_p_cmph_gt_RI __builtin_HEXAGON_A4_cmphgti |
1554 | |
1555 | /* ========================================================================== |
1556 | Assembly Syntax: Pd4=cmph.gtu(Rs32,Rt32) |
1557 | C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RR(Word32 Rs, Word32 Rt) |
1558 | Instruction Type: S_3op |
1559 | Execution Slots: SLOT23 |
1560 | ========================================================================== */ |
1561 | |
1562 | #define Q6_p_cmph_gtu_RR __builtin_HEXAGON_A4_cmphgtu |
1563 | |
1564 | /* ========================================================================== |
1565 | Assembly Syntax: Pd4=cmph.gtu(Rs32,#u7) |
1566 | C Intrinsic Prototype: Byte Q6_p_cmph_gtu_RI(Word32 Rs, Word32 Iu7) |
1567 | Instruction Type: ALU64 |
1568 | Execution Slots: SLOT23 |
1569 | ========================================================================== */ |
1570 | |
1571 | #define Q6_p_cmph_gtu_RI __builtin_HEXAGON_A4_cmphgtui |
1572 | |
1573 | /* ========================================================================== |
1574 | Assembly Syntax: Rdd32=combine(#s8,Rs32) |
1575 | C Intrinsic Prototype: Word64 Q6_P_combine_IR(Word32 Is8, Word32 Rs) |
1576 | Instruction Type: ALU32_2op |
1577 | Execution Slots: SLOT0123 |
1578 | ========================================================================== */ |
1579 | |
1580 | #define Q6_P_combine_IR __builtin_HEXAGON_A4_combineir |
1581 | |
1582 | /* ========================================================================== |
1583 | Assembly Syntax: Rdd32=combine(Rs32,#s8) |
1584 | C Intrinsic Prototype: Word64 Q6_P_combine_RI(Word32 Rs, Word32 Is8) |
1585 | Instruction Type: ALU32_2op |
1586 | Execution Slots: SLOT0123 |
1587 | ========================================================================== */ |
1588 | |
1589 | #define Q6_P_combine_RI __builtin_HEXAGON_A4_combineri |
1590 | |
1591 | /* ========================================================================== |
1592 | Assembly Syntax: Rd32=cround(Rs32,#u5) |
1593 | C Intrinsic Prototype: Word32 Q6_R_cround_RI(Word32 Rs, Word32 Iu5) |
1594 | Instruction Type: S_2op |
1595 | Execution Slots: SLOT23 |
1596 | ========================================================================== */ |
1597 | |
1598 | #define Q6_R_cround_RI __builtin_HEXAGON_A4_cround_ri |
1599 | |
1600 | /* ========================================================================== |
1601 | Assembly Syntax: Rd32=cround(Rs32,Rt32) |
1602 | C Intrinsic Prototype: Word32 Q6_R_cround_RR(Word32 Rs, Word32 Rt) |
1603 | Instruction Type: S_3op |
1604 | Execution Slots: SLOT23 |
1605 | ========================================================================== */ |
1606 | |
1607 | #define Q6_R_cround_RR __builtin_HEXAGON_A4_cround_rr |
1608 | |
1609 | /* ========================================================================== |
1610 | Assembly Syntax: Rd32=modwrap(Rs32,Rt32) |
1611 | C Intrinsic Prototype: Word32 Q6_R_modwrap_RR(Word32 Rs, Word32 Rt) |
1612 | Instruction Type: ALU64 |
1613 | Execution Slots: SLOT23 |
1614 | ========================================================================== */ |
1615 | |
1616 | #define Q6_R_modwrap_RR __builtin_HEXAGON_A4_modwrapu |
1617 | |
1618 | /* ========================================================================== |
1619 | Assembly Syntax: Rd32=or(Rt32,~Rs32) |
1620 | C Intrinsic Prototype: Word32 Q6_R_or_RnR(Word32 Rt, Word32 Rs) |
1621 | Instruction Type: ALU32_3op |
1622 | Execution Slots: SLOT0123 |
1623 | ========================================================================== */ |
1624 | |
1625 | #define Q6_R_or_RnR __builtin_HEXAGON_A4_orn |
1626 | |
1627 | /* ========================================================================== |
1628 | Assembly Syntax: Rdd32=or(Rtt32,~Rss32) |
1629 | C Intrinsic Prototype: Word64 Q6_P_or_PnP(Word64 Rtt, Word64 Rss) |
1630 | Instruction Type: ALU64 |
1631 | Execution Slots: SLOT23 |
1632 | ========================================================================== */ |
1633 | |
1634 | #define Q6_P_or_PnP __builtin_HEXAGON_A4_ornp |
1635 | |
1636 | /* ========================================================================== |
1637 | Assembly Syntax: Rd32=cmp.eq(Rs32,Rt32) |
1638 | C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RR(Word32 Rs, Word32 Rt) |
1639 | Instruction Type: ALU32_3op |
1640 | Execution Slots: SLOT0123 |
1641 | ========================================================================== */ |
1642 | |
1643 | #define Q6_R_cmp_eq_RR __builtin_HEXAGON_A4_rcmpeq |
1644 | |
1645 | /* ========================================================================== |
1646 | Assembly Syntax: Rd32=cmp.eq(Rs32,#s8) |
1647 | C Intrinsic Prototype: Word32 Q6_R_cmp_eq_RI(Word32 Rs, Word32 Is8) |
1648 | Instruction Type: ALU32_2op |
1649 | Execution Slots: SLOT0123 |
1650 | ========================================================================== */ |
1651 | |
1652 | #define Q6_R_cmp_eq_RI __builtin_HEXAGON_A4_rcmpeqi |
1653 | |
1654 | /* ========================================================================== |
1655 | Assembly Syntax: Rd32=!cmp.eq(Rs32,Rt32) |
1656 | C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RR(Word32 Rs, Word32 Rt) |
1657 | Instruction Type: ALU32_3op |
1658 | Execution Slots: SLOT0123 |
1659 | ========================================================================== */ |
1660 | |
1661 | #define Q6_R_not_cmp_eq_RR __builtin_HEXAGON_A4_rcmpneq |
1662 | |
1663 | /* ========================================================================== |
1664 | Assembly Syntax: Rd32=!cmp.eq(Rs32,#s8) |
1665 | C Intrinsic Prototype: Word32 Q6_R_not_cmp_eq_RI(Word32 Rs, Word32 Is8) |
1666 | Instruction Type: ALU32_2op |
1667 | Execution Slots: SLOT0123 |
1668 | ========================================================================== */ |
1669 | |
1670 | #define Q6_R_not_cmp_eq_RI __builtin_HEXAGON_A4_rcmpneqi |
1671 | |
1672 | /* ========================================================================== |
1673 | Assembly Syntax: Rd32=round(Rs32,#u5) |
1674 | C Intrinsic Prototype: Word32 Q6_R_round_RI(Word32 Rs, Word32 Iu5) |
1675 | Instruction Type: S_2op |
1676 | Execution Slots: SLOT23 |
1677 | ========================================================================== */ |
1678 | |
1679 | #define Q6_R_round_RI __builtin_HEXAGON_A4_round_ri |
1680 | |
1681 | /* ========================================================================== |
1682 | Assembly Syntax: Rd32=round(Rs32,#u5):sat |
1683 | C Intrinsic Prototype: Word32 Q6_R_round_RI_sat(Word32 Rs, Word32 Iu5) |
1684 | Instruction Type: S_2op |
1685 | Execution Slots: SLOT23 |
1686 | ========================================================================== */ |
1687 | |
1688 | #define Q6_R_round_RI_sat __builtin_HEXAGON_A4_round_ri_sat |
1689 | |
1690 | /* ========================================================================== |
1691 | Assembly Syntax: Rd32=round(Rs32,Rt32) |
1692 | C Intrinsic Prototype: Word32 Q6_R_round_RR(Word32 Rs, Word32 Rt) |
1693 | Instruction Type: S_3op |
1694 | Execution Slots: SLOT23 |
1695 | ========================================================================== */ |
1696 | |
1697 | #define Q6_R_round_RR __builtin_HEXAGON_A4_round_rr |
1698 | |
1699 | /* ========================================================================== |
1700 | Assembly Syntax: Rd32=round(Rs32,Rt32):sat |
1701 | C Intrinsic Prototype: Word32 Q6_R_round_RR_sat(Word32 Rs, Word32 Rt) |
1702 | Instruction Type: S_3op |
1703 | Execution Slots: SLOT23 |
1704 | ========================================================================== */ |
1705 | |
1706 | #define Q6_R_round_RR_sat __builtin_HEXAGON_A4_round_rr_sat |
1707 | |
1708 | /* ========================================================================== |
1709 | Assembly Syntax: Pd4=tlbmatch(Rss32,Rt32) |
1710 | C Intrinsic Prototype: Byte Q6_p_tlbmatch_PR(Word64 Rss, Word32 Rt) |
1711 | Instruction Type: ALU64 |
1712 | Execution Slots: SLOT23 |
1713 | ========================================================================== */ |
1714 | |
1715 | #define Q6_p_tlbmatch_PR __builtin_HEXAGON_A4_tlbmatch |
1716 | |
1717 | /* ========================================================================== |
1718 | Assembly Syntax: Pd4=any8(vcmpb.eq(Rss32,Rtt32)) |
1719 | C Intrinsic Prototype: Byte Q6_p_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) |
1720 | Instruction Type: ALU64 |
1721 | Execution Slots: SLOT23 |
1722 | ========================================================================== */ |
1723 | |
1724 | #define Q6_p_any8_vcmpb_eq_PP __builtin_HEXAGON_A4_vcmpbeq_any |
1725 | |
1726 | /* ========================================================================== |
1727 | Assembly Syntax: Pd4=vcmpb.eq(Rss32,#u8) |
1728 | C Intrinsic Prototype: Byte Q6_p_vcmpb_eq_PI(Word64 Rss, Word32 Iu8) |
1729 | Instruction Type: ALU64 |
1730 | Execution Slots: SLOT23 |
1731 | ========================================================================== */ |
1732 | |
1733 | #define Q6_p_vcmpb_eq_PI __builtin_HEXAGON_A4_vcmpbeqi |
1734 | |
1735 | /* ========================================================================== |
1736 | Assembly Syntax: Pd4=vcmpb.gt(Rss32,Rtt32) |
1737 | C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PP(Word64 Rss, Word64 Rtt) |
1738 | Instruction Type: ALU64 |
1739 | Execution Slots: SLOT23 |
1740 | ========================================================================== */ |
1741 | |
1742 | #define Q6_p_vcmpb_gt_PP __builtin_HEXAGON_A4_vcmpbgt |
1743 | |
1744 | /* ========================================================================== |
1745 | Assembly Syntax: Pd4=vcmpb.gt(Rss32,#s8) |
1746 | C Intrinsic Prototype: Byte Q6_p_vcmpb_gt_PI(Word64 Rss, Word32 Is8) |
1747 | Instruction Type: ALU64 |
1748 | Execution Slots: SLOT23 |
1749 | ========================================================================== */ |
1750 | |
1751 | #define Q6_p_vcmpb_gt_PI __builtin_HEXAGON_A4_vcmpbgti |
1752 | |
1753 | /* ========================================================================== |
1754 | Assembly Syntax: Pd4=vcmpb.gtu(Rss32,#u7) |
1755 | C Intrinsic Prototype: Byte Q6_p_vcmpb_gtu_PI(Word64 Rss, Word32 Iu7) |
1756 | Instruction Type: ALU64 |
1757 | Execution Slots: SLOT23 |
1758 | ========================================================================== */ |
1759 | |
1760 | #define Q6_p_vcmpb_gtu_PI __builtin_HEXAGON_A4_vcmpbgtui |
1761 | |
1762 | /* ========================================================================== |
1763 | Assembly Syntax: Pd4=vcmph.eq(Rss32,#s8) |
1764 | C Intrinsic Prototype: Byte Q6_p_vcmph_eq_PI(Word64 Rss, Word32 Is8) |
1765 | Instruction Type: ALU64 |
1766 | Execution Slots: SLOT23 |
1767 | ========================================================================== */ |
1768 | |
1769 | #define Q6_p_vcmph_eq_PI __builtin_HEXAGON_A4_vcmpheqi |
1770 | |
1771 | /* ========================================================================== |
1772 | Assembly Syntax: Pd4=vcmph.gt(Rss32,#s8) |
1773 | C Intrinsic Prototype: Byte Q6_p_vcmph_gt_PI(Word64 Rss, Word32 Is8) |
1774 | Instruction Type: ALU64 |
1775 | Execution Slots: SLOT23 |
1776 | ========================================================================== */ |
1777 | |
1778 | #define Q6_p_vcmph_gt_PI __builtin_HEXAGON_A4_vcmphgti |
1779 | |
1780 | /* ========================================================================== |
1781 | Assembly Syntax: Pd4=vcmph.gtu(Rss32,#u7) |
1782 | C Intrinsic Prototype: Byte Q6_p_vcmph_gtu_PI(Word64 Rss, Word32 Iu7) |
1783 | Instruction Type: ALU64 |
1784 | Execution Slots: SLOT23 |
1785 | ========================================================================== */ |
1786 | |
1787 | #define Q6_p_vcmph_gtu_PI __builtin_HEXAGON_A4_vcmphgtui |
1788 | |
1789 | /* ========================================================================== |
1790 | Assembly Syntax: Pd4=vcmpw.eq(Rss32,#s8) |
1791 | C Intrinsic Prototype: Byte Q6_p_vcmpw_eq_PI(Word64 Rss, Word32 Is8) |
1792 | Instruction Type: ALU64 |
1793 | Execution Slots: SLOT23 |
1794 | ========================================================================== */ |
1795 | |
1796 | #define Q6_p_vcmpw_eq_PI __builtin_HEXAGON_A4_vcmpweqi |
1797 | |
1798 | /* ========================================================================== |
1799 | Assembly Syntax: Pd4=vcmpw.gt(Rss32,#s8) |
1800 | C Intrinsic Prototype: Byte Q6_p_vcmpw_gt_PI(Word64 Rss, Word32 Is8) |
1801 | Instruction Type: ALU64 |
1802 | Execution Slots: SLOT23 |
1803 | ========================================================================== */ |
1804 | |
1805 | #define Q6_p_vcmpw_gt_PI __builtin_HEXAGON_A4_vcmpwgti |
1806 | |
1807 | /* ========================================================================== |
1808 | Assembly Syntax: Pd4=vcmpw.gtu(Rss32,#u7) |
1809 | C Intrinsic Prototype: Byte Q6_p_vcmpw_gtu_PI(Word64 Rss, Word32 Iu7) |
1810 | Instruction Type: ALU64 |
1811 | Execution Slots: SLOT23 |
1812 | ========================================================================== */ |
1813 | |
1814 | #define Q6_p_vcmpw_gtu_PI __builtin_HEXAGON_A4_vcmpwgtui |
1815 | |
1816 | /* ========================================================================== |
1817 | Assembly Syntax: Rxx32=vrmaxh(Rss32,Ru32) |
1818 | C Intrinsic Prototype: Word64 Q6_P_vrmaxh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1819 | Instruction Type: S_3op |
1820 | Execution Slots: SLOT23 |
1821 | ========================================================================== */ |
1822 | |
1823 | #define Q6_P_vrmaxh_PR __builtin_HEXAGON_A4_vrmaxh |
1824 | |
1825 | /* ========================================================================== |
1826 | Assembly Syntax: Rxx32=vrmaxuh(Rss32,Ru32) |
1827 | C Intrinsic Prototype: Word64 Q6_P_vrmaxuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1828 | Instruction Type: S_3op |
1829 | Execution Slots: SLOT23 |
1830 | ========================================================================== */ |
1831 | |
1832 | #define Q6_P_vrmaxuh_PR __builtin_HEXAGON_A4_vrmaxuh |
1833 | |
1834 | /* ========================================================================== |
1835 | Assembly Syntax: Rxx32=vrmaxuw(Rss32,Ru32) |
1836 | C Intrinsic Prototype: Word64 Q6_P_vrmaxuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1837 | Instruction Type: S_3op |
1838 | Execution Slots: SLOT23 |
1839 | ========================================================================== */ |
1840 | |
1841 | #define Q6_P_vrmaxuw_PR __builtin_HEXAGON_A4_vrmaxuw |
1842 | |
1843 | /* ========================================================================== |
1844 | Assembly Syntax: Rxx32=vrmaxw(Rss32,Ru32) |
1845 | C Intrinsic Prototype: Word64 Q6_P_vrmaxw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1846 | Instruction Type: S_3op |
1847 | Execution Slots: SLOT23 |
1848 | ========================================================================== */ |
1849 | |
1850 | #define Q6_P_vrmaxw_PR __builtin_HEXAGON_A4_vrmaxw |
1851 | |
1852 | /* ========================================================================== |
1853 | Assembly Syntax: Rxx32=vrminh(Rss32,Ru32) |
1854 | C Intrinsic Prototype: Word64 Q6_P_vrminh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1855 | Instruction Type: S_3op |
1856 | Execution Slots: SLOT23 |
1857 | ========================================================================== */ |
1858 | |
1859 | #define Q6_P_vrminh_PR __builtin_HEXAGON_A4_vrminh |
1860 | |
1861 | /* ========================================================================== |
1862 | Assembly Syntax: Rxx32=vrminuh(Rss32,Ru32) |
1863 | C Intrinsic Prototype: Word64 Q6_P_vrminuh_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1864 | Instruction Type: S_3op |
1865 | Execution Slots: SLOT23 |
1866 | ========================================================================== */ |
1867 | |
1868 | #define Q6_P_vrminuh_PR __builtin_HEXAGON_A4_vrminuh |
1869 | |
1870 | /* ========================================================================== |
1871 | Assembly Syntax: Rxx32=vrminuw(Rss32,Ru32) |
1872 | C Intrinsic Prototype: Word64 Q6_P_vrminuw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1873 | Instruction Type: S_3op |
1874 | Execution Slots: SLOT23 |
1875 | ========================================================================== */ |
1876 | |
1877 | #define Q6_P_vrminuw_PR __builtin_HEXAGON_A4_vrminuw |
1878 | |
1879 | /* ========================================================================== |
1880 | Assembly Syntax: Rxx32=vrminw(Rss32,Ru32) |
1881 | C Intrinsic Prototype: Word64 Q6_P_vrminw_PR(Word64 Rxx, Word64 Rss, Word32 Ru) |
1882 | Instruction Type: S_3op |
1883 | Execution Slots: SLOT23 |
1884 | ========================================================================== */ |
1885 | |
1886 | #define Q6_P_vrminw_PR __builtin_HEXAGON_A4_vrminw |
1887 | |
1888 | /* ========================================================================== |
1889 | Assembly Syntax: Rd32=vaddhub(Rss32,Rtt32):sat |
1890 | C Intrinsic Prototype: Word32 Q6_R_vaddhub_PP_sat(Word64 Rss, Word64 Rtt) |
1891 | Instruction Type: S_3op |
1892 | Execution Slots: SLOT23 |
1893 | ========================================================================== */ |
1894 | |
1895 | #define Q6_R_vaddhub_PP_sat __builtin_HEXAGON_A5_vaddhubs |
1896 | |
1897 | /* ========================================================================== |
1898 | Assembly Syntax: Pd4=all8(Ps4) |
1899 | C Intrinsic Prototype: Byte Q6_p_all8_p(Byte Ps) |
1900 | Instruction Type: CR |
1901 | Execution Slots: SLOT23 |
1902 | ========================================================================== */ |
1903 | |
1904 | #define Q6_p_all8_p __builtin_HEXAGON_C2_all8 |
1905 | |
1906 | /* ========================================================================== |
1907 | Assembly Syntax: Pd4=and(Pt4,Ps4) |
1908 | C Intrinsic Prototype: Byte Q6_p_and_pp(Byte Pt, Byte Ps) |
1909 | Instruction Type: CR |
1910 | Execution Slots: SLOT23 |
1911 | ========================================================================== */ |
1912 | |
1913 | #define Q6_p_and_pp __builtin_HEXAGON_C2_and |
1914 | |
1915 | /* ========================================================================== |
1916 | Assembly Syntax: Pd4=and(Pt4,!Ps4) |
1917 | C Intrinsic Prototype: Byte Q6_p_and_pnp(Byte Pt, Byte Ps) |
1918 | Instruction Type: CR |
1919 | Execution Slots: SLOT23 |
1920 | ========================================================================== */ |
1921 | |
1922 | #define Q6_p_and_pnp __builtin_HEXAGON_C2_andn |
1923 | |
1924 | /* ========================================================================== |
1925 | Assembly Syntax: Pd4=any8(Ps4) |
1926 | C Intrinsic Prototype: Byte Q6_p_any8_p(Byte Ps) |
1927 | Instruction Type: CR |
1928 | Execution Slots: SLOT23 |
1929 | ========================================================================== */ |
1930 | |
1931 | #define Q6_p_any8_p __builtin_HEXAGON_C2_any8 |
1932 | |
1933 | /* ========================================================================== |
1934 | Assembly Syntax: Pd4=bitsclr(Rs32,Rt32) |
1935 | C Intrinsic Prototype: Byte Q6_p_bitsclr_RR(Word32 Rs, Word32 Rt) |
1936 | Instruction Type: S_3op |
1937 | Execution Slots: SLOT23 |
1938 | ========================================================================== */ |
1939 | |
1940 | #define Q6_p_bitsclr_RR __builtin_HEXAGON_C2_bitsclr |
1941 | |
1942 | /* ========================================================================== |
1943 | Assembly Syntax: Pd4=bitsclr(Rs32,#u6) |
1944 | C Intrinsic Prototype: Byte Q6_p_bitsclr_RI(Word32 Rs, Word32 Iu6) |
1945 | Instruction Type: S_2op |
1946 | Execution Slots: SLOT23 |
1947 | ========================================================================== */ |
1948 | |
1949 | #define Q6_p_bitsclr_RI __builtin_HEXAGON_C2_bitsclri |
1950 | |
1951 | /* ========================================================================== |
1952 | Assembly Syntax: Pd4=bitsset(Rs32,Rt32) |
1953 | C Intrinsic Prototype: Byte Q6_p_bitsset_RR(Word32 Rs, Word32 Rt) |
1954 | Instruction Type: S_3op |
1955 | Execution Slots: SLOT23 |
1956 | ========================================================================== */ |
1957 | |
1958 | #define Q6_p_bitsset_RR __builtin_HEXAGON_C2_bitsset |
1959 | |
1960 | /* ========================================================================== |
1961 | Assembly Syntax: Pd4=cmp.eq(Rs32,Rt32) |
1962 | C Intrinsic Prototype: Byte Q6_p_cmp_eq_RR(Word32 Rs, Word32 Rt) |
1963 | Instruction Type: ALU32_3op |
1964 | Execution Slots: SLOT0123 |
1965 | ========================================================================== */ |
1966 | |
1967 | #define Q6_p_cmp_eq_RR __builtin_HEXAGON_C2_cmpeq |
1968 | |
1969 | /* ========================================================================== |
1970 | Assembly Syntax: Pd4=cmp.eq(Rs32,#s10) |
1971 | C Intrinsic Prototype: Byte Q6_p_cmp_eq_RI(Word32 Rs, Word32 Is10) |
1972 | Instruction Type: ALU32_2op |
1973 | Execution Slots: SLOT0123 |
1974 | ========================================================================== */ |
1975 | |
1976 | #define Q6_p_cmp_eq_RI __builtin_HEXAGON_C2_cmpeqi |
1977 | |
1978 | /* ========================================================================== |
1979 | Assembly Syntax: Pd4=cmp.eq(Rss32,Rtt32) |
1980 | C Intrinsic Prototype: Byte Q6_p_cmp_eq_PP(Word64 Rss, Word64 Rtt) |
1981 | Instruction Type: ALU64 |
1982 | Execution Slots: SLOT23 |
1983 | ========================================================================== */ |
1984 | |
1985 | #define Q6_p_cmp_eq_PP __builtin_HEXAGON_C2_cmpeqp |
1986 | |
1987 | /* ========================================================================== |
1988 | Assembly Syntax: Pd4=cmp.ge(Rs32,#s8) |
1989 | C Intrinsic Prototype: Byte Q6_p_cmp_ge_RI(Word32 Rs, Word32 Is8) |
1990 | Instruction Type: ALU32_2op |
1991 | Execution Slots: SLOT0123 |
1992 | ========================================================================== */ |
1993 | |
1994 | #define Q6_p_cmp_ge_RI __builtin_HEXAGON_C2_cmpgei |
1995 | |
1996 | /* ========================================================================== |
1997 | Assembly Syntax: Pd4=cmp.geu(Rs32,#u8) |
1998 | C Intrinsic Prototype: Byte Q6_p_cmp_geu_RI(Word32 Rs, Word32 Iu8) |
1999 | Instruction Type: ALU32_2op |
2000 | Execution Slots: SLOT0123 |
2001 | ========================================================================== */ |
2002 | |
2003 | #define Q6_p_cmp_geu_RI __builtin_HEXAGON_C2_cmpgeui |
2004 | |
2005 | /* ========================================================================== |
2006 | Assembly Syntax: Pd4=cmp.gt(Rs32,Rt32) |
2007 | C Intrinsic Prototype: Byte Q6_p_cmp_gt_RR(Word32 Rs, Word32 Rt) |
2008 | Instruction Type: ALU32_3op |
2009 | Execution Slots: SLOT0123 |
2010 | ========================================================================== */ |
2011 | |
2012 | #define Q6_p_cmp_gt_RR __builtin_HEXAGON_C2_cmpgt |
2013 | |
2014 | /* ========================================================================== |
2015 | Assembly Syntax: Pd4=cmp.gt(Rs32,#s10) |
2016 | C Intrinsic Prototype: Byte Q6_p_cmp_gt_RI(Word32 Rs, Word32 Is10) |
2017 | Instruction Type: ALU32_2op |
2018 | Execution Slots: SLOT0123 |
2019 | ========================================================================== */ |
2020 | |
2021 | #define Q6_p_cmp_gt_RI __builtin_HEXAGON_C2_cmpgti |
2022 | |
2023 | /* ========================================================================== |
2024 | Assembly Syntax: Pd4=cmp.gt(Rss32,Rtt32) |
2025 | C Intrinsic Prototype: Byte Q6_p_cmp_gt_PP(Word64 Rss, Word64 Rtt) |
2026 | Instruction Type: ALU64 |
2027 | Execution Slots: SLOT23 |
2028 | ========================================================================== */ |
2029 | |
2030 | #define Q6_p_cmp_gt_PP __builtin_HEXAGON_C2_cmpgtp |
2031 | |
2032 | /* ========================================================================== |
2033 | Assembly Syntax: Pd4=cmp.gtu(Rs32,Rt32) |
2034 | C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RR(Word32 Rs, Word32 Rt) |
2035 | Instruction Type: ALU32_3op |
2036 | Execution Slots: SLOT0123 |
2037 | ========================================================================== */ |
2038 | |
2039 | #define Q6_p_cmp_gtu_RR __builtin_HEXAGON_C2_cmpgtu |
2040 | |
2041 | /* ========================================================================== |
2042 | Assembly Syntax: Pd4=cmp.gtu(Rs32,#u9) |
2043 | C Intrinsic Prototype: Byte Q6_p_cmp_gtu_RI(Word32 Rs, Word32 Iu9) |
2044 | Instruction Type: ALU32_2op |
2045 | Execution Slots: SLOT0123 |
2046 | ========================================================================== */ |
2047 | |
2048 | #define Q6_p_cmp_gtu_RI __builtin_HEXAGON_C2_cmpgtui |
2049 | |
2050 | /* ========================================================================== |
2051 | Assembly Syntax: Pd4=cmp.gtu(Rss32,Rtt32) |
2052 | C Intrinsic Prototype: Byte Q6_p_cmp_gtu_PP(Word64 Rss, Word64 Rtt) |
2053 | Instruction Type: ALU64 |
2054 | Execution Slots: SLOT23 |
2055 | ========================================================================== */ |
2056 | |
2057 | #define Q6_p_cmp_gtu_PP __builtin_HEXAGON_C2_cmpgtup |
2058 | |
2059 | /* ========================================================================== |
2060 | Assembly Syntax: Pd4=cmp.lt(Rs32,Rt32) |
2061 | C Intrinsic Prototype: Byte Q6_p_cmp_lt_RR(Word32 Rs, Word32 Rt) |
2062 | Instruction Type: ALU32_3op |
2063 | Execution Slots: SLOT0123 |
2064 | ========================================================================== */ |
2065 | |
2066 | #define Q6_p_cmp_lt_RR __builtin_HEXAGON_C2_cmplt |
2067 | |
2068 | /* ========================================================================== |
2069 | Assembly Syntax: Pd4=cmp.ltu(Rs32,Rt32) |
2070 | C Intrinsic Prototype: Byte Q6_p_cmp_ltu_RR(Word32 Rs, Word32 Rt) |
2071 | Instruction Type: ALU32_3op |
2072 | Execution Slots: SLOT0123 |
2073 | ========================================================================== */ |
2074 | |
2075 | #define Q6_p_cmp_ltu_RR __builtin_HEXAGON_C2_cmpltu |
2076 | |
2077 | /* ========================================================================== |
2078 | Assembly Syntax: Rdd32=mask(Pt4) |
2079 | C Intrinsic Prototype: Word64 Q6_P_mask_p(Byte Pt) |
2080 | Instruction Type: S_2op |
2081 | Execution Slots: SLOT23 |
2082 | ========================================================================== */ |
2083 | |
2084 | #define Q6_P_mask_p __builtin_HEXAGON_C2_mask |
2085 | |
2086 | /* ========================================================================== |
2087 | Assembly Syntax: Rd32=mux(Pu4,Rs32,Rt32) |
2088 | C Intrinsic Prototype: Word32 Q6_R_mux_pRR(Byte Pu, Word32 Rs, Word32 Rt) |
2089 | Instruction Type: ALU32_3op |
2090 | Execution Slots: SLOT0123 |
2091 | ========================================================================== */ |
2092 | |
2093 | #define Q6_R_mux_pRR __builtin_HEXAGON_C2_mux |
2094 | |
2095 | /* ========================================================================== |
2096 | Assembly Syntax: Rd32=mux(Pu4,#s8,#S8) |
2097 | C Intrinsic Prototype: Word32 Q6_R_mux_pII(Byte Pu, Word32 Is8, Word32 IS8) |
2098 | Instruction Type: ALU32_2op |
2099 | Execution Slots: SLOT0123 |
2100 | ========================================================================== */ |
2101 | |
2102 | #define Q6_R_mux_pII __builtin_HEXAGON_C2_muxii |
2103 | |
2104 | /* ========================================================================== |
2105 | Assembly Syntax: Rd32=mux(Pu4,Rs32,#s8) |
2106 | C Intrinsic Prototype: Word32 Q6_R_mux_pRI(Byte Pu, Word32 Rs, Word32 Is8) |
2107 | Instruction Type: ALU32_2op |
2108 | Execution Slots: SLOT0123 |
2109 | ========================================================================== */ |
2110 | |
2111 | #define Q6_R_mux_pRI __builtin_HEXAGON_C2_muxir |
2112 | |
2113 | /* ========================================================================== |
2114 | Assembly Syntax: Rd32=mux(Pu4,#s8,Rs32) |
2115 | C Intrinsic Prototype: Word32 Q6_R_mux_pIR(Byte Pu, Word32 Is8, Word32 Rs) |
2116 | Instruction Type: ALU32_2op |
2117 | Execution Slots: SLOT0123 |
2118 | ========================================================================== */ |
2119 | |
2120 | #define Q6_R_mux_pIR __builtin_HEXAGON_C2_muxri |
2121 | |
2122 | /* ========================================================================== |
2123 | Assembly Syntax: Pd4=not(Ps4) |
2124 | C Intrinsic Prototype: Byte Q6_p_not_p(Byte Ps) |
2125 | Instruction Type: CR |
2126 | Execution Slots: SLOT23 |
2127 | ========================================================================== */ |
2128 | |
2129 | #define Q6_p_not_p __builtin_HEXAGON_C2_not |
2130 | |
2131 | /* ========================================================================== |
2132 | Assembly Syntax: Pd4=or(Pt4,Ps4) |
2133 | C Intrinsic Prototype: Byte Q6_p_or_pp(Byte Pt, Byte Ps) |
2134 | Instruction Type: CR |
2135 | Execution Slots: SLOT23 |
2136 | ========================================================================== */ |
2137 | |
2138 | #define Q6_p_or_pp __builtin_HEXAGON_C2_or |
2139 | |
2140 | /* ========================================================================== |
2141 | Assembly Syntax: Pd4=or(Pt4,!Ps4) |
2142 | C Intrinsic Prototype: Byte Q6_p_or_pnp(Byte Pt, Byte Ps) |
2143 | Instruction Type: CR |
2144 | Execution Slots: SLOT23 |
2145 | ========================================================================== */ |
2146 | |
2147 | #define Q6_p_or_pnp __builtin_HEXAGON_C2_orn |
2148 | |
2149 | /* ========================================================================== |
2150 | Assembly Syntax: Pd4=Ps4 |
2151 | C Intrinsic Prototype: Byte Q6_p_equals_p(Byte Ps) |
2152 | Instruction Type: MAPPING |
2153 | Execution Slots: SLOT0123 |
2154 | ========================================================================== */ |
2155 | |
2156 | #define Q6_p_equals_p __builtin_HEXAGON_C2_pxfer_map |
2157 | |
2158 | /* ========================================================================== |
2159 | Assembly Syntax: Rd32=Ps4 |
2160 | C Intrinsic Prototype: Word32 Q6_R_equals_p(Byte Ps) |
2161 | Instruction Type: S_2op |
2162 | Execution Slots: SLOT23 |
2163 | ========================================================================== */ |
2164 | |
2165 | #define Q6_R_equals_p __builtin_HEXAGON_C2_tfrpr |
2166 | |
2167 | /* ========================================================================== |
2168 | Assembly Syntax: Pd4=Rs32 |
2169 | C Intrinsic Prototype: Byte Q6_p_equals_R(Word32 Rs) |
2170 | Instruction Type: S_2op |
2171 | Execution Slots: SLOT23 |
2172 | ========================================================================== */ |
2173 | |
2174 | #define Q6_p_equals_R __builtin_HEXAGON_C2_tfrrp |
2175 | |
2176 | /* ========================================================================== |
2177 | Assembly Syntax: Rd32=vitpack(Ps4,Pt4) |
2178 | C Intrinsic Prototype: Word32 Q6_R_vitpack_pp(Byte Ps, Byte Pt) |
2179 | Instruction Type: S_2op |
2180 | Execution Slots: SLOT23 |
2181 | ========================================================================== */ |
2182 | |
2183 | #define Q6_R_vitpack_pp __builtin_HEXAGON_C2_vitpack |
2184 | |
2185 | /* ========================================================================== |
2186 | Assembly Syntax: Rdd32=vmux(Pu4,Rss32,Rtt32) |
2187 | C Intrinsic Prototype: Word64 Q6_P_vmux_pPP(Byte Pu, Word64 Rss, Word64 Rtt) |
2188 | Instruction Type: ALU64 |
2189 | Execution Slots: SLOT23 |
2190 | ========================================================================== */ |
2191 | |
2192 | #define Q6_P_vmux_pPP __builtin_HEXAGON_C2_vmux |
2193 | |
2194 | /* ========================================================================== |
2195 | Assembly Syntax: Pd4=xor(Ps4,Pt4) |
2196 | C Intrinsic Prototype: Byte Q6_p_xor_pp(Byte Ps, Byte Pt) |
2197 | Instruction Type: CR |
2198 | Execution Slots: SLOT23 |
2199 | ========================================================================== */ |
2200 | |
2201 | #define Q6_p_xor_pp __builtin_HEXAGON_C2_xor |
2202 | |
2203 | /* ========================================================================== |
2204 | Assembly Syntax: Pd4=and(Ps4,and(Pt4,Pu4)) |
2205 | C Intrinsic Prototype: Byte Q6_p_and_and_ppp(Byte Ps, Byte Pt, Byte Pu) |
2206 | Instruction Type: CR |
2207 | Execution Slots: SLOT23 |
2208 | ========================================================================== */ |
2209 | |
2210 | #define Q6_p_and_and_ppp __builtin_HEXAGON_C4_and_and |
2211 | |
2212 | /* ========================================================================== |
2213 | Assembly Syntax: Pd4=and(Ps4,and(Pt4,!Pu4)) |
2214 | C Intrinsic Prototype: Byte Q6_p_and_and_ppnp(Byte Ps, Byte Pt, Byte Pu) |
2215 | Instruction Type: CR |
2216 | Execution Slots: SLOT23 |
2217 | ========================================================================== */ |
2218 | |
2219 | #define Q6_p_and_and_ppnp __builtin_HEXAGON_C4_and_andn |
2220 | |
2221 | /* ========================================================================== |
2222 | Assembly Syntax: Pd4=and(Ps4,or(Pt4,Pu4)) |
2223 | C Intrinsic Prototype: Byte Q6_p_and_or_ppp(Byte Ps, Byte Pt, Byte Pu) |
2224 | Instruction Type: CR |
2225 | Execution Slots: SLOT23 |
2226 | ========================================================================== */ |
2227 | |
2228 | #define Q6_p_and_or_ppp __builtin_HEXAGON_C4_and_or |
2229 | |
2230 | /* ========================================================================== |
2231 | Assembly Syntax: Pd4=and(Ps4,or(Pt4,!Pu4)) |
2232 | C Intrinsic Prototype: Byte Q6_p_and_or_ppnp(Byte Ps, Byte Pt, Byte Pu) |
2233 | Instruction Type: CR |
2234 | Execution Slots: SLOT23 |
2235 | ========================================================================== */ |
2236 | |
2237 | #define Q6_p_and_or_ppnp __builtin_HEXAGON_C4_and_orn |
2238 | |
2239 | /* ========================================================================== |
2240 | Assembly Syntax: Pd4=!cmp.gt(Rs32,Rt32) |
2241 | C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RR(Word32 Rs, Word32 Rt) |
2242 | Instruction Type: ALU32_3op |
2243 | Execution Slots: SLOT0123 |
2244 | ========================================================================== */ |
2245 | |
2246 | #define Q6_p_not_cmp_gt_RR __builtin_HEXAGON_C4_cmplte |
2247 | |
2248 | /* ========================================================================== |
2249 | Assembly Syntax: Pd4=!cmp.gt(Rs32,#s10) |
2250 | C Intrinsic Prototype: Byte Q6_p_not_cmp_gt_RI(Word32 Rs, Word32 Is10) |
2251 | Instruction Type: ALU32_2op |
2252 | Execution Slots: SLOT0123 |
2253 | ========================================================================== */ |
2254 | |
2255 | #define Q6_p_not_cmp_gt_RI __builtin_HEXAGON_C4_cmpltei |
2256 | |
2257 | /* ========================================================================== |
2258 | Assembly Syntax: Pd4=!cmp.gtu(Rs32,Rt32) |
2259 | C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RR(Word32 Rs, Word32 Rt) |
2260 | Instruction Type: ALU32_3op |
2261 | Execution Slots: SLOT0123 |
2262 | ========================================================================== */ |
2263 | |
2264 | #define Q6_p_not_cmp_gtu_RR __builtin_HEXAGON_C4_cmplteu |
2265 | |
2266 | /* ========================================================================== |
2267 | Assembly Syntax: Pd4=!cmp.gtu(Rs32,#u9) |
2268 | C Intrinsic Prototype: Byte Q6_p_not_cmp_gtu_RI(Word32 Rs, Word32 Iu9) |
2269 | Instruction Type: ALU32_2op |
2270 | Execution Slots: SLOT0123 |
2271 | ========================================================================== */ |
2272 | |
2273 | #define Q6_p_not_cmp_gtu_RI __builtin_HEXAGON_C4_cmplteui |
2274 | |
2275 | /* ========================================================================== |
2276 | Assembly Syntax: Pd4=!cmp.eq(Rs32,Rt32) |
2277 | C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RR(Word32 Rs, Word32 Rt) |
2278 | Instruction Type: ALU32_3op |
2279 | Execution Slots: SLOT0123 |
2280 | ========================================================================== */ |
2281 | |
2282 | #define Q6_p_not_cmp_eq_RR __builtin_HEXAGON_C4_cmpneq |
2283 | |
2284 | /* ========================================================================== |
2285 | Assembly Syntax: Pd4=!cmp.eq(Rs32,#s10) |
2286 | C Intrinsic Prototype: Byte Q6_p_not_cmp_eq_RI(Word32 Rs, Word32 Is10) |
2287 | Instruction Type: ALU32_2op |
2288 | Execution Slots: SLOT0123 |
2289 | ========================================================================== */ |
2290 | |
2291 | #define Q6_p_not_cmp_eq_RI __builtin_HEXAGON_C4_cmpneqi |
2292 | |
2293 | /* ========================================================================== |
2294 | Assembly Syntax: Pd4=fastcorner9(Ps4,Pt4) |
2295 | C Intrinsic Prototype: Byte Q6_p_fastcorner9_pp(Byte Ps, Byte Pt) |
2296 | Instruction Type: CR |
2297 | Execution Slots: SLOT23 |
2298 | ========================================================================== */ |
2299 | |
2300 | #define Q6_p_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9 |
2301 | |
2302 | /* ========================================================================== |
2303 | Assembly Syntax: Pd4=!fastcorner9(Ps4,Pt4) |
2304 | C Intrinsic Prototype: Byte Q6_p_not_fastcorner9_pp(Byte Ps, Byte Pt) |
2305 | Instruction Type: CR |
2306 | Execution Slots: SLOT23 |
2307 | ========================================================================== */ |
2308 | |
2309 | #define Q6_p_not_fastcorner9_pp __builtin_HEXAGON_C4_fastcorner9_not |
2310 | |
2311 | /* ========================================================================== |
2312 | Assembly Syntax: Pd4=!bitsclr(Rs32,Rt32) |
2313 | C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RR(Word32 Rs, Word32 Rt) |
2314 | Instruction Type: S_3op |
2315 | Execution Slots: SLOT23 |
2316 | ========================================================================== */ |
2317 | |
2318 | #define Q6_p_not_bitsclr_RR __builtin_HEXAGON_C4_nbitsclr |
2319 | |
2320 | /* ========================================================================== |
2321 | Assembly Syntax: Pd4=!bitsclr(Rs32,#u6) |
2322 | C Intrinsic Prototype: Byte Q6_p_not_bitsclr_RI(Word32 Rs, Word32 Iu6) |
2323 | Instruction Type: S_2op |
2324 | Execution Slots: SLOT23 |
2325 | ========================================================================== */ |
2326 | |
2327 | #define Q6_p_not_bitsclr_RI __builtin_HEXAGON_C4_nbitsclri |
2328 | |
2329 | /* ========================================================================== |
2330 | Assembly Syntax: Pd4=!bitsset(Rs32,Rt32) |
2331 | C Intrinsic Prototype: Byte Q6_p_not_bitsset_RR(Word32 Rs, Word32 Rt) |
2332 | Instruction Type: S_3op |
2333 | Execution Slots: SLOT23 |
2334 | ========================================================================== */ |
2335 | |
2336 | #define Q6_p_not_bitsset_RR __builtin_HEXAGON_C4_nbitsset |
2337 | |
2338 | /* ========================================================================== |
2339 | Assembly Syntax: Pd4=or(Ps4,and(Pt4,Pu4)) |
2340 | C Intrinsic Prototype: Byte Q6_p_or_and_ppp(Byte Ps, Byte Pt, Byte Pu) |
2341 | Instruction Type: CR |
2342 | Execution Slots: SLOT23 |
2343 | ========================================================================== */ |
2344 | |
2345 | #define Q6_p_or_and_ppp __builtin_HEXAGON_C4_or_and |
2346 | |
2347 | /* ========================================================================== |
2348 | Assembly Syntax: Pd4=or(Ps4,and(Pt4,!Pu4)) |
2349 | C Intrinsic Prototype: Byte Q6_p_or_and_ppnp(Byte Ps, Byte Pt, Byte Pu) |
2350 | Instruction Type: CR |
2351 | Execution Slots: SLOT23 |
2352 | ========================================================================== */ |
2353 | |
2354 | #define Q6_p_or_and_ppnp __builtin_HEXAGON_C4_or_andn |
2355 | |
2356 | /* ========================================================================== |
2357 | Assembly Syntax: Pd4=or(Ps4,or(Pt4,Pu4)) |
2358 | C Intrinsic Prototype: Byte Q6_p_or_or_ppp(Byte Ps, Byte Pt, Byte Pu) |
2359 | Instruction Type: CR |
2360 | Execution Slots: SLOT23 |
2361 | ========================================================================== */ |
2362 | |
2363 | #define Q6_p_or_or_ppp __builtin_HEXAGON_C4_or_or |
2364 | |
2365 | /* ========================================================================== |
2366 | Assembly Syntax: Pd4=or(Ps4,or(Pt4,!Pu4)) |
2367 | C Intrinsic Prototype: Byte Q6_p_or_or_ppnp(Byte Ps, Byte Pt, Byte Pu) |
2368 | Instruction Type: CR |
2369 | Execution Slots: SLOT23 |
2370 | ========================================================================== */ |
2371 | |
2372 | #define Q6_p_or_or_ppnp __builtin_HEXAGON_C4_or_orn |
2373 | |
2374 | /* ========================================================================== |
2375 | Assembly Syntax: Rdd32=convert_d2df(Rss32) |
2376 | C Intrinsic Prototype: Float64 Q6_P_convert_d2df_P(Word64 Rss) |
2377 | Instruction Type: S_2op |
2378 | Execution Slots: SLOT23 |
2379 | ========================================================================== */ |
2380 | |
2381 | #define Q6_P_convert_d2df_P __builtin_HEXAGON_F2_conv_d2df |
2382 | |
2383 | /* ========================================================================== |
2384 | Assembly Syntax: Rd32=convert_d2sf(Rss32) |
2385 | C Intrinsic Prototype: Float32 Q6_R_convert_d2sf_P(Word64 Rss) |
2386 | Instruction Type: S_2op |
2387 | Execution Slots: SLOT23 |
2388 | ========================================================================== */ |
2389 | |
2390 | #define Q6_R_convert_d2sf_P __builtin_HEXAGON_F2_conv_d2sf |
2391 | |
2392 | /* ========================================================================== |
2393 | Assembly Syntax: Rdd32=convert_df2d(Rss32) |
2394 | C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P(Float64 Rss) |
2395 | Instruction Type: S_2op |
2396 | Execution Slots: SLOT23 |
2397 | ========================================================================== */ |
2398 | |
2399 | #define Q6_P_convert_df2d_P __builtin_HEXAGON_F2_conv_df2d |
2400 | |
2401 | /* ========================================================================== |
2402 | Assembly Syntax: Rdd32=convert_df2d(Rss32):chop |
2403 | C Intrinsic Prototype: Word64 Q6_P_convert_df2d_P_chop(Float64 Rss) |
2404 | Instruction Type: S_2op |
2405 | Execution Slots: SLOT23 |
2406 | ========================================================================== */ |
2407 | |
2408 | #define Q6_P_convert_df2d_P_chop __builtin_HEXAGON_F2_conv_df2d_chop |
2409 | |
2410 | /* ========================================================================== |
2411 | Assembly Syntax: Rd32=convert_df2sf(Rss32) |
2412 | C Intrinsic Prototype: Float32 Q6_R_convert_df2sf_P(Float64 Rss) |
2413 | Instruction Type: S_2op |
2414 | Execution Slots: SLOT23 |
2415 | ========================================================================== */ |
2416 | |
2417 | #define Q6_R_convert_df2sf_P __builtin_HEXAGON_F2_conv_df2sf |
2418 | |
2419 | /* ========================================================================== |
2420 | Assembly Syntax: Rdd32=convert_df2ud(Rss32) |
2421 | C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P(Float64 Rss) |
2422 | Instruction Type: S_2op |
2423 | Execution Slots: SLOT23 |
2424 | ========================================================================== */ |
2425 | |
2426 | #define Q6_P_convert_df2ud_P __builtin_HEXAGON_F2_conv_df2ud |
2427 | |
2428 | /* ========================================================================== |
2429 | Assembly Syntax: Rdd32=convert_df2ud(Rss32):chop |
2430 | C Intrinsic Prototype: Word64 Q6_P_convert_df2ud_P_chop(Float64 Rss) |
2431 | Instruction Type: S_2op |
2432 | Execution Slots: SLOT23 |
2433 | ========================================================================== */ |
2434 | |
2435 | #define Q6_P_convert_df2ud_P_chop __builtin_HEXAGON_F2_conv_df2ud_chop |
2436 | |
2437 | /* ========================================================================== |
2438 | Assembly Syntax: Rd32=convert_df2uw(Rss32) |
2439 | C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P(Float64 Rss) |
2440 | Instruction Type: S_2op |
2441 | Execution Slots: SLOT23 |
2442 | ========================================================================== */ |
2443 | |
2444 | #define Q6_R_convert_df2uw_P __builtin_HEXAGON_F2_conv_df2uw |
2445 | |
2446 | /* ========================================================================== |
2447 | Assembly Syntax: Rd32=convert_df2uw(Rss32):chop |
2448 | C Intrinsic Prototype: Word32 Q6_R_convert_df2uw_P_chop(Float64 Rss) |
2449 | Instruction Type: S_2op |
2450 | Execution Slots: SLOT23 |
2451 | ========================================================================== */ |
2452 | |
2453 | #define Q6_R_convert_df2uw_P_chop __builtin_HEXAGON_F2_conv_df2uw_chop |
2454 | |
2455 | /* ========================================================================== |
2456 | Assembly Syntax: Rd32=convert_df2w(Rss32) |
2457 | C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P(Float64 Rss) |
2458 | Instruction Type: S_2op |
2459 | Execution Slots: SLOT23 |
2460 | ========================================================================== */ |
2461 | |
2462 | #define Q6_R_convert_df2w_P __builtin_HEXAGON_F2_conv_df2w |
2463 | |
2464 | /* ========================================================================== |
2465 | Assembly Syntax: Rd32=convert_df2w(Rss32):chop |
2466 | C Intrinsic Prototype: Word32 Q6_R_convert_df2w_P_chop(Float64 Rss) |
2467 | Instruction Type: S_2op |
2468 | Execution Slots: SLOT23 |
2469 | ========================================================================== */ |
2470 | |
2471 | #define Q6_R_convert_df2w_P_chop __builtin_HEXAGON_F2_conv_df2w_chop |
2472 | |
2473 | /* ========================================================================== |
2474 | Assembly Syntax: Rdd32=convert_sf2d(Rs32) |
2475 | C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R(Float32 Rs) |
2476 | Instruction Type: S_2op |
2477 | Execution Slots: SLOT23 |
2478 | ========================================================================== */ |
2479 | |
2480 | #define Q6_P_convert_sf2d_R __builtin_HEXAGON_F2_conv_sf2d |
2481 | |
2482 | /* ========================================================================== |
2483 | Assembly Syntax: Rdd32=convert_sf2d(Rs32):chop |
2484 | C Intrinsic Prototype: Word64 Q6_P_convert_sf2d_R_chop(Float32 Rs) |
2485 | Instruction Type: S_2op |
2486 | Execution Slots: SLOT23 |
2487 | ========================================================================== */ |
2488 | |
2489 | #define Q6_P_convert_sf2d_R_chop __builtin_HEXAGON_F2_conv_sf2d_chop |
2490 | |
2491 | /* ========================================================================== |
2492 | Assembly Syntax: Rdd32=convert_sf2df(Rs32) |
2493 | C Intrinsic Prototype: Float64 Q6_P_convert_sf2df_R(Float32 Rs) |
2494 | Instruction Type: S_2op |
2495 | Execution Slots: SLOT23 |
2496 | ========================================================================== */ |
2497 | |
2498 | #define Q6_P_convert_sf2df_R __builtin_HEXAGON_F2_conv_sf2df |
2499 | |
2500 | /* ========================================================================== |
2501 | Assembly Syntax: Rdd32=convert_sf2ud(Rs32) |
2502 | C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R(Float32 Rs) |
2503 | Instruction Type: S_2op |
2504 | Execution Slots: SLOT23 |
2505 | ========================================================================== */ |
2506 | |
2507 | #define Q6_P_convert_sf2ud_R __builtin_HEXAGON_F2_conv_sf2ud |
2508 | |
2509 | /* ========================================================================== |
2510 | Assembly Syntax: Rdd32=convert_sf2ud(Rs32):chop |
2511 | C Intrinsic Prototype: Word64 Q6_P_convert_sf2ud_R_chop(Float32 Rs) |
2512 | Instruction Type: S_2op |
2513 | Execution Slots: SLOT23 |
2514 | ========================================================================== */ |
2515 | |
2516 | #define Q6_P_convert_sf2ud_R_chop __builtin_HEXAGON_F2_conv_sf2ud_chop |
2517 | |
2518 | /* ========================================================================== |
2519 | Assembly Syntax: Rd32=convert_sf2uw(Rs32) |
2520 | C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R(Float32 Rs) |
2521 | Instruction Type: S_2op |
2522 | Execution Slots: SLOT23 |
2523 | ========================================================================== */ |
2524 | |
2525 | #define Q6_R_convert_sf2uw_R __builtin_HEXAGON_F2_conv_sf2uw |
2526 | |
2527 | /* ========================================================================== |
2528 | Assembly Syntax: Rd32=convert_sf2uw(Rs32):chop |
2529 | C Intrinsic Prototype: Word32 Q6_R_convert_sf2uw_R_chop(Float32 Rs) |
2530 | Instruction Type: S_2op |
2531 | Execution Slots: SLOT23 |
2532 | ========================================================================== */ |
2533 | |
2534 | #define Q6_R_convert_sf2uw_R_chop __builtin_HEXAGON_F2_conv_sf2uw_chop |
2535 | |
2536 | /* ========================================================================== |
2537 | Assembly Syntax: Rd32=convert_sf2w(Rs32) |
2538 | C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R(Float32 Rs) |
2539 | Instruction Type: S_2op |
2540 | Execution Slots: SLOT23 |
2541 | ========================================================================== */ |
2542 | |
2543 | #define Q6_R_convert_sf2w_R __builtin_HEXAGON_F2_conv_sf2w |
2544 | |
2545 | /* ========================================================================== |
2546 | Assembly Syntax: Rd32=convert_sf2w(Rs32):chop |
2547 | C Intrinsic Prototype: Word32 Q6_R_convert_sf2w_R_chop(Float32 Rs) |
2548 | Instruction Type: S_2op |
2549 | Execution Slots: SLOT23 |
2550 | ========================================================================== */ |
2551 | |
2552 | #define Q6_R_convert_sf2w_R_chop __builtin_HEXAGON_F2_conv_sf2w_chop |
2553 | |
2554 | /* ========================================================================== |
2555 | Assembly Syntax: Rdd32=convert_ud2df(Rss32) |
2556 | C Intrinsic Prototype: Float64 Q6_P_convert_ud2df_P(Word64 Rss) |
2557 | Instruction Type: S_2op |
2558 | Execution Slots: SLOT23 |
2559 | ========================================================================== */ |
2560 | |
2561 | #define Q6_P_convert_ud2df_P __builtin_HEXAGON_F2_conv_ud2df |
2562 | |
2563 | /* ========================================================================== |
2564 | Assembly Syntax: Rd32=convert_ud2sf(Rss32) |
2565 | C Intrinsic Prototype: Float32 Q6_R_convert_ud2sf_P(Word64 Rss) |
2566 | Instruction Type: S_2op |
2567 | Execution Slots: SLOT23 |
2568 | ========================================================================== */ |
2569 | |
2570 | #define Q6_R_convert_ud2sf_P __builtin_HEXAGON_F2_conv_ud2sf |
2571 | |
2572 | /* ========================================================================== |
2573 | Assembly Syntax: Rdd32=convert_uw2df(Rs32) |
2574 | C Intrinsic Prototype: Float64 Q6_P_convert_uw2df_R(Word32 Rs) |
2575 | Instruction Type: S_2op |
2576 | Execution Slots: SLOT23 |
2577 | ========================================================================== */ |
2578 | |
2579 | #define Q6_P_convert_uw2df_R __builtin_HEXAGON_F2_conv_uw2df |
2580 | |
2581 | /* ========================================================================== |
2582 | Assembly Syntax: Rd32=convert_uw2sf(Rs32) |
2583 | C Intrinsic Prototype: Float32 Q6_R_convert_uw2sf_R(Word32 Rs) |
2584 | Instruction Type: S_2op |
2585 | Execution Slots: SLOT23 |
2586 | ========================================================================== */ |
2587 | |
2588 | #define Q6_R_convert_uw2sf_R __builtin_HEXAGON_F2_conv_uw2sf |
2589 | |
2590 | /* ========================================================================== |
2591 | Assembly Syntax: Rdd32=convert_w2df(Rs32) |
2592 | C Intrinsic Prototype: Float64 Q6_P_convert_w2df_R(Word32 Rs) |
2593 | Instruction Type: S_2op |
2594 | Execution Slots: SLOT23 |
2595 | ========================================================================== */ |
2596 | |
2597 | #define Q6_P_convert_w2df_R __builtin_HEXAGON_F2_conv_w2df |
2598 | |
2599 | /* ========================================================================== |
2600 | Assembly Syntax: Rd32=convert_w2sf(Rs32) |
2601 | C Intrinsic Prototype: Float32 Q6_R_convert_w2sf_R(Word32 Rs) |
2602 | Instruction Type: S_2op |
2603 | Execution Slots: SLOT23 |
2604 | ========================================================================== */ |
2605 | |
2606 | #define Q6_R_convert_w2sf_R __builtin_HEXAGON_F2_conv_w2sf |
2607 | |
2608 | /* ========================================================================== |
2609 | Assembly Syntax: Pd4=dfclass(Rss32,#u5) |
2610 | C Intrinsic Prototype: Byte Q6_p_dfclass_PI(Float64 Rss, Word32 Iu5) |
2611 | Instruction Type: ALU64 |
2612 | Execution Slots: SLOT23 |
2613 | ========================================================================== */ |
2614 | |
2615 | #define Q6_p_dfclass_PI __builtin_HEXAGON_F2_dfclass |
2616 | |
2617 | /* ========================================================================== |
2618 | Assembly Syntax: Pd4=dfcmp.eq(Rss32,Rtt32) |
2619 | C Intrinsic Prototype: Byte Q6_p_dfcmp_eq_PP(Float64 Rss, Float64 Rtt) |
2620 | Instruction Type: ALU64 |
2621 | Execution Slots: SLOT23 |
2622 | ========================================================================== */ |
2623 | |
2624 | #define Q6_p_dfcmp_eq_PP __builtin_HEXAGON_F2_dfcmpeq |
2625 | |
2626 | /* ========================================================================== |
2627 | Assembly Syntax: Pd4=dfcmp.ge(Rss32,Rtt32) |
2628 | C Intrinsic Prototype: Byte Q6_p_dfcmp_ge_PP(Float64 Rss, Float64 Rtt) |
2629 | Instruction Type: ALU64 |
2630 | Execution Slots: SLOT23 |
2631 | ========================================================================== */ |
2632 | |
2633 | #define Q6_p_dfcmp_ge_PP __builtin_HEXAGON_F2_dfcmpge |
2634 | |
2635 | /* ========================================================================== |
2636 | Assembly Syntax: Pd4=dfcmp.gt(Rss32,Rtt32) |
2637 | C Intrinsic Prototype: Byte Q6_p_dfcmp_gt_PP(Float64 Rss, Float64 Rtt) |
2638 | Instruction Type: ALU64 |
2639 | Execution Slots: SLOT23 |
2640 | ========================================================================== */ |
2641 | |
2642 | #define Q6_p_dfcmp_gt_PP __builtin_HEXAGON_F2_dfcmpgt |
2643 | |
2644 | /* ========================================================================== |
2645 | Assembly Syntax: Pd4=dfcmp.uo(Rss32,Rtt32) |
2646 | C Intrinsic Prototype: Byte Q6_p_dfcmp_uo_PP(Float64 Rss, Float64 Rtt) |
2647 | Instruction Type: ALU64 |
2648 | Execution Slots: SLOT23 |
2649 | ========================================================================== */ |
2650 | |
2651 | #define Q6_p_dfcmp_uo_PP __builtin_HEXAGON_F2_dfcmpuo |
2652 | |
2653 | /* ========================================================================== |
2654 | Assembly Syntax: Rdd32=dfmake(#u10):neg |
2655 | C Intrinsic Prototype: Float64 Q6_P_dfmake_I_neg(Word32 Iu10) |
2656 | Instruction Type: ALU64 |
2657 | Execution Slots: SLOT23 |
2658 | ========================================================================== */ |
2659 | |
2660 | #define Q6_P_dfmake_I_neg __builtin_HEXAGON_F2_dfimm_n |
2661 | |
2662 | /* ========================================================================== |
2663 | Assembly Syntax: Rdd32=dfmake(#u10):pos |
2664 | C Intrinsic Prototype: Float64 Q6_P_dfmake_I_pos(Word32 Iu10) |
2665 | Instruction Type: ALU64 |
2666 | Execution Slots: SLOT23 |
2667 | ========================================================================== */ |
2668 | |
2669 | #define Q6_P_dfmake_I_pos __builtin_HEXAGON_F2_dfimm_p |
2670 | |
2671 | /* ========================================================================== |
2672 | Assembly Syntax: Rd32=sfadd(Rs32,Rt32) |
2673 | C Intrinsic Prototype: Float32 Q6_R_sfadd_RR(Float32 Rs, Float32 Rt) |
2674 | Instruction Type: M |
2675 | Execution Slots: SLOT23 |
2676 | ========================================================================== */ |
2677 | |
2678 | #define Q6_R_sfadd_RR __builtin_HEXAGON_F2_sfadd |
2679 | |
2680 | /* ========================================================================== |
2681 | Assembly Syntax: Pd4=sfclass(Rs32,#u5) |
2682 | C Intrinsic Prototype: Byte Q6_p_sfclass_RI(Float32 Rs, Word32 Iu5) |
2683 | Instruction Type: S_2op |
2684 | Execution Slots: SLOT23 |
2685 | ========================================================================== */ |
2686 | |
2687 | #define Q6_p_sfclass_RI __builtin_HEXAGON_F2_sfclass |
2688 | |
2689 | /* ========================================================================== |
2690 | Assembly Syntax: Pd4=sfcmp.eq(Rs32,Rt32) |
2691 | C Intrinsic Prototype: Byte Q6_p_sfcmp_eq_RR(Float32 Rs, Float32 Rt) |
2692 | Instruction Type: S_3op |
2693 | Execution Slots: SLOT23 |
2694 | ========================================================================== */ |
2695 | |
2696 | #define Q6_p_sfcmp_eq_RR __builtin_HEXAGON_F2_sfcmpeq |
2697 | |
2698 | /* ========================================================================== |
2699 | Assembly Syntax: Pd4=sfcmp.ge(Rs32,Rt32) |
2700 | C Intrinsic Prototype: Byte Q6_p_sfcmp_ge_RR(Float32 Rs, Float32 Rt) |
2701 | Instruction Type: S_3op |
2702 | Execution Slots: SLOT23 |
2703 | ========================================================================== */ |
2704 | |
2705 | #define Q6_p_sfcmp_ge_RR __builtin_HEXAGON_F2_sfcmpge |
2706 | |
2707 | /* ========================================================================== |
2708 | Assembly Syntax: Pd4=sfcmp.gt(Rs32,Rt32) |
2709 | C Intrinsic Prototype: Byte Q6_p_sfcmp_gt_RR(Float32 Rs, Float32 Rt) |
2710 | Instruction Type: S_3op |
2711 | Execution Slots: SLOT23 |
2712 | ========================================================================== */ |
2713 | |
2714 | #define Q6_p_sfcmp_gt_RR __builtin_HEXAGON_F2_sfcmpgt |
2715 | |
2716 | /* ========================================================================== |
2717 | Assembly Syntax: Pd4=sfcmp.uo(Rs32,Rt32) |
2718 | C Intrinsic Prototype: Byte Q6_p_sfcmp_uo_RR(Float32 Rs, Float32 Rt) |
2719 | Instruction Type: S_3op |
2720 | Execution Slots: SLOT23 |
2721 | ========================================================================== */ |
2722 | |
2723 | #define Q6_p_sfcmp_uo_RR __builtin_HEXAGON_F2_sfcmpuo |
2724 | |
2725 | /* ========================================================================== |
2726 | Assembly Syntax: Rd32=sffixupd(Rs32,Rt32) |
2727 | C Intrinsic Prototype: Float32 Q6_R_sffixupd_RR(Float32 Rs, Float32 Rt) |
2728 | Instruction Type: M |
2729 | Execution Slots: SLOT23 |
2730 | ========================================================================== */ |
2731 | |
2732 | #define Q6_R_sffixupd_RR __builtin_HEXAGON_F2_sffixupd |
2733 | |
2734 | /* ========================================================================== |
2735 | Assembly Syntax: Rd32=sffixupn(Rs32,Rt32) |
2736 | C Intrinsic Prototype: Float32 Q6_R_sffixupn_RR(Float32 Rs, Float32 Rt) |
2737 | Instruction Type: M |
2738 | Execution Slots: SLOT23 |
2739 | ========================================================================== */ |
2740 | |
2741 | #define Q6_R_sffixupn_RR __builtin_HEXAGON_F2_sffixupn |
2742 | |
2743 | /* ========================================================================== |
2744 | Assembly Syntax: Rd32=sffixupr(Rs32) |
2745 | C Intrinsic Prototype: Float32 Q6_R_sffixupr_R(Float32 Rs) |
2746 | Instruction Type: S_2op |
2747 | Execution Slots: SLOT23 |
2748 | ========================================================================== */ |
2749 | |
2750 | #define Q6_R_sffixupr_R __builtin_HEXAGON_F2_sffixupr |
2751 | |
2752 | /* ========================================================================== |
2753 | Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32) |
2754 | C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR(Float32 Rx, Float32 Rs, Float32 Rt) |
2755 | Instruction Type: M |
2756 | Execution Slots: SLOT23 |
2757 | ========================================================================== */ |
2758 | |
2759 | #define Q6_R_sfmpyacc_RR __builtin_HEXAGON_F2_sffma |
2760 | |
2761 | /* ========================================================================== |
2762 | Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32):lib |
2763 | C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) |
2764 | Instruction Type: M |
2765 | Execution Slots: SLOT23 |
2766 | ========================================================================== */ |
2767 | |
2768 | #define Q6_R_sfmpyacc_RR_lib __builtin_HEXAGON_F2_sffma_lib |
2769 | |
2770 | /* ========================================================================== |
2771 | Assembly Syntax: Rx32+=sfmpy(Rs32,Rt32,Pu4):scale |
2772 | C Intrinsic Prototype: Float32 Q6_R_sfmpyacc_RRp_scale(Float32 Rx, Float32 Rs, Float32 Rt, Byte Pu) |
2773 | Instruction Type: M |
2774 | Execution Slots: SLOT23 |
2775 | ========================================================================== */ |
2776 | |
2777 | #define Q6_R_sfmpyacc_RRp_scale __builtin_HEXAGON_F2_sffma_sc |
2778 | |
2779 | /* ========================================================================== |
2780 | Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32) |
2781 | C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR(Float32 Rx, Float32 Rs, Float32 Rt) |
2782 | Instruction Type: M |
2783 | Execution Slots: SLOT23 |
2784 | ========================================================================== */ |
2785 | |
2786 | #define Q6_R_sfmpynac_RR __builtin_HEXAGON_F2_sffms |
2787 | |
2788 | /* ========================================================================== |
2789 | Assembly Syntax: Rx32-=sfmpy(Rs32,Rt32):lib |
2790 | C Intrinsic Prototype: Float32 Q6_R_sfmpynac_RR_lib(Float32 Rx, Float32 Rs, Float32 Rt) |
2791 | Instruction Type: M |
2792 | Execution Slots: SLOT23 |
2793 | ========================================================================== */ |
2794 | |
2795 | #define Q6_R_sfmpynac_RR_lib __builtin_HEXAGON_F2_sffms_lib |
2796 | |
2797 | /* ========================================================================== |
2798 | Assembly Syntax: Rd32=sfmake(#u10):neg |
2799 | C Intrinsic Prototype: Float32 Q6_R_sfmake_I_neg(Word32 Iu10) |
2800 | Instruction Type: ALU64 |
2801 | Execution Slots: SLOT23 |
2802 | ========================================================================== */ |
2803 | |
2804 | #define Q6_R_sfmake_I_neg __builtin_HEXAGON_F2_sfimm_n |
2805 | |
2806 | /* ========================================================================== |
2807 | Assembly Syntax: Rd32=sfmake(#u10):pos |
2808 | C Intrinsic Prototype: Float32 Q6_R_sfmake_I_pos(Word32 Iu10) |
2809 | Instruction Type: ALU64 |
2810 | Execution Slots: SLOT23 |
2811 | ========================================================================== */ |
2812 | |
2813 | #define Q6_R_sfmake_I_pos __builtin_HEXAGON_F2_sfimm_p |
2814 | |
2815 | /* ========================================================================== |
2816 | Assembly Syntax: Rd32=sfmax(Rs32,Rt32) |
2817 | C Intrinsic Prototype: Float32 Q6_R_sfmax_RR(Float32 Rs, Float32 Rt) |
2818 | Instruction Type: M |
2819 | Execution Slots: SLOT23 |
2820 | ========================================================================== */ |
2821 | |
2822 | #define Q6_R_sfmax_RR __builtin_HEXAGON_F2_sfmax |
2823 | |
2824 | /* ========================================================================== |
2825 | Assembly Syntax: Rd32=sfmin(Rs32,Rt32) |
2826 | C Intrinsic Prototype: Float32 Q6_R_sfmin_RR(Float32 Rs, Float32 Rt) |
2827 | Instruction Type: M |
2828 | Execution Slots: SLOT23 |
2829 | ========================================================================== */ |
2830 | |
2831 | #define Q6_R_sfmin_RR __builtin_HEXAGON_F2_sfmin |
2832 | |
2833 | /* ========================================================================== |
2834 | Assembly Syntax: Rd32=sfmpy(Rs32,Rt32) |
2835 | C Intrinsic Prototype: Float32 Q6_R_sfmpy_RR(Float32 Rs, Float32 Rt) |
2836 | Instruction Type: M |
2837 | Execution Slots: SLOT23 |
2838 | ========================================================================== */ |
2839 | |
2840 | #define Q6_R_sfmpy_RR __builtin_HEXAGON_F2_sfmpy |
2841 | |
2842 | /* ========================================================================== |
2843 | Assembly Syntax: Rd32=sfsub(Rs32,Rt32) |
2844 | C Intrinsic Prototype: Float32 Q6_R_sfsub_RR(Float32 Rs, Float32 Rt) |
2845 | Instruction Type: M |
2846 | Execution Slots: SLOT23 |
2847 | ========================================================================== */ |
2848 | |
2849 | #define Q6_R_sfsub_RR __builtin_HEXAGON_F2_sfsub |
2850 | |
2851 | /* ========================================================================== |
2852 | Assembly Syntax: Rd32=memb(Rx32++#s4:0:circ(Mu2)) |
2853 | C Intrinsic Prototype: Word32 Q6_R_memb_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) |
2854 | Instruction Type: LD |
2855 | Execution Slots: SLOT01 |
2856 | ========================================================================== */ |
2857 | |
2858 | #define Q6_R_memb_IM_circ __builtin_HEXAGON_L2_loadrb_pci |
2859 | |
2860 | /* ========================================================================== |
2861 | Assembly Syntax: Rd32=memb(Rx32++I:circ(Mu2)) |
2862 | C Intrinsic Prototype: Word32 Q6_R_memb_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2863 | Instruction Type: LD |
2864 | Execution Slots: SLOT01 |
2865 | ========================================================================== */ |
2866 | |
2867 | #define Q6_R_memb_M_circ __builtin_HEXAGON_L2_loadrb_pcr |
2868 | |
2869 | /* ========================================================================== |
2870 | Assembly Syntax: Rdd32=memd(Rx32++#s4:3:circ(Mu2)) |
2871 | C Intrinsic Prototype: Word64 Q6_P_memd_IM_circ(void** Rx, Word32 Is4_3, Word32 Mu, void* BaseAddress) |
2872 | Instruction Type: LD |
2873 | Execution Slots: SLOT01 |
2874 | ========================================================================== */ |
2875 | |
2876 | #define Q6_P_memd_IM_circ __builtin_HEXAGON_L2_loadrd_pci |
2877 | |
2878 | /* ========================================================================== |
2879 | Assembly Syntax: Rdd32=memd(Rx32++I:circ(Mu2)) |
2880 | C Intrinsic Prototype: Word64 Q6_P_memd_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2881 | Instruction Type: LD |
2882 | Execution Slots: SLOT01 |
2883 | ========================================================================== */ |
2884 | |
2885 | #define Q6_P_memd_M_circ __builtin_HEXAGON_L2_loadrd_pcr |
2886 | |
2887 | /* ========================================================================== |
2888 | Assembly Syntax: Rd32=memh(Rx32++#s4:1:circ(Mu2)) |
2889 | C Intrinsic Prototype: Word32 Q6_R_memh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) |
2890 | Instruction Type: LD |
2891 | Execution Slots: SLOT01 |
2892 | ========================================================================== */ |
2893 | |
2894 | #define Q6_R_memh_IM_circ __builtin_HEXAGON_L2_loadrh_pci |
2895 | |
2896 | /* ========================================================================== |
2897 | Assembly Syntax: Rd32=memh(Rx32++I:circ(Mu2)) |
2898 | C Intrinsic Prototype: Word32 Q6_R_memh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2899 | Instruction Type: LD |
2900 | Execution Slots: SLOT01 |
2901 | ========================================================================== */ |
2902 | |
2903 | #define Q6_R_memh_M_circ __builtin_HEXAGON_L2_loadrh_pcr |
2904 | |
2905 | /* ========================================================================== |
2906 | Assembly Syntax: Rd32=memw(Rx32++#s4:2:circ(Mu2)) |
2907 | C Intrinsic Prototype: Word32 Q6_R_memw_IM_circ(void** Rx, Word32 Is4_2, Word32 Mu, void* BaseAddress) |
2908 | Instruction Type: LD |
2909 | Execution Slots: SLOT01 |
2910 | ========================================================================== */ |
2911 | |
2912 | #define Q6_R_memw_IM_circ __builtin_HEXAGON_L2_loadri_pci |
2913 | |
2914 | /* ========================================================================== |
2915 | Assembly Syntax: Rd32=memw(Rx32++I:circ(Mu2)) |
2916 | C Intrinsic Prototype: Word32 Q6_R_memw_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2917 | Instruction Type: LD |
2918 | Execution Slots: SLOT01 |
2919 | ========================================================================== */ |
2920 | |
2921 | #define Q6_R_memw_M_circ __builtin_HEXAGON_L2_loadri_pcr |
2922 | |
2923 | /* ========================================================================== |
2924 | Assembly Syntax: Rd32=memub(Rx32++#s4:0:circ(Mu2)) |
2925 | C Intrinsic Prototype: Word32 Q6_R_memub_IM_circ(void** Rx, Word32 Is4_0, Word32 Mu, void* BaseAddress) |
2926 | Instruction Type: LD |
2927 | Execution Slots: SLOT01 |
2928 | ========================================================================== */ |
2929 | |
2930 | #define Q6_R_memub_IM_circ __builtin_HEXAGON_L2_loadrub_pci |
2931 | |
2932 | /* ========================================================================== |
2933 | Assembly Syntax: Rd32=memub(Rx32++I:circ(Mu2)) |
2934 | C Intrinsic Prototype: Word32 Q6_R_memub_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2935 | Instruction Type: LD |
2936 | Execution Slots: SLOT01 |
2937 | ========================================================================== */ |
2938 | |
2939 | #define Q6_R_memub_M_circ __builtin_HEXAGON_L2_loadrub_pcr |
2940 | |
2941 | /* ========================================================================== |
2942 | Assembly Syntax: Rd32=memuh(Rx32++#s4:1:circ(Mu2)) |
2943 | C Intrinsic Prototype: Word32 Q6_R_memuh_IM_circ(void** Rx, Word32 Is4_1, Word32 Mu, void* BaseAddress) |
2944 | Instruction Type: LD |
2945 | Execution Slots: SLOT01 |
2946 | ========================================================================== */ |
2947 | |
2948 | #define Q6_R_memuh_IM_circ __builtin_HEXAGON_L2_loadruh_pci |
2949 | |
2950 | /* ========================================================================== |
2951 | Assembly Syntax: Rd32=memuh(Rx32++I:circ(Mu2)) |
2952 | C Intrinsic Prototype: Word32 Q6_R_memuh_M_circ(void** Rx, Word32 Mu, void* BaseAddress) |
2953 | Instruction Type: LD |
2954 | Execution Slots: SLOT01 |
2955 | ========================================================================== */ |
2956 | |
2957 | #define Q6_R_memuh_M_circ __builtin_HEXAGON_L2_loadruh_pcr |
2958 | |
2959 | /* ========================================================================== |
2960 | Assembly Syntax: Rx32+=add(Rs32,Rt32) |
2961 | C Intrinsic Prototype: Word32 Q6_R_addacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
2962 | Instruction Type: M |
2963 | Execution Slots: SLOT23 |
2964 | ========================================================================== */ |
2965 | |
2966 | #define Q6_R_addacc_RR __builtin_HEXAGON_M2_acci |
2967 | |
2968 | /* ========================================================================== |
2969 | Assembly Syntax: Rx32+=add(Rs32,#s8) |
2970 | C Intrinsic Prototype: Word32 Q6_R_addacc_RI(Word32 Rx, Word32 Rs, Word32 Is8) |
2971 | Instruction Type: M |
2972 | Execution Slots: SLOT23 |
2973 | ========================================================================== */ |
2974 | |
2975 | #define Q6_R_addacc_RI __builtin_HEXAGON_M2_accii |
2976 | |
2977 | /* ========================================================================== |
2978 | Assembly Syntax: Rxx32+=cmpyi(Rs32,Rt32) |
2979 | C Intrinsic Prototype: Word64 Q6_P_cmpyiacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
2980 | Instruction Type: M |
2981 | Execution Slots: SLOT23 |
2982 | ========================================================================== */ |
2983 | |
2984 | #define Q6_P_cmpyiacc_RR __builtin_HEXAGON_M2_cmaci_s0 |
2985 | |
2986 | /* ========================================================================== |
2987 | Assembly Syntax: Rxx32+=cmpyr(Rs32,Rt32) |
2988 | C Intrinsic Prototype: Word64 Q6_P_cmpyracc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
2989 | Instruction Type: M |
2990 | Execution Slots: SLOT23 |
2991 | ========================================================================== */ |
2992 | |
2993 | #define Q6_P_cmpyracc_RR __builtin_HEXAGON_M2_cmacr_s0 |
2994 | |
2995 | /* ========================================================================== |
2996 | Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):sat |
2997 | C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
2998 | Instruction Type: M |
2999 | Execution Slots: SLOT23 |
3000 | ========================================================================== */ |
3001 | |
3002 | #define Q6_P_cmpyacc_RR_sat __builtin_HEXAGON_M2_cmacs_s0 |
3003 | |
3004 | /* ========================================================================== |
3005 | Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32):<<1:sat |
3006 | C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3007 | Instruction Type: M |
3008 | Execution Slots: SLOT23 |
3009 | ========================================================================== */ |
3010 | |
3011 | #define Q6_P_cmpyacc_RR_s1_sat __builtin_HEXAGON_M2_cmacs_s1 |
3012 | |
3013 | /* ========================================================================== |
3014 | Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):sat |
3015 | C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3016 | Instruction Type: M |
3017 | Execution Slots: SLOT23 |
3018 | ========================================================================== */ |
3019 | |
3020 | #define Q6_P_cmpyacc_RR_conj_sat __builtin_HEXAGON_M2_cmacsc_s0 |
3021 | |
3022 | /* ========================================================================== |
3023 | Assembly Syntax: Rxx32+=cmpy(Rs32,Rt32*):<<1:sat |
3024 | C Intrinsic Prototype: Word64 Q6_P_cmpyacc_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3025 | Instruction Type: M |
3026 | Execution Slots: SLOT23 |
3027 | ========================================================================== */ |
3028 | |
3029 | #define Q6_P_cmpyacc_RR_conj_s1_sat __builtin_HEXAGON_M2_cmacsc_s1 |
3030 | |
3031 | /* ========================================================================== |
3032 | Assembly Syntax: Rdd32=cmpyi(Rs32,Rt32) |
3033 | C Intrinsic Prototype: Word64 Q6_P_cmpyi_RR(Word32 Rs, Word32 Rt) |
3034 | Instruction Type: M |
3035 | Execution Slots: SLOT23 |
3036 | ========================================================================== */ |
3037 | |
3038 | #define Q6_P_cmpyi_RR __builtin_HEXAGON_M2_cmpyi_s0 |
3039 | |
3040 | /* ========================================================================== |
3041 | Assembly Syntax: Rdd32=cmpyr(Rs32,Rt32) |
3042 | C Intrinsic Prototype: Word64 Q6_P_cmpyr_RR(Word32 Rs, Word32 Rt) |
3043 | Instruction Type: M |
3044 | Execution Slots: SLOT23 |
3045 | ========================================================================== */ |
3046 | |
3047 | #define Q6_P_cmpyr_RR __builtin_HEXAGON_M2_cmpyr_s0 |
3048 | |
3049 | /* ========================================================================== |
3050 | Assembly Syntax: Rd32=cmpy(Rs32,Rt32):rnd:sat |
3051 | C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_rnd_sat(Word32 Rs, Word32 Rt) |
3052 | Instruction Type: M |
3053 | Execution Slots: SLOT23 |
3054 | ========================================================================== */ |
3055 | |
3056 | #define Q6_R_cmpy_RR_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s0 |
3057 | |
3058 | /* ========================================================================== |
3059 | Assembly Syntax: Rd32=cmpy(Rs32,Rt32):<<1:rnd:sat |
3060 | C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) |
3061 | Instruction Type: M |
3062 | Execution Slots: SLOT23 |
3063 | ========================================================================== */ |
3064 | |
3065 | #define Q6_R_cmpy_RR_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrs_s1 |
3066 | |
3067 | /* ========================================================================== |
3068 | Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):rnd:sat |
3069 | C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_rnd_sat(Word32 Rs, Word32 Rt) |
3070 | Instruction Type: M |
3071 | Execution Slots: SLOT23 |
3072 | ========================================================================== */ |
3073 | |
3074 | #define Q6_R_cmpy_RR_conj_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s0 |
3075 | |
3076 | /* ========================================================================== |
3077 | Assembly Syntax: Rd32=cmpy(Rs32,Rt32*):<<1:rnd:sat |
3078 | C Intrinsic Prototype: Word32 Q6_R_cmpy_RR_conj_s1_rnd_sat(Word32 Rs, Word32 Rt) |
3079 | Instruction Type: M |
3080 | Execution Slots: SLOT23 |
3081 | ========================================================================== */ |
3082 | |
3083 | #define Q6_R_cmpy_RR_conj_s1_rnd_sat __builtin_HEXAGON_M2_cmpyrsc_s1 |
3084 | |
3085 | /* ========================================================================== |
3086 | Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):sat |
3087 | C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_sat(Word32 Rs, Word32 Rt) |
3088 | Instruction Type: M |
3089 | Execution Slots: SLOT23 |
3090 | ========================================================================== */ |
3091 | |
3092 | #define Q6_P_cmpy_RR_sat __builtin_HEXAGON_M2_cmpys_s0 |
3093 | |
3094 | /* ========================================================================== |
3095 | Assembly Syntax: Rdd32=cmpy(Rs32,Rt32):<<1:sat |
3096 | C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_s1_sat(Word32 Rs, Word32 Rt) |
3097 | Instruction Type: M |
3098 | Execution Slots: SLOT23 |
3099 | ========================================================================== */ |
3100 | |
3101 | #define Q6_P_cmpy_RR_s1_sat __builtin_HEXAGON_M2_cmpys_s1 |
3102 | |
3103 | /* ========================================================================== |
3104 | Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):sat |
3105 | C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_sat(Word32 Rs, Word32 Rt) |
3106 | Instruction Type: M |
3107 | Execution Slots: SLOT23 |
3108 | ========================================================================== */ |
3109 | |
3110 | #define Q6_P_cmpy_RR_conj_sat __builtin_HEXAGON_M2_cmpysc_s0 |
3111 | |
3112 | /* ========================================================================== |
3113 | Assembly Syntax: Rdd32=cmpy(Rs32,Rt32*):<<1:sat |
3114 | C Intrinsic Prototype: Word64 Q6_P_cmpy_RR_conj_s1_sat(Word32 Rs, Word32 Rt) |
3115 | Instruction Type: M |
3116 | Execution Slots: SLOT23 |
3117 | ========================================================================== */ |
3118 | |
3119 | #define Q6_P_cmpy_RR_conj_s1_sat __builtin_HEXAGON_M2_cmpysc_s1 |
3120 | |
3121 | /* ========================================================================== |
3122 | Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):sat |
3123 | C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3124 | Instruction Type: M |
3125 | Execution Slots: SLOT23 |
3126 | ========================================================================== */ |
3127 | |
3128 | #define Q6_P_cmpynac_RR_sat __builtin_HEXAGON_M2_cnacs_s0 |
3129 | |
3130 | /* ========================================================================== |
3131 | Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32):<<1:sat |
3132 | C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3133 | Instruction Type: M |
3134 | Execution Slots: SLOT23 |
3135 | ========================================================================== */ |
3136 | |
3137 | #define Q6_P_cmpynac_RR_s1_sat __builtin_HEXAGON_M2_cnacs_s1 |
3138 | |
3139 | /* ========================================================================== |
3140 | Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):sat |
3141 | C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3142 | Instruction Type: M |
3143 | Execution Slots: SLOT23 |
3144 | ========================================================================== */ |
3145 | |
3146 | #define Q6_P_cmpynac_RR_conj_sat __builtin_HEXAGON_M2_cnacsc_s0 |
3147 | |
3148 | /* ========================================================================== |
3149 | Assembly Syntax: Rxx32-=cmpy(Rs32,Rt32*):<<1:sat |
3150 | C Intrinsic Prototype: Word64 Q6_P_cmpynac_RR_conj_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
3151 | Instruction Type: M |
3152 | Execution Slots: SLOT23 |
3153 | ========================================================================== */ |
3154 | |
3155 | #define Q6_P_cmpynac_RR_conj_s1_sat __builtin_HEXAGON_M2_cnacsc_s1 |
3156 | |
3157 | /* ========================================================================== |
3158 | Assembly Syntax: Rxx32+=mpy(Rs32,Rt32) |
3159 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
3160 | Instruction Type: M |
3161 | Execution Slots: SLOT23 |
3162 | ========================================================================== */ |
3163 | |
3164 | #define Q6_P_mpyacc_RR __builtin_HEXAGON_M2_dpmpyss_acc_s0 |
3165 | |
3166 | /* ========================================================================== |
3167 | Assembly Syntax: Rxx32-=mpy(Rs32,Rt32) |
3168 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
3169 | Instruction Type: M |
3170 | Execution Slots: SLOT23 |
3171 | ========================================================================== */ |
3172 | |
3173 | #define Q6_P_mpynac_RR __builtin_HEXAGON_M2_dpmpyss_nac_s0 |
3174 | |
3175 | /* ========================================================================== |
3176 | Assembly Syntax: Rd32=mpy(Rs32,Rt32):rnd |
3177 | C Intrinsic Prototype: Word32 Q6_R_mpy_RR_rnd(Word32 Rs, Word32 Rt) |
3178 | Instruction Type: M |
3179 | Execution Slots: SLOT23 |
3180 | ========================================================================== */ |
3181 | |
3182 | #define Q6_R_mpy_RR_rnd __builtin_HEXAGON_M2_dpmpyss_rnd_s0 |
3183 | |
3184 | /* ========================================================================== |
3185 | Assembly Syntax: Rdd32=mpy(Rs32,Rt32) |
3186 | C Intrinsic Prototype: Word64 Q6_P_mpy_RR(Word32 Rs, Word32 Rt) |
3187 | Instruction Type: M |
3188 | Execution Slots: SLOT23 |
3189 | ========================================================================== */ |
3190 | |
3191 | #define Q6_P_mpy_RR __builtin_HEXAGON_M2_dpmpyss_s0 |
3192 | |
3193 | /* ========================================================================== |
3194 | Assembly Syntax: Rxx32+=mpyu(Rs32,Rt32) |
3195 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
3196 | Instruction Type: M |
3197 | Execution Slots: SLOT23 |
3198 | ========================================================================== */ |
3199 | |
3200 | #define Q6_P_mpyuacc_RR __builtin_HEXAGON_M2_dpmpyuu_acc_s0 |
3201 | |
3202 | /* ========================================================================== |
3203 | Assembly Syntax: Rxx32-=mpyu(Rs32,Rt32) |
3204 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
3205 | Instruction Type: M |
3206 | Execution Slots: SLOT23 |
3207 | ========================================================================== */ |
3208 | |
3209 | #define Q6_P_mpyunac_RR __builtin_HEXAGON_M2_dpmpyuu_nac_s0 |
3210 | |
3211 | /* ========================================================================== |
3212 | Assembly Syntax: Rdd32=mpyu(Rs32,Rt32) |
3213 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RR(Word32 Rs, Word32 Rt) |
3214 | Instruction Type: M |
3215 | Execution Slots: SLOT23 |
3216 | ========================================================================== */ |
3217 | |
3218 | #define Q6_P_mpyu_RR __builtin_HEXAGON_M2_dpmpyuu_s0 |
3219 | |
3220 | /* ========================================================================== |
3221 | Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:rnd:sat |
3222 | C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_rnd_sat(Word32 Rs, Word32 Rt) |
3223 | Instruction Type: M |
3224 | Execution Slots: SLOT23 |
3225 | ========================================================================== */ |
3226 | |
3227 | #define Q6_R_mpy_RRh_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyh_rs1 |
3228 | |
3229 | /* ========================================================================== |
3230 | Assembly Syntax: Rd32=mpy(Rs32,Rt32.h):<<1:sat |
3231 | C Intrinsic Prototype: Word32 Q6_R_mpy_RRh_s1_sat(Word32 Rs, Word32 Rt) |
3232 | Instruction Type: M |
3233 | Execution Slots: SLOT23 |
3234 | ========================================================================== */ |
3235 | |
3236 | #define Q6_R_mpy_RRh_s1_sat __builtin_HEXAGON_M2_hmmpyh_s1 |
3237 | |
3238 | /* ========================================================================== |
3239 | Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:rnd:sat |
3240 | C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_rnd_sat(Word32 Rs, Word32 Rt) |
3241 | Instruction Type: M |
3242 | Execution Slots: SLOT23 |
3243 | ========================================================================== */ |
3244 | |
3245 | #define Q6_R_mpy_RRl_s1_rnd_sat __builtin_HEXAGON_M2_hmmpyl_rs1 |
3246 | |
3247 | /* ========================================================================== |
3248 | Assembly Syntax: Rd32=mpy(Rs32,Rt32.l):<<1:sat |
3249 | C Intrinsic Prototype: Word32 Q6_R_mpy_RRl_s1_sat(Word32 Rs, Word32 Rt) |
3250 | Instruction Type: M |
3251 | Execution Slots: SLOT23 |
3252 | ========================================================================== */ |
3253 | |
3254 | #define Q6_R_mpy_RRl_s1_sat __builtin_HEXAGON_M2_hmmpyl_s1 |
3255 | |
3256 | /* ========================================================================== |
3257 | Assembly Syntax: Rx32+=mpyi(Rs32,Rt32) |
3258 | C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
3259 | Instruction Type: M |
3260 | Execution Slots: SLOT23 |
3261 | ========================================================================== */ |
3262 | |
3263 | #define Q6_R_mpyiacc_RR __builtin_HEXAGON_M2_maci |
3264 | |
3265 | /* ========================================================================== |
3266 | Assembly Syntax: Rx32-=mpyi(Rs32,#u8) |
3267 | C Intrinsic Prototype: Word32 Q6_R_mpyinac_RI(Word32 Rx, Word32 Rs, Word32 Iu8) |
3268 | Instruction Type: M |
3269 | Execution Slots: SLOT23 |
3270 | ========================================================================== */ |
3271 | |
3272 | #define Q6_R_mpyinac_RI __builtin_HEXAGON_M2_macsin |
3273 | |
3274 | /* ========================================================================== |
3275 | Assembly Syntax: Rx32+=mpyi(Rs32,#u8) |
3276 | C Intrinsic Prototype: Word32 Q6_R_mpyiacc_RI(Word32 Rx, Word32 Rs, Word32 Iu8) |
3277 | Instruction Type: M |
3278 | Execution Slots: SLOT23 |
3279 | ========================================================================== */ |
3280 | |
3281 | #define Q6_R_mpyiacc_RI __builtin_HEXAGON_M2_macsip |
3282 | |
3283 | /* ========================================================================== |
3284 | Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):rnd:sat |
3285 | C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3286 | Instruction Type: M |
3287 | Execution Slots: SLOT23 |
3288 | ========================================================================== */ |
3289 | |
3290 | #define Q6_P_vmpywohacc_PP_rnd_sat __builtin_HEXAGON_M2_mmachs_rs0 |
3291 | |
3292 | /* ========================================================================== |
3293 | Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:rnd:sat |
3294 | C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3295 | Instruction Type: M |
3296 | Execution Slots: SLOT23 |
3297 | ========================================================================== */ |
3298 | |
3299 | #define Q6_P_vmpywohacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmachs_rs1 |
3300 | |
3301 | /* ========================================================================== |
3302 | Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):sat |
3303 | C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3304 | Instruction Type: M |
3305 | Execution Slots: SLOT23 |
3306 | ========================================================================== */ |
3307 | |
3308 | #define Q6_P_vmpywohacc_PP_sat __builtin_HEXAGON_M2_mmachs_s0 |
3309 | |
3310 | /* ========================================================================== |
3311 | Assembly Syntax: Rxx32+=vmpywoh(Rss32,Rtt32):<<1:sat |
3312 | C Intrinsic Prototype: Word64 Q6_P_vmpywohacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3313 | Instruction Type: M |
3314 | Execution Slots: SLOT23 |
3315 | ========================================================================== */ |
3316 | |
3317 | #define Q6_P_vmpywohacc_PP_s1_sat __builtin_HEXAGON_M2_mmachs_s1 |
3318 | |
3319 | /* ========================================================================== |
3320 | Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):rnd:sat |
3321 | C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3322 | Instruction Type: M |
3323 | Execution Slots: SLOT23 |
3324 | ========================================================================== */ |
3325 | |
3326 | #define Q6_P_vmpywehacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacls_rs0 |
3327 | |
3328 | /* ========================================================================== |
3329 | Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:rnd:sat |
3330 | C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3331 | Instruction Type: M |
3332 | Execution Slots: SLOT23 |
3333 | ========================================================================== */ |
3334 | |
3335 | #define Q6_P_vmpywehacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacls_rs1 |
3336 | |
3337 | /* ========================================================================== |
3338 | Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):sat |
3339 | C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3340 | Instruction Type: M |
3341 | Execution Slots: SLOT23 |
3342 | ========================================================================== */ |
3343 | |
3344 | #define Q6_P_vmpywehacc_PP_sat __builtin_HEXAGON_M2_mmacls_s0 |
3345 | |
3346 | /* ========================================================================== |
3347 | Assembly Syntax: Rxx32+=vmpyweh(Rss32,Rtt32):<<1:sat |
3348 | C Intrinsic Prototype: Word64 Q6_P_vmpywehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3349 | Instruction Type: M |
3350 | Execution Slots: SLOT23 |
3351 | ========================================================================== */ |
3352 | |
3353 | #define Q6_P_vmpywehacc_PP_s1_sat __builtin_HEXAGON_M2_mmacls_s1 |
3354 | |
3355 | /* ========================================================================== |
3356 | Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):rnd:sat |
3357 | C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3358 | Instruction Type: M |
3359 | Execution Slots: SLOT23 |
3360 | ========================================================================== */ |
3361 | |
3362 | #define Q6_P_vmpywouhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs0 |
3363 | |
3364 | /* ========================================================================== |
3365 | Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:rnd:sat |
3366 | C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3367 | Instruction Type: M |
3368 | Execution Slots: SLOT23 |
3369 | ========================================================================== */ |
3370 | |
3371 | #define Q6_P_vmpywouhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmacuhs_rs1 |
3372 | |
3373 | /* ========================================================================== |
3374 | Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):sat |
3375 | C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3376 | Instruction Type: M |
3377 | Execution Slots: SLOT23 |
3378 | ========================================================================== */ |
3379 | |
3380 | #define Q6_P_vmpywouhacc_PP_sat __builtin_HEXAGON_M2_mmacuhs_s0 |
3381 | |
3382 | /* ========================================================================== |
3383 | Assembly Syntax: Rxx32+=vmpywouh(Rss32,Rtt32):<<1:sat |
3384 | C Intrinsic Prototype: Word64 Q6_P_vmpywouhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3385 | Instruction Type: M |
3386 | Execution Slots: SLOT23 |
3387 | ========================================================================== */ |
3388 | |
3389 | #define Q6_P_vmpywouhacc_PP_s1_sat __builtin_HEXAGON_M2_mmacuhs_s1 |
3390 | |
3391 | /* ========================================================================== |
3392 | Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):rnd:sat |
3393 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3394 | Instruction Type: M |
3395 | Execution Slots: SLOT23 |
3396 | ========================================================================== */ |
3397 | |
3398 | #define Q6_P_vmpyweuhacc_PP_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs0 |
3399 | |
3400 | /* ========================================================================== |
3401 | Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat |
3402 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_rnd_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3403 | Instruction Type: M |
3404 | Execution Slots: SLOT23 |
3405 | ========================================================================== */ |
3406 | |
3407 | #define Q6_P_vmpyweuhacc_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmaculs_rs1 |
3408 | |
3409 | /* ========================================================================== |
3410 | Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):sat |
3411 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3412 | Instruction Type: M |
3413 | Execution Slots: SLOT23 |
3414 | ========================================================================== */ |
3415 | |
3416 | #define Q6_P_vmpyweuhacc_PP_sat __builtin_HEXAGON_M2_mmaculs_s0 |
3417 | |
3418 | /* ========================================================================== |
3419 | Assembly Syntax: Rxx32+=vmpyweuh(Rss32,Rtt32):<<1:sat |
3420 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuhacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
3421 | Instruction Type: M |
3422 | Execution Slots: SLOT23 |
3423 | ========================================================================== */ |
3424 | |
3425 | #define Q6_P_vmpyweuhacc_PP_s1_sat __builtin_HEXAGON_M2_mmaculs_s1 |
3426 | |
3427 | /* ========================================================================== |
3428 | Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):rnd:sat |
3429 | C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_rnd_sat(Word64 Rss, Word64 Rtt) |
3430 | Instruction Type: M |
3431 | Execution Slots: SLOT23 |
3432 | ========================================================================== */ |
3433 | |
3434 | #define Q6_P_vmpywoh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs0 |
3435 | |
3436 | /* ========================================================================== |
3437 | Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:rnd:sat |
3438 | C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
3439 | Instruction Type: M |
3440 | Execution Slots: SLOT23 |
3441 | ========================================================================== */ |
3442 | |
3443 | #define Q6_P_vmpywoh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyh_rs1 |
3444 | |
3445 | /* ========================================================================== |
3446 | Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):sat |
3447 | C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_sat(Word64 Rss, Word64 Rtt) |
3448 | Instruction Type: M |
3449 | Execution Slots: SLOT23 |
3450 | ========================================================================== */ |
3451 | |
3452 | #define Q6_P_vmpywoh_PP_sat __builtin_HEXAGON_M2_mmpyh_s0 |
3453 | |
3454 | /* ========================================================================== |
3455 | Assembly Syntax: Rdd32=vmpywoh(Rss32,Rtt32):<<1:sat |
3456 | C Intrinsic Prototype: Word64 Q6_P_vmpywoh_PP_s1_sat(Word64 Rss, Word64 Rtt) |
3457 | Instruction Type: M |
3458 | Execution Slots: SLOT23 |
3459 | ========================================================================== */ |
3460 | |
3461 | #define Q6_P_vmpywoh_PP_s1_sat __builtin_HEXAGON_M2_mmpyh_s1 |
3462 | |
3463 | /* ========================================================================== |
3464 | Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):rnd:sat |
3465 | C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_rnd_sat(Word64 Rss, Word64 Rtt) |
3466 | Instruction Type: M |
3467 | Execution Slots: SLOT23 |
3468 | ========================================================================== */ |
3469 | |
3470 | #define Q6_P_vmpyweh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs0 |
3471 | |
3472 | /* ========================================================================== |
3473 | Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:rnd:sat |
3474 | C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
3475 | Instruction Type: M |
3476 | Execution Slots: SLOT23 |
3477 | ========================================================================== */ |
3478 | |
3479 | #define Q6_P_vmpyweh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyl_rs1 |
3480 | |
3481 | /* ========================================================================== |
3482 | Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):sat |
3483 | C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_sat(Word64 Rss, Word64 Rtt) |
3484 | Instruction Type: M |
3485 | Execution Slots: SLOT23 |
3486 | ========================================================================== */ |
3487 | |
3488 | #define Q6_P_vmpyweh_PP_sat __builtin_HEXAGON_M2_mmpyl_s0 |
3489 | |
3490 | /* ========================================================================== |
3491 | Assembly Syntax: Rdd32=vmpyweh(Rss32,Rtt32):<<1:sat |
3492 | C Intrinsic Prototype: Word64 Q6_P_vmpyweh_PP_s1_sat(Word64 Rss, Word64 Rtt) |
3493 | Instruction Type: M |
3494 | Execution Slots: SLOT23 |
3495 | ========================================================================== */ |
3496 | |
3497 | #define Q6_P_vmpyweh_PP_s1_sat __builtin_HEXAGON_M2_mmpyl_s1 |
3498 | |
3499 | /* ========================================================================== |
3500 | Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):rnd:sat |
3501 | C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_rnd_sat(Word64 Rss, Word64 Rtt) |
3502 | Instruction Type: M |
3503 | Execution Slots: SLOT23 |
3504 | ========================================================================== */ |
3505 | |
3506 | #define Q6_P_vmpywouh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs0 |
3507 | |
3508 | /* ========================================================================== |
3509 | Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:rnd:sat |
3510 | C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
3511 | Instruction Type: M |
3512 | Execution Slots: SLOT23 |
3513 | ========================================================================== */ |
3514 | |
3515 | #define Q6_P_vmpywouh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyuh_rs1 |
3516 | |
3517 | /* ========================================================================== |
3518 | Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):sat |
3519 | C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_sat(Word64 Rss, Word64 Rtt) |
3520 | Instruction Type: M |
3521 | Execution Slots: SLOT23 |
3522 | ========================================================================== */ |
3523 | |
3524 | #define Q6_P_vmpywouh_PP_sat __builtin_HEXAGON_M2_mmpyuh_s0 |
3525 | |
3526 | /* ========================================================================== |
3527 | Assembly Syntax: Rdd32=vmpywouh(Rss32,Rtt32):<<1:sat |
3528 | C Intrinsic Prototype: Word64 Q6_P_vmpywouh_PP_s1_sat(Word64 Rss, Word64 Rtt) |
3529 | Instruction Type: M |
3530 | Execution Slots: SLOT23 |
3531 | ========================================================================== */ |
3532 | |
3533 | #define Q6_P_vmpywouh_PP_s1_sat __builtin_HEXAGON_M2_mmpyuh_s1 |
3534 | |
3535 | /* ========================================================================== |
3536 | Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):rnd:sat |
3537 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_rnd_sat(Word64 Rss, Word64 Rtt) |
3538 | Instruction Type: M |
3539 | Execution Slots: SLOT23 |
3540 | ========================================================================== */ |
3541 | |
3542 | #define Q6_P_vmpyweuh_PP_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs0 |
3543 | |
3544 | /* ========================================================================== |
3545 | Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:rnd:sat |
3546 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
3547 | Instruction Type: M |
3548 | Execution Slots: SLOT23 |
3549 | ========================================================================== */ |
3550 | |
3551 | #define Q6_P_vmpyweuh_PP_s1_rnd_sat __builtin_HEXAGON_M2_mmpyul_rs1 |
3552 | |
3553 | /* ========================================================================== |
3554 | Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):sat |
3555 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_sat(Word64 Rss, Word64 Rtt) |
3556 | Instruction Type: M |
3557 | Execution Slots: SLOT23 |
3558 | ========================================================================== */ |
3559 | |
3560 | #define Q6_P_vmpyweuh_PP_sat __builtin_HEXAGON_M2_mmpyul_s0 |
3561 | |
3562 | /* ========================================================================== |
3563 | Assembly Syntax: Rdd32=vmpyweuh(Rss32,Rtt32):<<1:sat |
3564 | C Intrinsic Prototype: Word64 Q6_P_vmpyweuh_PP_s1_sat(Word64 Rss, Word64 Rtt) |
3565 | Instruction Type: M |
3566 | Execution Slots: SLOT23 |
3567 | ========================================================================== */ |
3568 | |
3569 | #define Q6_P_vmpyweuh_PP_s1_sat __builtin_HEXAGON_M2_mmpyul_s1 |
3570 | |
3571 | /* ========================================================================== |
3572 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h) |
3573 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) |
3574 | Instruction Type: M |
3575 | Execution Slots: SLOT23 |
3576 | ========================================================================== */ |
3577 | |
3578 | #define Q6_R_mpyacc_RhRh __builtin_HEXAGON_M2_mpy_acc_hh_s0 |
3579 | |
3580 | /* ========================================================================== |
3581 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1 |
3582 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3583 | Instruction Type: M |
3584 | Execution Slots: SLOT23 |
3585 | ========================================================================== */ |
3586 | |
3587 | #define Q6_R_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpy_acc_hh_s1 |
3588 | |
3589 | /* ========================================================================== |
3590 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l) |
3591 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) |
3592 | Instruction Type: M |
3593 | Execution Slots: SLOT23 |
3594 | ========================================================================== */ |
3595 | |
3596 | #define Q6_R_mpyacc_RhRl __builtin_HEXAGON_M2_mpy_acc_hl_s0 |
3597 | |
3598 | /* ========================================================================== |
3599 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1 |
3600 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3601 | Instruction Type: M |
3602 | Execution Slots: SLOT23 |
3603 | ========================================================================== */ |
3604 | |
3605 | #define Q6_R_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpy_acc_hl_s1 |
3606 | |
3607 | /* ========================================================================== |
3608 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h) |
3609 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) |
3610 | Instruction Type: M |
3611 | Execution Slots: SLOT23 |
3612 | ========================================================================== */ |
3613 | |
3614 | #define Q6_R_mpyacc_RlRh __builtin_HEXAGON_M2_mpy_acc_lh_s0 |
3615 | |
3616 | /* ========================================================================== |
3617 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1 |
3618 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3619 | Instruction Type: M |
3620 | Execution Slots: SLOT23 |
3621 | ========================================================================== */ |
3622 | |
3623 | #define Q6_R_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpy_acc_lh_s1 |
3624 | |
3625 | /* ========================================================================== |
3626 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l) |
3627 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) |
3628 | Instruction Type: M |
3629 | Execution Slots: SLOT23 |
3630 | ========================================================================== */ |
3631 | |
3632 | #define Q6_R_mpyacc_RlRl __builtin_HEXAGON_M2_mpy_acc_ll_s0 |
3633 | |
3634 | /* ========================================================================== |
3635 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1 |
3636 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3637 | Instruction Type: M |
3638 | Execution Slots: SLOT23 |
3639 | ========================================================================== */ |
3640 | |
3641 | #define Q6_R_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpy_acc_ll_s1 |
3642 | |
3643 | /* ========================================================================== |
3644 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):sat |
3645 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3646 | Instruction Type: M |
3647 | Execution Slots: SLOT23 |
3648 | ========================================================================== */ |
3649 | |
3650 | #define Q6_R_mpyacc_RhRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s0 |
3651 | |
3652 | /* ========================================================================== |
3653 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.h):<<1:sat |
3654 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3655 | Instruction Type: M |
3656 | Execution Slots: SLOT23 |
3657 | ========================================================================== */ |
3658 | |
3659 | #define Q6_R_mpyacc_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hh_s1 |
3660 | |
3661 | /* ========================================================================== |
3662 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):sat |
3663 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3664 | Instruction Type: M |
3665 | Execution Slots: SLOT23 |
3666 | ========================================================================== */ |
3667 | |
3668 | #define Q6_R_mpyacc_RhRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s0 |
3669 | |
3670 | /* ========================================================================== |
3671 | Assembly Syntax: Rx32+=mpy(Rs32.h,Rt32.l):<<1:sat |
3672 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3673 | Instruction Type: M |
3674 | Execution Slots: SLOT23 |
3675 | ========================================================================== */ |
3676 | |
3677 | #define Q6_R_mpyacc_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_hl_s1 |
3678 | |
3679 | /* ========================================================================== |
3680 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):sat |
3681 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3682 | Instruction Type: M |
3683 | Execution Slots: SLOT23 |
3684 | ========================================================================== */ |
3685 | |
3686 | #define Q6_R_mpyacc_RlRh_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s0 |
3687 | |
3688 | /* ========================================================================== |
3689 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.h):<<1:sat |
3690 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3691 | Instruction Type: M |
3692 | Execution Slots: SLOT23 |
3693 | ========================================================================== */ |
3694 | |
3695 | #define Q6_R_mpyacc_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_lh_s1 |
3696 | |
3697 | /* ========================================================================== |
3698 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):sat |
3699 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3700 | Instruction Type: M |
3701 | Execution Slots: SLOT23 |
3702 | ========================================================================== */ |
3703 | |
3704 | #define Q6_R_mpyacc_RlRl_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s0 |
3705 | |
3706 | /* ========================================================================== |
3707 | Assembly Syntax: Rx32+=mpy(Rs32.l,Rt32.l):<<1:sat |
3708 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3709 | Instruction Type: M |
3710 | Execution Slots: SLOT23 |
3711 | ========================================================================== */ |
3712 | |
3713 | #define Q6_R_mpyacc_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_acc_sat_ll_s1 |
3714 | |
3715 | /* ========================================================================== |
3716 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h) |
3717 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh(Word32 Rs, Word32 Rt) |
3718 | Instruction Type: M |
3719 | Execution Slots: SLOT23 |
3720 | ========================================================================== */ |
3721 | |
3722 | #define Q6_R_mpy_RhRh __builtin_HEXAGON_M2_mpy_hh_s0 |
3723 | |
3724 | /* ========================================================================== |
3725 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1 |
3726 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1(Word32 Rs, Word32 Rt) |
3727 | Instruction Type: M |
3728 | Execution Slots: SLOT23 |
3729 | ========================================================================== */ |
3730 | |
3731 | #define Q6_R_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpy_hh_s1 |
3732 | |
3733 | /* ========================================================================== |
3734 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l) |
3735 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl(Word32 Rs, Word32 Rt) |
3736 | Instruction Type: M |
3737 | Execution Slots: SLOT23 |
3738 | ========================================================================== */ |
3739 | |
3740 | #define Q6_R_mpy_RhRl __builtin_HEXAGON_M2_mpy_hl_s0 |
3741 | |
3742 | /* ========================================================================== |
3743 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1 |
3744 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1(Word32 Rs, Word32 Rt) |
3745 | Instruction Type: M |
3746 | Execution Slots: SLOT23 |
3747 | ========================================================================== */ |
3748 | |
3749 | #define Q6_R_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpy_hl_s1 |
3750 | |
3751 | /* ========================================================================== |
3752 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h) |
3753 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh(Word32 Rs, Word32 Rt) |
3754 | Instruction Type: M |
3755 | Execution Slots: SLOT23 |
3756 | ========================================================================== */ |
3757 | |
3758 | #define Q6_R_mpy_RlRh __builtin_HEXAGON_M2_mpy_lh_s0 |
3759 | |
3760 | /* ========================================================================== |
3761 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1 |
3762 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1(Word32 Rs, Word32 Rt) |
3763 | Instruction Type: M |
3764 | Execution Slots: SLOT23 |
3765 | ========================================================================== */ |
3766 | |
3767 | #define Q6_R_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpy_lh_s1 |
3768 | |
3769 | /* ========================================================================== |
3770 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l) |
3771 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl(Word32 Rs, Word32 Rt) |
3772 | Instruction Type: M |
3773 | Execution Slots: SLOT23 |
3774 | ========================================================================== */ |
3775 | |
3776 | #define Q6_R_mpy_RlRl __builtin_HEXAGON_M2_mpy_ll_s0 |
3777 | |
3778 | /* ========================================================================== |
3779 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1 |
3780 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1(Word32 Rs, Word32 Rt) |
3781 | Instruction Type: M |
3782 | Execution Slots: SLOT23 |
3783 | ========================================================================== */ |
3784 | |
3785 | #define Q6_R_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpy_ll_s1 |
3786 | |
3787 | /* ========================================================================== |
3788 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h) |
3789 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) |
3790 | Instruction Type: M |
3791 | Execution Slots: SLOT23 |
3792 | ========================================================================== */ |
3793 | |
3794 | #define Q6_R_mpynac_RhRh __builtin_HEXAGON_M2_mpy_nac_hh_s0 |
3795 | |
3796 | /* ========================================================================== |
3797 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1 |
3798 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3799 | Instruction Type: M |
3800 | Execution Slots: SLOT23 |
3801 | ========================================================================== */ |
3802 | |
3803 | #define Q6_R_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpy_nac_hh_s1 |
3804 | |
3805 | /* ========================================================================== |
3806 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l) |
3807 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) |
3808 | Instruction Type: M |
3809 | Execution Slots: SLOT23 |
3810 | ========================================================================== */ |
3811 | |
3812 | #define Q6_R_mpynac_RhRl __builtin_HEXAGON_M2_mpy_nac_hl_s0 |
3813 | |
3814 | /* ========================================================================== |
3815 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1 |
3816 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3817 | Instruction Type: M |
3818 | Execution Slots: SLOT23 |
3819 | ========================================================================== */ |
3820 | |
3821 | #define Q6_R_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpy_nac_hl_s1 |
3822 | |
3823 | /* ========================================================================== |
3824 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h) |
3825 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) |
3826 | Instruction Type: M |
3827 | Execution Slots: SLOT23 |
3828 | ========================================================================== */ |
3829 | |
3830 | #define Q6_R_mpynac_RlRh __builtin_HEXAGON_M2_mpy_nac_lh_s0 |
3831 | |
3832 | /* ========================================================================== |
3833 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1 |
3834 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3835 | Instruction Type: M |
3836 | Execution Slots: SLOT23 |
3837 | ========================================================================== */ |
3838 | |
3839 | #define Q6_R_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpy_nac_lh_s1 |
3840 | |
3841 | /* ========================================================================== |
3842 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l) |
3843 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) |
3844 | Instruction Type: M |
3845 | Execution Slots: SLOT23 |
3846 | ========================================================================== */ |
3847 | |
3848 | #define Q6_R_mpynac_RlRl __builtin_HEXAGON_M2_mpy_nac_ll_s0 |
3849 | |
3850 | /* ========================================================================== |
3851 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1 |
3852 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
3853 | Instruction Type: M |
3854 | Execution Slots: SLOT23 |
3855 | ========================================================================== */ |
3856 | |
3857 | #define Q6_R_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpy_nac_ll_s1 |
3858 | |
3859 | /* ========================================================================== |
3860 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):sat |
3861 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3862 | Instruction Type: M |
3863 | Execution Slots: SLOT23 |
3864 | ========================================================================== */ |
3865 | |
3866 | #define Q6_R_mpynac_RhRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s0 |
3867 | |
3868 | /* ========================================================================== |
3869 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.h):<<1:sat |
3870 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3871 | Instruction Type: M |
3872 | Execution Slots: SLOT23 |
3873 | ========================================================================== */ |
3874 | |
3875 | #define Q6_R_mpynac_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hh_s1 |
3876 | |
3877 | /* ========================================================================== |
3878 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):sat |
3879 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3880 | Instruction Type: M |
3881 | Execution Slots: SLOT23 |
3882 | ========================================================================== */ |
3883 | |
3884 | #define Q6_R_mpynac_RhRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s0 |
3885 | |
3886 | /* ========================================================================== |
3887 | Assembly Syntax: Rx32-=mpy(Rs32.h,Rt32.l):<<1:sat |
3888 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RhRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3889 | Instruction Type: M |
3890 | Execution Slots: SLOT23 |
3891 | ========================================================================== */ |
3892 | |
3893 | #define Q6_R_mpynac_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_hl_s1 |
3894 | |
3895 | /* ========================================================================== |
3896 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):sat |
3897 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3898 | Instruction Type: M |
3899 | Execution Slots: SLOT23 |
3900 | ========================================================================== */ |
3901 | |
3902 | #define Q6_R_mpynac_RlRh_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s0 |
3903 | |
3904 | /* ========================================================================== |
3905 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.h):<<1:sat |
3906 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRh_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3907 | Instruction Type: M |
3908 | Execution Slots: SLOT23 |
3909 | ========================================================================== */ |
3910 | |
3911 | #define Q6_R_mpynac_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_lh_s1 |
3912 | |
3913 | /* ========================================================================== |
3914 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):sat |
3915 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3916 | Instruction Type: M |
3917 | Execution Slots: SLOT23 |
3918 | ========================================================================== */ |
3919 | |
3920 | #define Q6_R_mpynac_RlRl_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s0 |
3921 | |
3922 | /* ========================================================================== |
3923 | Assembly Syntax: Rx32-=mpy(Rs32.l,Rt32.l):<<1:sat |
3924 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RlRl_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
3925 | Instruction Type: M |
3926 | Execution Slots: SLOT23 |
3927 | ========================================================================== */ |
3928 | |
3929 | #define Q6_R_mpynac_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_nac_sat_ll_s1 |
3930 | |
3931 | /* ========================================================================== |
3932 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd |
3933 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) |
3934 | Instruction Type: M |
3935 | Execution Slots: SLOT23 |
3936 | ========================================================================== */ |
3937 | |
3938 | #define Q6_R_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s0 |
3939 | |
3940 | /* ========================================================================== |
3941 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd |
3942 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) |
3943 | Instruction Type: M |
3944 | Execution Slots: SLOT23 |
3945 | ========================================================================== */ |
3946 | |
3947 | #define Q6_R_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hh_s1 |
3948 | |
3949 | /* ========================================================================== |
3950 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd |
3951 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) |
3952 | Instruction Type: M |
3953 | Execution Slots: SLOT23 |
3954 | ========================================================================== */ |
3955 | |
3956 | #define Q6_R_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s0 |
3957 | |
3958 | /* ========================================================================== |
3959 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd |
3960 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) |
3961 | Instruction Type: M |
3962 | Execution Slots: SLOT23 |
3963 | ========================================================================== */ |
3964 | |
3965 | #define Q6_R_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_hl_s1 |
3966 | |
3967 | /* ========================================================================== |
3968 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd |
3969 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) |
3970 | Instruction Type: M |
3971 | Execution Slots: SLOT23 |
3972 | ========================================================================== */ |
3973 | |
3974 | #define Q6_R_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s0 |
3975 | |
3976 | /* ========================================================================== |
3977 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd |
3978 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) |
3979 | Instruction Type: M |
3980 | Execution Slots: SLOT23 |
3981 | ========================================================================== */ |
3982 | |
3983 | #define Q6_R_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_lh_s1 |
3984 | |
3985 | /* ========================================================================== |
3986 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd |
3987 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) |
3988 | Instruction Type: M |
3989 | Execution Slots: SLOT23 |
3990 | ========================================================================== */ |
3991 | |
3992 | #define Q6_R_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s0 |
3993 | |
3994 | /* ========================================================================== |
3995 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd |
3996 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) |
3997 | Instruction Type: M |
3998 | Execution Slots: SLOT23 |
3999 | ========================================================================== */ |
4000 | |
4001 | #define Q6_R_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpy_rnd_ll_s1 |
4002 | |
4003 | /* ========================================================================== |
4004 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):sat |
4005 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_sat(Word32 Rs, Word32 Rt) |
4006 | Instruction Type: M |
4007 | Execution Slots: SLOT23 |
4008 | ========================================================================== */ |
4009 | |
4010 | #define Q6_R_mpy_RhRh_sat __builtin_HEXAGON_M2_mpy_sat_hh_s0 |
4011 | |
4012 | /* ========================================================================== |
4013 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:sat |
4014 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_sat(Word32 Rs, Word32 Rt) |
4015 | Instruction Type: M |
4016 | Execution Slots: SLOT23 |
4017 | ========================================================================== */ |
4018 | |
4019 | #define Q6_R_mpy_RhRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_hh_s1 |
4020 | |
4021 | /* ========================================================================== |
4022 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):sat |
4023 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_sat(Word32 Rs, Word32 Rt) |
4024 | Instruction Type: M |
4025 | Execution Slots: SLOT23 |
4026 | ========================================================================== */ |
4027 | |
4028 | #define Q6_R_mpy_RhRl_sat __builtin_HEXAGON_M2_mpy_sat_hl_s0 |
4029 | |
4030 | /* ========================================================================== |
4031 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:sat |
4032 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_sat(Word32 Rs, Word32 Rt) |
4033 | Instruction Type: M |
4034 | Execution Slots: SLOT23 |
4035 | ========================================================================== */ |
4036 | |
4037 | #define Q6_R_mpy_RhRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_hl_s1 |
4038 | |
4039 | /* ========================================================================== |
4040 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):sat |
4041 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_sat(Word32 Rs, Word32 Rt) |
4042 | Instruction Type: M |
4043 | Execution Slots: SLOT23 |
4044 | ========================================================================== */ |
4045 | |
4046 | #define Q6_R_mpy_RlRh_sat __builtin_HEXAGON_M2_mpy_sat_lh_s0 |
4047 | |
4048 | /* ========================================================================== |
4049 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:sat |
4050 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_sat(Word32 Rs, Word32 Rt) |
4051 | Instruction Type: M |
4052 | Execution Slots: SLOT23 |
4053 | ========================================================================== */ |
4054 | |
4055 | #define Q6_R_mpy_RlRh_s1_sat __builtin_HEXAGON_M2_mpy_sat_lh_s1 |
4056 | |
4057 | /* ========================================================================== |
4058 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):sat |
4059 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_sat(Word32 Rs, Word32 Rt) |
4060 | Instruction Type: M |
4061 | Execution Slots: SLOT23 |
4062 | ========================================================================== */ |
4063 | |
4064 | #define Q6_R_mpy_RlRl_sat __builtin_HEXAGON_M2_mpy_sat_ll_s0 |
4065 | |
4066 | /* ========================================================================== |
4067 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:sat |
4068 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_sat(Word32 Rs, Word32 Rt) |
4069 | Instruction Type: M |
4070 | Execution Slots: SLOT23 |
4071 | ========================================================================== */ |
4072 | |
4073 | #define Q6_R_mpy_RlRl_s1_sat __builtin_HEXAGON_M2_mpy_sat_ll_s1 |
4074 | |
4075 | /* ========================================================================== |
4076 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):rnd:sat |
4077 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_rnd_sat(Word32 Rs, Word32 Rt) |
4078 | Instruction Type: M |
4079 | Execution Slots: SLOT23 |
4080 | ========================================================================== */ |
4081 | |
4082 | #define Q6_R_mpy_RhRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0 |
4083 | |
4084 | /* ========================================================================== |
4085 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.h):<<1:rnd:sat |
4086 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRh_s1_rnd_sat(Word32 Rs, Word32 Rt) |
4087 | Instruction Type: M |
4088 | Execution Slots: SLOT23 |
4089 | ========================================================================== */ |
4090 | |
4091 | #define Q6_R_mpy_RhRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1 |
4092 | |
4093 | /* ========================================================================== |
4094 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):rnd:sat |
4095 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_rnd_sat(Word32 Rs, Word32 Rt) |
4096 | Instruction Type: M |
4097 | Execution Slots: SLOT23 |
4098 | ========================================================================== */ |
4099 | |
4100 | #define Q6_R_mpy_RhRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0 |
4101 | |
4102 | /* ========================================================================== |
4103 | Assembly Syntax: Rd32=mpy(Rs32.h,Rt32.l):<<1:rnd:sat |
4104 | C Intrinsic Prototype: Word32 Q6_R_mpy_RhRl_s1_rnd_sat(Word32 Rs, Word32 Rt) |
4105 | Instruction Type: M |
4106 | Execution Slots: SLOT23 |
4107 | ========================================================================== */ |
4108 | |
4109 | #define Q6_R_mpy_RhRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1 |
4110 | |
4111 | /* ========================================================================== |
4112 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):rnd:sat |
4113 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_rnd_sat(Word32 Rs, Word32 Rt) |
4114 | Instruction Type: M |
4115 | Execution Slots: SLOT23 |
4116 | ========================================================================== */ |
4117 | |
4118 | #define Q6_R_mpy_RlRh_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0 |
4119 | |
4120 | /* ========================================================================== |
4121 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.h):<<1:rnd:sat |
4122 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRh_s1_rnd_sat(Word32 Rs, Word32 Rt) |
4123 | Instruction Type: M |
4124 | Execution Slots: SLOT23 |
4125 | ========================================================================== */ |
4126 | |
4127 | #define Q6_R_mpy_RlRh_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1 |
4128 | |
4129 | /* ========================================================================== |
4130 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):rnd:sat |
4131 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_rnd_sat(Word32 Rs, Word32 Rt) |
4132 | Instruction Type: M |
4133 | Execution Slots: SLOT23 |
4134 | ========================================================================== */ |
4135 | |
4136 | #define Q6_R_mpy_RlRl_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0 |
4137 | |
4138 | /* ========================================================================== |
4139 | Assembly Syntax: Rd32=mpy(Rs32.l,Rt32.l):<<1:rnd:sat |
4140 | C Intrinsic Prototype: Word32 Q6_R_mpy_RlRl_s1_rnd_sat(Word32 Rs, Word32 Rt) |
4141 | Instruction Type: M |
4142 | Execution Slots: SLOT23 |
4143 | ========================================================================== */ |
4144 | |
4145 | #define Q6_R_mpy_RlRl_s1_rnd_sat __builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1 |
4146 | |
4147 | /* ========================================================================== |
4148 | Assembly Syntax: Rd32=mpy(Rs32,Rt32) |
4149 | C Intrinsic Prototype: Word32 Q6_R_mpy_RR(Word32 Rs, Word32 Rt) |
4150 | Instruction Type: M |
4151 | Execution Slots: SLOT23 |
4152 | ========================================================================== */ |
4153 | |
4154 | #define Q6_R_mpy_RR __builtin_HEXAGON_M2_mpy_up |
4155 | |
4156 | /* ========================================================================== |
4157 | Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1 |
4158 | C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1(Word32 Rs, Word32 Rt) |
4159 | Instruction Type: M |
4160 | Execution Slots: SLOT23 |
4161 | ========================================================================== */ |
4162 | |
4163 | #define Q6_R_mpy_RR_s1 __builtin_HEXAGON_M2_mpy_up_s1 |
4164 | |
4165 | /* ========================================================================== |
4166 | Assembly Syntax: Rd32=mpy(Rs32,Rt32):<<1:sat |
4167 | C Intrinsic Prototype: Word32 Q6_R_mpy_RR_s1_sat(Word32 Rs, Word32 Rt) |
4168 | Instruction Type: M |
4169 | Execution Slots: SLOT23 |
4170 | ========================================================================== */ |
4171 | |
4172 | #define Q6_R_mpy_RR_s1_sat __builtin_HEXAGON_M2_mpy_up_s1_sat |
4173 | |
4174 | /* ========================================================================== |
4175 | Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h) |
4176 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4177 | Instruction Type: M |
4178 | Execution Slots: SLOT23 |
4179 | ========================================================================== */ |
4180 | |
4181 | #define Q6_P_mpyacc_RhRh __builtin_HEXAGON_M2_mpyd_acc_hh_s0 |
4182 | |
4183 | /* ========================================================================== |
4184 | Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.h):<<1 |
4185 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4186 | Instruction Type: M |
4187 | Execution Slots: SLOT23 |
4188 | ========================================================================== */ |
4189 | |
4190 | #define Q6_P_mpyacc_RhRh_s1 __builtin_HEXAGON_M2_mpyd_acc_hh_s1 |
4191 | |
4192 | /* ========================================================================== |
4193 | Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l) |
4194 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4195 | Instruction Type: M |
4196 | Execution Slots: SLOT23 |
4197 | ========================================================================== */ |
4198 | |
4199 | #define Q6_P_mpyacc_RhRl __builtin_HEXAGON_M2_mpyd_acc_hl_s0 |
4200 | |
4201 | /* ========================================================================== |
4202 | Assembly Syntax: Rxx32+=mpy(Rs32.h,Rt32.l):<<1 |
4203 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4204 | Instruction Type: M |
4205 | Execution Slots: SLOT23 |
4206 | ========================================================================== */ |
4207 | |
4208 | #define Q6_P_mpyacc_RhRl_s1 __builtin_HEXAGON_M2_mpyd_acc_hl_s1 |
4209 | |
4210 | /* ========================================================================== |
4211 | Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h) |
4212 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4213 | Instruction Type: M |
4214 | Execution Slots: SLOT23 |
4215 | ========================================================================== */ |
4216 | |
4217 | #define Q6_P_mpyacc_RlRh __builtin_HEXAGON_M2_mpyd_acc_lh_s0 |
4218 | |
4219 | /* ========================================================================== |
4220 | Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.h):<<1 |
4221 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4222 | Instruction Type: M |
4223 | Execution Slots: SLOT23 |
4224 | ========================================================================== */ |
4225 | |
4226 | #define Q6_P_mpyacc_RlRh_s1 __builtin_HEXAGON_M2_mpyd_acc_lh_s1 |
4227 | |
4228 | /* ========================================================================== |
4229 | Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l) |
4230 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4231 | Instruction Type: M |
4232 | Execution Slots: SLOT23 |
4233 | ========================================================================== */ |
4234 | |
4235 | #define Q6_P_mpyacc_RlRl __builtin_HEXAGON_M2_mpyd_acc_ll_s0 |
4236 | |
4237 | /* ========================================================================== |
4238 | Assembly Syntax: Rxx32+=mpy(Rs32.l,Rt32.l):<<1 |
4239 | C Intrinsic Prototype: Word64 Q6_P_mpyacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4240 | Instruction Type: M |
4241 | Execution Slots: SLOT23 |
4242 | ========================================================================== */ |
4243 | |
4244 | #define Q6_P_mpyacc_RlRl_s1 __builtin_HEXAGON_M2_mpyd_acc_ll_s1 |
4245 | |
4246 | /* ========================================================================== |
4247 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h) |
4248 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh(Word32 Rs, Word32 Rt) |
4249 | Instruction Type: M |
4250 | Execution Slots: SLOT23 |
4251 | ========================================================================== */ |
4252 | |
4253 | #define Q6_P_mpy_RhRh __builtin_HEXAGON_M2_mpyd_hh_s0 |
4254 | |
4255 | /* ========================================================================== |
4256 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1 |
4257 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1(Word32 Rs, Word32 Rt) |
4258 | Instruction Type: M |
4259 | Execution Slots: SLOT23 |
4260 | ========================================================================== */ |
4261 | |
4262 | #define Q6_P_mpy_RhRh_s1 __builtin_HEXAGON_M2_mpyd_hh_s1 |
4263 | |
4264 | /* ========================================================================== |
4265 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l) |
4266 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl(Word32 Rs, Word32 Rt) |
4267 | Instruction Type: M |
4268 | Execution Slots: SLOT23 |
4269 | ========================================================================== */ |
4270 | |
4271 | #define Q6_P_mpy_RhRl __builtin_HEXAGON_M2_mpyd_hl_s0 |
4272 | |
4273 | /* ========================================================================== |
4274 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1 |
4275 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1(Word32 Rs, Word32 Rt) |
4276 | Instruction Type: M |
4277 | Execution Slots: SLOT23 |
4278 | ========================================================================== */ |
4279 | |
4280 | #define Q6_P_mpy_RhRl_s1 __builtin_HEXAGON_M2_mpyd_hl_s1 |
4281 | |
4282 | /* ========================================================================== |
4283 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h) |
4284 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh(Word32 Rs, Word32 Rt) |
4285 | Instruction Type: M |
4286 | Execution Slots: SLOT23 |
4287 | ========================================================================== */ |
4288 | |
4289 | #define Q6_P_mpy_RlRh __builtin_HEXAGON_M2_mpyd_lh_s0 |
4290 | |
4291 | /* ========================================================================== |
4292 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1 |
4293 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1(Word32 Rs, Word32 Rt) |
4294 | Instruction Type: M |
4295 | Execution Slots: SLOT23 |
4296 | ========================================================================== */ |
4297 | |
4298 | #define Q6_P_mpy_RlRh_s1 __builtin_HEXAGON_M2_mpyd_lh_s1 |
4299 | |
4300 | /* ========================================================================== |
4301 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l) |
4302 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl(Word32 Rs, Word32 Rt) |
4303 | Instruction Type: M |
4304 | Execution Slots: SLOT23 |
4305 | ========================================================================== */ |
4306 | |
4307 | #define Q6_P_mpy_RlRl __builtin_HEXAGON_M2_mpyd_ll_s0 |
4308 | |
4309 | /* ========================================================================== |
4310 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1 |
4311 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1(Word32 Rs, Word32 Rt) |
4312 | Instruction Type: M |
4313 | Execution Slots: SLOT23 |
4314 | ========================================================================== */ |
4315 | |
4316 | #define Q6_P_mpy_RlRl_s1 __builtin_HEXAGON_M2_mpyd_ll_s1 |
4317 | |
4318 | /* ========================================================================== |
4319 | Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h) |
4320 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4321 | Instruction Type: M |
4322 | Execution Slots: SLOT23 |
4323 | ========================================================================== */ |
4324 | |
4325 | #define Q6_P_mpynac_RhRh __builtin_HEXAGON_M2_mpyd_nac_hh_s0 |
4326 | |
4327 | /* ========================================================================== |
4328 | Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.h):<<1 |
4329 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4330 | Instruction Type: M |
4331 | Execution Slots: SLOT23 |
4332 | ========================================================================== */ |
4333 | |
4334 | #define Q6_P_mpynac_RhRh_s1 __builtin_HEXAGON_M2_mpyd_nac_hh_s1 |
4335 | |
4336 | /* ========================================================================== |
4337 | Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l) |
4338 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4339 | Instruction Type: M |
4340 | Execution Slots: SLOT23 |
4341 | ========================================================================== */ |
4342 | |
4343 | #define Q6_P_mpynac_RhRl __builtin_HEXAGON_M2_mpyd_nac_hl_s0 |
4344 | |
4345 | /* ========================================================================== |
4346 | Assembly Syntax: Rxx32-=mpy(Rs32.h,Rt32.l):<<1 |
4347 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4348 | Instruction Type: M |
4349 | Execution Slots: SLOT23 |
4350 | ========================================================================== */ |
4351 | |
4352 | #define Q6_P_mpynac_RhRl_s1 __builtin_HEXAGON_M2_mpyd_nac_hl_s1 |
4353 | |
4354 | /* ========================================================================== |
4355 | Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h) |
4356 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4357 | Instruction Type: M |
4358 | Execution Slots: SLOT23 |
4359 | ========================================================================== */ |
4360 | |
4361 | #define Q6_P_mpynac_RlRh __builtin_HEXAGON_M2_mpyd_nac_lh_s0 |
4362 | |
4363 | /* ========================================================================== |
4364 | Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.h):<<1 |
4365 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4366 | Instruction Type: M |
4367 | Execution Slots: SLOT23 |
4368 | ========================================================================== */ |
4369 | |
4370 | #define Q6_P_mpynac_RlRh_s1 __builtin_HEXAGON_M2_mpyd_nac_lh_s1 |
4371 | |
4372 | /* ========================================================================== |
4373 | Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l) |
4374 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4375 | Instruction Type: M |
4376 | Execution Slots: SLOT23 |
4377 | ========================================================================== */ |
4378 | |
4379 | #define Q6_P_mpynac_RlRl __builtin_HEXAGON_M2_mpyd_nac_ll_s0 |
4380 | |
4381 | /* ========================================================================== |
4382 | Assembly Syntax: Rxx32-=mpy(Rs32.l,Rt32.l):<<1 |
4383 | C Intrinsic Prototype: Word64 Q6_P_mpynac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4384 | Instruction Type: M |
4385 | Execution Slots: SLOT23 |
4386 | ========================================================================== */ |
4387 | |
4388 | #define Q6_P_mpynac_RlRl_s1 __builtin_HEXAGON_M2_mpyd_nac_ll_s1 |
4389 | |
4390 | /* ========================================================================== |
4391 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):rnd |
4392 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_rnd(Word32 Rs, Word32 Rt) |
4393 | Instruction Type: M |
4394 | Execution Slots: SLOT23 |
4395 | ========================================================================== */ |
4396 | |
4397 | #define Q6_P_mpy_RhRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s0 |
4398 | |
4399 | /* ========================================================================== |
4400 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.h):<<1:rnd |
4401 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRh_s1_rnd(Word32 Rs, Word32 Rt) |
4402 | Instruction Type: M |
4403 | Execution Slots: SLOT23 |
4404 | ========================================================================== */ |
4405 | |
4406 | #define Q6_P_mpy_RhRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hh_s1 |
4407 | |
4408 | /* ========================================================================== |
4409 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):rnd |
4410 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_rnd(Word32 Rs, Word32 Rt) |
4411 | Instruction Type: M |
4412 | Execution Slots: SLOT23 |
4413 | ========================================================================== */ |
4414 | |
4415 | #define Q6_P_mpy_RhRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s0 |
4416 | |
4417 | /* ========================================================================== |
4418 | Assembly Syntax: Rdd32=mpy(Rs32.h,Rt32.l):<<1:rnd |
4419 | C Intrinsic Prototype: Word64 Q6_P_mpy_RhRl_s1_rnd(Word32 Rs, Word32 Rt) |
4420 | Instruction Type: M |
4421 | Execution Slots: SLOT23 |
4422 | ========================================================================== */ |
4423 | |
4424 | #define Q6_P_mpy_RhRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_hl_s1 |
4425 | |
4426 | /* ========================================================================== |
4427 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):rnd |
4428 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_rnd(Word32 Rs, Word32 Rt) |
4429 | Instruction Type: M |
4430 | Execution Slots: SLOT23 |
4431 | ========================================================================== */ |
4432 | |
4433 | #define Q6_P_mpy_RlRh_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s0 |
4434 | |
4435 | /* ========================================================================== |
4436 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.h):<<1:rnd |
4437 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRh_s1_rnd(Word32 Rs, Word32 Rt) |
4438 | Instruction Type: M |
4439 | Execution Slots: SLOT23 |
4440 | ========================================================================== */ |
4441 | |
4442 | #define Q6_P_mpy_RlRh_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_lh_s1 |
4443 | |
4444 | /* ========================================================================== |
4445 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):rnd |
4446 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_rnd(Word32 Rs, Word32 Rt) |
4447 | Instruction Type: M |
4448 | Execution Slots: SLOT23 |
4449 | ========================================================================== */ |
4450 | |
4451 | #define Q6_P_mpy_RlRl_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s0 |
4452 | |
4453 | /* ========================================================================== |
4454 | Assembly Syntax: Rdd32=mpy(Rs32.l,Rt32.l):<<1:rnd |
4455 | C Intrinsic Prototype: Word64 Q6_P_mpy_RlRl_s1_rnd(Word32 Rs, Word32 Rt) |
4456 | Instruction Type: M |
4457 | Execution Slots: SLOT23 |
4458 | ========================================================================== */ |
4459 | |
4460 | #define Q6_P_mpy_RlRl_s1_rnd __builtin_HEXAGON_M2_mpyd_rnd_ll_s1 |
4461 | |
4462 | /* ========================================================================== |
4463 | Assembly Syntax: Rd32=mpyi(Rs32,Rt32) |
4464 | C Intrinsic Prototype: Word32 Q6_R_mpyi_RR(Word32 Rs, Word32 Rt) |
4465 | Instruction Type: M |
4466 | Execution Slots: SLOT23 |
4467 | ========================================================================== */ |
4468 | |
4469 | #define Q6_R_mpyi_RR __builtin_HEXAGON_M2_mpyi |
4470 | |
4471 | /* ========================================================================== |
4472 | Assembly Syntax: Rd32=mpyi(Rs32,#m9) |
4473 | C Intrinsic Prototype: Word32 Q6_R_mpyi_RI(Word32 Rs, Word32 Im9) |
4474 | Instruction Type: M |
4475 | Execution Slots: SLOT0123 |
4476 | ========================================================================== */ |
4477 | |
4478 | #define Q6_R_mpyi_RI __builtin_HEXAGON_M2_mpysmi |
4479 | |
4480 | /* ========================================================================== |
4481 | Assembly Syntax: Rd32=mpysu(Rs32,Rt32) |
4482 | C Intrinsic Prototype: Word32 Q6_R_mpysu_RR(Word32 Rs, Word32 Rt) |
4483 | Instruction Type: M |
4484 | Execution Slots: SLOT23 |
4485 | ========================================================================== */ |
4486 | |
4487 | #define Q6_R_mpysu_RR __builtin_HEXAGON_M2_mpysu_up |
4488 | |
4489 | /* ========================================================================== |
4490 | Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h) |
4491 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) |
4492 | Instruction Type: M |
4493 | Execution Slots: SLOT23 |
4494 | ========================================================================== */ |
4495 | |
4496 | #define Q6_R_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyu_acc_hh_s0 |
4497 | |
4498 | /* ========================================================================== |
4499 | Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.h):<<1 |
4500 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4501 | Instruction Type: M |
4502 | Execution Slots: SLOT23 |
4503 | ========================================================================== */ |
4504 | |
4505 | #define Q6_R_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyu_acc_hh_s1 |
4506 | |
4507 | /* ========================================================================== |
4508 | Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l) |
4509 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) |
4510 | Instruction Type: M |
4511 | Execution Slots: SLOT23 |
4512 | ========================================================================== */ |
4513 | |
4514 | #define Q6_R_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyu_acc_hl_s0 |
4515 | |
4516 | /* ========================================================================== |
4517 | Assembly Syntax: Rx32+=mpyu(Rs32.h,Rt32.l):<<1 |
4518 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4519 | Instruction Type: M |
4520 | Execution Slots: SLOT23 |
4521 | ========================================================================== */ |
4522 | |
4523 | #define Q6_R_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyu_acc_hl_s1 |
4524 | |
4525 | /* ========================================================================== |
4526 | Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h) |
4527 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) |
4528 | Instruction Type: M |
4529 | Execution Slots: SLOT23 |
4530 | ========================================================================== */ |
4531 | |
4532 | #define Q6_R_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyu_acc_lh_s0 |
4533 | |
4534 | /* ========================================================================== |
4535 | Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.h):<<1 |
4536 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4537 | Instruction Type: M |
4538 | Execution Slots: SLOT23 |
4539 | ========================================================================== */ |
4540 | |
4541 | #define Q6_R_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyu_acc_lh_s1 |
4542 | |
4543 | /* ========================================================================== |
4544 | Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l) |
4545 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) |
4546 | Instruction Type: M |
4547 | Execution Slots: SLOT23 |
4548 | ========================================================================== */ |
4549 | |
4550 | #define Q6_R_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyu_acc_ll_s0 |
4551 | |
4552 | /* ========================================================================== |
4553 | Assembly Syntax: Rx32+=mpyu(Rs32.l,Rt32.l):<<1 |
4554 | C Intrinsic Prototype: Word32 Q6_R_mpyuacc_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4555 | Instruction Type: M |
4556 | Execution Slots: SLOT23 |
4557 | ========================================================================== */ |
4558 | |
4559 | #define Q6_R_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyu_acc_ll_s1 |
4560 | |
4561 | /* ========================================================================== |
4562 | Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h) |
4563 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh(Word32 Rs, Word32 Rt) |
4564 | Instruction Type: M |
4565 | Execution Slots: SLOT23 |
4566 | ========================================================================== */ |
4567 | |
4568 | #define Q6_R_mpyu_RhRh __builtin_HEXAGON_M2_mpyu_hh_s0 |
4569 | |
4570 | /* ========================================================================== |
4571 | Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.h):<<1 |
4572 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) |
4573 | Instruction Type: M |
4574 | Execution Slots: SLOT23 |
4575 | ========================================================================== */ |
4576 | |
4577 | #define Q6_R_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyu_hh_s1 |
4578 | |
4579 | /* ========================================================================== |
4580 | Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l) |
4581 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl(Word32 Rs, Word32 Rt) |
4582 | Instruction Type: M |
4583 | Execution Slots: SLOT23 |
4584 | ========================================================================== */ |
4585 | |
4586 | #define Q6_R_mpyu_RhRl __builtin_HEXAGON_M2_mpyu_hl_s0 |
4587 | |
4588 | /* ========================================================================== |
4589 | Assembly Syntax: Rd32=mpyu(Rs32.h,Rt32.l):<<1 |
4590 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) |
4591 | Instruction Type: M |
4592 | Execution Slots: SLOT23 |
4593 | ========================================================================== */ |
4594 | |
4595 | #define Q6_R_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyu_hl_s1 |
4596 | |
4597 | /* ========================================================================== |
4598 | Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h) |
4599 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh(Word32 Rs, Word32 Rt) |
4600 | Instruction Type: M |
4601 | Execution Slots: SLOT23 |
4602 | ========================================================================== */ |
4603 | |
4604 | #define Q6_R_mpyu_RlRh __builtin_HEXAGON_M2_mpyu_lh_s0 |
4605 | |
4606 | /* ========================================================================== |
4607 | Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.h):<<1 |
4608 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) |
4609 | Instruction Type: M |
4610 | Execution Slots: SLOT23 |
4611 | ========================================================================== */ |
4612 | |
4613 | #define Q6_R_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyu_lh_s1 |
4614 | |
4615 | /* ========================================================================== |
4616 | Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l) |
4617 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl(Word32 Rs, Word32 Rt) |
4618 | Instruction Type: M |
4619 | Execution Slots: SLOT23 |
4620 | ========================================================================== */ |
4621 | |
4622 | #define Q6_R_mpyu_RlRl __builtin_HEXAGON_M2_mpyu_ll_s0 |
4623 | |
4624 | /* ========================================================================== |
4625 | Assembly Syntax: Rd32=mpyu(Rs32.l,Rt32.l):<<1 |
4626 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) |
4627 | Instruction Type: M |
4628 | Execution Slots: SLOT23 |
4629 | ========================================================================== */ |
4630 | |
4631 | #define Q6_R_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyu_ll_s1 |
4632 | |
4633 | /* ========================================================================== |
4634 | Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h) |
4635 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh(Word32 Rx, Word32 Rs, Word32 Rt) |
4636 | Instruction Type: M |
4637 | Execution Slots: SLOT23 |
4638 | ========================================================================== */ |
4639 | |
4640 | #define Q6_R_mpyunac_RhRh __builtin_HEXAGON_M2_mpyu_nac_hh_s0 |
4641 | |
4642 | /* ========================================================================== |
4643 | Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.h):<<1 |
4644 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4645 | Instruction Type: M |
4646 | Execution Slots: SLOT23 |
4647 | ========================================================================== */ |
4648 | |
4649 | #define Q6_R_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyu_nac_hh_s1 |
4650 | |
4651 | /* ========================================================================== |
4652 | Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l) |
4653 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl(Word32 Rx, Word32 Rs, Word32 Rt) |
4654 | Instruction Type: M |
4655 | Execution Slots: SLOT23 |
4656 | ========================================================================== */ |
4657 | |
4658 | #define Q6_R_mpyunac_RhRl __builtin_HEXAGON_M2_mpyu_nac_hl_s0 |
4659 | |
4660 | /* ========================================================================== |
4661 | Assembly Syntax: Rx32-=mpyu(Rs32.h,Rt32.l):<<1 |
4662 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RhRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4663 | Instruction Type: M |
4664 | Execution Slots: SLOT23 |
4665 | ========================================================================== */ |
4666 | |
4667 | #define Q6_R_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyu_nac_hl_s1 |
4668 | |
4669 | /* ========================================================================== |
4670 | Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h) |
4671 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh(Word32 Rx, Word32 Rs, Word32 Rt) |
4672 | Instruction Type: M |
4673 | Execution Slots: SLOT23 |
4674 | ========================================================================== */ |
4675 | |
4676 | #define Q6_R_mpyunac_RlRh __builtin_HEXAGON_M2_mpyu_nac_lh_s0 |
4677 | |
4678 | /* ========================================================================== |
4679 | Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.h):<<1 |
4680 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRh_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4681 | Instruction Type: M |
4682 | Execution Slots: SLOT23 |
4683 | ========================================================================== */ |
4684 | |
4685 | #define Q6_R_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyu_nac_lh_s1 |
4686 | |
4687 | /* ========================================================================== |
4688 | Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l) |
4689 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl(Word32 Rx, Word32 Rs, Word32 Rt) |
4690 | Instruction Type: M |
4691 | Execution Slots: SLOT23 |
4692 | ========================================================================== */ |
4693 | |
4694 | #define Q6_R_mpyunac_RlRl __builtin_HEXAGON_M2_mpyu_nac_ll_s0 |
4695 | |
4696 | /* ========================================================================== |
4697 | Assembly Syntax: Rx32-=mpyu(Rs32.l,Rt32.l):<<1 |
4698 | C Intrinsic Prototype: Word32 Q6_R_mpyunac_RlRl_s1(Word32 Rx, Word32 Rs, Word32 Rt) |
4699 | Instruction Type: M |
4700 | Execution Slots: SLOT23 |
4701 | ========================================================================== */ |
4702 | |
4703 | #define Q6_R_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyu_nac_ll_s1 |
4704 | |
4705 | /* ========================================================================== |
4706 | Assembly Syntax: Rd32=mpyu(Rs32,Rt32) |
4707 | C Intrinsic Prototype: UWord32 Q6_R_mpyu_RR(Word32 Rs, Word32 Rt) |
4708 | Instruction Type: M |
4709 | Execution Slots: SLOT23 |
4710 | ========================================================================== */ |
4711 | |
4712 | #define Q6_R_mpyu_RR __builtin_HEXAGON_M2_mpyu_up |
4713 | |
4714 | /* ========================================================================== |
4715 | Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h) |
4716 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4717 | Instruction Type: M |
4718 | Execution Slots: SLOT23 |
4719 | ========================================================================== */ |
4720 | |
4721 | #define Q6_P_mpyuacc_RhRh __builtin_HEXAGON_M2_mpyud_acc_hh_s0 |
4722 | |
4723 | /* ========================================================================== |
4724 | Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.h):<<1 |
4725 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4726 | Instruction Type: M |
4727 | Execution Slots: SLOT23 |
4728 | ========================================================================== */ |
4729 | |
4730 | #define Q6_P_mpyuacc_RhRh_s1 __builtin_HEXAGON_M2_mpyud_acc_hh_s1 |
4731 | |
4732 | /* ========================================================================== |
4733 | Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l) |
4734 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4735 | Instruction Type: M |
4736 | Execution Slots: SLOT23 |
4737 | ========================================================================== */ |
4738 | |
4739 | #define Q6_P_mpyuacc_RhRl __builtin_HEXAGON_M2_mpyud_acc_hl_s0 |
4740 | |
4741 | /* ========================================================================== |
4742 | Assembly Syntax: Rxx32+=mpyu(Rs32.h,Rt32.l):<<1 |
4743 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4744 | Instruction Type: M |
4745 | Execution Slots: SLOT23 |
4746 | ========================================================================== */ |
4747 | |
4748 | #define Q6_P_mpyuacc_RhRl_s1 __builtin_HEXAGON_M2_mpyud_acc_hl_s1 |
4749 | |
4750 | /* ========================================================================== |
4751 | Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h) |
4752 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4753 | Instruction Type: M |
4754 | Execution Slots: SLOT23 |
4755 | ========================================================================== */ |
4756 | |
4757 | #define Q6_P_mpyuacc_RlRh __builtin_HEXAGON_M2_mpyud_acc_lh_s0 |
4758 | |
4759 | /* ========================================================================== |
4760 | Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.h):<<1 |
4761 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4762 | Instruction Type: M |
4763 | Execution Slots: SLOT23 |
4764 | ========================================================================== */ |
4765 | |
4766 | #define Q6_P_mpyuacc_RlRh_s1 __builtin_HEXAGON_M2_mpyud_acc_lh_s1 |
4767 | |
4768 | /* ========================================================================== |
4769 | Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l) |
4770 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4771 | Instruction Type: M |
4772 | Execution Slots: SLOT23 |
4773 | ========================================================================== */ |
4774 | |
4775 | #define Q6_P_mpyuacc_RlRl __builtin_HEXAGON_M2_mpyud_acc_ll_s0 |
4776 | |
4777 | /* ========================================================================== |
4778 | Assembly Syntax: Rxx32+=mpyu(Rs32.l,Rt32.l):<<1 |
4779 | C Intrinsic Prototype: Word64 Q6_P_mpyuacc_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4780 | Instruction Type: M |
4781 | Execution Slots: SLOT23 |
4782 | ========================================================================== */ |
4783 | |
4784 | #define Q6_P_mpyuacc_RlRl_s1 __builtin_HEXAGON_M2_mpyud_acc_ll_s1 |
4785 | |
4786 | /* ========================================================================== |
4787 | Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h) |
4788 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh(Word32 Rs, Word32 Rt) |
4789 | Instruction Type: M |
4790 | Execution Slots: SLOT23 |
4791 | ========================================================================== */ |
4792 | |
4793 | #define Q6_P_mpyu_RhRh __builtin_HEXAGON_M2_mpyud_hh_s0 |
4794 | |
4795 | /* ========================================================================== |
4796 | Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.h):<<1 |
4797 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRh_s1(Word32 Rs, Word32 Rt) |
4798 | Instruction Type: M |
4799 | Execution Slots: SLOT23 |
4800 | ========================================================================== */ |
4801 | |
4802 | #define Q6_P_mpyu_RhRh_s1 __builtin_HEXAGON_M2_mpyud_hh_s1 |
4803 | |
4804 | /* ========================================================================== |
4805 | Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l) |
4806 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl(Word32 Rs, Word32 Rt) |
4807 | Instruction Type: M |
4808 | Execution Slots: SLOT23 |
4809 | ========================================================================== */ |
4810 | |
4811 | #define Q6_P_mpyu_RhRl __builtin_HEXAGON_M2_mpyud_hl_s0 |
4812 | |
4813 | /* ========================================================================== |
4814 | Assembly Syntax: Rdd32=mpyu(Rs32.h,Rt32.l):<<1 |
4815 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RhRl_s1(Word32 Rs, Word32 Rt) |
4816 | Instruction Type: M |
4817 | Execution Slots: SLOT23 |
4818 | ========================================================================== */ |
4819 | |
4820 | #define Q6_P_mpyu_RhRl_s1 __builtin_HEXAGON_M2_mpyud_hl_s1 |
4821 | |
4822 | /* ========================================================================== |
4823 | Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h) |
4824 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh(Word32 Rs, Word32 Rt) |
4825 | Instruction Type: M |
4826 | Execution Slots: SLOT23 |
4827 | ========================================================================== */ |
4828 | |
4829 | #define Q6_P_mpyu_RlRh __builtin_HEXAGON_M2_mpyud_lh_s0 |
4830 | |
4831 | /* ========================================================================== |
4832 | Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.h):<<1 |
4833 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRh_s1(Word32 Rs, Word32 Rt) |
4834 | Instruction Type: M |
4835 | Execution Slots: SLOT23 |
4836 | ========================================================================== */ |
4837 | |
4838 | #define Q6_P_mpyu_RlRh_s1 __builtin_HEXAGON_M2_mpyud_lh_s1 |
4839 | |
4840 | /* ========================================================================== |
4841 | Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l) |
4842 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl(Word32 Rs, Word32 Rt) |
4843 | Instruction Type: M |
4844 | Execution Slots: SLOT23 |
4845 | ========================================================================== */ |
4846 | |
4847 | #define Q6_P_mpyu_RlRl __builtin_HEXAGON_M2_mpyud_ll_s0 |
4848 | |
4849 | /* ========================================================================== |
4850 | Assembly Syntax: Rdd32=mpyu(Rs32.l,Rt32.l):<<1 |
4851 | C Intrinsic Prototype: UWord64 Q6_P_mpyu_RlRl_s1(Word32 Rs, Word32 Rt) |
4852 | Instruction Type: M |
4853 | Execution Slots: SLOT23 |
4854 | ========================================================================== */ |
4855 | |
4856 | #define Q6_P_mpyu_RlRl_s1 __builtin_HEXAGON_M2_mpyud_ll_s1 |
4857 | |
4858 | /* ========================================================================== |
4859 | Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h) |
4860 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4861 | Instruction Type: M |
4862 | Execution Slots: SLOT23 |
4863 | ========================================================================== */ |
4864 | |
4865 | #define Q6_P_mpyunac_RhRh __builtin_HEXAGON_M2_mpyud_nac_hh_s0 |
4866 | |
4867 | /* ========================================================================== |
4868 | Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.h):<<1 |
4869 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4870 | Instruction Type: M |
4871 | Execution Slots: SLOT23 |
4872 | ========================================================================== */ |
4873 | |
4874 | #define Q6_P_mpyunac_RhRh_s1 __builtin_HEXAGON_M2_mpyud_nac_hh_s1 |
4875 | |
4876 | /* ========================================================================== |
4877 | Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l) |
4878 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4879 | Instruction Type: M |
4880 | Execution Slots: SLOT23 |
4881 | ========================================================================== */ |
4882 | |
4883 | #define Q6_P_mpyunac_RhRl __builtin_HEXAGON_M2_mpyud_nac_hl_s0 |
4884 | |
4885 | /* ========================================================================== |
4886 | Assembly Syntax: Rxx32-=mpyu(Rs32.h,Rt32.l):<<1 |
4887 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RhRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4888 | Instruction Type: M |
4889 | Execution Slots: SLOT23 |
4890 | ========================================================================== */ |
4891 | |
4892 | #define Q6_P_mpyunac_RhRl_s1 __builtin_HEXAGON_M2_mpyud_nac_hl_s1 |
4893 | |
4894 | /* ========================================================================== |
4895 | Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h) |
4896 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh(Word64 Rxx, Word32 Rs, Word32 Rt) |
4897 | Instruction Type: M |
4898 | Execution Slots: SLOT23 |
4899 | ========================================================================== */ |
4900 | |
4901 | #define Q6_P_mpyunac_RlRh __builtin_HEXAGON_M2_mpyud_nac_lh_s0 |
4902 | |
4903 | /* ========================================================================== |
4904 | Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.h):<<1 |
4905 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRh_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4906 | Instruction Type: M |
4907 | Execution Slots: SLOT23 |
4908 | ========================================================================== */ |
4909 | |
4910 | #define Q6_P_mpyunac_RlRh_s1 __builtin_HEXAGON_M2_mpyud_nac_lh_s1 |
4911 | |
4912 | /* ========================================================================== |
4913 | Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l) |
4914 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl(Word64 Rxx, Word32 Rs, Word32 Rt) |
4915 | Instruction Type: M |
4916 | Execution Slots: SLOT23 |
4917 | ========================================================================== */ |
4918 | |
4919 | #define Q6_P_mpyunac_RlRl __builtin_HEXAGON_M2_mpyud_nac_ll_s0 |
4920 | |
4921 | /* ========================================================================== |
4922 | Assembly Syntax: Rxx32-=mpyu(Rs32.l,Rt32.l):<<1 |
4923 | C Intrinsic Prototype: Word64 Q6_P_mpyunac_RlRl_s1(Word64 Rxx, Word32 Rs, Word32 Rt) |
4924 | Instruction Type: M |
4925 | Execution Slots: SLOT23 |
4926 | ========================================================================== */ |
4927 | |
4928 | #define Q6_P_mpyunac_RlRl_s1 __builtin_HEXAGON_M2_mpyud_nac_ll_s1 |
4929 | |
4930 | /* ========================================================================== |
4931 | Assembly Syntax: Rd32=mpyui(Rs32,Rt32) |
4932 | C Intrinsic Prototype: Word32 Q6_R_mpyui_RR(Word32 Rs, Word32 Rt) |
4933 | Instruction Type: M |
4934 | Execution Slots: SLOT0123 |
4935 | ========================================================================== */ |
4936 | |
4937 | #define Q6_R_mpyui_RR __builtin_HEXAGON_M2_mpyui |
4938 | |
4939 | /* ========================================================================== |
4940 | Assembly Syntax: Rx32-=add(Rs32,Rt32) |
4941 | C Intrinsic Prototype: Word32 Q6_R_addnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
4942 | Instruction Type: M |
4943 | Execution Slots: SLOT23 |
4944 | ========================================================================== */ |
4945 | |
4946 | #define Q6_R_addnac_RR __builtin_HEXAGON_M2_nacci |
4947 | |
4948 | /* ========================================================================== |
4949 | Assembly Syntax: Rx32-=add(Rs32,#s8) |
4950 | C Intrinsic Prototype: Word32 Q6_R_addnac_RI(Word32 Rx, Word32 Rs, Word32 Is8) |
4951 | Instruction Type: M |
4952 | Execution Slots: SLOT23 |
4953 | ========================================================================== */ |
4954 | |
4955 | #define Q6_R_addnac_RI __builtin_HEXAGON_M2_naccii |
4956 | |
4957 | /* ========================================================================== |
4958 | Assembly Syntax: Rx32+=sub(Rt32,Rs32) |
4959 | C Intrinsic Prototype: Word32 Q6_R_subacc_RR(Word32 Rx, Word32 Rt, Word32 Rs) |
4960 | Instruction Type: M |
4961 | Execution Slots: SLOT23 |
4962 | ========================================================================== */ |
4963 | |
4964 | #define Q6_R_subacc_RR __builtin_HEXAGON_M2_subacc |
4965 | |
4966 | /* ========================================================================== |
4967 | Assembly Syntax: Rdd32=vabsdiffh(Rtt32,Rss32) |
4968 | C Intrinsic Prototype: Word64 Q6_P_vabsdiffh_PP(Word64 Rtt, Word64 Rss) |
4969 | Instruction Type: M |
4970 | Execution Slots: SLOT23 |
4971 | ========================================================================== */ |
4972 | |
4973 | #define Q6_P_vabsdiffh_PP __builtin_HEXAGON_M2_vabsdiffh |
4974 | |
4975 | /* ========================================================================== |
4976 | Assembly Syntax: Rdd32=vabsdiffw(Rtt32,Rss32) |
4977 | C Intrinsic Prototype: Word64 Q6_P_vabsdiffw_PP(Word64 Rtt, Word64 Rss) |
4978 | Instruction Type: M |
4979 | Execution Slots: SLOT23 |
4980 | ========================================================================== */ |
4981 | |
4982 | #define Q6_P_vabsdiffw_PP __builtin_HEXAGON_M2_vabsdiffw |
4983 | |
4984 | /* ========================================================================== |
4985 | Assembly Syntax: Rxx32+=vcmpyi(Rss32,Rtt32):sat |
4986 | C Intrinsic Prototype: Word64 Q6_P_vcmpyiacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
4987 | Instruction Type: M |
4988 | Execution Slots: SLOT23 |
4989 | ========================================================================== */ |
4990 | |
4991 | #define Q6_P_vcmpyiacc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_i |
4992 | |
4993 | /* ========================================================================== |
4994 | Assembly Syntax: Rxx32+=vcmpyr(Rss32,Rtt32):sat |
4995 | C Intrinsic Prototype: Word64 Q6_P_vcmpyracc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
4996 | Instruction Type: M |
4997 | Execution Slots: SLOT23 |
4998 | ========================================================================== */ |
4999 | |
5000 | #define Q6_P_vcmpyracc_PP_sat __builtin_HEXAGON_M2_vcmac_s0_sat_r |
5001 | |
5002 | /* ========================================================================== |
5003 | Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):sat |
5004 | C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_sat(Word64 Rss, Word64 Rtt) |
5005 | Instruction Type: M |
5006 | Execution Slots: SLOT23 |
5007 | ========================================================================== */ |
5008 | |
5009 | #define Q6_P_vcmpyi_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_i |
5010 | |
5011 | /* ========================================================================== |
5012 | Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):sat |
5013 | C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_sat(Word64 Rss, Word64 Rtt) |
5014 | Instruction Type: M |
5015 | Execution Slots: SLOT23 |
5016 | ========================================================================== */ |
5017 | |
5018 | #define Q6_P_vcmpyr_PP_sat __builtin_HEXAGON_M2_vcmpy_s0_sat_r |
5019 | |
5020 | /* ========================================================================== |
5021 | Assembly Syntax: Rdd32=vcmpyi(Rss32,Rtt32):<<1:sat |
5022 | C Intrinsic Prototype: Word64 Q6_P_vcmpyi_PP_s1_sat(Word64 Rss, Word64 Rtt) |
5023 | Instruction Type: M |
5024 | Execution Slots: SLOT23 |
5025 | ========================================================================== */ |
5026 | |
5027 | #define Q6_P_vcmpyi_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_i |
5028 | |
5029 | /* ========================================================================== |
5030 | Assembly Syntax: Rdd32=vcmpyr(Rss32,Rtt32):<<1:sat |
5031 | C Intrinsic Prototype: Word64 Q6_P_vcmpyr_PP_s1_sat(Word64 Rss, Word64 Rtt) |
5032 | Instruction Type: M |
5033 | Execution Slots: SLOT23 |
5034 | ========================================================================== */ |
5035 | |
5036 | #define Q6_P_vcmpyr_PP_s1_sat __builtin_HEXAGON_M2_vcmpy_s1_sat_r |
5037 | |
5038 | /* ========================================================================== |
5039 | Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):sat |
5040 | C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5041 | Instruction Type: M |
5042 | Execution Slots: SLOT23 |
5043 | ========================================================================== */ |
5044 | |
5045 | #define Q6_P_vdmpyacc_PP_sat __builtin_HEXAGON_M2_vdmacs_s0 |
5046 | |
5047 | /* ========================================================================== |
5048 | Assembly Syntax: Rxx32+=vdmpy(Rss32,Rtt32):<<1:sat |
5049 | C Intrinsic Prototype: Word64 Q6_P_vdmpyacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5050 | Instruction Type: M |
5051 | Execution Slots: SLOT23 |
5052 | ========================================================================== */ |
5053 | |
5054 | #define Q6_P_vdmpyacc_PP_s1_sat __builtin_HEXAGON_M2_vdmacs_s1 |
5055 | |
5056 | /* ========================================================================== |
5057 | Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):rnd:sat |
5058 | C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_rnd_sat(Word64 Rss, Word64 Rtt) |
5059 | Instruction Type: M |
5060 | Execution Slots: SLOT23 |
5061 | ========================================================================== */ |
5062 | |
5063 | #define Q6_R_vdmpy_PP_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s0 |
5064 | |
5065 | /* ========================================================================== |
5066 | Assembly Syntax: Rd32=vdmpy(Rss32,Rtt32):<<1:rnd:sat |
5067 | C Intrinsic Prototype: Word32 Q6_R_vdmpy_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
5068 | Instruction Type: M |
5069 | Execution Slots: SLOT23 |
5070 | ========================================================================== */ |
5071 | |
5072 | #define Q6_R_vdmpy_PP_s1_rnd_sat __builtin_HEXAGON_M2_vdmpyrs_s1 |
5073 | |
5074 | /* ========================================================================== |
5075 | Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):sat |
5076 | C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_sat(Word64 Rss, Word64 Rtt) |
5077 | Instruction Type: M |
5078 | Execution Slots: SLOT23 |
5079 | ========================================================================== */ |
5080 | |
5081 | #define Q6_P_vdmpy_PP_sat __builtin_HEXAGON_M2_vdmpys_s0 |
5082 | |
5083 | /* ========================================================================== |
5084 | Assembly Syntax: Rdd32=vdmpy(Rss32,Rtt32):<<1:sat |
5085 | C Intrinsic Prototype: Word64 Q6_P_vdmpy_PP_s1_sat(Word64 Rss, Word64 Rtt) |
5086 | Instruction Type: M |
5087 | Execution Slots: SLOT23 |
5088 | ========================================================================== */ |
5089 | |
5090 | #define Q6_P_vdmpy_PP_s1_sat __builtin_HEXAGON_M2_vdmpys_s1 |
5091 | |
5092 | /* ========================================================================== |
5093 | Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32) |
5094 | C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
5095 | Instruction Type: M |
5096 | Execution Slots: SLOT23 |
5097 | ========================================================================== */ |
5098 | |
5099 | #define Q6_P_vmpyhacc_RR __builtin_HEXAGON_M2_vmac2 |
5100 | |
5101 | /* ========================================================================== |
5102 | Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32) |
5103 | C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5104 | Instruction Type: M |
5105 | Execution Slots: SLOT23 |
5106 | ========================================================================== */ |
5107 | |
5108 | #define Q6_P_vmpyehacc_PP __builtin_HEXAGON_M2_vmac2es |
5109 | |
5110 | /* ========================================================================== |
5111 | Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):sat |
5112 | C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5113 | Instruction Type: M |
5114 | Execution Slots: SLOT23 |
5115 | ========================================================================== */ |
5116 | |
5117 | #define Q6_P_vmpyehacc_PP_sat __builtin_HEXAGON_M2_vmac2es_s0 |
5118 | |
5119 | /* ========================================================================== |
5120 | Assembly Syntax: Rxx32+=vmpyeh(Rss32,Rtt32):<<1:sat |
5121 | C Intrinsic Prototype: Word64 Q6_P_vmpyehacc_PP_s1_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5122 | Instruction Type: M |
5123 | Execution Slots: SLOT23 |
5124 | ========================================================================== */ |
5125 | |
5126 | #define Q6_P_vmpyehacc_PP_s1_sat __builtin_HEXAGON_M2_vmac2es_s1 |
5127 | |
5128 | /* ========================================================================== |
5129 | Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):sat |
5130 | C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
5131 | Instruction Type: M |
5132 | Execution Slots: SLOT23 |
5133 | ========================================================================== */ |
5134 | |
5135 | #define Q6_P_vmpyhacc_RR_sat __builtin_HEXAGON_M2_vmac2s_s0 |
5136 | |
5137 | /* ========================================================================== |
5138 | Assembly Syntax: Rxx32+=vmpyh(Rs32,Rt32):<<1:sat |
5139 | C Intrinsic Prototype: Word64 Q6_P_vmpyhacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
5140 | Instruction Type: M |
5141 | Execution Slots: SLOT23 |
5142 | ========================================================================== */ |
5143 | |
5144 | #define Q6_P_vmpyhacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2s_s1 |
5145 | |
5146 | /* ========================================================================== |
5147 | Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):sat |
5148 | C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
5149 | Instruction Type: M |
5150 | Execution Slots: SLOT23 |
5151 | ========================================================================== */ |
5152 | |
5153 | #define Q6_P_vmpyhsuacc_RR_sat __builtin_HEXAGON_M2_vmac2su_s0 |
5154 | |
5155 | /* ========================================================================== |
5156 | Assembly Syntax: Rxx32+=vmpyhsu(Rs32,Rt32):<<1:sat |
5157 | C Intrinsic Prototype: Word64 Q6_P_vmpyhsuacc_RR_s1_sat(Word64 Rxx, Word32 Rs, Word32 Rt) |
5158 | Instruction Type: M |
5159 | Execution Slots: SLOT23 |
5160 | ========================================================================== */ |
5161 | |
5162 | #define Q6_P_vmpyhsuacc_RR_s1_sat __builtin_HEXAGON_M2_vmac2su_s1 |
5163 | |
5164 | /* ========================================================================== |
5165 | Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):sat |
5166 | C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_sat(Word64 Rss, Word64 Rtt) |
5167 | Instruction Type: M |
5168 | Execution Slots: SLOT23 |
5169 | ========================================================================== */ |
5170 | |
5171 | #define Q6_P_vmpyeh_PP_sat __builtin_HEXAGON_M2_vmpy2es_s0 |
5172 | |
5173 | /* ========================================================================== |
5174 | Assembly Syntax: Rdd32=vmpyeh(Rss32,Rtt32):<<1:sat |
5175 | C Intrinsic Prototype: Word64 Q6_P_vmpyeh_PP_s1_sat(Word64 Rss, Word64 Rtt) |
5176 | Instruction Type: M |
5177 | Execution Slots: SLOT23 |
5178 | ========================================================================== */ |
5179 | |
5180 | #define Q6_P_vmpyeh_PP_s1_sat __builtin_HEXAGON_M2_vmpy2es_s1 |
5181 | |
5182 | /* ========================================================================== |
5183 | Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):sat |
5184 | C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_sat(Word32 Rs, Word32 Rt) |
5185 | Instruction Type: M |
5186 | Execution Slots: SLOT23 |
5187 | ========================================================================== */ |
5188 | |
5189 | #define Q6_P_vmpyh_RR_sat __builtin_HEXAGON_M2_vmpy2s_s0 |
5190 | |
5191 | /* ========================================================================== |
5192 | Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):rnd:sat |
5193 | C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_rnd_sat(Word32 Rs, Word32 Rt) |
5194 | Instruction Type: M |
5195 | Execution Slots: SLOT23 |
5196 | ========================================================================== */ |
5197 | |
5198 | #define Q6_R_vmpyh_RR_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s0pack |
5199 | |
5200 | /* ========================================================================== |
5201 | Assembly Syntax: Rdd32=vmpyh(Rs32,Rt32):<<1:sat |
5202 | C Intrinsic Prototype: Word64 Q6_P_vmpyh_RR_s1_sat(Word32 Rs, Word32 Rt) |
5203 | Instruction Type: M |
5204 | Execution Slots: SLOT23 |
5205 | ========================================================================== */ |
5206 | |
5207 | #define Q6_P_vmpyh_RR_s1_sat __builtin_HEXAGON_M2_vmpy2s_s1 |
5208 | |
5209 | /* ========================================================================== |
5210 | Assembly Syntax: Rd32=vmpyh(Rs32,Rt32):<<1:rnd:sat |
5211 | C Intrinsic Prototype: Word32 Q6_R_vmpyh_RR_s1_rnd_sat(Word32 Rs, Word32 Rt) |
5212 | Instruction Type: M |
5213 | Execution Slots: SLOT23 |
5214 | ========================================================================== */ |
5215 | |
5216 | #define Q6_R_vmpyh_RR_s1_rnd_sat __builtin_HEXAGON_M2_vmpy2s_s1pack |
5217 | |
5218 | /* ========================================================================== |
5219 | Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):sat |
5220 | C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_sat(Word32 Rs, Word32 Rt) |
5221 | Instruction Type: M |
5222 | Execution Slots: SLOT23 |
5223 | ========================================================================== */ |
5224 | |
5225 | #define Q6_P_vmpyhsu_RR_sat __builtin_HEXAGON_M2_vmpy2su_s0 |
5226 | |
5227 | /* ========================================================================== |
5228 | Assembly Syntax: Rdd32=vmpyhsu(Rs32,Rt32):<<1:sat |
5229 | C Intrinsic Prototype: Word64 Q6_P_vmpyhsu_RR_s1_sat(Word32 Rs, Word32 Rt) |
5230 | Instruction Type: M |
5231 | Execution Slots: SLOT23 |
5232 | ========================================================================== */ |
5233 | |
5234 | #define Q6_P_vmpyhsu_RR_s1_sat __builtin_HEXAGON_M2_vmpy2su_s1 |
5235 | |
5236 | /* ========================================================================== |
5237 | Assembly Syntax: Rd32=vraddh(Rss32,Rtt32) |
5238 | C Intrinsic Prototype: Word32 Q6_R_vraddh_PP(Word64 Rss, Word64 Rtt) |
5239 | Instruction Type: M |
5240 | Execution Slots: SLOT23 |
5241 | ========================================================================== */ |
5242 | |
5243 | #define Q6_R_vraddh_PP __builtin_HEXAGON_M2_vraddh |
5244 | |
5245 | /* ========================================================================== |
5246 | Assembly Syntax: Rd32=vradduh(Rss32,Rtt32) |
5247 | C Intrinsic Prototype: Word32 Q6_R_vradduh_PP(Word64 Rss, Word64 Rtt) |
5248 | Instruction Type: M |
5249 | Execution Slots: SLOT23 |
5250 | ========================================================================== */ |
5251 | |
5252 | #define Q6_R_vradduh_PP __builtin_HEXAGON_M2_vradduh |
5253 | |
5254 | /* ========================================================================== |
5255 | Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32) |
5256 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5257 | Instruction Type: M |
5258 | Execution Slots: SLOT23 |
5259 | ========================================================================== */ |
5260 | |
5261 | #define Q6_P_vrcmpyiacc_PP __builtin_HEXAGON_M2_vrcmaci_s0 |
5262 | |
5263 | /* ========================================================================== |
5264 | Assembly Syntax: Rxx32+=vrcmpyi(Rss32,Rtt32*) |
5265 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyiacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5266 | Instruction Type: M |
5267 | Execution Slots: SLOT23 |
5268 | ========================================================================== */ |
5269 | |
5270 | #define Q6_P_vrcmpyiacc_PP_conj __builtin_HEXAGON_M2_vrcmaci_s0c |
5271 | |
5272 | /* ========================================================================== |
5273 | Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32) |
5274 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5275 | Instruction Type: M |
5276 | Execution Slots: SLOT23 |
5277 | ========================================================================== */ |
5278 | |
5279 | #define Q6_P_vrcmpyracc_PP __builtin_HEXAGON_M2_vrcmacr_s0 |
5280 | |
5281 | /* ========================================================================== |
5282 | Assembly Syntax: Rxx32+=vrcmpyr(Rss32,Rtt32*) |
5283 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyracc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5284 | Instruction Type: M |
5285 | Execution Slots: SLOT23 |
5286 | ========================================================================== */ |
5287 | |
5288 | #define Q6_P_vrcmpyracc_PP_conj __builtin_HEXAGON_M2_vrcmacr_s0c |
5289 | |
5290 | /* ========================================================================== |
5291 | Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32) |
5292 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP(Word64 Rss, Word64 Rtt) |
5293 | Instruction Type: M |
5294 | Execution Slots: SLOT23 |
5295 | ========================================================================== */ |
5296 | |
5297 | #define Q6_P_vrcmpyi_PP __builtin_HEXAGON_M2_vrcmpyi_s0 |
5298 | |
5299 | /* ========================================================================== |
5300 | Assembly Syntax: Rdd32=vrcmpyi(Rss32,Rtt32*) |
5301 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyi_PP_conj(Word64 Rss, Word64 Rtt) |
5302 | Instruction Type: M |
5303 | Execution Slots: SLOT23 |
5304 | ========================================================================== */ |
5305 | |
5306 | #define Q6_P_vrcmpyi_PP_conj __builtin_HEXAGON_M2_vrcmpyi_s0c |
5307 | |
5308 | /* ========================================================================== |
5309 | Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32) |
5310 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP(Word64 Rss, Word64 Rtt) |
5311 | Instruction Type: M |
5312 | Execution Slots: SLOT23 |
5313 | ========================================================================== */ |
5314 | |
5315 | #define Q6_P_vrcmpyr_PP __builtin_HEXAGON_M2_vrcmpyr_s0 |
5316 | |
5317 | /* ========================================================================== |
5318 | Assembly Syntax: Rdd32=vrcmpyr(Rss32,Rtt32*) |
5319 | C Intrinsic Prototype: Word64 Q6_P_vrcmpyr_PP_conj(Word64 Rss, Word64 Rtt) |
5320 | Instruction Type: M |
5321 | Execution Slots: SLOT23 |
5322 | ========================================================================== */ |
5323 | |
5324 | #define Q6_P_vrcmpyr_PP_conj __builtin_HEXAGON_M2_vrcmpyr_s0c |
5325 | |
5326 | /* ========================================================================== |
5327 | Assembly Syntax: Rxx32+=vrcmpys(Rss32,Rt32):<<1:sat |
5328 | C Intrinsic Prototype: Word64 Q6_P_vrcmpysacc_PR_s1_sat(Word64 Rxx, Word64 Rss, Word32 Rt) |
5329 | Instruction Type: M |
5330 | Execution Slots: SLOT0123 |
5331 | ========================================================================== */ |
5332 | |
5333 | #define Q6_P_vrcmpysacc_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_acc_s1 |
5334 | |
5335 | /* ========================================================================== |
5336 | Assembly Syntax: Rdd32=vrcmpys(Rss32,Rt32):<<1:sat |
5337 | C Intrinsic Prototype: Word64 Q6_P_vrcmpys_PR_s1_sat(Word64 Rss, Word32 Rt) |
5338 | Instruction Type: M |
5339 | Execution Slots: SLOT0123 |
5340 | ========================================================================== */ |
5341 | |
5342 | #define Q6_P_vrcmpys_PR_s1_sat __builtin_HEXAGON_M2_vrcmpys_s1 |
5343 | |
5344 | /* ========================================================================== |
5345 | Assembly Syntax: Rd32=vrcmpys(Rss32,Rt32):<<1:rnd:sat |
5346 | C Intrinsic Prototype: Word32 Q6_R_vrcmpys_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) |
5347 | Instruction Type: M |
5348 | Execution Slots: SLOT0123 |
5349 | ========================================================================== */ |
5350 | |
5351 | #define Q6_R_vrcmpys_PR_s1_rnd_sat __builtin_HEXAGON_M2_vrcmpys_s1rp |
5352 | |
5353 | /* ========================================================================== |
5354 | Assembly Syntax: Rxx32+=vrmpyh(Rss32,Rtt32) |
5355 | C Intrinsic Prototype: Word64 Q6_P_vrmpyhacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5356 | Instruction Type: M |
5357 | Execution Slots: SLOT23 |
5358 | ========================================================================== */ |
5359 | |
5360 | #define Q6_P_vrmpyhacc_PP __builtin_HEXAGON_M2_vrmac_s0 |
5361 | |
5362 | /* ========================================================================== |
5363 | Assembly Syntax: Rdd32=vrmpyh(Rss32,Rtt32) |
5364 | C Intrinsic Prototype: Word64 Q6_P_vrmpyh_PP(Word64 Rss, Word64 Rtt) |
5365 | Instruction Type: M |
5366 | Execution Slots: SLOT23 |
5367 | ========================================================================== */ |
5368 | |
5369 | #define Q6_P_vrmpyh_PP __builtin_HEXAGON_M2_vrmpy_s0 |
5370 | |
5371 | /* ========================================================================== |
5372 | Assembly Syntax: Rx32^=xor(Rs32,Rt32) |
5373 | C Intrinsic Prototype: Word32 Q6_R_xorxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5374 | Instruction Type: M |
5375 | Execution Slots: SLOT23 |
5376 | ========================================================================== */ |
5377 | |
5378 | #define Q6_R_xorxacc_RR __builtin_HEXAGON_M2_xor_xacc |
5379 | |
5380 | /* ========================================================================== |
5381 | Assembly Syntax: Rx32&=and(Rs32,Rt32) |
5382 | C Intrinsic Prototype: Word32 Q6_R_andand_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5383 | Instruction Type: M |
5384 | Execution Slots: SLOT23 |
5385 | ========================================================================== */ |
5386 | |
5387 | #define Q6_R_andand_RR __builtin_HEXAGON_M4_and_and |
5388 | |
5389 | /* ========================================================================== |
5390 | Assembly Syntax: Rx32&=and(Rs32,~Rt32) |
5391 | C Intrinsic Prototype: Word32 Q6_R_andand_RnR(Word32 Rx, Word32 Rs, Word32 Rt) |
5392 | Instruction Type: M |
5393 | Execution Slots: SLOT23 |
5394 | ========================================================================== */ |
5395 | |
5396 | #define Q6_R_andand_RnR __builtin_HEXAGON_M4_and_andn |
5397 | |
5398 | /* ========================================================================== |
5399 | Assembly Syntax: Rx32&=or(Rs32,Rt32) |
5400 | C Intrinsic Prototype: Word32 Q6_R_orand_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5401 | Instruction Type: M |
5402 | Execution Slots: SLOT23 |
5403 | ========================================================================== */ |
5404 | |
5405 | #define Q6_R_orand_RR __builtin_HEXAGON_M4_and_or |
5406 | |
5407 | /* ========================================================================== |
5408 | Assembly Syntax: Rx32&=xor(Rs32,Rt32) |
5409 | C Intrinsic Prototype: Word32 Q6_R_xorand_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5410 | Instruction Type: M |
5411 | Execution Slots: SLOT23 |
5412 | ========================================================================== */ |
5413 | |
5414 | #define Q6_R_xorand_RR __builtin_HEXAGON_M4_and_xor |
5415 | |
5416 | /* ========================================================================== |
5417 | Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32):<<1:rnd:sat |
5418 | C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) |
5419 | Instruction Type: S_3op |
5420 | Execution Slots: SLOT23 |
5421 | ========================================================================== */ |
5422 | |
5423 | #define Q6_R_cmpyiwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_wh |
5424 | |
5425 | /* ========================================================================== |
5426 | Assembly Syntax: Rd32=cmpyiwh(Rss32,Rt32*):<<1:rnd:sat |
5427 | C Intrinsic Prototype: Word32 Q6_R_cmpyiwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) |
5428 | Instruction Type: S_3op |
5429 | Execution Slots: SLOT23 |
5430 | ========================================================================== */ |
5431 | |
5432 | #define Q6_R_cmpyiwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyi_whc |
5433 | |
5434 | /* ========================================================================== |
5435 | Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32):<<1:rnd:sat |
5436 | C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_s1_rnd_sat(Word64 Rss, Word32 Rt) |
5437 | Instruction Type: S_3op |
5438 | Execution Slots: SLOT23 |
5439 | ========================================================================== */ |
5440 | |
5441 | #define Q6_R_cmpyrwh_PR_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_wh |
5442 | |
5443 | /* ========================================================================== |
5444 | Assembly Syntax: Rd32=cmpyrwh(Rss32,Rt32*):<<1:rnd:sat |
5445 | C Intrinsic Prototype: Word32 Q6_R_cmpyrwh_PR_conj_s1_rnd_sat(Word64 Rss, Word32 Rt) |
5446 | Instruction Type: S_3op |
5447 | Execution Slots: SLOT23 |
5448 | ========================================================================== */ |
5449 | |
5450 | #define Q6_R_cmpyrwh_PR_conj_s1_rnd_sat __builtin_HEXAGON_M4_cmpyr_whc |
5451 | |
5452 | /* ========================================================================== |
5453 | Assembly Syntax: Rx32+=mpy(Rs32,Rt32):<<1:sat |
5454 | C Intrinsic Prototype: Word32 Q6_R_mpyacc_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
5455 | Instruction Type: M |
5456 | Execution Slots: SLOT23 |
5457 | ========================================================================== */ |
5458 | |
5459 | #define Q6_R_mpyacc_RR_s1_sat __builtin_HEXAGON_M4_mac_up_s1_sat |
5460 | |
5461 | /* ========================================================================== |
5462 | Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,#U6)) |
5463 | C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRI(Word32 Iu6, Word32 Rs, Word32 IU6) |
5464 | Instruction Type: ALU64 |
5465 | Execution Slots: SLOT23 |
5466 | ========================================================================== */ |
5467 | |
5468 | #define Q6_R_add_mpyi_IRI __builtin_HEXAGON_M4_mpyri_addi |
5469 | |
5470 | /* ========================================================================== |
5471 | Assembly Syntax: Rd32=add(Ru32,mpyi(Rs32,#u6)) |
5472 | C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRI(Word32 Ru, Word32 Rs, Word32 Iu6) |
5473 | Instruction Type: ALU64 |
5474 | Execution Slots: SLOT23 |
5475 | ========================================================================== */ |
5476 | |
5477 | #define Q6_R_add_mpyi_RRI __builtin_HEXAGON_M4_mpyri_addr |
5478 | |
5479 | /* ========================================================================== |
5480 | Assembly Syntax: Rd32=add(Ru32,mpyi(#u6:2,Rs32)) |
5481 | C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RIR(Word32 Ru, Word32 Iu6_2, Word32 Rs) |
5482 | Instruction Type: ALU64 |
5483 | Execution Slots: SLOT23 |
5484 | ========================================================================== */ |
5485 | |
5486 | #define Q6_R_add_mpyi_RIR __builtin_HEXAGON_M4_mpyri_addr_u2 |
5487 | |
5488 | /* ========================================================================== |
5489 | Assembly Syntax: Rd32=add(#u6,mpyi(Rs32,Rt32)) |
5490 | C Intrinsic Prototype: Word32 Q6_R_add_mpyi_IRR(Word32 Iu6, Word32 Rs, Word32 Rt) |
5491 | Instruction Type: ALU64 |
5492 | Execution Slots: SLOT23 |
5493 | ========================================================================== */ |
5494 | |
5495 | #define Q6_R_add_mpyi_IRR __builtin_HEXAGON_M4_mpyrr_addi |
5496 | |
5497 | /* ========================================================================== |
5498 | Assembly Syntax: Ry32=add(Ru32,mpyi(Ry32,Rs32)) |
5499 | C Intrinsic Prototype: Word32 Q6_R_add_mpyi_RRR(Word32 Ru, Word32 Ry, Word32 Rs) |
5500 | Instruction Type: M |
5501 | Execution Slots: SLOT23 |
5502 | ========================================================================== */ |
5503 | |
5504 | #define Q6_R_add_mpyi_RRR __builtin_HEXAGON_M4_mpyrr_addr |
5505 | |
5506 | /* ========================================================================== |
5507 | Assembly Syntax: Rx32-=mpy(Rs32,Rt32):<<1:sat |
5508 | C Intrinsic Prototype: Word32 Q6_R_mpynac_RR_s1_sat(Word32 Rx, Word32 Rs, Word32 Rt) |
5509 | Instruction Type: M |
5510 | Execution Slots: SLOT23 |
5511 | ========================================================================== */ |
5512 | |
5513 | #define Q6_R_mpynac_RR_s1_sat __builtin_HEXAGON_M4_nac_up_s1_sat |
5514 | |
5515 | /* ========================================================================== |
5516 | Assembly Syntax: Rx32|=and(Rs32,Rt32) |
5517 | C Intrinsic Prototype: Word32 Q6_R_andor_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5518 | Instruction Type: M |
5519 | Execution Slots: SLOT23 |
5520 | ========================================================================== */ |
5521 | |
5522 | #define Q6_R_andor_RR __builtin_HEXAGON_M4_or_and |
5523 | |
5524 | /* ========================================================================== |
5525 | Assembly Syntax: Rx32|=and(Rs32,~Rt32) |
5526 | C Intrinsic Prototype: Word32 Q6_R_andor_RnR(Word32 Rx, Word32 Rs, Word32 Rt) |
5527 | Instruction Type: M |
5528 | Execution Slots: SLOT23 |
5529 | ========================================================================== */ |
5530 | |
5531 | #define Q6_R_andor_RnR __builtin_HEXAGON_M4_or_andn |
5532 | |
5533 | /* ========================================================================== |
5534 | Assembly Syntax: Rx32|=or(Rs32,Rt32) |
5535 | C Intrinsic Prototype: Word32 Q6_R_oror_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5536 | Instruction Type: M |
5537 | Execution Slots: SLOT23 |
5538 | ========================================================================== */ |
5539 | |
5540 | #define Q6_R_oror_RR __builtin_HEXAGON_M4_or_or |
5541 | |
5542 | /* ========================================================================== |
5543 | Assembly Syntax: Rx32|=xor(Rs32,Rt32) |
5544 | C Intrinsic Prototype: Word32 Q6_R_xoror_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5545 | Instruction Type: M |
5546 | Execution Slots: SLOT23 |
5547 | ========================================================================== */ |
5548 | |
5549 | #define Q6_R_xoror_RR __builtin_HEXAGON_M4_or_xor |
5550 | |
5551 | /* ========================================================================== |
5552 | Assembly Syntax: Rdd32=pmpyw(Rs32,Rt32) |
5553 | C Intrinsic Prototype: Word64 Q6_P_pmpyw_RR(Word32 Rs, Word32 Rt) |
5554 | Instruction Type: M |
5555 | Execution Slots: SLOT23 |
5556 | ========================================================================== */ |
5557 | |
5558 | #define Q6_P_pmpyw_RR __builtin_HEXAGON_M4_pmpyw |
5559 | |
5560 | /* ========================================================================== |
5561 | Assembly Syntax: Rxx32^=pmpyw(Rs32,Rt32) |
5562 | C Intrinsic Prototype: Word64 Q6_P_pmpywxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
5563 | Instruction Type: M |
5564 | Execution Slots: SLOT23 |
5565 | ========================================================================== */ |
5566 | |
5567 | #define Q6_P_pmpywxacc_RR __builtin_HEXAGON_M4_pmpyw_acc |
5568 | |
5569 | /* ========================================================================== |
5570 | Assembly Syntax: Rdd32=vpmpyh(Rs32,Rt32) |
5571 | C Intrinsic Prototype: Word64 Q6_P_vpmpyh_RR(Word32 Rs, Word32 Rt) |
5572 | Instruction Type: M |
5573 | Execution Slots: SLOT23 |
5574 | ========================================================================== */ |
5575 | |
5576 | #define Q6_P_vpmpyh_RR __builtin_HEXAGON_M4_vpmpyh |
5577 | |
5578 | /* ========================================================================== |
5579 | Assembly Syntax: Rxx32^=vpmpyh(Rs32,Rt32) |
5580 | C Intrinsic Prototype: Word64 Q6_P_vpmpyhxacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
5581 | Instruction Type: M |
5582 | Execution Slots: SLOT23 |
5583 | ========================================================================== */ |
5584 | |
5585 | #define Q6_P_vpmpyhxacc_RR __builtin_HEXAGON_M4_vpmpyh_acc |
5586 | |
5587 | /* ========================================================================== |
5588 | Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32) |
5589 | C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5590 | Instruction Type: M |
5591 | Execution Slots: SLOT23 |
5592 | ========================================================================== */ |
5593 | |
5594 | #define Q6_P_vrmpywehacc_PP __builtin_HEXAGON_M4_vrmpyeh_acc_s0 |
5595 | |
5596 | /* ========================================================================== |
5597 | Assembly Syntax: Rxx32+=vrmpyweh(Rss32,Rtt32):<<1 |
5598 | C Intrinsic Prototype: Word64 Q6_P_vrmpywehacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5599 | Instruction Type: M |
5600 | Execution Slots: SLOT23 |
5601 | ========================================================================== */ |
5602 | |
5603 | #define Q6_P_vrmpywehacc_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_acc_s1 |
5604 | |
5605 | /* ========================================================================== |
5606 | Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32) |
5607 | C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP(Word64 Rss, Word64 Rtt) |
5608 | Instruction Type: M |
5609 | Execution Slots: SLOT23 |
5610 | ========================================================================== */ |
5611 | |
5612 | #define Q6_P_vrmpyweh_PP __builtin_HEXAGON_M4_vrmpyeh_s0 |
5613 | |
5614 | /* ========================================================================== |
5615 | Assembly Syntax: Rdd32=vrmpyweh(Rss32,Rtt32):<<1 |
5616 | C Intrinsic Prototype: Word64 Q6_P_vrmpyweh_PP_s1(Word64 Rss, Word64 Rtt) |
5617 | Instruction Type: M |
5618 | Execution Slots: SLOT23 |
5619 | ========================================================================== */ |
5620 | |
5621 | #define Q6_P_vrmpyweh_PP_s1 __builtin_HEXAGON_M4_vrmpyeh_s1 |
5622 | |
5623 | /* ========================================================================== |
5624 | Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32) |
5625 | C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5626 | Instruction Type: M |
5627 | Execution Slots: SLOT23 |
5628 | ========================================================================== */ |
5629 | |
5630 | #define Q6_P_vrmpywohacc_PP __builtin_HEXAGON_M4_vrmpyoh_acc_s0 |
5631 | |
5632 | /* ========================================================================== |
5633 | Assembly Syntax: Rxx32+=vrmpywoh(Rss32,Rtt32):<<1 |
5634 | C Intrinsic Prototype: Word64 Q6_P_vrmpywohacc_PP_s1(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5635 | Instruction Type: M |
5636 | Execution Slots: SLOT23 |
5637 | ========================================================================== */ |
5638 | |
5639 | #define Q6_P_vrmpywohacc_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_acc_s1 |
5640 | |
5641 | /* ========================================================================== |
5642 | Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32) |
5643 | C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP(Word64 Rss, Word64 Rtt) |
5644 | Instruction Type: M |
5645 | Execution Slots: SLOT23 |
5646 | ========================================================================== */ |
5647 | |
5648 | #define Q6_P_vrmpywoh_PP __builtin_HEXAGON_M4_vrmpyoh_s0 |
5649 | |
5650 | /* ========================================================================== |
5651 | Assembly Syntax: Rdd32=vrmpywoh(Rss32,Rtt32):<<1 |
5652 | C Intrinsic Prototype: Word64 Q6_P_vrmpywoh_PP_s1(Word64 Rss, Word64 Rtt) |
5653 | Instruction Type: M |
5654 | Execution Slots: SLOT23 |
5655 | ========================================================================== */ |
5656 | |
5657 | #define Q6_P_vrmpywoh_PP_s1 __builtin_HEXAGON_M4_vrmpyoh_s1 |
5658 | |
5659 | /* ========================================================================== |
5660 | Assembly Syntax: Rx32^=and(Rs32,Rt32) |
5661 | C Intrinsic Prototype: Word32 Q6_R_andxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5662 | Instruction Type: M |
5663 | Execution Slots: SLOT23 |
5664 | ========================================================================== */ |
5665 | |
5666 | #define Q6_R_andxacc_RR __builtin_HEXAGON_M4_xor_and |
5667 | |
5668 | /* ========================================================================== |
5669 | Assembly Syntax: Rx32^=and(Rs32,~Rt32) |
5670 | C Intrinsic Prototype: Word32 Q6_R_andxacc_RnR(Word32 Rx, Word32 Rs, Word32 Rt) |
5671 | Instruction Type: M |
5672 | Execution Slots: SLOT23 |
5673 | ========================================================================== */ |
5674 | |
5675 | #define Q6_R_andxacc_RnR __builtin_HEXAGON_M4_xor_andn |
5676 | |
5677 | /* ========================================================================== |
5678 | Assembly Syntax: Rx32^=or(Rs32,Rt32) |
5679 | C Intrinsic Prototype: Word32 Q6_R_orxacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5680 | Instruction Type: M |
5681 | Execution Slots: SLOT23 |
5682 | ========================================================================== */ |
5683 | |
5684 | #define Q6_R_orxacc_RR __builtin_HEXAGON_M4_xor_or |
5685 | |
5686 | /* ========================================================================== |
5687 | Assembly Syntax: Rxx32^=xor(Rss32,Rtt32) |
5688 | C Intrinsic Prototype: Word64 Q6_P_xorxacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5689 | Instruction Type: S_3op |
5690 | Execution Slots: SLOT23 |
5691 | ========================================================================== */ |
5692 | |
5693 | #define Q6_P_xorxacc_PP __builtin_HEXAGON_M4_xor_xacc |
5694 | |
5695 | /* ========================================================================== |
5696 | Assembly Syntax: Rxx32+=vdmpybsu(Rss32,Rtt32):sat |
5697 | C Intrinsic Prototype: Word64 Q6_P_vdmpybsuacc_PP_sat(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5698 | Instruction Type: M |
5699 | Execution Slots: SLOT23 |
5700 | ========================================================================== */ |
5701 | |
5702 | #define Q6_P_vdmpybsuacc_PP_sat __builtin_HEXAGON_M5_vdmacbsu |
5703 | |
5704 | /* ========================================================================== |
5705 | Assembly Syntax: Rdd32=vdmpybsu(Rss32,Rtt32):sat |
5706 | C Intrinsic Prototype: Word64 Q6_P_vdmpybsu_PP_sat(Word64 Rss, Word64 Rtt) |
5707 | Instruction Type: M |
5708 | Execution Slots: SLOT23 |
5709 | ========================================================================== */ |
5710 | |
5711 | #define Q6_P_vdmpybsu_PP_sat __builtin_HEXAGON_M5_vdmpybsu |
5712 | |
5713 | /* ========================================================================== |
5714 | Assembly Syntax: Rxx32+=vmpybsu(Rs32,Rt32) |
5715 | C Intrinsic Prototype: Word64 Q6_P_vmpybsuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
5716 | Instruction Type: M |
5717 | Execution Slots: SLOT23 |
5718 | ========================================================================== */ |
5719 | |
5720 | #define Q6_P_vmpybsuacc_RR __builtin_HEXAGON_M5_vmacbsu |
5721 | |
5722 | /* ========================================================================== |
5723 | Assembly Syntax: Rxx32+=vmpybu(Rs32,Rt32) |
5724 | C Intrinsic Prototype: Word64 Q6_P_vmpybuacc_RR(Word64 Rxx, Word32 Rs, Word32 Rt) |
5725 | Instruction Type: M |
5726 | Execution Slots: SLOT23 |
5727 | ========================================================================== */ |
5728 | |
5729 | #define Q6_P_vmpybuacc_RR __builtin_HEXAGON_M5_vmacbuu |
5730 | |
5731 | /* ========================================================================== |
5732 | Assembly Syntax: Rdd32=vmpybsu(Rs32,Rt32) |
5733 | C Intrinsic Prototype: Word64 Q6_P_vmpybsu_RR(Word32 Rs, Word32 Rt) |
5734 | Instruction Type: M |
5735 | Execution Slots: SLOT23 |
5736 | ========================================================================== */ |
5737 | |
5738 | #define Q6_P_vmpybsu_RR __builtin_HEXAGON_M5_vmpybsu |
5739 | |
5740 | /* ========================================================================== |
5741 | Assembly Syntax: Rdd32=vmpybu(Rs32,Rt32) |
5742 | C Intrinsic Prototype: Word64 Q6_P_vmpybu_RR(Word32 Rs, Word32 Rt) |
5743 | Instruction Type: M |
5744 | Execution Slots: SLOT23 |
5745 | ========================================================================== */ |
5746 | |
5747 | #define Q6_P_vmpybu_RR __builtin_HEXAGON_M5_vmpybuu |
5748 | |
5749 | /* ========================================================================== |
5750 | Assembly Syntax: Rxx32+=vrmpybsu(Rss32,Rtt32) |
5751 | C Intrinsic Prototype: Word64 Q6_P_vrmpybsuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5752 | Instruction Type: M |
5753 | Execution Slots: SLOT23 |
5754 | ========================================================================== */ |
5755 | |
5756 | #define Q6_P_vrmpybsuacc_PP __builtin_HEXAGON_M5_vrmacbsu |
5757 | |
5758 | /* ========================================================================== |
5759 | Assembly Syntax: Rxx32+=vrmpybu(Rss32,Rtt32) |
5760 | C Intrinsic Prototype: Word64 Q6_P_vrmpybuacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
5761 | Instruction Type: M |
5762 | Execution Slots: SLOT23 |
5763 | ========================================================================== */ |
5764 | |
5765 | #define Q6_P_vrmpybuacc_PP __builtin_HEXAGON_M5_vrmacbuu |
5766 | |
5767 | /* ========================================================================== |
5768 | Assembly Syntax: Rdd32=vrmpybsu(Rss32,Rtt32) |
5769 | C Intrinsic Prototype: Word64 Q6_P_vrmpybsu_PP(Word64 Rss, Word64 Rtt) |
5770 | Instruction Type: M |
5771 | Execution Slots: SLOT23 |
5772 | ========================================================================== */ |
5773 | |
5774 | #define Q6_P_vrmpybsu_PP __builtin_HEXAGON_M5_vrmpybsu |
5775 | |
5776 | /* ========================================================================== |
5777 | Assembly Syntax: Rdd32=vrmpybu(Rss32,Rtt32) |
5778 | C Intrinsic Prototype: Word64 Q6_P_vrmpybu_PP(Word64 Rss, Word64 Rtt) |
5779 | Instruction Type: M |
5780 | Execution Slots: SLOT23 |
5781 | ========================================================================== */ |
5782 | |
5783 | #define Q6_P_vrmpybu_PP __builtin_HEXAGON_M5_vrmpybuu |
5784 | |
5785 | /* ========================================================================== |
5786 | Assembly Syntax: Rd32=addasl(Rt32,Rs32,#u3) |
5787 | C Intrinsic Prototype: Word32 Q6_R_addasl_RRI(Word32 Rt, Word32 Rs, Word32 Iu3) |
5788 | Instruction Type: S_3op |
5789 | Execution Slots: SLOT23 |
5790 | ========================================================================== */ |
5791 | |
5792 | #define Q6_R_addasl_RRI __builtin_HEXAGON_S2_addasl_rrri |
5793 | |
5794 | /* ========================================================================== |
5795 | Assembly Syntax: Rdd32=asl(Rss32,#u6) |
5796 | C Intrinsic Prototype: Word64 Q6_P_asl_PI(Word64 Rss, Word32 Iu6) |
5797 | Instruction Type: S_2op |
5798 | Execution Slots: SLOT23 |
5799 | ========================================================================== */ |
5800 | |
5801 | #define Q6_P_asl_PI __builtin_HEXAGON_S2_asl_i_p |
5802 | |
5803 | /* ========================================================================== |
5804 | Assembly Syntax: Rxx32+=asl(Rss32,#u6) |
5805 | C Intrinsic Prototype: Word64 Q6_P_aslacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
5806 | Instruction Type: S_2op |
5807 | Execution Slots: SLOT23 |
5808 | ========================================================================== */ |
5809 | |
5810 | #define Q6_P_aslacc_PI __builtin_HEXAGON_S2_asl_i_p_acc |
5811 | |
5812 | /* ========================================================================== |
5813 | Assembly Syntax: Rxx32&=asl(Rss32,#u6) |
5814 | C Intrinsic Prototype: Word64 Q6_P_asland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
5815 | Instruction Type: S_2op |
5816 | Execution Slots: SLOT23 |
5817 | ========================================================================== */ |
5818 | |
5819 | #define Q6_P_asland_PI __builtin_HEXAGON_S2_asl_i_p_and |
5820 | |
5821 | /* ========================================================================== |
5822 | Assembly Syntax: Rxx32-=asl(Rss32,#u6) |
5823 | C Intrinsic Prototype: Word64 Q6_P_aslnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
5824 | Instruction Type: S_2op |
5825 | Execution Slots: SLOT23 |
5826 | ========================================================================== */ |
5827 | |
5828 | #define Q6_P_aslnac_PI __builtin_HEXAGON_S2_asl_i_p_nac |
5829 | |
5830 | /* ========================================================================== |
5831 | Assembly Syntax: Rxx32|=asl(Rss32,#u6) |
5832 | C Intrinsic Prototype: Word64 Q6_P_aslor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
5833 | Instruction Type: S_2op |
5834 | Execution Slots: SLOT23 |
5835 | ========================================================================== */ |
5836 | |
5837 | #define Q6_P_aslor_PI __builtin_HEXAGON_S2_asl_i_p_or |
5838 | |
5839 | /* ========================================================================== |
5840 | Assembly Syntax: Rxx32^=asl(Rss32,#u6) |
5841 | C Intrinsic Prototype: Word64 Q6_P_aslxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
5842 | Instruction Type: S_2op |
5843 | Execution Slots: SLOT23 |
5844 | ========================================================================== */ |
5845 | |
5846 | #define Q6_P_aslxacc_PI __builtin_HEXAGON_S2_asl_i_p_xacc |
5847 | |
5848 | /* ========================================================================== |
5849 | Assembly Syntax: Rd32=asl(Rs32,#u5) |
5850 | C Intrinsic Prototype: Word32 Q6_R_asl_RI(Word32 Rs, Word32 Iu5) |
5851 | Instruction Type: S_2op |
5852 | Execution Slots: SLOT23 |
5853 | ========================================================================== */ |
5854 | |
5855 | #define Q6_R_asl_RI __builtin_HEXAGON_S2_asl_i_r |
5856 | |
5857 | /* ========================================================================== |
5858 | Assembly Syntax: Rx32+=asl(Rs32,#u5) |
5859 | C Intrinsic Prototype: Word32 Q6_R_aslacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
5860 | Instruction Type: S_2op |
5861 | Execution Slots: SLOT23 |
5862 | ========================================================================== */ |
5863 | |
5864 | #define Q6_R_aslacc_RI __builtin_HEXAGON_S2_asl_i_r_acc |
5865 | |
5866 | /* ========================================================================== |
5867 | Assembly Syntax: Rx32&=asl(Rs32,#u5) |
5868 | C Intrinsic Prototype: Word32 Q6_R_asland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
5869 | Instruction Type: S_2op |
5870 | Execution Slots: SLOT23 |
5871 | ========================================================================== */ |
5872 | |
5873 | #define Q6_R_asland_RI __builtin_HEXAGON_S2_asl_i_r_and |
5874 | |
5875 | /* ========================================================================== |
5876 | Assembly Syntax: Rx32-=asl(Rs32,#u5) |
5877 | C Intrinsic Prototype: Word32 Q6_R_aslnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
5878 | Instruction Type: S_2op |
5879 | Execution Slots: SLOT23 |
5880 | ========================================================================== */ |
5881 | |
5882 | #define Q6_R_aslnac_RI __builtin_HEXAGON_S2_asl_i_r_nac |
5883 | |
5884 | /* ========================================================================== |
5885 | Assembly Syntax: Rx32|=asl(Rs32,#u5) |
5886 | C Intrinsic Prototype: Word32 Q6_R_aslor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
5887 | Instruction Type: S_2op |
5888 | Execution Slots: SLOT23 |
5889 | ========================================================================== */ |
5890 | |
5891 | #define Q6_R_aslor_RI __builtin_HEXAGON_S2_asl_i_r_or |
5892 | |
5893 | /* ========================================================================== |
5894 | Assembly Syntax: Rd32=asl(Rs32,#u5):sat |
5895 | C Intrinsic Prototype: Word32 Q6_R_asl_RI_sat(Word32 Rs, Word32 Iu5) |
5896 | Instruction Type: S_2op |
5897 | Execution Slots: SLOT23 |
5898 | ========================================================================== */ |
5899 | |
5900 | #define Q6_R_asl_RI_sat __builtin_HEXAGON_S2_asl_i_r_sat |
5901 | |
5902 | /* ========================================================================== |
5903 | Assembly Syntax: Rx32^=asl(Rs32,#u5) |
5904 | C Intrinsic Prototype: Word32 Q6_R_aslxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
5905 | Instruction Type: S_2op |
5906 | Execution Slots: SLOT23 |
5907 | ========================================================================== */ |
5908 | |
5909 | #define Q6_R_aslxacc_RI __builtin_HEXAGON_S2_asl_i_r_xacc |
5910 | |
5911 | /* ========================================================================== |
5912 | Assembly Syntax: Rdd32=vaslh(Rss32,#u4) |
5913 | C Intrinsic Prototype: Word64 Q6_P_vaslh_PI(Word64 Rss, Word32 Iu4) |
5914 | Instruction Type: S_2op |
5915 | Execution Slots: SLOT23 |
5916 | ========================================================================== */ |
5917 | |
5918 | #define Q6_P_vaslh_PI __builtin_HEXAGON_S2_asl_i_vh |
5919 | |
5920 | /* ========================================================================== |
5921 | Assembly Syntax: Rdd32=vaslw(Rss32,#u5) |
5922 | C Intrinsic Prototype: Word64 Q6_P_vaslw_PI(Word64 Rss, Word32 Iu5) |
5923 | Instruction Type: S_2op |
5924 | Execution Slots: SLOT23 |
5925 | ========================================================================== */ |
5926 | |
5927 | #define Q6_P_vaslw_PI __builtin_HEXAGON_S2_asl_i_vw |
5928 | |
5929 | /* ========================================================================== |
5930 | Assembly Syntax: Rdd32=asl(Rss32,Rt32) |
5931 | C Intrinsic Prototype: Word64 Q6_P_asl_PR(Word64 Rss, Word32 Rt) |
5932 | Instruction Type: S_3op |
5933 | Execution Slots: SLOT23 |
5934 | ========================================================================== */ |
5935 | |
5936 | #define Q6_P_asl_PR __builtin_HEXAGON_S2_asl_r_p |
5937 | |
5938 | /* ========================================================================== |
5939 | Assembly Syntax: Rxx32+=asl(Rss32,Rt32) |
5940 | C Intrinsic Prototype: Word64 Q6_P_aslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
5941 | Instruction Type: S_3op |
5942 | Execution Slots: SLOT23 |
5943 | ========================================================================== */ |
5944 | |
5945 | #define Q6_P_aslacc_PR __builtin_HEXAGON_S2_asl_r_p_acc |
5946 | |
5947 | /* ========================================================================== |
5948 | Assembly Syntax: Rxx32&=asl(Rss32,Rt32) |
5949 | C Intrinsic Prototype: Word64 Q6_P_asland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
5950 | Instruction Type: S_3op |
5951 | Execution Slots: SLOT23 |
5952 | ========================================================================== */ |
5953 | |
5954 | #define Q6_P_asland_PR __builtin_HEXAGON_S2_asl_r_p_and |
5955 | |
5956 | /* ========================================================================== |
5957 | Assembly Syntax: Rxx32-=asl(Rss32,Rt32) |
5958 | C Intrinsic Prototype: Word64 Q6_P_aslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
5959 | Instruction Type: S_3op |
5960 | Execution Slots: SLOT23 |
5961 | ========================================================================== */ |
5962 | |
5963 | #define Q6_P_aslnac_PR __builtin_HEXAGON_S2_asl_r_p_nac |
5964 | |
5965 | /* ========================================================================== |
5966 | Assembly Syntax: Rxx32|=asl(Rss32,Rt32) |
5967 | C Intrinsic Prototype: Word64 Q6_P_aslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
5968 | Instruction Type: S_3op |
5969 | Execution Slots: SLOT23 |
5970 | ========================================================================== */ |
5971 | |
5972 | #define Q6_P_aslor_PR __builtin_HEXAGON_S2_asl_r_p_or |
5973 | |
5974 | /* ========================================================================== |
5975 | Assembly Syntax: Rxx32^=asl(Rss32,Rt32) |
5976 | C Intrinsic Prototype: Word64 Q6_P_aslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
5977 | Instruction Type: S_3op |
5978 | Execution Slots: SLOT23 |
5979 | ========================================================================== */ |
5980 | |
5981 | #define Q6_P_aslxacc_PR __builtin_HEXAGON_S2_asl_r_p_xor |
5982 | |
5983 | /* ========================================================================== |
5984 | Assembly Syntax: Rd32=asl(Rs32,Rt32) |
5985 | C Intrinsic Prototype: Word32 Q6_R_asl_RR(Word32 Rs, Word32 Rt) |
5986 | Instruction Type: S_3op |
5987 | Execution Slots: SLOT23 |
5988 | ========================================================================== */ |
5989 | |
5990 | #define Q6_R_asl_RR __builtin_HEXAGON_S2_asl_r_r |
5991 | |
5992 | /* ========================================================================== |
5993 | Assembly Syntax: Rx32+=asl(Rs32,Rt32) |
5994 | C Intrinsic Prototype: Word32 Q6_R_aslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
5995 | Instruction Type: S_3op |
5996 | Execution Slots: SLOT23 |
5997 | ========================================================================== */ |
5998 | |
5999 | #define Q6_R_aslacc_RR __builtin_HEXAGON_S2_asl_r_r_acc |
6000 | |
6001 | /* ========================================================================== |
6002 | Assembly Syntax: Rx32&=asl(Rs32,Rt32) |
6003 | C Intrinsic Prototype: Word32 Q6_R_asland_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6004 | Instruction Type: S_3op |
6005 | Execution Slots: SLOT23 |
6006 | ========================================================================== */ |
6007 | |
6008 | #define Q6_R_asland_RR __builtin_HEXAGON_S2_asl_r_r_and |
6009 | |
6010 | /* ========================================================================== |
6011 | Assembly Syntax: Rx32-=asl(Rs32,Rt32) |
6012 | C Intrinsic Prototype: Word32 Q6_R_aslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6013 | Instruction Type: S_3op |
6014 | Execution Slots: SLOT23 |
6015 | ========================================================================== */ |
6016 | |
6017 | #define Q6_R_aslnac_RR __builtin_HEXAGON_S2_asl_r_r_nac |
6018 | |
6019 | /* ========================================================================== |
6020 | Assembly Syntax: Rx32|=asl(Rs32,Rt32) |
6021 | C Intrinsic Prototype: Word32 Q6_R_aslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6022 | Instruction Type: S_3op |
6023 | Execution Slots: SLOT23 |
6024 | ========================================================================== */ |
6025 | |
6026 | #define Q6_R_aslor_RR __builtin_HEXAGON_S2_asl_r_r_or |
6027 | |
6028 | /* ========================================================================== |
6029 | Assembly Syntax: Rd32=asl(Rs32,Rt32):sat |
6030 | C Intrinsic Prototype: Word32 Q6_R_asl_RR_sat(Word32 Rs, Word32 Rt) |
6031 | Instruction Type: S_3op |
6032 | Execution Slots: SLOT23 |
6033 | ========================================================================== */ |
6034 | |
6035 | #define Q6_R_asl_RR_sat __builtin_HEXAGON_S2_asl_r_r_sat |
6036 | |
6037 | /* ========================================================================== |
6038 | Assembly Syntax: Rdd32=vaslh(Rss32,Rt32) |
6039 | C Intrinsic Prototype: Word64 Q6_P_vaslh_PR(Word64 Rss, Word32 Rt) |
6040 | Instruction Type: S_3op |
6041 | Execution Slots: SLOT23 |
6042 | ========================================================================== */ |
6043 | |
6044 | #define Q6_P_vaslh_PR __builtin_HEXAGON_S2_asl_r_vh |
6045 | |
6046 | /* ========================================================================== |
6047 | Assembly Syntax: Rdd32=vaslw(Rss32,Rt32) |
6048 | C Intrinsic Prototype: Word64 Q6_P_vaslw_PR(Word64 Rss, Word32 Rt) |
6049 | Instruction Type: S_3op |
6050 | Execution Slots: SLOT23 |
6051 | ========================================================================== */ |
6052 | |
6053 | #define Q6_P_vaslw_PR __builtin_HEXAGON_S2_asl_r_vw |
6054 | |
6055 | /* ========================================================================== |
6056 | Assembly Syntax: Rdd32=asr(Rss32,#u6) |
6057 | C Intrinsic Prototype: Word64 Q6_P_asr_PI(Word64 Rss, Word32 Iu6) |
6058 | Instruction Type: S_2op |
6059 | Execution Slots: SLOT23 |
6060 | ========================================================================== */ |
6061 | |
6062 | #define Q6_P_asr_PI __builtin_HEXAGON_S2_asr_i_p |
6063 | |
6064 | /* ========================================================================== |
6065 | Assembly Syntax: Rxx32+=asr(Rss32,#u6) |
6066 | C Intrinsic Prototype: Word64 Q6_P_asracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6067 | Instruction Type: S_2op |
6068 | Execution Slots: SLOT23 |
6069 | ========================================================================== */ |
6070 | |
6071 | #define Q6_P_asracc_PI __builtin_HEXAGON_S2_asr_i_p_acc |
6072 | |
6073 | /* ========================================================================== |
6074 | Assembly Syntax: Rxx32&=asr(Rss32,#u6) |
6075 | C Intrinsic Prototype: Word64 Q6_P_asrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6076 | Instruction Type: S_2op |
6077 | Execution Slots: SLOT23 |
6078 | ========================================================================== */ |
6079 | |
6080 | #define Q6_P_asrand_PI __builtin_HEXAGON_S2_asr_i_p_and |
6081 | |
6082 | /* ========================================================================== |
6083 | Assembly Syntax: Rxx32-=asr(Rss32,#u6) |
6084 | C Intrinsic Prototype: Word64 Q6_P_asrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6085 | Instruction Type: S_2op |
6086 | Execution Slots: SLOT23 |
6087 | ========================================================================== */ |
6088 | |
6089 | #define Q6_P_asrnac_PI __builtin_HEXAGON_S2_asr_i_p_nac |
6090 | |
6091 | /* ========================================================================== |
6092 | Assembly Syntax: Rxx32|=asr(Rss32,#u6) |
6093 | C Intrinsic Prototype: Word64 Q6_P_asror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6094 | Instruction Type: S_2op |
6095 | Execution Slots: SLOT23 |
6096 | ========================================================================== */ |
6097 | |
6098 | #define Q6_P_asror_PI __builtin_HEXAGON_S2_asr_i_p_or |
6099 | |
6100 | /* ========================================================================== |
6101 | Assembly Syntax: Rdd32=asr(Rss32,#u6):rnd |
6102 | C Intrinsic Prototype: Word64 Q6_P_asr_PI_rnd(Word64 Rss, Word32 Iu6) |
6103 | Instruction Type: S_2op |
6104 | Execution Slots: SLOT23 |
6105 | ========================================================================== */ |
6106 | |
6107 | #define Q6_P_asr_PI_rnd __builtin_HEXAGON_S2_asr_i_p_rnd |
6108 | |
6109 | /* ========================================================================== |
6110 | Assembly Syntax: Rdd32=asrrnd(Rss32,#u6) |
6111 | C Intrinsic Prototype: Word64 Q6_P_asrrnd_PI(Word64 Rss, Word32 Iu6) |
6112 | Instruction Type: S_2op |
6113 | Execution Slots: SLOT0123 |
6114 | ========================================================================== */ |
6115 | |
6116 | #define Q6_P_asrrnd_PI __builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax |
6117 | |
6118 | /* ========================================================================== |
6119 | Assembly Syntax: Rd32=asr(Rs32,#u5) |
6120 | C Intrinsic Prototype: Word32 Q6_R_asr_RI(Word32 Rs, Word32 Iu5) |
6121 | Instruction Type: S_2op |
6122 | Execution Slots: SLOT23 |
6123 | ========================================================================== */ |
6124 | |
6125 | #define Q6_R_asr_RI __builtin_HEXAGON_S2_asr_i_r |
6126 | |
6127 | /* ========================================================================== |
6128 | Assembly Syntax: Rx32+=asr(Rs32,#u5) |
6129 | C Intrinsic Prototype: Word32 Q6_R_asracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6130 | Instruction Type: S_2op |
6131 | Execution Slots: SLOT23 |
6132 | ========================================================================== */ |
6133 | |
6134 | #define Q6_R_asracc_RI __builtin_HEXAGON_S2_asr_i_r_acc |
6135 | |
6136 | /* ========================================================================== |
6137 | Assembly Syntax: Rx32&=asr(Rs32,#u5) |
6138 | C Intrinsic Prototype: Word32 Q6_R_asrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6139 | Instruction Type: S_2op |
6140 | Execution Slots: SLOT23 |
6141 | ========================================================================== */ |
6142 | |
6143 | #define Q6_R_asrand_RI __builtin_HEXAGON_S2_asr_i_r_and |
6144 | |
6145 | /* ========================================================================== |
6146 | Assembly Syntax: Rx32-=asr(Rs32,#u5) |
6147 | C Intrinsic Prototype: Word32 Q6_R_asrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6148 | Instruction Type: S_2op |
6149 | Execution Slots: SLOT23 |
6150 | ========================================================================== */ |
6151 | |
6152 | #define Q6_R_asrnac_RI __builtin_HEXAGON_S2_asr_i_r_nac |
6153 | |
6154 | /* ========================================================================== |
6155 | Assembly Syntax: Rx32|=asr(Rs32,#u5) |
6156 | C Intrinsic Prototype: Word32 Q6_R_asror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6157 | Instruction Type: S_2op |
6158 | Execution Slots: SLOT23 |
6159 | ========================================================================== */ |
6160 | |
6161 | #define Q6_R_asror_RI __builtin_HEXAGON_S2_asr_i_r_or |
6162 | |
6163 | /* ========================================================================== |
6164 | Assembly Syntax: Rd32=asr(Rs32,#u5):rnd |
6165 | C Intrinsic Prototype: Word32 Q6_R_asr_RI_rnd(Word32 Rs, Word32 Iu5) |
6166 | Instruction Type: S_2op |
6167 | Execution Slots: SLOT23 |
6168 | ========================================================================== */ |
6169 | |
6170 | #define Q6_R_asr_RI_rnd __builtin_HEXAGON_S2_asr_i_r_rnd |
6171 | |
6172 | /* ========================================================================== |
6173 | Assembly Syntax: Rd32=asrrnd(Rs32,#u5) |
6174 | C Intrinsic Prototype: Word32 Q6_R_asrrnd_RI(Word32 Rs, Word32 Iu5) |
6175 | Instruction Type: S_2op |
6176 | Execution Slots: SLOT0123 |
6177 | ========================================================================== */ |
6178 | |
6179 | #define Q6_R_asrrnd_RI __builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax |
6180 | |
6181 | /* ========================================================================== |
6182 | Assembly Syntax: Rd32=vasrw(Rss32,#u5) |
6183 | C Intrinsic Prototype: Word32 Q6_R_vasrw_PI(Word64 Rss, Word32 Iu5) |
6184 | Instruction Type: S_2op |
6185 | Execution Slots: SLOT23 |
6186 | ========================================================================== */ |
6187 | |
6188 | #define Q6_R_vasrw_PI __builtin_HEXAGON_S2_asr_i_svw_trun |
6189 | |
6190 | /* ========================================================================== |
6191 | Assembly Syntax: Rdd32=vasrh(Rss32,#u4) |
6192 | C Intrinsic Prototype: Word64 Q6_P_vasrh_PI(Word64 Rss, Word32 Iu4) |
6193 | Instruction Type: S_2op |
6194 | Execution Slots: SLOT23 |
6195 | ========================================================================== */ |
6196 | |
6197 | #define Q6_P_vasrh_PI __builtin_HEXAGON_S2_asr_i_vh |
6198 | |
6199 | /* ========================================================================== |
6200 | Assembly Syntax: Rdd32=vasrw(Rss32,#u5) |
6201 | C Intrinsic Prototype: Word64 Q6_P_vasrw_PI(Word64 Rss, Word32 Iu5) |
6202 | Instruction Type: S_2op |
6203 | Execution Slots: SLOT23 |
6204 | ========================================================================== */ |
6205 | |
6206 | #define Q6_P_vasrw_PI __builtin_HEXAGON_S2_asr_i_vw |
6207 | |
6208 | /* ========================================================================== |
6209 | Assembly Syntax: Rdd32=asr(Rss32,Rt32) |
6210 | C Intrinsic Prototype: Word64 Q6_P_asr_PR(Word64 Rss, Word32 Rt) |
6211 | Instruction Type: S_3op |
6212 | Execution Slots: SLOT23 |
6213 | ========================================================================== */ |
6214 | |
6215 | #define Q6_P_asr_PR __builtin_HEXAGON_S2_asr_r_p |
6216 | |
6217 | /* ========================================================================== |
6218 | Assembly Syntax: Rxx32+=asr(Rss32,Rt32) |
6219 | C Intrinsic Prototype: Word64 Q6_P_asracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6220 | Instruction Type: S_3op |
6221 | Execution Slots: SLOT23 |
6222 | ========================================================================== */ |
6223 | |
6224 | #define Q6_P_asracc_PR __builtin_HEXAGON_S2_asr_r_p_acc |
6225 | |
6226 | /* ========================================================================== |
6227 | Assembly Syntax: Rxx32&=asr(Rss32,Rt32) |
6228 | C Intrinsic Prototype: Word64 Q6_P_asrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6229 | Instruction Type: S_3op |
6230 | Execution Slots: SLOT23 |
6231 | ========================================================================== */ |
6232 | |
6233 | #define Q6_P_asrand_PR __builtin_HEXAGON_S2_asr_r_p_and |
6234 | |
6235 | /* ========================================================================== |
6236 | Assembly Syntax: Rxx32-=asr(Rss32,Rt32) |
6237 | C Intrinsic Prototype: Word64 Q6_P_asrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6238 | Instruction Type: S_3op |
6239 | Execution Slots: SLOT23 |
6240 | ========================================================================== */ |
6241 | |
6242 | #define Q6_P_asrnac_PR __builtin_HEXAGON_S2_asr_r_p_nac |
6243 | |
6244 | /* ========================================================================== |
6245 | Assembly Syntax: Rxx32|=asr(Rss32,Rt32) |
6246 | C Intrinsic Prototype: Word64 Q6_P_asror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6247 | Instruction Type: S_3op |
6248 | Execution Slots: SLOT23 |
6249 | ========================================================================== */ |
6250 | |
6251 | #define Q6_P_asror_PR __builtin_HEXAGON_S2_asr_r_p_or |
6252 | |
6253 | /* ========================================================================== |
6254 | Assembly Syntax: Rxx32^=asr(Rss32,Rt32) |
6255 | C Intrinsic Prototype: Word64 Q6_P_asrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6256 | Instruction Type: S_3op |
6257 | Execution Slots: SLOT23 |
6258 | ========================================================================== */ |
6259 | |
6260 | #define Q6_P_asrxacc_PR __builtin_HEXAGON_S2_asr_r_p_xor |
6261 | |
6262 | /* ========================================================================== |
6263 | Assembly Syntax: Rd32=asr(Rs32,Rt32) |
6264 | C Intrinsic Prototype: Word32 Q6_R_asr_RR(Word32 Rs, Word32 Rt) |
6265 | Instruction Type: S_3op |
6266 | Execution Slots: SLOT23 |
6267 | ========================================================================== */ |
6268 | |
6269 | #define Q6_R_asr_RR __builtin_HEXAGON_S2_asr_r_r |
6270 | |
6271 | /* ========================================================================== |
6272 | Assembly Syntax: Rx32+=asr(Rs32,Rt32) |
6273 | C Intrinsic Prototype: Word32 Q6_R_asracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6274 | Instruction Type: S_3op |
6275 | Execution Slots: SLOT23 |
6276 | ========================================================================== */ |
6277 | |
6278 | #define Q6_R_asracc_RR __builtin_HEXAGON_S2_asr_r_r_acc |
6279 | |
6280 | /* ========================================================================== |
6281 | Assembly Syntax: Rx32&=asr(Rs32,Rt32) |
6282 | C Intrinsic Prototype: Word32 Q6_R_asrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6283 | Instruction Type: S_3op |
6284 | Execution Slots: SLOT23 |
6285 | ========================================================================== */ |
6286 | |
6287 | #define Q6_R_asrand_RR __builtin_HEXAGON_S2_asr_r_r_and |
6288 | |
6289 | /* ========================================================================== |
6290 | Assembly Syntax: Rx32-=asr(Rs32,Rt32) |
6291 | C Intrinsic Prototype: Word32 Q6_R_asrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6292 | Instruction Type: S_3op |
6293 | Execution Slots: SLOT23 |
6294 | ========================================================================== */ |
6295 | |
6296 | #define Q6_R_asrnac_RR __builtin_HEXAGON_S2_asr_r_r_nac |
6297 | |
6298 | /* ========================================================================== |
6299 | Assembly Syntax: Rx32|=asr(Rs32,Rt32) |
6300 | C Intrinsic Prototype: Word32 Q6_R_asror_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6301 | Instruction Type: S_3op |
6302 | Execution Slots: SLOT23 |
6303 | ========================================================================== */ |
6304 | |
6305 | #define Q6_R_asror_RR __builtin_HEXAGON_S2_asr_r_r_or |
6306 | |
6307 | /* ========================================================================== |
6308 | Assembly Syntax: Rd32=asr(Rs32,Rt32):sat |
6309 | C Intrinsic Prototype: Word32 Q6_R_asr_RR_sat(Word32 Rs, Word32 Rt) |
6310 | Instruction Type: S_3op |
6311 | Execution Slots: SLOT23 |
6312 | ========================================================================== */ |
6313 | |
6314 | #define Q6_R_asr_RR_sat __builtin_HEXAGON_S2_asr_r_r_sat |
6315 | |
6316 | /* ========================================================================== |
6317 | Assembly Syntax: Rd32=vasrw(Rss32,Rt32) |
6318 | C Intrinsic Prototype: Word32 Q6_R_vasrw_PR(Word64 Rss, Word32 Rt) |
6319 | Instruction Type: S_3op |
6320 | Execution Slots: SLOT23 |
6321 | ========================================================================== */ |
6322 | |
6323 | #define Q6_R_vasrw_PR __builtin_HEXAGON_S2_asr_r_svw_trun |
6324 | |
6325 | /* ========================================================================== |
6326 | Assembly Syntax: Rdd32=vasrh(Rss32,Rt32) |
6327 | C Intrinsic Prototype: Word64 Q6_P_vasrh_PR(Word64 Rss, Word32 Rt) |
6328 | Instruction Type: S_3op |
6329 | Execution Slots: SLOT23 |
6330 | ========================================================================== */ |
6331 | |
6332 | #define Q6_P_vasrh_PR __builtin_HEXAGON_S2_asr_r_vh |
6333 | |
6334 | /* ========================================================================== |
6335 | Assembly Syntax: Rdd32=vasrw(Rss32,Rt32) |
6336 | C Intrinsic Prototype: Word64 Q6_P_vasrw_PR(Word64 Rss, Word32 Rt) |
6337 | Instruction Type: S_3op |
6338 | Execution Slots: SLOT23 |
6339 | ========================================================================== */ |
6340 | |
6341 | #define Q6_P_vasrw_PR __builtin_HEXAGON_S2_asr_r_vw |
6342 | |
6343 | /* ========================================================================== |
6344 | Assembly Syntax: Rd32=brev(Rs32) |
6345 | C Intrinsic Prototype: Word32 Q6_R_brev_R(Word32 Rs) |
6346 | Instruction Type: S_2op |
6347 | Execution Slots: SLOT23 |
6348 | ========================================================================== */ |
6349 | |
6350 | #define Q6_R_brev_R __builtin_HEXAGON_S2_brev |
6351 | |
6352 | /* ========================================================================== |
6353 | Assembly Syntax: Rdd32=brev(Rss32) |
6354 | C Intrinsic Prototype: Word64 Q6_P_brev_P(Word64 Rss) |
6355 | Instruction Type: S_2op |
6356 | Execution Slots: SLOT23 |
6357 | ========================================================================== */ |
6358 | |
6359 | #define Q6_P_brev_P __builtin_HEXAGON_S2_brevp |
6360 | |
6361 | /* ========================================================================== |
6362 | Assembly Syntax: Rd32=cl0(Rs32) |
6363 | C Intrinsic Prototype: Word32 Q6_R_cl0_R(Word32 Rs) |
6364 | Instruction Type: S_2op |
6365 | Execution Slots: SLOT23 |
6366 | ========================================================================== */ |
6367 | |
6368 | #define Q6_R_cl0_R __builtin_HEXAGON_S2_cl0 |
6369 | |
6370 | /* ========================================================================== |
6371 | Assembly Syntax: Rd32=cl0(Rss32) |
6372 | C Intrinsic Prototype: Word32 Q6_R_cl0_P(Word64 Rss) |
6373 | Instruction Type: S_2op |
6374 | Execution Slots: SLOT23 |
6375 | ========================================================================== */ |
6376 | |
6377 | #define Q6_R_cl0_P __builtin_HEXAGON_S2_cl0p |
6378 | |
6379 | /* ========================================================================== |
6380 | Assembly Syntax: Rd32=cl1(Rs32) |
6381 | C Intrinsic Prototype: Word32 Q6_R_cl1_R(Word32 Rs) |
6382 | Instruction Type: S_2op |
6383 | Execution Slots: SLOT23 |
6384 | ========================================================================== */ |
6385 | |
6386 | #define Q6_R_cl1_R __builtin_HEXAGON_S2_cl1 |
6387 | |
6388 | /* ========================================================================== |
6389 | Assembly Syntax: Rd32=cl1(Rss32) |
6390 | C Intrinsic Prototype: Word32 Q6_R_cl1_P(Word64 Rss) |
6391 | Instruction Type: S_2op |
6392 | Execution Slots: SLOT23 |
6393 | ========================================================================== */ |
6394 | |
6395 | #define Q6_R_cl1_P __builtin_HEXAGON_S2_cl1p |
6396 | |
6397 | /* ========================================================================== |
6398 | Assembly Syntax: Rd32=clb(Rs32) |
6399 | C Intrinsic Prototype: Word32 Q6_R_clb_R(Word32 Rs) |
6400 | Instruction Type: S_2op |
6401 | Execution Slots: SLOT23 |
6402 | ========================================================================== */ |
6403 | |
6404 | #define Q6_R_clb_R __builtin_HEXAGON_S2_clb |
6405 | |
6406 | /* ========================================================================== |
6407 | Assembly Syntax: Rd32=normamt(Rs32) |
6408 | C Intrinsic Prototype: Word32 Q6_R_normamt_R(Word32 Rs) |
6409 | Instruction Type: S_2op |
6410 | Execution Slots: SLOT23 |
6411 | ========================================================================== */ |
6412 | |
6413 | #define Q6_R_normamt_R __builtin_HEXAGON_S2_clbnorm |
6414 | |
6415 | /* ========================================================================== |
6416 | Assembly Syntax: Rd32=clb(Rss32) |
6417 | C Intrinsic Prototype: Word32 Q6_R_clb_P(Word64 Rss) |
6418 | Instruction Type: S_2op |
6419 | Execution Slots: SLOT23 |
6420 | ========================================================================== */ |
6421 | |
6422 | #define Q6_R_clb_P __builtin_HEXAGON_S2_clbp |
6423 | |
6424 | /* ========================================================================== |
6425 | Assembly Syntax: Rd32=clrbit(Rs32,#u5) |
6426 | C Intrinsic Prototype: Word32 Q6_R_clrbit_RI(Word32 Rs, Word32 Iu5) |
6427 | Instruction Type: S_2op |
6428 | Execution Slots: SLOT23 |
6429 | ========================================================================== */ |
6430 | |
6431 | #define Q6_R_clrbit_RI __builtin_HEXAGON_S2_clrbit_i |
6432 | |
6433 | /* ========================================================================== |
6434 | Assembly Syntax: Rd32=clrbit(Rs32,Rt32) |
6435 | C Intrinsic Prototype: Word32 Q6_R_clrbit_RR(Word32 Rs, Word32 Rt) |
6436 | Instruction Type: S_3op |
6437 | Execution Slots: SLOT23 |
6438 | ========================================================================== */ |
6439 | |
6440 | #define Q6_R_clrbit_RR __builtin_HEXAGON_S2_clrbit_r |
6441 | |
6442 | /* ========================================================================== |
6443 | Assembly Syntax: Rd32=ct0(Rs32) |
6444 | C Intrinsic Prototype: Word32 Q6_R_ct0_R(Word32 Rs) |
6445 | Instruction Type: S_2op |
6446 | Execution Slots: SLOT23 |
6447 | ========================================================================== */ |
6448 | |
6449 | #define Q6_R_ct0_R __builtin_HEXAGON_S2_ct0 |
6450 | |
6451 | /* ========================================================================== |
6452 | Assembly Syntax: Rd32=ct0(Rss32) |
6453 | C Intrinsic Prototype: Word32 Q6_R_ct0_P(Word64 Rss) |
6454 | Instruction Type: S_2op |
6455 | Execution Slots: SLOT23 |
6456 | ========================================================================== */ |
6457 | |
6458 | #define Q6_R_ct0_P __builtin_HEXAGON_S2_ct0p |
6459 | |
6460 | /* ========================================================================== |
6461 | Assembly Syntax: Rd32=ct1(Rs32) |
6462 | C Intrinsic Prototype: Word32 Q6_R_ct1_R(Word32 Rs) |
6463 | Instruction Type: S_2op |
6464 | Execution Slots: SLOT23 |
6465 | ========================================================================== */ |
6466 | |
6467 | #define Q6_R_ct1_R __builtin_HEXAGON_S2_ct1 |
6468 | |
6469 | /* ========================================================================== |
6470 | Assembly Syntax: Rd32=ct1(Rss32) |
6471 | C Intrinsic Prototype: Word32 Q6_R_ct1_P(Word64 Rss) |
6472 | Instruction Type: S_2op |
6473 | Execution Slots: SLOT23 |
6474 | ========================================================================== */ |
6475 | |
6476 | #define Q6_R_ct1_P __builtin_HEXAGON_S2_ct1p |
6477 | |
6478 | /* ========================================================================== |
6479 | Assembly Syntax: Rdd32=deinterleave(Rss32) |
6480 | C Intrinsic Prototype: Word64 Q6_P_deinterleave_P(Word64 Rss) |
6481 | Instruction Type: S_2op |
6482 | Execution Slots: SLOT23 |
6483 | ========================================================================== */ |
6484 | |
6485 | #define Q6_P_deinterleave_P __builtin_HEXAGON_S2_deinterleave |
6486 | |
6487 | /* ========================================================================== |
6488 | Assembly Syntax: Rd32=extractu(Rs32,#u5,#U5) |
6489 | C Intrinsic Prototype: Word32 Q6_R_extractu_RII(Word32 Rs, Word32 Iu5, Word32 IU5) |
6490 | Instruction Type: S_2op |
6491 | Execution Slots: SLOT23 |
6492 | ========================================================================== */ |
6493 | |
6494 | #define Q6_R_extractu_RII __builtin_HEXAGON_S2_extractu |
6495 | |
6496 | /* ========================================================================== |
6497 | Assembly Syntax: Rd32=extractu(Rs32,Rtt32) |
6498 | C Intrinsic Prototype: Word32 Q6_R_extractu_RP(Word32 Rs, Word64 Rtt) |
6499 | Instruction Type: S_3op |
6500 | Execution Slots: SLOT23 |
6501 | ========================================================================== */ |
6502 | |
6503 | #define Q6_R_extractu_RP __builtin_HEXAGON_S2_extractu_rp |
6504 | |
6505 | /* ========================================================================== |
6506 | Assembly Syntax: Rdd32=extractu(Rss32,#u6,#U6) |
6507 | C Intrinsic Prototype: Word64 Q6_P_extractu_PII(Word64 Rss, Word32 Iu6, Word32 IU6) |
6508 | Instruction Type: S_2op |
6509 | Execution Slots: SLOT23 |
6510 | ========================================================================== */ |
6511 | |
6512 | #define Q6_P_extractu_PII __builtin_HEXAGON_S2_extractup |
6513 | |
6514 | /* ========================================================================== |
6515 | Assembly Syntax: Rdd32=extractu(Rss32,Rtt32) |
6516 | C Intrinsic Prototype: Word64 Q6_P_extractu_PP(Word64 Rss, Word64 Rtt) |
6517 | Instruction Type: S_3op |
6518 | Execution Slots: SLOT23 |
6519 | ========================================================================== */ |
6520 | |
6521 | #define Q6_P_extractu_PP __builtin_HEXAGON_S2_extractup_rp |
6522 | |
6523 | /* ========================================================================== |
6524 | Assembly Syntax: Rx32=insert(Rs32,#u5,#U5) |
6525 | C Intrinsic Prototype: Word32 Q6_R_insert_RII(Word32 Rx, Word32 Rs, Word32 Iu5, Word32 IU5) |
6526 | Instruction Type: S_2op |
6527 | Execution Slots: SLOT23 |
6528 | ========================================================================== */ |
6529 | |
6530 | #define Q6_R_insert_RII __builtin_HEXAGON_S2_insert |
6531 | |
6532 | /* ========================================================================== |
6533 | Assembly Syntax: Rx32=insert(Rs32,Rtt32) |
6534 | C Intrinsic Prototype: Word32 Q6_R_insert_RP(Word32 Rx, Word32 Rs, Word64 Rtt) |
6535 | Instruction Type: S_3op |
6536 | Execution Slots: SLOT23 |
6537 | ========================================================================== */ |
6538 | |
6539 | #define Q6_R_insert_RP __builtin_HEXAGON_S2_insert_rp |
6540 | |
6541 | /* ========================================================================== |
6542 | Assembly Syntax: Rxx32=insert(Rss32,#u6,#U6) |
6543 | C Intrinsic Prototype: Word64 Q6_P_insert_PII(Word64 Rxx, Word64 Rss, Word32 Iu6, Word32 IU6) |
6544 | Instruction Type: S_2op |
6545 | Execution Slots: SLOT23 |
6546 | ========================================================================== */ |
6547 | |
6548 | #define Q6_P_insert_PII __builtin_HEXAGON_S2_insertp |
6549 | |
6550 | /* ========================================================================== |
6551 | Assembly Syntax: Rxx32=insert(Rss32,Rtt32) |
6552 | C Intrinsic Prototype: Word64 Q6_P_insert_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
6553 | Instruction Type: S_3op |
6554 | Execution Slots: SLOT23 |
6555 | ========================================================================== */ |
6556 | |
6557 | #define Q6_P_insert_PP __builtin_HEXAGON_S2_insertp_rp |
6558 | |
6559 | /* ========================================================================== |
6560 | Assembly Syntax: Rdd32=interleave(Rss32) |
6561 | C Intrinsic Prototype: Word64 Q6_P_interleave_P(Word64 Rss) |
6562 | Instruction Type: S_2op |
6563 | Execution Slots: SLOT23 |
6564 | ========================================================================== */ |
6565 | |
6566 | #define Q6_P_interleave_P __builtin_HEXAGON_S2_interleave |
6567 | |
6568 | /* ========================================================================== |
6569 | Assembly Syntax: Rdd32=lfs(Rss32,Rtt32) |
6570 | C Intrinsic Prototype: Word64 Q6_P_lfs_PP(Word64 Rss, Word64 Rtt) |
6571 | Instruction Type: S_3op |
6572 | Execution Slots: SLOT23 |
6573 | ========================================================================== */ |
6574 | |
6575 | #define Q6_P_lfs_PP __builtin_HEXAGON_S2_lfsp |
6576 | |
6577 | /* ========================================================================== |
6578 | Assembly Syntax: Rdd32=lsl(Rss32,Rt32) |
6579 | C Intrinsic Prototype: Word64 Q6_P_lsl_PR(Word64 Rss, Word32 Rt) |
6580 | Instruction Type: S_3op |
6581 | Execution Slots: SLOT23 |
6582 | ========================================================================== */ |
6583 | |
6584 | #define Q6_P_lsl_PR __builtin_HEXAGON_S2_lsl_r_p |
6585 | |
6586 | /* ========================================================================== |
6587 | Assembly Syntax: Rxx32+=lsl(Rss32,Rt32) |
6588 | C Intrinsic Prototype: Word64 Q6_P_lslacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6589 | Instruction Type: S_3op |
6590 | Execution Slots: SLOT23 |
6591 | ========================================================================== */ |
6592 | |
6593 | #define Q6_P_lslacc_PR __builtin_HEXAGON_S2_lsl_r_p_acc |
6594 | |
6595 | /* ========================================================================== |
6596 | Assembly Syntax: Rxx32&=lsl(Rss32,Rt32) |
6597 | C Intrinsic Prototype: Word64 Q6_P_lsland_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6598 | Instruction Type: S_3op |
6599 | Execution Slots: SLOT23 |
6600 | ========================================================================== */ |
6601 | |
6602 | #define Q6_P_lsland_PR __builtin_HEXAGON_S2_lsl_r_p_and |
6603 | |
6604 | /* ========================================================================== |
6605 | Assembly Syntax: Rxx32-=lsl(Rss32,Rt32) |
6606 | C Intrinsic Prototype: Word64 Q6_P_lslnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6607 | Instruction Type: S_3op |
6608 | Execution Slots: SLOT23 |
6609 | ========================================================================== */ |
6610 | |
6611 | #define Q6_P_lslnac_PR __builtin_HEXAGON_S2_lsl_r_p_nac |
6612 | |
6613 | /* ========================================================================== |
6614 | Assembly Syntax: Rxx32|=lsl(Rss32,Rt32) |
6615 | C Intrinsic Prototype: Word64 Q6_P_lslor_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6616 | Instruction Type: S_3op |
6617 | Execution Slots: SLOT23 |
6618 | ========================================================================== */ |
6619 | |
6620 | #define Q6_P_lslor_PR __builtin_HEXAGON_S2_lsl_r_p_or |
6621 | |
6622 | /* ========================================================================== |
6623 | Assembly Syntax: Rxx32^=lsl(Rss32,Rt32) |
6624 | C Intrinsic Prototype: Word64 Q6_P_lslxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6625 | Instruction Type: S_3op |
6626 | Execution Slots: SLOT23 |
6627 | ========================================================================== */ |
6628 | |
6629 | #define Q6_P_lslxacc_PR __builtin_HEXAGON_S2_lsl_r_p_xor |
6630 | |
6631 | /* ========================================================================== |
6632 | Assembly Syntax: Rd32=lsl(Rs32,Rt32) |
6633 | C Intrinsic Prototype: Word32 Q6_R_lsl_RR(Word32 Rs, Word32 Rt) |
6634 | Instruction Type: S_3op |
6635 | Execution Slots: SLOT23 |
6636 | ========================================================================== */ |
6637 | |
6638 | #define Q6_R_lsl_RR __builtin_HEXAGON_S2_lsl_r_r |
6639 | |
6640 | /* ========================================================================== |
6641 | Assembly Syntax: Rx32+=lsl(Rs32,Rt32) |
6642 | C Intrinsic Prototype: Word32 Q6_R_lslacc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6643 | Instruction Type: S_3op |
6644 | Execution Slots: SLOT23 |
6645 | ========================================================================== */ |
6646 | |
6647 | #define Q6_R_lslacc_RR __builtin_HEXAGON_S2_lsl_r_r_acc |
6648 | |
6649 | /* ========================================================================== |
6650 | Assembly Syntax: Rx32&=lsl(Rs32,Rt32) |
6651 | C Intrinsic Prototype: Word32 Q6_R_lsland_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6652 | Instruction Type: S_3op |
6653 | Execution Slots: SLOT23 |
6654 | ========================================================================== */ |
6655 | |
6656 | #define Q6_R_lsland_RR __builtin_HEXAGON_S2_lsl_r_r_and |
6657 | |
6658 | /* ========================================================================== |
6659 | Assembly Syntax: Rx32-=lsl(Rs32,Rt32) |
6660 | C Intrinsic Prototype: Word32 Q6_R_lslnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6661 | Instruction Type: S_3op |
6662 | Execution Slots: SLOT23 |
6663 | ========================================================================== */ |
6664 | |
6665 | #define Q6_R_lslnac_RR __builtin_HEXAGON_S2_lsl_r_r_nac |
6666 | |
6667 | /* ========================================================================== |
6668 | Assembly Syntax: Rx32|=lsl(Rs32,Rt32) |
6669 | C Intrinsic Prototype: Word32 Q6_R_lslor_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6670 | Instruction Type: S_3op |
6671 | Execution Slots: SLOT23 |
6672 | ========================================================================== */ |
6673 | |
6674 | #define Q6_R_lslor_RR __builtin_HEXAGON_S2_lsl_r_r_or |
6675 | |
6676 | /* ========================================================================== |
6677 | Assembly Syntax: Rdd32=vlslh(Rss32,Rt32) |
6678 | C Intrinsic Prototype: Word64 Q6_P_vlslh_PR(Word64 Rss, Word32 Rt) |
6679 | Instruction Type: S_3op |
6680 | Execution Slots: SLOT23 |
6681 | ========================================================================== */ |
6682 | |
6683 | #define Q6_P_vlslh_PR __builtin_HEXAGON_S2_lsl_r_vh |
6684 | |
6685 | /* ========================================================================== |
6686 | Assembly Syntax: Rdd32=vlslw(Rss32,Rt32) |
6687 | C Intrinsic Prototype: Word64 Q6_P_vlslw_PR(Word64 Rss, Word32 Rt) |
6688 | Instruction Type: S_3op |
6689 | Execution Slots: SLOT23 |
6690 | ========================================================================== */ |
6691 | |
6692 | #define Q6_P_vlslw_PR __builtin_HEXAGON_S2_lsl_r_vw |
6693 | |
6694 | /* ========================================================================== |
6695 | Assembly Syntax: Rdd32=lsr(Rss32,#u6) |
6696 | C Intrinsic Prototype: Word64 Q6_P_lsr_PI(Word64 Rss, Word32 Iu6) |
6697 | Instruction Type: S_2op |
6698 | Execution Slots: SLOT23 |
6699 | ========================================================================== */ |
6700 | |
6701 | #define Q6_P_lsr_PI __builtin_HEXAGON_S2_lsr_i_p |
6702 | |
6703 | /* ========================================================================== |
6704 | Assembly Syntax: Rxx32+=lsr(Rss32,#u6) |
6705 | C Intrinsic Prototype: Word64 Q6_P_lsracc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6706 | Instruction Type: S_2op |
6707 | Execution Slots: SLOT23 |
6708 | ========================================================================== */ |
6709 | |
6710 | #define Q6_P_lsracc_PI __builtin_HEXAGON_S2_lsr_i_p_acc |
6711 | |
6712 | /* ========================================================================== |
6713 | Assembly Syntax: Rxx32&=lsr(Rss32,#u6) |
6714 | C Intrinsic Prototype: Word64 Q6_P_lsrand_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6715 | Instruction Type: S_2op |
6716 | Execution Slots: SLOT23 |
6717 | ========================================================================== */ |
6718 | |
6719 | #define Q6_P_lsrand_PI __builtin_HEXAGON_S2_lsr_i_p_and |
6720 | |
6721 | /* ========================================================================== |
6722 | Assembly Syntax: Rxx32-=lsr(Rss32,#u6) |
6723 | C Intrinsic Prototype: Word64 Q6_P_lsrnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6724 | Instruction Type: S_2op |
6725 | Execution Slots: SLOT23 |
6726 | ========================================================================== */ |
6727 | |
6728 | #define Q6_P_lsrnac_PI __builtin_HEXAGON_S2_lsr_i_p_nac |
6729 | |
6730 | /* ========================================================================== |
6731 | Assembly Syntax: Rxx32|=lsr(Rss32,#u6) |
6732 | C Intrinsic Prototype: Word64 Q6_P_lsror_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6733 | Instruction Type: S_2op |
6734 | Execution Slots: SLOT23 |
6735 | ========================================================================== */ |
6736 | |
6737 | #define Q6_P_lsror_PI __builtin_HEXAGON_S2_lsr_i_p_or |
6738 | |
6739 | /* ========================================================================== |
6740 | Assembly Syntax: Rxx32^=lsr(Rss32,#u6) |
6741 | C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
6742 | Instruction Type: S_2op |
6743 | Execution Slots: SLOT23 |
6744 | ========================================================================== */ |
6745 | |
6746 | #define Q6_P_lsrxacc_PI __builtin_HEXAGON_S2_lsr_i_p_xacc |
6747 | |
6748 | /* ========================================================================== |
6749 | Assembly Syntax: Rd32=lsr(Rs32,#u5) |
6750 | C Intrinsic Prototype: Word32 Q6_R_lsr_RI(Word32 Rs, Word32 Iu5) |
6751 | Instruction Type: S_2op |
6752 | Execution Slots: SLOT23 |
6753 | ========================================================================== */ |
6754 | |
6755 | #define Q6_R_lsr_RI __builtin_HEXAGON_S2_lsr_i_r |
6756 | |
6757 | /* ========================================================================== |
6758 | Assembly Syntax: Rx32+=lsr(Rs32,#u5) |
6759 | C Intrinsic Prototype: Word32 Q6_R_lsracc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6760 | Instruction Type: S_2op |
6761 | Execution Slots: SLOT23 |
6762 | ========================================================================== */ |
6763 | |
6764 | #define Q6_R_lsracc_RI __builtin_HEXAGON_S2_lsr_i_r_acc |
6765 | |
6766 | /* ========================================================================== |
6767 | Assembly Syntax: Rx32&=lsr(Rs32,#u5) |
6768 | C Intrinsic Prototype: Word32 Q6_R_lsrand_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6769 | Instruction Type: S_2op |
6770 | Execution Slots: SLOT23 |
6771 | ========================================================================== */ |
6772 | |
6773 | #define Q6_R_lsrand_RI __builtin_HEXAGON_S2_lsr_i_r_and |
6774 | |
6775 | /* ========================================================================== |
6776 | Assembly Syntax: Rx32-=lsr(Rs32,#u5) |
6777 | C Intrinsic Prototype: Word32 Q6_R_lsrnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6778 | Instruction Type: S_2op |
6779 | Execution Slots: SLOT23 |
6780 | ========================================================================== */ |
6781 | |
6782 | #define Q6_R_lsrnac_RI __builtin_HEXAGON_S2_lsr_i_r_nac |
6783 | |
6784 | /* ========================================================================== |
6785 | Assembly Syntax: Rx32|=lsr(Rs32,#u5) |
6786 | C Intrinsic Prototype: Word32 Q6_R_lsror_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6787 | Instruction Type: S_2op |
6788 | Execution Slots: SLOT23 |
6789 | ========================================================================== */ |
6790 | |
6791 | #define Q6_R_lsror_RI __builtin_HEXAGON_S2_lsr_i_r_or |
6792 | |
6793 | /* ========================================================================== |
6794 | Assembly Syntax: Rx32^=lsr(Rs32,#u5) |
6795 | C Intrinsic Prototype: Word32 Q6_R_lsrxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
6796 | Instruction Type: S_2op |
6797 | Execution Slots: SLOT23 |
6798 | ========================================================================== */ |
6799 | |
6800 | #define Q6_R_lsrxacc_RI __builtin_HEXAGON_S2_lsr_i_r_xacc |
6801 | |
6802 | /* ========================================================================== |
6803 | Assembly Syntax: Rdd32=vlsrh(Rss32,#u4) |
6804 | C Intrinsic Prototype: Word64 Q6_P_vlsrh_PI(Word64 Rss, Word32 Iu4) |
6805 | Instruction Type: S_2op |
6806 | Execution Slots: SLOT23 |
6807 | ========================================================================== */ |
6808 | |
6809 | #define Q6_P_vlsrh_PI __builtin_HEXAGON_S2_lsr_i_vh |
6810 | |
6811 | /* ========================================================================== |
6812 | Assembly Syntax: Rdd32=vlsrw(Rss32,#u5) |
6813 | C Intrinsic Prototype: Word64 Q6_P_vlsrw_PI(Word64 Rss, Word32 Iu5) |
6814 | Instruction Type: S_2op |
6815 | Execution Slots: SLOT23 |
6816 | ========================================================================== */ |
6817 | |
6818 | #define Q6_P_vlsrw_PI __builtin_HEXAGON_S2_lsr_i_vw |
6819 | |
6820 | /* ========================================================================== |
6821 | Assembly Syntax: Rdd32=lsr(Rss32,Rt32) |
6822 | C Intrinsic Prototype: Word64 Q6_P_lsr_PR(Word64 Rss, Word32 Rt) |
6823 | Instruction Type: S_3op |
6824 | Execution Slots: SLOT23 |
6825 | ========================================================================== */ |
6826 | |
6827 | #define Q6_P_lsr_PR __builtin_HEXAGON_S2_lsr_r_p |
6828 | |
6829 | /* ========================================================================== |
6830 | Assembly Syntax: Rxx32+=lsr(Rss32,Rt32) |
6831 | C Intrinsic Prototype: Word64 Q6_P_lsracc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6832 | Instruction Type: S_3op |
6833 | Execution Slots: SLOT23 |
6834 | ========================================================================== */ |
6835 | |
6836 | #define Q6_P_lsracc_PR __builtin_HEXAGON_S2_lsr_r_p_acc |
6837 | |
6838 | /* ========================================================================== |
6839 | Assembly Syntax: Rxx32&=lsr(Rss32,Rt32) |
6840 | C Intrinsic Prototype: Word64 Q6_P_lsrand_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6841 | Instruction Type: S_3op |
6842 | Execution Slots: SLOT23 |
6843 | ========================================================================== */ |
6844 | |
6845 | #define Q6_P_lsrand_PR __builtin_HEXAGON_S2_lsr_r_p_and |
6846 | |
6847 | /* ========================================================================== |
6848 | Assembly Syntax: Rxx32-=lsr(Rss32,Rt32) |
6849 | C Intrinsic Prototype: Word64 Q6_P_lsrnac_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6850 | Instruction Type: S_3op |
6851 | Execution Slots: SLOT23 |
6852 | ========================================================================== */ |
6853 | |
6854 | #define Q6_P_lsrnac_PR __builtin_HEXAGON_S2_lsr_r_p_nac |
6855 | |
6856 | /* ========================================================================== |
6857 | Assembly Syntax: Rxx32|=lsr(Rss32,Rt32) |
6858 | C Intrinsic Prototype: Word64 Q6_P_lsror_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6859 | Instruction Type: S_3op |
6860 | Execution Slots: SLOT23 |
6861 | ========================================================================== */ |
6862 | |
6863 | #define Q6_P_lsror_PR __builtin_HEXAGON_S2_lsr_r_p_or |
6864 | |
6865 | /* ========================================================================== |
6866 | Assembly Syntax: Rxx32^=lsr(Rss32,Rt32) |
6867 | C Intrinsic Prototype: Word64 Q6_P_lsrxacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
6868 | Instruction Type: S_3op |
6869 | Execution Slots: SLOT23 |
6870 | ========================================================================== */ |
6871 | |
6872 | #define Q6_P_lsrxacc_PR __builtin_HEXAGON_S2_lsr_r_p_xor |
6873 | |
6874 | /* ========================================================================== |
6875 | Assembly Syntax: Rd32=lsr(Rs32,Rt32) |
6876 | C Intrinsic Prototype: Word32 Q6_R_lsr_RR(Word32 Rs, Word32 Rt) |
6877 | Instruction Type: S_3op |
6878 | Execution Slots: SLOT23 |
6879 | ========================================================================== */ |
6880 | |
6881 | #define Q6_R_lsr_RR __builtin_HEXAGON_S2_lsr_r_r |
6882 | |
6883 | /* ========================================================================== |
6884 | Assembly Syntax: Rx32+=lsr(Rs32,Rt32) |
6885 | C Intrinsic Prototype: Word32 Q6_R_lsracc_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6886 | Instruction Type: S_3op |
6887 | Execution Slots: SLOT23 |
6888 | ========================================================================== */ |
6889 | |
6890 | #define Q6_R_lsracc_RR __builtin_HEXAGON_S2_lsr_r_r_acc |
6891 | |
6892 | /* ========================================================================== |
6893 | Assembly Syntax: Rx32&=lsr(Rs32,Rt32) |
6894 | C Intrinsic Prototype: Word32 Q6_R_lsrand_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6895 | Instruction Type: S_3op |
6896 | Execution Slots: SLOT23 |
6897 | ========================================================================== */ |
6898 | |
6899 | #define Q6_R_lsrand_RR __builtin_HEXAGON_S2_lsr_r_r_and |
6900 | |
6901 | /* ========================================================================== |
6902 | Assembly Syntax: Rx32-=lsr(Rs32,Rt32) |
6903 | C Intrinsic Prototype: Word32 Q6_R_lsrnac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6904 | Instruction Type: S_3op |
6905 | Execution Slots: SLOT23 |
6906 | ========================================================================== */ |
6907 | |
6908 | #define Q6_R_lsrnac_RR __builtin_HEXAGON_S2_lsr_r_r_nac |
6909 | |
6910 | /* ========================================================================== |
6911 | Assembly Syntax: Rx32|=lsr(Rs32,Rt32) |
6912 | C Intrinsic Prototype: Word32 Q6_R_lsror_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
6913 | Instruction Type: S_3op |
6914 | Execution Slots: SLOT23 |
6915 | ========================================================================== */ |
6916 | |
6917 | #define Q6_R_lsror_RR __builtin_HEXAGON_S2_lsr_r_r_or |
6918 | |
6919 | /* ========================================================================== |
6920 | Assembly Syntax: Rdd32=vlsrh(Rss32,Rt32) |
6921 | C Intrinsic Prototype: Word64 Q6_P_vlsrh_PR(Word64 Rss, Word32 Rt) |
6922 | Instruction Type: S_3op |
6923 | Execution Slots: SLOT23 |
6924 | ========================================================================== */ |
6925 | |
6926 | #define Q6_P_vlsrh_PR __builtin_HEXAGON_S2_lsr_r_vh |
6927 | |
6928 | /* ========================================================================== |
6929 | Assembly Syntax: Rdd32=vlsrw(Rss32,Rt32) |
6930 | C Intrinsic Prototype: Word64 Q6_P_vlsrw_PR(Word64 Rss, Word32 Rt) |
6931 | Instruction Type: S_3op |
6932 | Execution Slots: SLOT23 |
6933 | ========================================================================== */ |
6934 | |
6935 | #define Q6_P_vlsrw_PR __builtin_HEXAGON_S2_lsr_r_vw |
6936 | |
6937 | /* ========================================================================== |
6938 | Assembly Syntax: Rdd32=packhl(Rs32,Rt32) |
6939 | C Intrinsic Prototype: Word64 Q6_P_packhl_RR(Word32 Rs, Word32 Rt) |
6940 | Instruction Type: ALU32_3op |
6941 | Execution Slots: SLOT0123 |
6942 | ========================================================================== */ |
6943 | |
6944 | #define Q6_P_packhl_RR __builtin_HEXAGON_S2_packhl |
6945 | |
6946 | /* ========================================================================== |
6947 | Assembly Syntax: Rd32=parity(Rss32,Rtt32) |
6948 | C Intrinsic Prototype: Word32 Q6_R_parity_PP(Word64 Rss, Word64 Rtt) |
6949 | Instruction Type: ALU64 |
6950 | Execution Slots: SLOT23 |
6951 | ========================================================================== */ |
6952 | |
6953 | #define Q6_R_parity_PP __builtin_HEXAGON_S2_parityp |
6954 | |
6955 | /* ========================================================================== |
6956 | Assembly Syntax: Rd32=setbit(Rs32,#u5) |
6957 | C Intrinsic Prototype: Word32 Q6_R_setbit_RI(Word32 Rs, Word32 Iu5) |
6958 | Instruction Type: S_2op |
6959 | Execution Slots: SLOT23 |
6960 | ========================================================================== */ |
6961 | |
6962 | #define Q6_R_setbit_RI __builtin_HEXAGON_S2_setbit_i |
6963 | |
6964 | /* ========================================================================== |
6965 | Assembly Syntax: Rd32=setbit(Rs32,Rt32) |
6966 | C Intrinsic Prototype: Word32 Q6_R_setbit_RR(Word32 Rs, Word32 Rt) |
6967 | Instruction Type: S_3op |
6968 | Execution Slots: SLOT23 |
6969 | ========================================================================== */ |
6970 | |
6971 | #define Q6_R_setbit_RR __builtin_HEXAGON_S2_setbit_r |
6972 | |
6973 | /* ========================================================================== |
6974 | Assembly Syntax: Rdd32=shuffeb(Rss32,Rtt32) |
6975 | C Intrinsic Prototype: Word64 Q6_P_shuffeb_PP(Word64 Rss, Word64 Rtt) |
6976 | Instruction Type: S_3op |
6977 | Execution Slots: SLOT23 |
6978 | ========================================================================== */ |
6979 | |
6980 | #define Q6_P_shuffeb_PP __builtin_HEXAGON_S2_shuffeb |
6981 | |
6982 | /* ========================================================================== |
6983 | Assembly Syntax: Rdd32=shuffeh(Rss32,Rtt32) |
6984 | C Intrinsic Prototype: Word64 Q6_P_shuffeh_PP(Word64 Rss, Word64 Rtt) |
6985 | Instruction Type: S_3op |
6986 | Execution Slots: SLOT23 |
6987 | ========================================================================== */ |
6988 | |
6989 | #define Q6_P_shuffeh_PP __builtin_HEXAGON_S2_shuffeh |
6990 | |
6991 | /* ========================================================================== |
6992 | Assembly Syntax: Rdd32=shuffob(Rtt32,Rss32) |
6993 | C Intrinsic Prototype: Word64 Q6_P_shuffob_PP(Word64 Rtt, Word64 Rss) |
6994 | Instruction Type: S_3op |
6995 | Execution Slots: SLOT23 |
6996 | ========================================================================== */ |
6997 | |
6998 | #define Q6_P_shuffob_PP __builtin_HEXAGON_S2_shuffob |
6999 | |
7000 | /* ========================================================================== |
7001 | Assembly Syntax: Rdd32=shuffoh(Rtt32,Rss32) |
7002 | C Intrinsic Prototype: Word64 Q6_P_shuffoh_PP(Word64 Rtt, Word64 Rss) |
7003 | Instruction Type: S_3op |
7004 | Execution Slots: SLOT23 |
7005 | ========================================================================== */ |
7006 | |
7007 | #define Q6_P_shuffoh_PP __builtin_HEXAGON_S2_shuffoh |
7008 | |
7009 | /* ========================================================================== |
7010 | Assembly Syntax: memb(Rx32++#s4:0:circ(Mu2))=Rt32 |
7011 | C Intrinsic Prototype: void Q6_memb_IMR_circ(void** Rx, Word32 Is4_0, Word32 Mu, Word32 Rt, void* BaseAddress) |
7012 | Instruction Type: ST |
7013 | Execution Slots: SLOT01 |
7014 | ========================================================================== */ |
7015 | |
7016 | #define Q6_memb_IMR_circ __builtin_HEXAGON_S2_storerb_pci |
7017 | |
7018 | /* ========================================================================== |
7019 | Assembly Syntax: memb(Rx32++I:circ(Mu2))=Rt32 |
7020 | C Intrinsic Prototype: void Q6_memb_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) |
7021 | Instruction Type: ST |
7022 | Execution Slots: SLOT01 |
7023 | ========================================================================== */ |
7024 | |
7025 | #define Q6_memb_MR_circ __builtin_HEXAGON_S2_storerb_pcr |
7026 | |
7027 | /* ========================================================================== |
7028 | Assembly Syntax: memd(Rx32++#s4:3:circ(Mu2))=Rtt32 |
7029 | C Intrinsic Prototype: void Q6_memd_IMP_circ(void** Rx, Word32 Is4_3, Word32 Mu, Word64 Rtt, void* BaseAddress) |
7030 | Instruction Type: ST |
7031 | Execution Slots: SLOT01 |
7032 | ========================================================================== */ |
7033 | |
7034 | #define Q6_memd_IMP_circ __builtin_HEXAGON_S2_storerd_pci |
7035 | |
7036 | /* ========================================================================== |
7037 | Assembly Syntax: memd(Rx32++I:circ(Mu2))=Rtt32 |
7038 | C Intrinsic Prototype: void Q6_memd_MP_circ(void** Rx, Word32 Mu, Word64 Rtt, void* BaseAddress) |
7039 | Instruction Type: ST |
7040 | Execution Slots: SLOT01 |
7041 | ========================================================================== */ |
7042 | |
7043 | #define Q6_memd_MP_circ __builtin_HEXAGON_S2_storerd_pcr |
7044 | |
7045 | /* ========================================================================== |
7046 | Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32.h |
7047 | C Intrinsic Prototype: void Q6_memh_IMRh_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) |
7048 | Instruction Type: ST |
7049 | Execution Slots: SLOT01 |
7050 | ========================================================================== */ |
7051 | |
7052 | #define Q6_memh_IMRh_circ __builtin_HEXAGON_S2_storerf_pci |
7053 | |
7054 | /* ========================================================================== |
7055 | Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32.h |
7056 | C Intrinsic Prototype: void Q6_memh_MRh_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) |
7057 | Instruction Type: ST |
7058 | Execution Slots: SLOT01 |
7059 | ========================================================================== */ |
7060 | |
7061 | #define Q6_memh_MRh_circ __builtin_HEXAGON_S2_storerf_pcr |
7062 | |
7063 | /* ========================================================================== |
7064 | Assembly Syntax: memh(Rx32++#s4:1:circ(Mu2))=Rt32 |
7065 | C Intrinsic Prototype: void Q6_memh_IMR_circ(void** Rx, Word32 Is4_1, Word32 Mu, Word32 Rt, void* BaseAddress) |
7066 | Instruction Type: ST |
7067 | Execution Slots: SLOT01 |
7068 | ========================================================================== */ |
7069 | |
7070 | #define Q6_memh_IMR_circ __builtin_HEXAGON_S2_storerh_pci |
7071 | |
7072 | /* ========================================================================== |
7073 | Assembly Syntax: memh(Rx32++I:circ(Mu2))=Rt32 |
7074 | C Intrinsic Prototype: void Q6_memh_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) |
7075 | Instruction Type: ST |
7076 | Execution Slots: SLOT01 |
7077 | ========================================================================== */ |
7078 | |
7079 | #define Q6_memh_MR_circ __builtin_HEXAGON_S2_storerh_pcr |
7080 | |
7081 | /* ========================================================================== |
7082 | Assembly Syntax: memw(Rx32++#s4:2:circ(Mu2))=Rt32 |
7083 | C Intrinsic Prototype: void Q6_memw_IMR_circ(void** Rx, Word32 Is4_2, Word32 Mu, Word32 Rt, void* BaseAddress) |
7084 | Instruction Type: ST |
7085 | Execution Slots: SLOT01 |
7086 | ========================================================================== */ |
7087 | |
7088 | #define Q6_memw_IMR_circ __builtin_HEXAGON_S2_storeri_pci |
7089 | |
7090 | /* ========================================================================== |
7091 | Assembly Syntax: memw(Rx32++I:circ(Mu2))=Rt32 |
7092 | C Intrinsic Prototype: void Q6_memw_MR_circ(void** Rx, Word32 Mu, Word32 Rt, void* BaseAddress) |
7093 | Instruction Type: ST |
7094 | Execution Slots: SLOT01 |
7095 | ========================================================================== */ |
7096 | |
7097 | #define Q6_memw_MR_circ __builtin_HEXAGON_S2_storeri_pcr |
7098 | |
7099 | /* ========================================================================== |
7100 | Assembly Syntax: Rd32=vsathb(Rs32) |
7101 | C Intrinsic Prototype: Word32 Q6_R_vsathb_R(Word32 Rs) |
7102 | Instruction Type: S_2op |
7103 | Execution Slots: SLOT23 |
7104 | ========================================================================== */ |
7105 | |
7106 | #define Q6_R_vsathb_R __builtin_HEXAGON_S2_svsathb |
7107 | |
7108 | /* ========================================================================== |
7109 | Assembly Syntax: Rd32=vsathub(Rs32) |
7110 | C Intrinsic Prototype: Word32 Q6_R_vsathub_R(Word32 Rs) |
7111 | Instruction Type: S_2op |
7112 | Execution Slots: SLOT23 |
7113 | ========================================================================== */ |
7114 | |
7115 | #define Q6_R_vsathub_R __builtin_HEXAGON_S2_svsathub |
7116 | |
7117 | /* ========================================================================== |
7118 | Assembly Syntax: Rx32=tableidxb(Rs32,#u4,#U5) |
7119 | C Intrinsic Prototype: Word32 Q6_R_tableidxb_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) |
7120 | Instruction Type: S_2op |
7121 | Execution Slots: SLOT0123 |
7122 | ========================================================================== */ |
7123 | |
7124 | #define Q6_R_tableidxb_RII __builtin_HEXAGON_S2_tableidxb_goodsyntax |
7125 | |
7126 | /* ========================================================================== |
7127 | Assembly Syntax: Rx32=tableidxd(Rs32,#u4,#U5) |
7128 | C Intrinsic Prototype: Word32 Q6_R_tableidxd_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) |
7129 | Instruction Type: S_2op |
7130 | Execution Slots: SLOT0123 |
7131 | ========================================================================== */ |
7132 | |
7133 | #define Q6_R_tableidxd_RII __builtin_HEXAGON_S2_tableidxd_goodsyntax |
7134 | |
7135 | /* ========================================================================== |
7136 | Assembly Syntax: Rx32=tableidxh(Rs32,#u4,#U5) |
7137 | C Intrinsic Prototype: Word32 Q6_R_tableidxh_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) |
7138 | Instruction Type: S_2op |
7139 | Execution Slots: SLOT0123 |
7140 | ========================================================================== */ |
7141 | |
7142 | #define Q6_R_tableidxh_RII __builtin_HEXAGON_S2_tableidxh_goodsyntax |
7143 | |
7144 | /* ========================================================================== |
7145 | Assembly Syntax: Rx32=tableidxw(Rs32,#u4,#U5) |
7146 | C Intrinsic Prototype: Word32 Q6_R_tableidxw_RII(Word32 Rx, Word32 Rs, Word32 Iu4, Word32 IU5) |
7147 | Instruction Type: S_2op |
7148 | Execution Slots: SLOT0123 |
7149 | ========================================================================== */ |
7150 | |
7151 | #define Q6_R_tableidxw_RII __builtin_HEXAGON_S2_tableidxw_goodsyntax |
7152 | |
7153 | /* ========================================================================== |
7154 | Assembly Syntax: Rd32=togglebit(Rs32,#u5) |
7155 | C Intrinsic Prototype: Word32 Q6_R_togglebit_RI(Word32 Rs, Word32 Iu5) |
7156 | Instruction Type: S_2op |
7157 | Execution Slots: SLOT23 |
7158 | ========================================================================== */ |
7159 | |
7160 | #define Q6_R_togglebit_RI __builtin_HEXAGON_S2_togglebit_i |
7161 | |
7162 | /* ========================================================================== |
7163 | Assembly Syntax: Rd32=togglebit(Rs32,Rt32) |
7164 | C Intrinsic Prototype: Word32 Q6_R_togglebit_RR(Word32 Rs, Word32 Rt) |
7165 | Instruction Type: S_3op |
7166 | Execution Slots: SLOT23 |
7167 | ========================================================================== */ |
7168 | |
7169 | #define Q6_R_togglebit_RR __builtin_HEXAGON_S2_togglebit_r |
7170 | |
7171 | /* ========================================================================== |
7172 | Assembly Syntax: Pd4=tstbit(Rs32,#u5) |
7173 | C Intrinsic Prototype: Byte Q6_p_tstbit_RI(Word32 Rs, Word32 Iu5) |
7174 | Instruction Type: S_2op |
7175 | Execution Slots: SLOT23 |
7176 | ========================================================================== */ |
7177 | |
7178 | #define Q6_p_tstbit_RI __builtin_HEXAGON_S2_tstbit_i |
7179 | |
7180 | /* ========================================================================== |
7181 | Assembly Syntax: Pd4=tstbit(Rs32,Rt32) |
7182 | C Intrinsic Prototype: Byte Q6_p_tstbit_RR(Word32 Rs, Word32 Rt) |
7183 | Instruction Type: S_3op |
7184 | Execution Slots: SLOT23 |
7185 | ========================================================================== */ |
7186 | |
7187 | #define Q6_p_tstbit_RR __builtin_HEXAGON_S2_tstbit_r |
7188 | |
7189 | /* ========================================================================== |
7190 | Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,#u3) |
7191 | C Intrinsic Prototype: Word64 Q6_P_valignb_PPI(Word64 Rtt, Word64 Rss, Word32 Iu3) |
7192 | Instruction Type: S_3op |
7193 | Execution Slots: SLOT23 |
7194 | ========================================================================== */ |
7195 | |
7196 | #define Q6_P_valignb_PPI __builtin_HEXAGON_S2_valignib |
7197 | |
7198 | /* ========================================================================== |
7199 | Assembly Syntax: Rdd32=valignb(Rtt32,Rss32,Pu4) |
7200 | C Intrinsic Prototype: Word64 Q6_P_valignb_PPp(Word64 Rtt, Word64 Rss, Byte Pu) |
7201 | Instruction Type: S_3op |
7202 | Execution Slots: SLOT23 |
7203 | ========================================================================== */ |
7204 | |
7205 | #define Q6_P_valignb_PPp __builtin_HEXAGON_S2_valignrb |
7206 | |
7207 | /* ========================================================================== |
7208 | Assembly Syntax: Rdd32=vcnegh(Rss32,Rt32) |
7209 | C Intrinsic Prototype: Word64 Q6_P_vcnegh_PR(Word64 Rss, Word32 Rt) |
7210 | Instruction Type: S_3op |
7211 | Execution Slots: SLOT23 |
7212 | ========================================================================== */ |
7213 | |
7214 | #define Q6_P_vcnegh_PR __builtin_HEXAGON_S2_vcnegh |
7215 | |
7216 | /* ========================================================================== |
7217 | Assembly Syntax: Rdd32=vcrotate(Rss32,Rt32) |
7218 | C Intrinsic Prototype: Word64 Q6_P_vcrotate_PR(Word64 Rss, Word32 Rt) |
7219 | Instruction Type: S_3op |
7220 | Execution Slots: SLOT23 |
7221 | ========================================================================== */ |
7222 | |
7223 | #define Q6_P_vcrotate_PR __builtin_HEXAGON_S2_vcrotate |
7224 | |
7225 | /* ========================================================================== |
7226 | Assembly Syntax: Rxx32+=vrcnegh(Rss32,Rt32) |
7227 | C Intrinsic Prototype: Word64 Q6_P_vrcneghacc_PR(Word64 Rxx, Word64 Rss, Word32 Rt) |
7228 | Instruction Type: S_3op |
7229 | Execution Slots: SLOT23 |
7230 | ========================================================================== */ |
7231 | |
7232 | #define Q6_P_vrcneghacc_PR __builtin_HEXAGON_S2_vrcnegh |
7233 | |
7234 | /* ========================================================================== |
7235 | Assembly Syntax: Rd32=vrndwh(Rss32) |
7236 | C Intrinsic Prototype: Word32 Q6_R_vrndwh_P(Word64 Rss) |
7237 | Instruction Type: S_2op |
7238 | Execution Slots: SLOT23 |
7239 | ========================================================================== */ |
7240 | |
7241 | #define Q6_R_vrndwh_P __builtin_HEXAGON_S2_vrndpackwh |
7242 | |
7243 | /* ========================================================================== |
7244 | Assembly Syntax: Rd32=vrndwh(Rss32):sat |
7245 | C Intrinsic Prototype: Word32 Q6_R_vrndwh_P_sat(Word64 Rss) |
7246 | Instruction Type: S_2op |
7247 | Execution Slots: SLOT23 |
7248 | ========================================================================== */ |
7249 | |
7250 | #define Q6_R_vrndwh_P_sat __builtin_HEXAGON_S2_vrndpackwhs |
7251 | |
7252 | /* ========================================================================== |
7253 | Assembly Syntax: Rd32=vsathb(Rss32) |
7254 | C Intrinsic Prototype: Word32 Q6_R_vsathb_P(Word64 Rss) |
7255 | Instruction Type: S_2op |
7256 | Execution Slots: SLOT23 |
7257 | ========================================================================== */ |
7258 | |
7259 | #define Q6_R_vsathb_P __builtin_HEXAGON_S2_vsathb |
7260 | |
7261 | /* ========================================================================== |
7262 | Assembly Syntax: Rdd32=vsathb(Rss32) |
7263 | C Intrinsic Prototype: Word64 Q6_P_vsathb_P(Word64 Rss) |
7264 | Instruction Type: S_2op |
7265 | Execution Slots: SLOT23 |
7266 | ========================================================================== */ |
7267 | |
7268 | #define Q6_P_vsathb_P __builtin_HEXAGON_S2_vsathb_nopack |
7269 | |
7270 | /* ========================================================================== |
7271 | Assembly Syntax: Rd32=vsathub(Rss32) |
7272 | C Intrinsic Prototype: Word32 Q6_R_vsathub_P(Word64 Rss) |
7273 | Instruction Type: S_2op |
7274 | Execution Slots: SLOT23 |
7275 | ========================================================================== */ |
7276 | |
7277 | #define Q6_R_vsathub_P __builtin_HEXAGON_S2_vsathub |
7278 | |
7279 | /* ========================================================================== |
7280 | Assembly Syntax: Rdd32=vsathub(Rss32) |
7281 | C Intrinsic Prototype: Word64 Q6_P_vsathub_P(Word64 Rss) |
7282 | Instruction Type: S_2op |
7283 | Execution Slots: SLOT23 |
7284 | ========================================================================== */ |
7285 | |
7286 | #define Q6_P_vsathub_P __builtin_HEXAGON_S2_vsathub_nopack |
7287 | |
7288 | /* ========================================================================== |
7289 | Assembly Syntax: Rd32=vsatwh(Rss32) |
7290 | C Intrinsic Prototype: Word32 Q6_R_vsatwh_P(Word64 Rss) |
7291 | Instruction Type: S_2op |
7292 | Execution Slots: SLOT23 |
7293 | ========================================================================== */ |
7294 | |
7295 | #define Q6_R_vsatwh_P __builtin_HEXAGON_S2_vsatwh |
7296 | |
7297 | /* ========================================================================== |
7298 | Assembly Syntax: Rdd32=vsatwh(Rss32) |
7299 | C Intrinsic Prototype: Word64 Q6_P_vsatwh_P(Word64 Rss) |
7300 | Instruction Type: S_2op |
7301 | Execution Slots: SLOT23 |
7302 | ========================================================================== */ |
7303 | |
7304 | #define Q6_P_vsatwh_P __builtin_HEXAGON_S2_vsatwh_nopack |
7305 | |
7306 | /* ========================================================================== |
7307 | Assembly Syntax: Rd32=vsatwuh(Rss32) |
7308 | C Intrinsic Prototype: Word32 Q6_R_vsatwuh_P(Word64 Rss) |
7309 | Instruction Type: S_2op |
7310 | Execution Slots: SLOT23 |
7311 | ========================================================================== */ |
7312 | |
7313 | #define Q6_R_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh |
7314 | |
7315 | /* ========================================================================== |
7316 | Assembly Syntax: Rdd32=vsatwuh(Rss32) |
7317 | C Intrinsic Prototype: Word64 Q6_P_vsatwuh_P(Word64 Rss) |
7318 | Instruction Type: S_2op |
7319 | Execution Slots: SLOT23 |
7320 | ========================================================================== */ |
7321 | |
7322 | #define Q6_P_vsatwuh_P __builtin_HEXAGON_S2_vsatwuh_nopack |
7323 | |
7324 | /* ========================================================================== |
7325 | Assembly Syntax: Rd32=vsplatb(Rs32) |
7326 | C Intrinsic Prototype: Word32 Q6_R_vsplatb_R(Word32 Rs) |
7327 | Instruction Type: S_2op |
7328 | Execution Slots: SLOT23 |
7329 | ========================================================================== */ |
7330 | |
7331 | #define Q6_R_vsplatb_R __builtin_HEXAGON_S2_vsplatrb |
7332 | |
7333 | /* ========================================================================== |
7334 | Assembly Syntax: Rdd32=vsplath(Rs32) |
7335 | C Intrinsic Prototype: Word64 Q6_P_vsplath_R(Word32 Rs) |
7336 | Instruction Type: S_2op |
7337 | Execution Slots: SLOT23 |
7338 | ========================================================================== */ |
7339 | |
7340 | #define Q6_P_vsplath_R __builtin_HEXAGON_S2_vsplatrh |
7341 | |
7342 | /* ========================================================================== |
7343 | Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,#u3) |
7344 | C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPI(Word64 Rss, Word64 Rtt, Word32 Iu3) |
7345 | Instruction Type: S_3op |
7346 | Execution Slots: SLOT23 |
7347 | ========================================================================== */ |
7348 | |
7349 | #define Q6_P_vspliceb_PPI __builtin_HEXAGON_S2_vspliceib |
7350 | |
7351 | /* ========================================================================== |
7352 | Assembly Syntax: Rdd32=vspliceb(Rss32,Rtt32,Pu4) |
7353 | C Intrinsic Prototype: Word64 Q6_P_vspliceb_PPp(Word64 Rss, Word64 Rtt, Byte Pu) |
7354 | Instruction Type: S_3op |
7355 | Execution Slots: SLOT23 |
7356 | ========================================================================== */ |
7357 | |
7358 | #define Q6_P_vspliceb_PPp __builtin_HEXAGON_S2_vsplicerb |
7359 | |
7360 | /* ========================================================================== |
7361 | Assembly Syntax: Rdd32=vsxtbh(Rs32) |
7362 | C Intrinsic Prototype: Word64 Q6_P_vsxtbh_R(Word32 Rs) |
7363 | Instruction Type: S_2op |
7364 | Execution Slots: SLOT23 |
7365 | ========================================================================== */ |
7366 | |
7367 | #define Q6_P_vsxtbh_R __builtin_HEXAGON_S2_vsxtbh |
7368 | |
7369 | /* ========================================================================== |
7370 | Assembly Syntax: Rdd32=vsxthw(Rs32) |
7371 | C Intrinsic Prototype: Word64 Q6_P_vsxthw_R(Word32 Rs) |
7372 | Instruction Type: S_2op |
7373 | Execution Slots: SLOT23 |
7374 | ========================================================================== */ |
7375 | |
7376 | #define Q6_P_vsxthw_R __builtin_HEXAGON_S2_vsxthw |
7377 | |
7378 | /* ========================================================================== |
7379 | Assembly Syntax: Rd32=vtrunehb(Rss32) |
7380 | C Intrinsic Prototype: Word32 Q6_R_vtrunehb_P(Word64 Rss) |
7381 | Instruction Type: S_2op |
7382 | Execution Slots: SLOT23 |
7383 | ========================================================================== */ |
7384 | |
7385 | #define Q6_R_vtrunehb_P __builtin_HEXAGON_S2_vtrunehb |
7386 | |
7387 | /* ========================================================================== |
7388 | Assembly Syntax: Rdd32=vtrunewh(Rss32,Rtt32) |
7389 | C Intrinsic Prototype: Word64 Q6_P_vtrunewh_PP(Word64 Rss, Word64 Rtt) |
7390 | Instruction Type: S_3op |
7391 | Execution Slots: SLOT23 |
7392 | ========================================================================== */ |
7393 | |
7394 | #define Q6_P_vtrunewh_PP __builtin_HEXAGON_S2_vtrunewh |
7395 | |
7396 | /* ========================================================================== |
7397 | Assembly Syntax: Rd32=vtrunohb(Rss32) |
7398 | C Intrinsic Prototype: Word32 Q6_R_vtrunohb_P(Word64 Rss) |
7399 | Instruction Type: S_2op |
7400 | Execution Slots: SLOT23 |
7401 | ========================================================================== */ |
7402 | |
7403 | #define Q6_R_vtrunohb_P __builtin_HEXAGON_S2_vtrunohb |
7404 | |
7405 | /* ========================================================================== |
7406 | Assembly Syntax: Rdd32=vtrunowh(Rss32,Rtt32) |
7407 | C Intrinsic Prototype: Word64 Q6_P_vtrunowh_PP(Word64 Rss, Word64 Rtt) |
7408 | Instruction Type: S_3op |
7409 | Execution Slots: SLOT23 |
7410 | ========================================================================== */ |
7411 | |
7412 | #define Q6_P_vtrunowh_PP __builtin_HEXAGON_S2_vtrunowh |
7413 | |
7414 | /* ========================================================================== |
7415 | Assembly Syntax: Rdd32=vzxtbh(Rs32) |
7416 | C Intrinsic Prototype: Word64 Q6_P_vzxtbh_R(Word32 Rs) |
7417 | Instruction Type: S_2op |
7418 | Execution Slots: SLOT23 |
7419 | ========================================================================== */ |
7420 | |
7421 | #define Q6_P_vzxtbh_R __builtin_HEXAGON_S2_vzxtbh |
7422 | |
7423 | /* ========================================================================== |
7424 | Assembly Syntax: Rdd32=vzxthw(Rs32) |
7425 | C Intrinsic Prototype: Word64 Q6_P_vzxthw_R(Word32 Rs) |
7426 | Instruction Type: S_2op |
7427 | Execution Slots: SLOT23 |
7428 | ========================================================================== */ |
7429 | |
7430 | #define Q6_P_vzxthw_R __builtin_HEXAGON_S2_vzxthw |
7431 | |
7432 | /* ========================================================================== |
7433 | Assembly Syntax: Rd32=add(Rs32,add(Ru32,#s6)) |
7434 | C Intrinsic Prototype: Word32 Q6_R_add_add_RRI(Word32 Rs, Word32 Ru, Word32 Is6) |
7435 | Instruction Type: ALU64 |
7436 | Execution Slots: SLOT23 |
7437 | ========================================================================== */ |
7438 | |
7439 | #define Q6_R_add_add_RRI __builtin_HEXAGON_S4_addaddi |
7440 | |
7441 | /* ========================================================================== |
7442 | Assembly Syntax: Rx32=add(#u8,asl(Rx32,#U5)) |
7443 | C Intrinsic Prototype: Word32 Q6_R_add_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7444 | Instruction Type: ALU64 |
7445 | Execution Slots: SLOT23 |
7446 | ========================================================================== */ |
7447 | |
7448 | #define Q6_R_add_asl_IRI __builtin_HEXAGON_S4_addi_asl_ri |
7449 | |
7450 | /* ========================================================================== |
7451 | Assembly Syntax: Rx32=add(#u8,lsr(Rx32,#U5)) |
7452 | C Intrinsic Prototype: Word32 Q6_R_add_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7453 | Instruction Type: ALU64 |
7454 | Execution Slots: SLOT23 |
7455 | ========================================================================== */ |
7456 | |
7457 | #define Q6_R_add_lsr_IRI __builtin_HEXAGON_S4_addi_lsr_ri |
7458 | |
7459 | /* ========================================================================== |
7460 | Assembly Syntax: Rx32=and(#u8,asl(Rx32,#U5)) |
7461 | C Intrinsic Prototype: Word32 Q6_R_and_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7462 | Instruction Type: ALU64 |
7463 | Execution Slots: SLOT23 |
7464 | ========================================================================== */ |
7465 | |
7466 | #define Q6_R_and_asl_IRI __builtin_HEXAGON_S4_andi_asl_ri |
7467 | |
7468 | /* ========================================================================== |
7469 | Assembly Syntax: Rx32=and(#u8,lsr(Rx32,#U5)) |
7470 | C Intrinsic Prototype: Word32 Q6_R_and_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7471 | Instruction Type: ALU64 |
7472 | Execution Slots: SLOT23 |
7473 | ========================================================================== */ |
7474 | |
7475 | #define Q6_R_and_lsr_IRI __builtin_HEXAGON_S4_andi_lsr_ri |
7476 | |
7477 | /* ========================================================================== |
7478 | Assembly Syntax: Rd32=add(clb(Rs32),#s6) |
7479 | C Intrinsic Prototype: Word32 Q6_R_add_clb_RI(Word32 Rs, Word32 Is6) |
7480 | Instruction Type: S_2op |
7481 | Execution Slots: SLOT23 |
7482 | ========================================================================== */ |
7483 | |
7484 | #define Q6_R_add_clb_RI __builtin_HEXAGON_S4_clbaddi |
7485 | |
7486 | /* ========================================================================== |
7487 | Assembly Syntax: Rd32=add(clb(Rss32),#s6) |
7488 | C Intrinsic Prototype: Word32 Q6_R_add_clb_PI(Word64 Rss, Word32 Is6) |
7489 | Instruction Type: S_2op |
7490 | Execution Slots: SLOT23 |
7491 | ========================================================================== */ |
7492 | |
7493 | #define Q6_R_add_clb_PI __builtin_HEXAGON_S4_clbpaddi |
7494 | |
7495 | /* ========================================================================== |
7496 | Assembly Syntax: Rd32=normamt(Rss32) |
7497 | C Intrinsic Prototype: Word32 Q6_R_normamt_P(Word64 Rss) |
7498 | Instruction Type: S_2op |
7499 | Execution Slots: SLOT23 |
7500 | ========================================================================== */ |
7501 | |
7502 | #define Q6_R_normamt_P __builtin_HEXAGON_S4_clbpnorm |
7503 | |
7504 | /* ========================================================================== |
7505 | Assembly Syntax: Rd32=extract(Rs32,#u5,#U5) |
7506 | C Intrinsic Prototype: Word32 Q6_R_extract_RII(Word32 Rs, Word32 Iu5, Word32 IU5) |
7507 | Instruction Type: S_2op |
7508 | Execution Slots: SLOT23 |
7509 | ========================================================================== */ |
7510 | |
7511 | #define Q6_R_extract_RII __builtin_HEXAGON_S4_extract |
7512 | |
7513 | /* ========================================================================== |
7514 | Assembly Syntax: Rd32=extract(Rs32,Rtt32) |
7515 | C Intrinsic Prototype: Word32 Q6_R_extract_RP(Word32 Rs, Word64 Rtt) |
7516 | Instruction Type: S_3op |
7517 | Execution Slots: SLOT23 |
7518 | ========================================================================== */ |
7519 | |
7520 | #define Q6_R_extract_RP __builtin_HEXAGON_S4_extract_rp |
7521 | |
7522 | /* ========================================================================== |
7523 | Assembly Syntax: Rdd32=extract(Rss32,#u6,#U6) |
7524 | C Intrinsic Prototype: Word64 Q6_P_extract_PII(Word64 Rss, Word32 Iu6, Word32 IU6) |
7525 | Instruction Type: S_2op |
7526 | Execution Slots: SLOT23 |
7527 | ========================================================================== */ |
7528 | |
7529 | #define Q6_P_extract_PII __builtin_HEXAGON_S4_extractp |
7530 | |
7531 | /* ========================================================================== |
7532 | Assembly Syntax: Rdd32=extract(Rss32,Rtt32) |
7533 | C Intrinsic Prototype: Word64 Q6_P_extract_PP(Word64 Rss, Word64 Rtt) |
7534 | Instruction Type: S_3op |
7535 | Execution Slots: SLOT23 |
7536 | ========================================================================== */ |
7537 | |
7538 | #define Q6_P_extract_PP __builtin_HEXAGON_S4_extractp_rp |
7539 | |
7540 | /* ========================================================================== |
7541 | Assembly Syntax: Rd32=lsl(#s6,Rt32) |
7542 | C Intrinsic Prototype: Word32 Q6_R_lsl_IR(Word32 Is6, Word32 Rt) |
7543 | Instruction Type: S_3op |
7544 | Execution Slots: SLOT23 |
7545 | ========================================================================== */ |
7546 | |
7547 | #define Q6_R_lsl_IR __builtin_HEXAGON_S4_lsli |
7548 | |
7549 | /* ========================================================================== |
7550 | Assembly Syntax: Pd4=!tstbit(Rs32,#u5) |
7551 | C Intrinsic Prototype: Byte Q6_p_not_tstbit_RI(Word32 Rs, Word32 Iu5) |
7552 | Instruction Type: S_2op |
7553 | Execution Slots: SLOT23 |
7554 | ========================================================================== */ |
7555 | |
7556 | #define Q6_p_not_tstbit_RI __builtin_HEXAGON_S4_ntstbit_i |
7557 | |
7558 | /* ========================================================================== |
7559 | Assembly Syntax: Pd4=!tstbit(Rs32,Rt32) |
7560 | C Intrinsic Prototype: Byte Q6_p_not_tstbit_RR(Word32 Rs, Word32 Rt) |
7561 | Instruction Type: S_3op |
7562 | Execution Slots: SLOT23 |
7563 | ========================================================================== */ |
7564 | |
7565 | #define Q6_p_not_tstbit_RR __builtin_HEXAGON_S4_ntstbit_r |
7566 | |
7567 | /* ========================================================================== |
7568 | Assembly Syntax: Rx32|=and(Rs32,#s10) |
7569 | C Intrinsic Prototype: Word32 Q6_R_andor_RI(Word32 Rx, Word32 Rs, Word32 Is10) |
7570 | Instruction Type: ALU64 |
7571 | Execution Slots: SLOT23 |
7572 | ========================================================================== */ |
7573 | |
7574 | #define Q6_R_andor_RI __builtin_HEXAGON_S4_or_andi |
7575 | |
7576 | /* ========================================================================== |
7577 | Assembly Syntax: Rx32=or(Ru32,and(Rx32,#s10)) |
7578 | C Intrinsic Prototype: Word32 Q6_R_or_and_RRI(Word32 Ru, Word32 Rx, Word32 Is10) |
7579 | Instruction Type: ALU64 |
7580 | Execution Slots: SLOT23 |
7581 | ========================================================================== */ |
7582 | |
7583 | #define Q6_R_or_and_RRI __builtin_HEXAGON_S4_or_andix |
7584 | |
7585 | /* ========================================================================== |
7586 | Assembly Syntax: Rx32|=or(Rs32,#s10) |
7587 | C Intrinsic Prototype: Word32 Q6_R_oror_RI(Word32 Rx, Word32 Rs, Word32 Is10) |
7588 | Instruction Type: ALU64 |
7589 | Execution Slots: SLOT23 |
7590 | ========================================================================== */ |
7591 | |
7592 | #define Q6_R_oror_RI __builtin_HEXAGON_S4_or_ori |
7593 | |
7594 | /* ========================================================================== |
7595 | Assembly Syntax: Rx32=or(#u8,asl(Rx32,#U5)) |
7596 | C Intrinsic Prototype: Word32 Q6_R_or_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7597 | Instruction Type: ALU64 |
7598 | Execution Slots: SLOT23 |
7599 | ========================================================================== */ |
7600 | |
7601 | #define Q6_R_or_asl_IRI __builtin_HEXAGON_S4_ori_asl_ri |
7602 | |
7603 | /* ========================================================================== |
7604 | Assembly Syntax: Rx32=or(#u8,lsr(Rx32,#U5)) |
7605 | C Intrinsic Prototype: Word32 Q6_R_or_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7606 | Instruction Type: ALU64 |
7607 | Execution Slots: SLOT23 |
7608 | ========================================================================== */ |
7609 | |
7610 | #define Q6_R_or_lsr_IRI __builtin_HEXAGON_S4_ori_lsr_ri |
7611 | |
7612 | /* ========================================================================== |
7613 | Assembly Syntax: Rd32=parity(Rs32,Rt32) |
7614 | C Intrinsic Prototype: Word32 Q6_R_parity_RR(Word32 Rs, Word32 Rt) |
7615 | Instruction Type: ALU64 |
7616 | Execution Slots: SLOT23 |
7617 | ========================================================================== */ |
7618 | |
7619 | #define Q6_R_parity_RR __builtin_HEXAGON_S4_parity |
7620 | |
7621 | /* ========================================================================== |
7622 | Assembly Syntax: Rd32=add(Rs32,sub(#s6,Ru32)) |
7623 | C Intrinsic Prototype: Word32 Q6_R_add_sub_RIR(Word32 Rs, Word32 Is6, Word32 Ru) |
7624 | Instruction Type: ALU64 |
7625 | Execution Slots: SLOT23 |
7626 | ========================================================================== */ |
7627 | |
7628 | #define Q6_R_add_sub_RIR __builtin_HEXAGON_S4_subaddi |
7629 | |
7630 | /* ========================================================================== |
7631 | Assembly Syntax: Rx32=sub(#u8,asl(Rx32,#U5)) |
7632 | C Intrinsic Prototype: Word32 Q6_R_sub_asl_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7633 | Instruction Type: ALU64 |
7634 | Execution Slots: SLOT23 |
7635 | ========================================================================== */ |
7636 | |
7637 | #define Q6_R_sub_asl_IRI __builtin_HEXAGON_S4_subi_asl_ri |
7638 | |
7639 | /* ========================================================================== |
7640 | Assembly Syntax: Rx32=sub(#u8,lsr(Rx32,#U5)) |
7641 | C Intrinsic Prototype: Word32 Q6_R_sub_lsr_IRI(Word32 Iu8, Word32 Rx, Word32 IU5) |
7642 | Instruction Type: ALU64 |
7643 | Execution Slots: SLOT23 |
7644 | ========================================================================== */ |
7645 | |
7646 | #define Q6_R_sub_lsr_IRI __builtin_HEXAGON_S4_subi_lsr_ri |
7647 | |
7648 | /* ========================================================================== |
7649 | Assembly Syntax: Rdd32=vrcrotate(Rss32,Rt32,#u2) |
7650 | C Intrinsic Prototype: Word64 Q6_P_vrcrotate_PRI(Word64 Rss, Word32 Rt, Word32 Iu2) |
7651 | Instruction Type: S_3op |
7652 | Execution Slots: SLOT23 |
7653 | ========================================================================== */ |
7654 | |
7655 | #define Q6_P_vrcrotate_PRI __builtin_HEXAGON_S4_vrcrotate |
7656 | |
7657 | /* ========================================================================== |
7658 | Assembly Syntax: Rxx32+=vrcrotate(Rss32,Rt32,#u2) |
7659 | C Intrinsic Prototype: Word64 Q6_P_vrcrotateacc_PRI(Word64 Rxx, Word64 Rss, Word32 Rt, Word32 Iu2) |
7660 | Instruction Type: S_3op |
7661 | Execution Slots: SLOT23 |
7662 | ========================================================================== */ |
7663 | |
7664 | #define Q6_P_vrcrotateacc_PRI __builtin_HEXAGON_S4_vrcrotate_acc |
7665 | |
7666 | /* ========================================================================== |
7667 | Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):sat |
7668 | C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_sat(Word64 Rss, Word64 Rtt) |
7669 | Instruction Type: S_3op |
7670 | Execution Slots: SLOT23 |
7671 | ========================================================================== */ |
7672 | |
7673 | #define Q6_P_vxaddsubh_PP_sat __builtin_HEXAGON_S4_vxaddsubh |
7674 | |
7675 | /* ========================================================================== |
7676 | Assembly Syntax: Rdd32=vxaddsubh(Rss32,Rtt32):rnd:>>1:sat |
7677 | C Intrinsic Prototype: Word64 Q6_P_vxaddsubh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) |
7678 | Instruction Type: S_3op |
7679 | Execution Slots: SLOT23 |
7680 | ========================================================================== */ |
7681 | |
7682 | #define Q6_P_vxaddsubh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxaddsubhr |
7683 | |
7684 | /* ========================================================================== |
7685 | Assembly Syntax: Rdd32=vxaddsubw(Rss32,Rtt32):sat |
7686 | C Intrinsic Prototype: Word64 Q6_P_vxaddsubw_PP_sat(Word64 Rss, Word64 Rtt) |
7687 | Instruction Type: S_3op |
7688 | Execution Slots: SLOT23 |
7689 | ========================================================================== */ |
7690 | |
7691 | #define Q6_P_vxaddsubw_PP_sat __builtin_HEXAGON_S4_vxaddsubw |
7692 | |
7693 | /* ========================================================================== |
7694 | Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):sat |
7695 | C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_sat(Word64 Rss, Word64 Rtt) |
7696 | Instruction Type: S_3op |
7697 | Execution Slots: SLOT23 |
7698 | ========================================================================== */ |
7699 | |
7700 | #define Q6_P_vxsubaddh_PP_sat __builtin_HEXAGON_S4_vxsubaddh |
7701 | |
7702 | /* ========================================================================== |
7703 | Assembly Syntax: Rdd32=vxsubaddh(Rss32,Rtt32):rnd:>>1:sat |
7704 | C Intrinsic Prototype: Word64 Q6_P_vxsubaddh_PP_rnd_rs1_sat(Word64 Rss, Word64 Rtt) |
7705 | Instruction Type: S_3op |
7706 | Execution Slots: SLOT23 |
7707 | ========================================================================== */ |
7708 | |
7709 | #define Q6_P_vxsubaddh_PP_rnd_rs1_sat __builtin_HEXAGON_S4_vxsubaddhr |
7710 | |
7711 | /* ========================================================================== |
7712 | Assembly Syntax: Rdd32=vxsubaddw(Rss32,Rtt32):sat |
7713 | C Intrinsic Prototype: Word64 Q6_P_vxsubaddw_PP_sat(Word64 Rss, Word64 Rtt) |
7714 | Instruction Type: S_3op |
7715 | Execution Slots: SLOT23 |
7716 | ========================================================================== */ |
7717 | |
7718 | #define Q6_P_vxsubaddw_PP_sat __builtin_HEXAGON_S4_vxsubaddw |
7719 | |
7720 | /* ========================================================================== |
7721 | Assembly Syntax: Rd32=vasrhub(Rss32,#u4):rnd:sat |
7722 | C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_rnd_sat(Word64 Rss, Word32 Iu4) |
7723 | Instruction Type: S_2op |
7724 | Execution Slots: SLOT0123 |
7725 | ========================================================================== */ |
7726 | |
7727 | #define Q6_R_vasrhub_PI_rnd_sat __builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax |
7728 | |
7729 | /* ========================================================================== |
7730 | Assembly Syntax: Rd32=vasrhub(Rss32,#u4):sat |
7731 | C Intrinsic Prototype: Word32 Q6_R_vasrhub_PI_sat(Word64 Rss, Word32 Iu4) |
7732 | Instruction Type: S_2op |
7733 | Execution Slots: SLOT23 |
7734 | ========================================================================== */ |
7735 | |
7736 | #define Q6_R_vasrhub_PI_sat __builtin_HEXAGON_S5_asrhub_sat |
7737 | |
7738 | /* ========================================================================== |
7739 | Assembly Syntax: Rd32=popcount(Rss32) |
7740 | C Intrinsic Prototype: Word32 Q6_R_popcount_P(Word64 Rss) |
7741 | Instruction Type: S_2op |
7742 | Execution Slots: SLOT23 |
7743 | ========================================================================== */ |
7744 | |
7745 | #define Q6_R_popcount_P __builtin_HEXAGON_S5_popcountp |
7746 | |
7747 | /* ========================================================================== |
7748 | Assembly Syntax: Rdd32=vasrh(Rss32,#u4):rnd |
7749 | C Intrinsic Prototype: Word64 Q6_P_vasrh_PI_rnd(Word64 Rss, Word32 Iu4) |
7750 | Instruction Type: S_2op |
7751 | Execution Slots: SLOT0123 |
7752 | ========================================================================== */ |
7753 | |
7754 | #define Q6_P_vasrh_PI_rnd __builtin_HEXAGON_S5_vasrhrnd_goodsyntax |
7755 | |
7756 | /* ========================================================================== |
7757 | Assembly Syntax: dccleana(Rs32) |
7758 | C Intrinsic Prototype: void Q6_dccleana_A(Address Rs) |
7759 | Instruction Type: ST |
7760 | Execution Slots: SLOT0 |
7761 | ========================================================================== */ |
7762 | |
7763 | #define Q6_dccleana_A __builtin_HEXAGON_Y2_dccleana |
7764 | |
7765 | /* ========================================================================== |
7766 | Assembly Syntax: dccleaninva(Rs32) |
7767 | C Intrinsic Prototype: void Q6_dccleaninva_A(Address Rs) |
7768 | Instruction Type: ST |
7769 | Execution Slots: SLOT0 |
7770 | ========================================================================== */ |
7771 | |
7772 | #define Q6_dccleaninva_A __builtin_HEXAGON_Y2_dccleaninva |
7773 | |
7774 | /* ========================================================================== |
7775 | Assembly Syntax: dcfetch(Rs32) |
7776 | C Intrinsic Prototype: void Q6_dcfetch_A(Address Rs) |
7777 | Instruction Type: MAPPING |
7778 | Execution Slots: SLOT0123 |
7779 | ========================================================================== */ |
7780 | |
7781 | #define Q6_dcfetch_A __builtin_HEXAGON_Y2_dcfetch |
7782 | |
7783 | /* ========================================================================== |
7784 | Assembly Syntax: dcinva(Rs32) |
7785 | C Intrinsic Prototype: void Q6_dcinva_A(Address Rs) |
7786 | Instruction Type: ST |
7787 | Execution Slots: SLOT0 |
7788 | ========================================================================== */ |
7789 | |
7790 | #define Q6_dcinva_A __builtin_HEXAGON_Y2_dcinva |
7791 | |
7792 | /* ========================================================================== |
7793 | Assembly Syntax: dczeroa(Rs32) |
7794 | C Intrinsic Prototype: void Q6_dczeroa_A(Address Rs) |
7795 | Instruction Type: ST |
7796 | Execution Slots: SLOT0 |
7797 | ========================================================================== */ |
7798 | |
7799 | #define Q6_dczeroa_A __builtin_HEXAGON_Y2_dczeroa |
7800 | |
7801 | /* ========================================================================== |
7802 | Assembly Syntax: l2fetch(Rs32,Rt32) |
7803 | C Intrinsic Prototype: void Q6_l2fetch_AR(Address Rs, Word32 Rt) |
7804 | Instruction Type: ST |
7805 | Execution Slots: SLOT0 |
7806 | ========================================================================== */ |
7807 | |
7808 | #define Q6_l2fetch_AR __builtin_HEXAGON_Y4_l2fetch |
7809 | |
7810 | /* ========================================================================== |
7811 | Assembly Syntax: l2fetch(Rs32,Rtt32) |
7812 | C Intrinsic Prototype: void Q6_l2fetch_AP(Address Rs, Word64 Rtt) |
7813 | Instruction Type: ST |
7814 | Execution Slots: SLOT0 |
7815 | ========================================================================== */ |
7816 | |
7817 | #define Q6_l2fetch_AP __builtin_HEXAGON_Y5_l2fetch |
7818 | |
7819 | #if __HEXAGON_ARCH__ >= 60 |
7820 | /* ========================================================================== |
7821 | Assembly Syntax: Rdd32=rol(Rss32,#u6) |
7822 | C Intrinsic Prototype: Word64 Q6_P_rol_PI(Word64 Rss, Word32 Iu6) |
7823 | Instruction Type: S_2op |
7824 | Execution Slots: SLOT23 |
7825 | ========================================================================== */ |
7826 | |
7827 | #define Q6_P_rol_PI __builtin_HEXAGON_S6_rol_i_p |
7828 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7829 | |
7830 | #if __HEXAGON_ARCH__ >= 60 |
7831 | /* ========================================================================== |
7832 | Assembly Syntax: Rxx32+=rol(Rss32,#u6) |
7833 | C Intrinsic Prototype: Word64 Q6_P_rolacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
7834 | Instruction Type: S_2op |
7835 | Execution Slots: SLOT23 |
7836 | ========================================================================== */ |
7837 | |
7838 | #define Q6_P_rolacc_PI __builtin_HEXAGON_S6_rol_i_p_acc |
7839 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7840 | |
7841 | #if __HEXAGON_ARCH__ >= 60 |
7842 | /* ========================================================================== |
7843 | Assembly Syntax: Rxx32&=rol(Rss32,#u6) |
7844 | C Intrinsic Prototype: Word64 Q6_P_roland_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
7845 | Instruction Type: S_2op |
7846 | Execution Slots: SLOT23 |
7847 | ========================================================================== */ |
7848 | |
7849 | #define Q6_P_roland_PI __builtin_HEXAGON_S6_rol_i_p_and |
7850 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7851 | |
7852 | #if __HEXAGON_ARCH__ >= 60 |
7853 | /* ========================================================================== |
7854 | Assembly Syntax: Rxx32-=rol(Rss32,#u6) |
7855 | C Intrinsic Prototype: Word64 Q6_P_rolnac_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
7856 | Instruction Type: S_2op |
7857 | Execution Slots: SLOT23 |
7858 | ========================================================================== */ |
7859 | |
7860 | #define Q6_P_rolnac_PI __builtin_HEXAGON_S6_rol_i_p_nac |
7861 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7862 | |
7863 | #if __HEXAGON_ARCH__ >= 60 |
7864 | /* ========================================================================== |
7865 | Assembly Syntax: Rxx32|=rol(Rss32,#u6) |
7866 | C Intrinsic Prototype: Word64 Q6_P_rolor_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
7867 | Instruction Type: S_2op |
7868 | Execution Slots: SLOT23 |
7869 | ========================================================================== */ |
7870 | |
7871 | #define Q6_P_rolor_PI __builtin_HEXAGON_S6_rol_i_p_or |
7872 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7873 | |
7874 | #if __HEXAGON_ARCH__ >= 60 |
7875 | /* ========================================================================== |
7876 | Assembly Syntax: Rxx32^=rol(Rss32,#u6) |
7877 | C Intrinsic Prototype: Word64 Q6_P_rolxacc_PI(Word64 Rxx, Word64 Rss, Word32 Iu6) |
7878 | Instruction Type: S_2op |
7879 | Execution Slots: SLOT23 |
7880 | ========================================================================== */ |
7881 | |
7882 | #define Q6_P_rolxacc_PI __builtin_HEXAGON_S6_rol_i_p_xacc |
7883 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7884 | |
7885 | #if __HEXAGON_ARCH__ >= 60 |
7886 | /* ========================================================================== |
7887 | Assembly Syntax: Rd32=rol(Rs32,#u5) |
7888 | C Intrinsic Prototype: Word32 Q6_R_rol_RI(Word32 Rs, Word32 Iu5) |
7889 | Instruction Type: S_2op |
7890 | Execution Slots: SLOT23 |
7891 | ========================================================================== */ |
7892 | |
7893 | #define Q6_R_rol_RI __builtin_HEXAGON_S6_rol_i_r |
7894 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7895 | |
7896 | #if __HEXAGON_ARCH__ >= 60 |
7897 | /* ========================================================================== |
7898 | Assembly Syntax: Rx32+=rol(Rs32,#u5) |
7899 | C Intrinsic Prototype: Word32 Q6_R_rolacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
7900 | Instruction Type: S_2op |
7901 | Execution Slots: SLOT23 |
7902 | ========================================================================== */ |
7903 | |
7904 | #define Q6_R_rolacc_RI __builtin_HEXAGON_S6_rol_i_r_acc |
7905 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7906 | |
7907 | #if __HEXAGON_ARCH__ >= 60 |
7908 | /* ========================================================================== |
7909 | Assembly Syntax: Rx32&=rol(Rs32,#u5) |
7910 | C Intrinsic Prototype: Word32 Q6_R_roland_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
7911 | Instruction Type: S_2op |
7912 | Execution Slots: SLOT23 |
7913 | ========================================================================== */ |
7914 | |
7915 | #define Q6_R_roland_RI __builtin_HEXAGON_S6_rol_i_r_and |
7916 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7917 | |
7918 | #if __HEXAGON_ARCH__ >= 60 |
7919 | /* ========================================================================== |
7920 | Assembly Syntax: Rx32-=rol(Rs32,#u5) |
7921 | C Intrinsic Prototype: Word32 Q6_R_rolnac_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
7922 | Instruction Type: S_2op |
7923 | Execution Slots: SLOT23 |
7924 | ========================================================================== */ |
7925 | |
7926 | #define Q6_R_rolnac_RI __builtin_HEXAGON_S6_rol_i_r_nac |
7927 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7928 | |
7929 | #if __HEXAGON_ARCH__ >= 60 |
7930 | /* ========================================================================== |
7931 | Assembly Syntax: Rx32|=rol(Rs32,#u5) |
7932 | C Intrinsic Prototype: Word32 Q6_R_rolor_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
7933 | Instruction Type: S_2op |
7934 | Execution Slots: SLOT23 |
7935 | ========================================================================== */ |
7936 | |
7937 | #define Q6_R_rolor_RI __builtin_HEXAGON_S6_rol_i_r_or |
7938 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7939 | |
7940 | #if __HEXAGON_ARCH__ >= 60 |
7941 | /* ========================================================================== |
7942 | Assembly Syntax: Rx32^=rol(Rs32,#u5) |
7943 | C Intrinsic Prototype: Word32 Q6_R_rolxacc_RI(Word32 Rx, Word32 Rs, Word32 Iu5) |
7944 | Instruction Type: S_2op |
7945 | Execution Slots: SLOT23 |
7946 | ========================================================================== */ |
7947 | |
7948 | #define Q6_R_rolxacc_RI __builtin_HEXAGON_S6_rol_i_r_xacc |
7949 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
7950 | |
7951 | #if __HEXAGON_ARCH__ >= 62 |
7952 | /* ========================================================================== |
7953 | Assembly Syntax: Rdd32=vabsdiffb(Rtt32,Rss32) |
7954 | C Intrinsic Prototype: Word64 Q6_P_vabsdiffb_PP(Word64 Rtt, Word64 Rss) |
7955 | Instruction Type: M |
7956 | Execution Slots: SLOT23 |
7957 | ========================================================================== */ |
7958 | |
7959 | #define Q6_P_vabsdiffb_PP __builtin_HEXAGON_M6_vabsdiffb |
7960 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
7961 | |
7962 | #if __HEXAGON_ARCH__ >= 62 |
7963 | /* ========================================================================== |
7964 | Assembly Syntax: Rdd32=vabsdiffub(Rtt32,Rss32) |
7965 | C Intrinsic Prototype: Word64 Q6_P_vabsdiffub_PP(Word64 Rtt, Word64 Rss) |
7966 | Instruction Type: M |
7967 | Execution Slots: SLOT23 |
7968 | ========================================================================== */ |
7969 | |
7970 | #define Q6_P_vabsdiffub_PP __builtin_HEXAGON_M6_vabsdiffub |
7971 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
7972 | |
7973 | #if __HEXAGON_ARCH__ >= 62 |
7974 | /* ========================================================================== |
7975 | Assembly Syntax: Rdd32=vsplatb(Rs32) |
7976 | C Intrinsic Prototype: Word64 Q6_P_vsplatb_R(Word32 Rs) |
7977 | Instruction Type: S_2op |
7978 | Execution Slots: SLOT23 |
7979 | ========================================================================== */ |
7980 | |
7981 | #define Q6_P_vsplatb_R __builtin_HEXAGON_S6_vsplatrbp |
7982 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
7983 | |
7984 | #if __HEXAGON_ARCH__ >= 62 |
7985 | /* ========================================================================== |
7986 | Assembly Syntax: Rdd32=vtrunehb(Rss32,Rtt32) |
7987 | C Intrinsic Prototype: Word64 Q6_P_vtrunehb_PP(Word64 Rss, Word64 Rtt) |
7988 | Instruction Type: S_3op |
7989 | Execution Slots: SLOT23 |
7990 | ========================================================================== */ |
7991 | |
7992 | #define Q6_P_vtrunehb_PP __builtin_HEXAGON_S6_vtrunehb_ppp |
7993 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
7994 | |
7995 | #if __HEXAGON_ARCH__ >= 62 |
7996 | /* ========================================================================== |
7997 | Assembly Syntax: Rdd32=vtrunohb(Rss32,Rtt32) |
7998 | C Intrinsic Prototype: Word64 Q6_P_vtrunohb_PP(Word64 Rss, Word64 Rtt) |
7999 | Instruction Type: S_3op |
8000 | Execution Slots: SLOT23 |
8001 | ========================================================================== */ |
8002 | |
8003 | #define Q6_P_vtrunohb_PP __builtin_HEXAGON_S6_vtrunohb_ppp |
8004 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
8005 | |
8006 | #if __HEXAGON_ARCH__ >= 65 |
8007 | /* ========================================================================== |
8008 | Assembly Syntax: Pd4=!any8(vcmpb.eq(Rss32,Rtt32)) |
8009 | C Intrinsic Prototype: Byte Q6_p_not_any8_vcmpb_eq_PP(Word64 Rss, Word64 Rtt) |
8010 | Instruction Type: ALU64 |
8011 | Execution Slots: SLOT23 |
8012 | ========================================================================== */ |
8013 | |
8014 | #define Q6_p_not_any8_vcmpb_eq_PP __builtin_HEXAGON_A6_vcmpbeq_notany |
8015 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
8016 | |
8017 | #if __HEXAGON_ARCH__ >= 66 |
8018 | /* ========================================================================== |
8019 | Assembly Syntax: Rdd32=dfadd(Rss32,Rtt32) |
8020 | C Intrinsic Prototype: Float64 Q6_P_dfadd_PP(Float64 Rss, Float64 Rtt) |
8021 | Instruction Type: M |
8022 | Execution Slots: SLOT23 |
8023 | ========================================================================== */ |
8024 | |
8025 | #define Q6_P_dfadd_PP __builtin_HEXAGON_F2_dfadd |
8026 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
8027 | |
8028 | #if __HEXAGON_ARCH__ >= 66 |
8029 | /* ========================================================================== |
8030 | Assembly Syntax: Rdd32=dfsub(Rss32,Rtt32) |
8031 | C Intrinsic Prototype: Float64 Q6_P_dfsub_PP(Float64 Rss, Float64 Rtt) |
8032 | Instruction Type: M |
8033 | Execution Slots: SLOT23 |
8034 | ========================================================================== */ |
8035 | |
8036 | #define Q6_P_dfsub_PP __builtin_HEXAGON_F2_dfsub |
8037 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
8038 | |
8039 | #if __HEXAGON_ARCH__ >= 66 |
8040 | /* ========================================================================== |
8041 | Assembly Syntax: Rx32-=mpyi(Rs32,Rt32) |
8042 | C Intrinsic Prototype: Word32 Q6_R_mpyinac_RR(Word32 Rx, Word32 Rs, Word32 Rt) |
8043 | Instruction Type: M |
8044 | Execution Slots: SLOT23 |
8045 | ========================================================================== */ |
8046 | |
8047 | #define Q6_R_mpyinac_RR __builtin_HEXAGON_M2_mnaci |
8048 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
8049 | |
8050 | #if __HEXAGON_ARCH__ >= 66 |
8051 | /* ========================================================================== |
8052 | Assembly Syntax: Rd32=mask(#u5,#U5) |
8053 | C Intrinsic Prototype: Word32 Q6_R_mask_II(Word32 Iu5, Word32 IU5) |
8054 | Instruction Type: S_2op |
8055 | Execution Slots: SLOT23 |
8056 | ========================================================================== */ |
8057 | |
8058 | #define Q6_R_mask_II __builtin_HEXAGON_S2_mask |
8059 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
8060 | |
8061 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8062 | /* ========================================================================== |
8063 | Assembly Syntax: Rd32=clip(Rs32,#u5) |
8064 | C Intrinsic Prototype: Word32 Q6_R_clip_RI(Word32 Rs, Word32 Iu5) |
8065 | Instruction Type: S_2op |
8066 | Execution Slots: SLOT23 |
8067 | ========================================================================== */ |
8068 | |
8069 | #define Q6_R_clip_RI __builtin_HEXAGON_A7_clip |
8070 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8071 | |
8072 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8073 | /* ========================================================================== |
8074 | Assembly Syntax: Rdd32=cround(Rss32,#u6) |
8075 | C Intrinsic Prototype: Word64 Q6_P_cround_PI(Word64 Rss, Word32 Iu6) |
8076 | Instruction Type: S_2op |
8077 | Execution Slots: SLOT23 |
8078 | ========================================================================== */ |
8079 | |
8080 | #define Q6_P_cround_PI __builtin_HEXAGON_A7_croundd_ri |
8081 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8082 | |
8083 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8084 | /* ========================================================================== |
8085 | Assembly Syntax: Rdd32=cround(Rss32,Rt32) |
8086 | C Intrinsic Prototype: Word64 Q6_P_cround_PR(Word64 Rss, Word32 Rt) |
8087 | Instruction Type: S_3op |
8088 | Execution Slots: SLOT23 |
8089 | ========================================================================== */ |
8090 | |
8091 | #define Q6_P_cround_PR __builtin_HEXAGON_A7_croundd_rr |
8092 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8093 | |
8094 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8095 | /* ========================================================================== |
8096 | Assembly Syntax: Rdd32=vclip(Rss32,#u5) |
8097 | C Intrinsic Prototype: Word64 Q6_P_vclip_PI(Word64 Rss, Word32 Iu5) |
8098 | Instruction Type: S_2op |
8099 | Execution Slots: SLOT23 |
8100 | ========================================================================== */ |
8101 | |
8102 | #define Q6_P_vclip_PI __builtin_HEXAGON_A7_vclip |
8103 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8104 | |
8105 | #if __HEXAGON_ARCH__ >= 67 |
8106 | /* ========================================================================== |
8107 | Assembly Syntax: Rdd32=dfmax(Rss32,Rtt32) |
8108 | C Intrinsic Prototype: Float64 Q6_P_dfmax_PP(Float64 Rss, Float64 Rtt) |
8109 | Instruction Type: M |
8110 | Execution Slots: SLOT23 |
8111 | ========================================================================== */ |
8112 | |
8113 | #define Q6_P_dfmax_PP __builtin_HEXAGON_F2_dfmax |
8114 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8115 | |
8116 | #if __HEXAGON_ARCH__ >= 67 |
8117 | /* ========================================================================== |
8118 | Assembly Syntax: Rdd32=dfmin(Rss32,Rtt32) |
8119 | C Intrinsic Prototype: Float64 Q6_P_dfmin_PP(Float64 Rss, Float64 Rtt) |
8120 | Instruction Type: M |
8121 | Execution Slots: SLOT23 |
8122 | ========================================================================== */ |
8123 | |
8124 | #define Q6_P_dfmin_PP __builtin_HEXAGON_F2_dfmin |
8125 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8126 | |
8127 | #if __HEXAGON_ARCH__ >= 67 |
8128 | /* ========================================================================== |
8129 | Assembly Syntax: Rdd32=dfmpyfix(Rss32,Rtt32) |
8130 | C Intrinsic Prototype: Float64 Q6_P_dfmpyfix_PP(Float64 Rss, Float64 Rtt) |
8131 | Instruction Type: M |
8132 | Execution Slots: SLOT23 |
8133 | ========================================================================== */ |
8134 | |
8135 | #define Q6_P_dfmpyfix_PP __builtin_HEXAGON_F2_dfmpyfix |
8136 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8137 | |
8138 | #if __HEXAGON_ARCH__ >= 67 |
8139 | /* ========================================================================== |
8140 | Assembly Syntax: Rxx32+=dfmpyhh(Rss32,Rtt32) |
8141 | C Intrinsic Prototype: Float64 Q6_P_dfmpyhhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) |
8142 | Instruction Type: M |
8143 | Execution Slots: SLOT23 |
8144 | ========================================================================== */ |
8145 | |
8146 | #define Q6_P_dfmpyhhacc_PP __builtin_HEXAGON_F2_dfmpyhh |
8147 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8148 | |
8149 | #if __HEXAGON_ARCH__ >= 67 |
8150 | /* ========================================================================== |
8151 | Assembly Syntax: Rxx32+=dfmpylh(Rss32,Rtt32) |
8152 | C Intrinsic Prototype: Float64 Q6_P_dfmpylhacc_PP(Float64 Rxx, Float64 Rss, Float64 Rtt) |
8153 | Instruction Type: M |
8154 | Execution Slots: SLOT23 |
8155 | ========================================================================== */ |
8156 | |
8157 | #define Q6_P_dfmpylhacc_PP __builtin_HEXAGON_F2_dfmpylh |
8158 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8159 | |
8160 | #if __HEXAGON_ARCH__ >= 67 |
8161 | /* ========================================================================== |
8162 | Assembly Syntax: Rdd32=dfmpyll(Rss32,Rtt32) |
8163 | C Intrinsic Prototype: Float64 Q6_P_dfmpyll_PP(Float64 Rss, Float64 Rtt) |
8164 | Instruction Type: M |
8165 | Execution Slots: SLOT23 |
8166 | ========================================================================== */ |
8167 | |
8168 | #define Q6_P_dfmpyll_PP __builtin_HEXAGON_F2_dfmpyll |
8169 | #endif /* __HEXAGON_ARCH___ >= 67 */ |
8170 | |
8171 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8172 | /* ========================================================================== |
8173 | Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32) |
8174 | C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP(Word64 Rss, Word64 Rtt) |
8175 | Instruction Type: M |
8176 | Execution Slots: SLOT3 |
8177 | ========================================================================== */ |
8178 | |
8179 | #define Q6_P_cmpyiw_PP __builtin_HEXAGON_M7_dcmpyiw |
8180 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8181 | |
8182 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8183 | /* ========================================================================== |
8184 | Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32) |
8185 | C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
8186 | Instruction Type: M |
8187 | Execution Slots: SLOT3 |
8188 | ========================================================================== */ |
8189 | |
8190 | #define Q6_P_cmpyiwacc_PP __builtin_HEXAGON_M7_dcmpyiw_acc |
8191 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8192 | |
8193 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8194 | /* ========================================================================== |
8195 | Assembly Syntax: Rdd32=cmpyiw(Rss32,Rtt32*) |
8196 | C Intrinsic Prototype: Word64 Q6_P_cmpyiw_PP_conj(Word64 Rss, Word64 Rtt) |
8197 | Instruction Type: M |
8198 | Execution Slots: SLOT3 |
8199 | ========================================================================== */ |
8200 | |
8201 | #define Q6_P_cmpyiw_PP_conj __builtin_HEXAGON_M7_dcmpyiwc |
8202 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8203 | |
8204 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8205 | /* ========================================================================== |
8206 | Assembly Syntax: Rxx32+=cmpyiw(Rss32,Rtt32*) |
8207 | C Intrinsic Prototype: Word64 Q6_P_cmpyiwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) |
8208 | Instruction Type: M |
8209 | Execution Slots: SLOT3 |
8210 | ========================================================================== */ |
8211 | |
8212 | #define Q6_P_cmpyiwacc_PP_conj __builtin_HEXAGON_M7_dcmpyiwc_acc |
8213 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8214 | |
8215 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8216 | /* ========================================================================== |
8217 | Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32) |
8218 | C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP(Word64 Rss, Word64 Rtt) |
8219 | Instruction Type: M |
8220 | Execution Slots: SLOT3 |
8221 | ========================================================================== */ |
8222 | |
8223 | #define Q6_P_cmpyrw_PP __builtin_HEXAGON_M7_dcmpyrw |
8224 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8225 | |
8226 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8227 | /* ========================================================================== |
8228 | Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32) |
8229 | C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
8230 | Instruction Type: M |
8231 | Execution Slots: SLOT3 |
8232 | ========================================================================== */ |
8233 | |
8234 | #define Q6_P_cmpyrwacc_PP __builtin_HEXAGON_M7_dcmpyrw_acc |
8235 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8236 | |
8237 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8238 | /* ========================================================================== |
8239 | Assembly Syntax: Rdd32=cmpyrw(Rss32,Rtt32*) |
8240 | C Intrinsic Prototype: Word64 Q6_P_cmpyrw_PP_conj(Word64 Rss, Word64 Rtt) |
8241 | Instruction Type: M |
8242 | Execution Slots: SLOT3 |
8243 | ========================================================================== */ |
8244 | |
8245 | #define Q6_P_cmpyrw_PP_conj __builtin_HEXAGON_M7_dcmpyrwc |
8246 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8247 | |
8248 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8249 | /* ========================================================================== |
8250 | Assembly Syntax: Rxx32+=cmpyrw(Rss32,Rtt32*) |
8251 | C Intrinsic Prototype: Word64 Q6_P_cmpyrwacc_PP_conj(Word64 Rxx, Word64 Rss, Word64 Rtt) |
8252 | Instruction Type: M |
8253 | Execution Slots: SLOT3 |
8254 | ========================================================================== */ |
8255 | |
8256 | #define Q6_P_cmpyrwacc_PP_conj __builtin_HEXAGON_M7_dcmpyrwc_acc |
8257 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8258 | |
8259 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8260 | /* ========================================================================== |
8261 | Assembly Syntax: Rdd32=vdmpyw(Rss32,Rtt32) |
8262 | C Intrinsic Prototype: Word64 Q6_P_vdmpyw_PP(Word64 Rss, Word64 Rtt) |
8263 | Instruction Type: M |
8264 | Execution Slots: SLOT3 |
8265 | ========================================================================== */ |
8266 | |
8267 | #define Q6_P_vdmpyw_PP __builtin_HEXAGON_M7_vdmpy |
8268 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8269 | |
8270 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8271 | /* ========================================================================== |
8272 | Assembly Syntax: Rxx32+=vdmpyw(Rss32,Rtt32) |
8273 | C Intrinsic Prototype: Word64 Q6_P_vdmpywacc_PP(Word64 Rxx, Word64 Rss, Word64 Rtt) |
8274 | Instruction Type: M |
8275 | Execution Slots: SLOT3 |
8276 | ========================================================================== */ |
8277 | |
8278 | #define Q6_P_vdmpywacc_PP __builtin_HEXAGON_M7_vdmpy_acc |
8279 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8280 | |
8281 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8282 | /* ========================================================================== |
8283 | Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:sat |
8284 | C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_sat(Word64 Rss, Word64 Rtt) |
8285 | Instruction Type: M |
8286 | Execution Slots: SLOT3 |
8287 | ========================================================================== */ |
8288 | |
8289 | #define Q6_R_cmpyiw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyiw |
8290 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8291 | |
8292 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8293 | /* ========================================================================== |
8294 | Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32):<<1:rnd:sat |
8295 | C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
8296 | Instruction Type: M |
8297 | Execution Slots: SLOT3 |
8298 | ========================================================================== */ |
8299 | |
8300 | #define Q6_R_cmpyiw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiw_rnd |
8301 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8302 | |
8303 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8304 | /* ========================================================================== |
8305 | Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:sat |
8306 | C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) |
8307 | Instruction Type: M |
8308 | Execution Slots: SLOT3 |
8309 | ========================================================================== */ |
8310 | |
8311 | #define Q6_R_cmpyiw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyiwc |
8312 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8313 | |
8314 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8315 | /* ========================================================================== |
8316 | Assembly Syntax: Rd32=cmpyiw(Rss32,Rtt32*):<<1:rnd:sat |
8317 | C Intrinsic Prototype: Word32 Q6_R_cmpyiw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
8318 | Instruction Type: M |
8319 | Execution Slots: SLOT3 |
8320 | ========================================================================== */ |
8321 | |
8322 | #define Q6_R_cmpyiw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyiwc_rnd |
8323 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8324 | |
8325 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8326 | /* ========================================================================== |
8327 | Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:sat |
8328 | C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_sat(Word64 Rss, Word64 Rtt) |
8329 | Instruction Type: M |
8330 | Execution Slots: SLOT3 |
8331 | ========================================================================== */ |
8332 | |
8333 | #define Q6_R_cmpyrw_PP_s1_sat __builtin_HEXAGON_M7_wcmpyrw |
8334 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8335 | |
8336 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8337 | /* ========================================================================== |
8338 | Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32):<<1:rnd:sat |
8339 | C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
8340 | Instruction Type: M |
8341 | Execution Slots: SLOT3 |
8342 | ========================================================================== */ |
8343 | |
8344 | #define Q6_R_cmpyrw_PP_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrw_rnd |
8345 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8346 | |
8347 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8348 | /* ========================================================================== |
8349 | Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:sat |
8350 | C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_sat(Word64 Rss, Word64 Rtt) |
8351 | Instruction Type: M |
8352 | Execution Slots: SLOT3 |
8353 | ========================================================================== */ |
8354 | |
8355 | #define Q6_R_cmpyrw_PP_conj_s1_sat __builtin_HEXAGON_M7_wcmpyrwc |
8356 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8357 | |
8358 | #if __HEXAGON_ARCH__ >= 67 && defined __HEXAGON_AUDIO__ |
8359 | /* ========================================================================== |
8360 | Assembly Syntax: Rd32=cmpyrw(Rss32,Rtt32*):<<1:rnd:sat |
8361 | C Intrinsic Prototype: Word32 Q6_R_cmpyrw_PP_conj_s1_rnd_sat(Word64 Rss, Word64 Rtt) |
8362 | Instruction Type: M |
8363 | Execution Slots: SLOT3 |
8364 | ========================================================================== */ |
8365 | |
8366 | #define Q6_R_cmpyrw_PP_conj_s1_rnd_sat __builtin_HEXAGON_M7_wcmpyrwc_rnd |
8367 | #endif /* __HEXAGON_ARCH___ >= 67 && defined __HEXAGON_AUDIO__*/ |
8368 | |
8369 | #if __HEXAGON_ARCH__ >= 68 |
8370 | /* ========================================================================== |
8371 | Assembly Syntax: dmlink(Rs32,Rt32) |
8372 | C Intrinsic Prototype: void Q6_dmlink_AA(Address Rs, Address Rt) |
8373 | Instruction Type: ST |
8374 | Execution Slots: SLOT0 |
8375 | ========================================================================== */ |
8376 | |
8377 | #define Q6_dmlink_AA __builtin_HEXAGON_Y6_dmlink |
8378 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8379 | |
8380 | #if __HEXAGON_ARCH__ >= 68 |
8381 | /* ========================================================================== |
8382 | Assembly Syntax: Rd32=dmpause |
8383 | C Intrinsic Prototype: Word32 Q6_R_dmpause() |
8384 | Instruction Type: ST |
8385 | Execution Slots: SLOT0 |
8386 | ========================================================================== */ |
8387 | |
8388 | #define Q6_R_dmpause __builtin_HEXAGON_Y6_dmpause |
8389 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8390 | |
8391 | #if __HEXAGON_ARCH__ >= 68 |
8392 | /* ========================================================================== |
8393 | Assembly Syntax: Rd32=dmpoll |
8394 | C Intrinsic Prototype: Word32 Q6_R_dmpoll() |
8395 | Instruction Type: ST |
8396 | Execution Slots: SLOT0 |
8397 | ========================================================================== */ |
8398 | |
8399 | #define Q6_R_dmpoll __builtin_HEXAGON_Y6_dmpoll |
8400 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8401 | |
8402 | #if __HEXAGON_ARCH__ >= 68 |
8403 | /* ========================================================================== |
8404 | Assembly Syntax: dmresume(Rs32) |
8405 | C Intrinsic Prototype: void Q6_dmresume_A(Address Rs) |
8406 | Instruction Type: ST |
8407 | Execution Slots: SLOT0 |
8408 | ========================================================================== */ |
8409 | |
8410 | #define Q6_dmresume_A __builtin_HEXAGON_Y6_dmresume |
8411 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8412 | |
8413 | #if __HEXAGON_ARCH__ >= 68 |
8414 | /* ========================================================================== |
8415 | Assembly Syntax: dmstart(Rs32) |
8416 | C Intrinsic Prototype: void Q6_dmstart_A(Address Rs) |
8417 | Instruction Type: ST |
8418 | Execution Slots: SLOT0 |
8419 | ========================================================================== */ |
8420 | |
8421 | #define Q6_dmstart_A __builtin_HEXAGON_Y6_dmstart |
8422 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8423 | |
8424 | #if __HEXAGON_ARCH__ >= 68 |
8425 | /* ========================================================================== |
8426 | Assembly Syntax: Rd32=dmwait |
8427 | C Intrinsic Prototype: Word32 Q6_R_dmwait() |
8428 | Instruction Type: ST |
8429 | Execution Slots: SLOT0 |
8430 | ========================================================================== */ |
8431 | |
8432 | #define Q6_R_dmwait __builtin_HEXAGON_Y6_dmwait |
8433 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
8434 | |
8435 | #include <hexagon_circ_brev_intrinsics.h> |
8436 | #ifdef __HVX__ |
8437 | #include <hvx_hexagon_protos.h> |
8438 | #endif /* __HVX__ */ |
8439 | #endif |
8440 |
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