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1 | //===----------------------------------------------------------------------===// |
---|---|
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // Automatically generated file, do not edit! |
9 | //===----------------------------------------------------------------------===// |
10 | |
11 | |
12 | #ifndef _HVX_HEXAGON_PROTOS_H_ |
13 | #define _HVX_HEXAGON_PROTOS_H_ 1 |
14 | |
15 | #ifdef __HVX__ |
16 | #if __HVX_LENGTH__ == 128 |
17 | #define __BUILTIN_VECTOR_WRAP(a) a ## _128B |
18 | #else |
19 | #define __BUILTIN_VECTOR_WRAP(a) a |
20 | #endif |
21 | |
22 | #if __HVX_ARCH__ >= 60 |
23 | /* ========================================================================== |
24 | Assembly Syntax: Rd32=vextract(Vu32,Rs32) |
25 | C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) |
26 | Instruction Type: LD |
27 | Execution Slots: SLOT0 |
28 | ========================================================================== */ |
29 | |
30 | #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) |
31 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
32 | |
33 | #if __HVX_ARCH__ >= 60 |
34 | /* ========================================================================== |
35 | Assembly Syntax: Vd32=hi(Vss32) |
36 | C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) |
37 | Instruction Type: CVI_VA |
38 | Execution Slots: SLOT0123 |
39 | ========================================================================== */ |
40 | |
41 | #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) |
42 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
43 | |
44 | #if __HVX_ARCH__ >= 60 |
45 | /* ========================================================================== |
46 | Assembly Syntax: Vd32=lo(Vss32) |
47 | C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) |
48 | Instruction Type: CVI_VA |
49 | Execution Slots: SLOT0123 |
50 | ========================================================================== */ |
51 | |
52 | #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) |
53 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
54 | |
55 | #if __HVX_ARCH__ >= 60 |
56 | /* ========================================================================== |
57 | Assembly Syntax: Vd32=vsplat(Rt32) |
58 | C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) |
59 | Instruction Type: CVI_VX_LATE |
60 | Execution Slots: SLOT23 |
61 | ========================================================================== */ |
62 | |
63 | #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) |
64 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
65 | |
66 | #if __HVX_ARCH__ >= 60 |
67 | /* ========================================================================== |
68 | Assembly Syntax: Qd4=and(Qs4,Qt4) |
69 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
70 | Instruction Type: CVI_VA_DV |
71 | Execution Slots: SLOT0123 |
72 | ========================================================================== */ |
73 | |
74 | #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
75 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
76 | |
77 | #if __HVX_ARCH__ >= 60 |
78 | /* ========================================================================== |
79 | Assembly Syntax: Qd4=and(Qs4,!Qt4) |
80 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
81 | Instruction Type: CVI_VA_DV |
82 | Execution Slots: SLOT0123 |
83 | ========================================================================== */ |
84 | |
85 | #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
86 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
87 | |
88 | #if __HVX_ARCH__ >= 60 |
89 | /* ========================================================================== |
90 | Assembly Syntax: Qd4=not(Qs4) |
91 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) |
92 | Instruction Type: CVI_VA |
93 | Execution Slots: SLOT0123 |
94 | ========================================================================== */ |
95 | |
96 | #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) |
97 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
98 | |
99 | #if __HVX_ARCH__ >= 60 |
100 | /* ========================================================================== |
101 | Assembly Syntax: Qd4=or(Qs4,Qt4) |
102 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
103 | Instruction Type: CVI_VA_DV |
104 | Execution Slots: SLOT0123 |
105 | ========================================================================== */ |
106 | |
107 | #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
108 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
109 | |
110 | #if __HVX_ARCH__ >= 60 |
111 | /* ========================================================================== |
112 | Assembly Syntax: Qd4=or(Qs4,!Qt4) |
113 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
114 | Instruction Type: CVI_VA_DV |
115 | Execution Slots: SLOT0123 |
116 | ========================================================================== */ |
117 | |
118 | #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
119 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
120 | |
121 | #if __HVX_ARCH__ >= 60 |
122 | /* ========================================================================== |
123 | Assembly Syntax: Qd4=vsetq(Rt32) |
124 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) |
125 | Instruction Type: CVI_VP |
126 | Execution Slots: SLOT0123 |
127 | ========================================================================== */ |
128 | |
129 | #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) |
130 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
131 | |
132 | #if __HVX_ARCH__ >= 60 |
133 | /* ========================================================================== |
134 | Assembly Syntax: Qd4=xor(Qs4,Qt4) |
135 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
136 | Instruction Type: CVI_VA_DV |
137 | Execution Slots: SLOT0123 |
138 | ========================================================================== */ |
139 | |
140 | #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
141 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
142 | |
143 | #if __HVX_ARCH__ >= 60 |
144 | /* ========================================================================== |
145 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 |
146 | C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
147 | Instruction Type: CVI_VM_ST |
148 | Execution Slots: SLOT0 |
149 | ========================================================================== */ |
150 | |
151 | #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
152 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
153 | |
154 | #if __HVX_ARCH__ >= 60 |
155 | /* ========================================================================== |
156 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 |
157 | C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
158 | Instruction Type: CVI_VM_ST |
159 | Execution Slots: SLOT0 |
160 | ========================================================================== */ |
161 | |
162 | #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
163 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
164 | |
165 | #if __HVX_ARCH__ >= 60 |
166 | /* ========================================================================== |
167 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 |
168 | C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
169 | Instruction Type: CVI_VM_ST |
170 | Execution Slots: SLOT0 |
171 | ========================================================================== */ |
172 | |
173 | #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
174 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
175 | |
176 | #if __HVX_ARCH__ >= 60 |
177 | /* ========================================================================== |
178 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 |
179 | C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
180 | Instruction Type: CVI_VM_ST |
181 | Execution Slots: SLOT0 |
182 | ========================================================================== */ |
183 | |
184 | #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) |
185 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
186 | |
187 | #if __HVX_ARCH__ >= 60 |
188 | /* ========================================================================== |
189 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) |
190 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
191 | Instruction Type: CVI_VX |
192 | Execution Slots: SLOT23 |
193 | ========================================================================== */ |
194 | |
195 | #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) |
196 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
197 | |
198 | #if __HVX_ARCH__ >= 60 |
199 | /* ========================================================================== |
200 | Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) |
201 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
202 | Instruction Type: CVI_VX |
203 | Execution Slots: SLOT23 |
204 | ========================================================================== */ |
205 | |
206 | #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) |
207 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
208 | |
209 | #if __HVX_ARCH__ >= 60 |
210 | /* ========================================================================== |
211 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) |
212 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
213 | Instruction Type: CVI_VX |
214 | Execution Slots: SLOT23 |
215 | ========================================================================== */ |
216 | |
217 | #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) |
218 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
219 | |
220 | #if __HVX_ARCH__ >= 60 |
221 | /* ========================================================================== |
222 | Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) |
223 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
224 | Instruction Type: CVI_VX |
225 | Execution Slots: SLOT23 |
226 | ========================================================================== */ |
227 | |
228 | #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) |
229 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
230 | |
231 | #if __HVX_ARCH__ >= 60 |
232 | /* ========================================================================== |
233 | Assembly Syntax: Vd32.h=vabs(Vu32.h) |
234 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) |
235 | Instruction Type: CVI_VA |
236 | Execution Slots: SLOT0123 |
237 | ========================================================================== */ |
238 | |
239 | #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) |
240 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
241 | |
242 | #if __HVX_ARCH__ >= 60 |
243 | /* ========================================================================== |
244 | Assembly Syntax: Vd32.h=vabs(Vu32.h):sat |
245 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) |
246 | Instruction Type: CVI_VA |
247 | Execution Slots: SLOT0123 |
248 | ========================================================================== */ |
249 | |
250 | #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) |
251 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
252 | |
253 | #if __HVX_ARCH__ >= 60 |
254 | /* ========================================================================== |
255 | Assembly Syntax: Vd32.w=vabs(Vu32.w) |
256 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) |
257 | Instruction Type: CVI_VA |
258 | Execution Slots: SLOT0123 |
259 | ========================================================================== */ |
260 | |
261 | #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) |
262 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
263 | |
264 | #if __HVX_ARCH__ >= 60 |
265 | /* ========================================================================== |
266 | Assembly Syntax: Vd32.w=vabs(Vu32.w):sat |
267 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) |
268 | Instruction Type: CVI_VA |
269 | Execution Slots: SLOT0123 |
270 | ========================================================================== */ |
271 | |
272 | #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) |
273 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
274 | |
275 | #if __HVX_ARCH__ >= 60 |
276 | /* ========================================================================== |
277 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) |
278 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
279 | Instruction Type: CVI_VA |
280 | Execution Slots: SLOT0123 |
281 | ========================================================================== */ |
282 | |
283 | #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) |
284 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
285 | |
286 | #if __HVX_ARCH__ >= 60 |
287 | /* ========================================================================== |
288 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) |
289 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
290 | Instruction Type: CVI_VA_DV |
291 | Execution Slots: SLOT0123 |
292 | ========================================================================== */ |
293 | |
294 | #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) |
295 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
296 | |
297 | #if __HVX_ARCH__ >= 60 |
298 | /* ========================================================================== |
299 | Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b |
300 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
301 | Instruction Type: CVI_VA |
302 | Execution Slots: SLOT0123 |
303 | ========================================================================== */ |
304 | |
305 | #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
306 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
307 | |
308 | #if __HVX_ARCH__ >= 60 |
309 | /* ========================================================================== |
310 | Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b |
311 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
312 | Instruction Type: CVI_VA |
313 | Execution Slots: SLOT0123 |
314 | ========================================================================== */ |
315 | |
316 | #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
317 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
318 | |
319 | #if __HVX_ARCH__ >= 60 |
320 | /* ========================================================================== |
321 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) |
322 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
323 | Instruction Type: CVI_VA |
324 | Execution Slots: SLOT0123 |
325 | ========================================================================== */ |
326 | |
327 | #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) |
328 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
329 | |
330 | #if __HVX_ARCH__ >= 60 |
331 | /* ========================================================================== |
332 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) |
333 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
334 | Instruction Type: CVI_VA_DV |
335 | Execution Slots: SLOT0123 |
336 | ========================================================================== */ |
337 | |
338 | #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) |
339 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
340 | |
341 | #if __HVX_ARCH__ >= 60 |
342 | /* ========================================================================== |
343 | Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h |
344 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
345 | Instruction Type: CVI_VA |
346 | Execution Slots: SLOT0123 |
347 | ========================================================================== */ |
348 | |
349 | #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
350 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
351 | |
352 | #if __HVX_ARCH__ >= 60 |
353 | /* ========================================================================== |
354 | Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h |
355 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
356 | Instruction Type: CVI_VA |
357 | Execution Slots: SLOT0123 |
358 | ========================================================================== */ |
359 | |
360 | #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
361 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
362 | |
363 | #if __HVX_ARCH__ >= 60 |
364 | /* ========================================================================== |
365 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat |
366 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
367 | Instruction Type: CVI_VA |
368 | Execution Slots: SLOT0123 |
369 | ========================================================================== */ |
370 | |
371 | #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) |
372 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
373 | |
374 | #if __HVX_ARCH__ >= 60 |
375 | /* ========================================================================== |
376 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat |
377 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
378 | Instruction Type: CVI_VA_DV |
379 | Execution Slots: SLOT0123 |
380 | ========================================================================== */ |
381 | |
382 | #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) |
383 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
384 | |
385 | #if __HVX_ARCH__ >= 60 |
386 | /* ========================================================================== |
387 | Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) |
388 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
389 | Instruction Type: CVI_VX_DV |
390 | Execution Slots: SLOT23 |
391 | ========================================================================== */ |
392 | |
393 | #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) |
394 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
395 | |
396 | #if __HVX_ARCH__ >= 60 |
397 | /* ========================================================================== |
398 | Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) |
399 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
400 | Instruction Type: CVI_VX_DV |
401 | Execution Slots: SLOT23 |
402 | ========================================================================== */ |
403 | |
404 | #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) |
405 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
406 | |
407 | #if __HVX_ARCH__ >= 60 |
408 | /* ========================================================================== |
409 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat |
410 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
411 | Instruction Type: CVI_VA |
412 | Execution Slots: SLOT0123 |
413 | ========================================================================== */ |
414 | |
415 | #define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) |
416 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
417 | |
418 | #if __HVX_ARCH__ >= 60 |
419 | /* ========================================================================== |
420 | Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat |
421 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
422 | Instruction Type: CVI_VA_DV |
423 | Execution Slots: SLOT0123 |
424 | ========================================================================== */ |
425 | |
426 | #define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) |
427 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
428 | |
429 | #if __HVX_ARCH__ >= 60 |
430 | /* ========================================================================== |
431 | Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat |
432 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
433 | Instruction Type: CVI_VA |
434 | Execution Slots: SLOT0123 |
435 | ========================================================================== */ |
436 | |
437 | #define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) |
438 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
439 | |
440 | #if __HVX_ARCH__ >= 60 |
441 | /* ========================================================================== |
442 | Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat |
443 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
444 | Instruction Type: CVI_VA_DV |
445 | Execution Slots: SLOT0123 |
446 | ========================================================================== */ |
447 | |
448 | #define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) |
449 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
450 | |
451 | #if __HVX_ARCH__ >= 60 |
452 | /* ========================================================================== |
453 | Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) |
454 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
455 | Instruction Type: CVI_VX_DV |
456 | Execution Slots: SLOT23 |
457 | ========================================================================== */ |
458 | |
459 | #define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) |
460 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
461 | |
462 | #if __HVX_ARCH__ >= 60 |
463 | /* ========================================================================== |
464 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) |
465 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
466 | Instruction Type: CVI_VA |
467 | Execution Slots: SLOT0123 |
468 | ========================================================================== */ |
469 | |
470 | #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) |
471 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
472 | |
473 | #if __HVX_ARCH__ >= 60 |
474 | /* ========================================================================== |
475 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) |
476 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
477 | Instruction Type: CVI_VA_DV |
478 | Execution Slots: SLOT0123 |
479 | ========================================================================== */ |
480 | |
481 | #define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) |
482 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
483 | |
484 | #if __HVX_ARCH__ >= 60 |
485 | /* ========================================================================== |
486 | Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w |
487 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
488 | Instruction Type: CVI_VA |
489 | Execution Slots: SLOT0123 |
490 | ========================================================================== */ |
491 | |
492 | #define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
493 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
494 | |
495 | #if __HVX_ARCH__ >= 60 |
496 | /* ========================================================================== |
497 | Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w |
498 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
499 | Instruction Type: CVI_VA |
500 | Execution Slots: SLOT0123 |
501 | ========================================================================== */ |
502 | |
503 | #define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
504 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
505 | |
506 | #if __HVX_ARCH__ >= 60 |
507 | /* ========================================================================== |
508 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat |
509 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
510 | Instruction Type: CVI_VA |
511 | Execution Slots: SLOT0123 |
512 | ========================================================================== */ |
513 | |
514 | #define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) |
515 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
516 | |
517 | #if __HVX_ARCH__ >= 60 |
518 | /* ========================================================================== |
519 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat |
520 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
521 | Instruction Type: CVI_VA_DV |
522 | Execution Slots: SLOT0123 |
523 | ========================================================================== */ |
524 | |
525 | #define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) |
526 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
527 | |
528 | #if __HVX_ARCH__ >= 60 |
529 | /* ========================================================================== |
530 | Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) |
531 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
532 | Instruction Type: CVI_VP |
533 | Execution Slots: SLOT0123 |
534 | ========================================================================== */ |
535 | |
536 | #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) |
537 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
538 | |
539 | #if __HVX_ARCH__ >= 60 |
540 | /* ========================================================================== |
541 | Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) |
542 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
543 | Instruction Type: CVI_VP |
544 | Execution Slots: SLOT0123 |
545 | ========================================================================== */ |
546 | |
547 | #define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) |
548 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
549 | |
550 | #if __HVX_ARCH__ >= 60 |
551 | /* ========================================================================== |
552 | Assembly Syntax: Vd32=vand(Vu32,Vv32) |
553 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) |
554 | Instruction Type: CVI_VA |
555 | Execution Slots: SLOT0123 |
556 | ========================================================================== */ |
557 | |
558 | #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) |
559 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
560 | |
561 | #if __HVX_ARCH__ >= 60 |
562 | /* ========================================================================== |
563 | Assembly Syntax: Vd32=vand(Qu4,Rt32) |
564 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) |
565 | Instruction Type: CVI_VX_LATE |
566 | Execution Slots: SLOT23 |
567 | ========================================================================== */ |
568 | |
569 | #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
570 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
571 | |
572 | #if __HVX_ARCH__ >= 60 |
573 | /* ========================================================================== |
574 | Assembly Syntax: Vx32|=vand(Qu4,Rt32) |
575 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
576 | Instruction Type: CVI_VX_LATE |
577 | Execution Slots: SLOT23 |
578 | ========================================================================== */ |
579 | |
580 | #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
581 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
582 | |
583 | #if __HVX_ARCH__ >= 60 |
584 | /* ========================================================================== |
585 | Assembly Syntax: Qd4=vand(Vu32,Rt32) |
586 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) |
587 | Instruction Type: CVI_VX_LATE |
588 | Execution Slots: SLOT23 |
589 | ========================================================================== */ |
590 | |
591 | #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) |
592 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
593 | |
594 | #if __HVX_ARCH__ >= 60 |
595 | /* ========================================================================== |
596 | Assembly Syntax: Qx4|=vand(Vu32,Rt32) |
597 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) |
598 | Instruction Type: CVI_VX_LATE |
599 | Execution Slots: SLOT23 |
600 | ========================================================================== */ |
601 | |
602 | #define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) |
603 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
604 | |
605 | #if __HVX_ARCH__ >= 60 |
606 | /* ========================================================================== |
607 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) |
608 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) |
609 | Instruction Type: CVI_VS |
610 | Execution Slots: SLOT0123 |
611 | ========================================================================== */ |
612 | |
613 | #define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) |
614 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
615 | |
616 | #if __HVX_ARCH__ >= 60 |
617 | /* ========================================================================== |
618 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) |
619 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
620 | Instruction Type: CVI_VS |
621 | Execution Slots: SLOT0123 |
622 | ========================================================================== */ |
623 | |
624 | #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) |
625 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
626 | |
627 | #if __HVX_ARCH__ >= 60 |
628 | /* ========================================================================== |
629 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) |
630 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) |
631 | Instruction Type: CVI_VS |
632 | Execution Slots: SLOT0123 |
633 | ========================================================================== */ |
634 | |
635 | #define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) |
636 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
637 | |
638 | #if __HVX_ARCH__ >= 60 |
639 | /* ========================================================================== |
640 | Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) |
641 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
642 | Instruction Type: CVI_VS |
643 | Execution Slots: SLOT0123 |
644 | ========================================================================== */ |
645 | |
646 | #define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) |
647 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
648 | |
649 | #if __HVX_ARCH__ >= 60 |
650 | /* ========================================================================== |
651 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) |
652 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
653 | Instruction Type: CVI_VS |
654 | Execution Slots: SLOT0123 |
655 | ========================================================================== */ |
656 | |
657 | #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) |
658 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
659 | |
660 | #if __HVX_ARCH__ >= 60 |
661 | /* ========================================================================== |
662 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) |
663 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) |
664 | Instruction Type: CVI_VS |
665 | Execution Slots: SLOT0123 |
666 | ========================================================================== */ |
667 | |
668 | #define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) |
669 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
670 | |
671 | #if __HVX_ARCH__ >= 60 |
672 | /* ========================================================================== |
673 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
674 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
675 | Instruction Type: CVI_VS |
676 | Execution Slots: SLOT0123 |
677 | ========================================================================== */ |
678 | |
679 | #define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) |
680 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
681 | |
682 | #if __HVX_ARCH__ >= 60 |
683 | /* ========================================================================== |
684 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
685 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
686 | Instruction Type: CVI_VS |
687 | Execution Slots: SLOT0123 |
688 | ========================================================================== */ |
689 | |
690 | #define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) |
691 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
692 | |
693 | #if __HVX_ARCH__ >= 60 |
694 | /* ========================================================================== |
695 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat |
696 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
697 | Instruction Type: CVI_VS |
698 | Execution Slots: SLOT0123 |
699 | ========================================================================== */ |
700 | |
701 | #define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) |
702 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
703 | |
704 | #if __HVX_ARCH__ >= 60 |
705 | /* ========================================================================== |
706 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) |
707 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
708 | Instruction Type: CVI_VS |
709 | Execution Slots: SLOT0123 |
710 | ========================================================================== */ |
711 | |
712 | #define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) |
713 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
714 | |
715 | #if __HVX_ARCH__ >= 60 |
716 | /* ========================================================================== |
717 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) |
718 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) |
719 | Instruction Type: CVI_VS |
720 | Execution Slots: SLOT0123 |
721 | ========================================================================== */ |
722 | |
723 | #define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) |
724 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
725 | |
726 | #if __HVX_ARCH__ >= 60 |
727 | /* ========================================================================== |
728 | Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) |
729 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
730 | Instruction Type: CVI_VS |
731 | Execution Slots: SLOT0123 |
732 | ========================================================================== */ |
733 | |
734 | #define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) |
735 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
736 | |
737 | #if __HVX_ARCH__ >= 60 |
738 | /* ========================================================================== |
739 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) |
740 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
741 | Instruction Type: CVI_VS |
742 | Execution Slots: SLOT0123 |
743 | ========================================================================== */ |
744 | |
745 | #define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) |
746 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
747 | |
748 | #if __HVX_ARCH__ >= 60 |
749 | /* ========================================================================== |
750 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
751 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
752 | Instruction Type: CVI_VS |
753 | Execution Slots: SLOT0123 |
754 | ========================================================================== */ |
755 | |
756 | #define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) |
757 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
758 | |
759 | #if __HVX_ARCH__ >= 60 |
760 | /* ========================================================================== |
761 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat |
762 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
763 | Instruction Type: CVI_VS |
764 | Execution Slots: SLOT0123 |
765 | ========================================================================== */ |
766 | |
767 | #define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) |
768 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
769 | |
770 | #if __HVX_ARCH__ >= 60 |
771 | /* ========================================================================== |
772 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat |
773 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
774 | Instruction Type: CVI_VS |
775 | Execution Slots: SLOT0123 |
776 | ========================================================================== */ |
777 | |
778 | #define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) |
779 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
780 | |
781 | #if __HVX_ARCH__ >= 60 |
782 | /* ========================================================================== |
783 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) |
784 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
785 | Instruction Type: CVI_VS |
786 | Execution Slots: SLOT0123 |
787 | ========================================================================== */ |
788 | |
789 | #define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) |
790 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
791 | |
792 | #if __HVX_ARCH__ >= 60 |
793 | /* ========================================================================== |
794 | Assembly Syntax: Vd32=Vu32 |
795 | C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) |
796 | Instruction Type: CVI_VA |
797 | Execution Slots: SLOT0123 |
798 | ========================================================================== */ |
799 | |
800 | #define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) |
801 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
802 | |
803 | #if __HVX_ARCH__ >= 60 |
804 | /* ========================================================================== |
805 | Assembly Syntax: Vdd32=Vuu32 |
806 | C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) |
807 | Instruction Type: CVI_VA_DV |
808 | Execution Slots: SLOT0123 |
809 | ========================================================================== */ |
810 | |
811 | #define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) |
812 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
813 | |
814 | #if __HVX_ARCH__ >= 60 |
815 | /* ========================================================================== |
816 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) |
817 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
818 | Instruction Type: CVI_VA |
819 | Execution Slots: SLOT0123 |
820 | ========================================================================== */ |
821 | |
822 | #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) |
823 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
824 | |
825 | #if __HVX_ARCH__ >= 60 |
826 | /* ========================================================================== |
827 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd |
828 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
829 | Instruction Type: CVI_VA |
830 | Execution Slots: SLOT0123 |
831 | ========================================================================== */ |
832 | |
833 | #define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) |
834 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
835 | |
836 | #if __HVX_ARCH__ >= 60 |
837 | /* ========================================================================== |
838 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) |
839 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
840 | Instruction Type: CVI_VA |
841 | Execution Slots: SLOT0123 |
842 | ========================================================================== */ |
843 | |
844 | #define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) |
845 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
846 | |
847 | #if __HVX_ARCH__ >= 60 |
848 | /* ========================================================================== |
849 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd |
850 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) |
851 | Instruction Type: CVI_VA |
852 | Execution Slots: SLOT0123 |
853 | ========================================================================== */ |
854 | |
855 | #define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) |
856 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
857 | |
858 | #if __HVX_ARCH__ >= 60 |
859 | /* ========================================================================== |
860 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) |
861 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
862 | Instruction Type: CVI_VA |
863 | Execution Slots: SLOT0123 |
864 | ========================================================================== */ |
865 | |
866 | #define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) |
867 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
868 | |
869 | #if __HVX_ARCH__ >= 60 |
870 | /* ========================================================================== |
871 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd |
872 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
873 | Instruction Type: CVI_VA |
874 | Execution Slots: SLOT0123 |
875 | ========================================================================== */ |
876 | |
877 | #define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) |
878 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
879 | |
880 | #if __HVX_ARCH__ >= 60 |
881 | /* ========================================================================== |
882 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) |
883 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
884 | Instruction Type: CVI_VA |
885 | Execution Slots: SLOT0123 |
886 | ========================================================================== */ |
887 | |
888 | #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) |
889 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
890 | |
891 | #if __HVX_ARCH__ >= 60 |
892 | /* ========================================================================== |
893 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd |
894 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
895 | Instruction Type: CVI_VA |
896 | Execution Slots: SLOT0123 |
897 | ========================================================================== */ |
898 | |
899 | #define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) |
900 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
901 | |
902 | #if __HVX_ARCH__ >= 60 |
903 | /* ========================================================================== |
904 | Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) |
905 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) |
906 | Instruction Type: CVI_VS |
907 | Execution Slots: SLOT0123 |
908 | ========================================================================== */ |
909 | |
910 | #define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) |
911 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
912 | |
913 | #if __HVX_ARCH__ >= 60 |
914 | /* ========================================================================== |
915 | Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) |
916 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) |
917 | Instruction Type: CVI_VS |
918 | Execution Slots: SLOT0123 |
919 | ========================================================================== */ |
920 | |
921 | #define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) |
922 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
923 | |
924 | #if __HVX_ARCH__ >= 60 |
925 | /* ========================================================================== |
926 | Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) |
927 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) |
928 | Instruction Type: CVI_VA_DV |
929 | Execution Slots: SLOT0123 |
930 | ========================================================================== */ |
931 | |
932 | #define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) |
933 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
934 | |
935 | #if __HVX_ARCH__ >= 60 |
936 | /* ========================================================================== |
937 | Assembly Syntax: Vd32=#0 |
938 | C Intrinsic Prototype: HVX_Vector Q6_V_vzero() |
939 | Instruction Type: CVI_VA |
940 | Execution Slots: SLOT0123 |
941 | ========================================================================== */ |
942 | |
943 | #define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() |
944 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
945 | |
946 | #if __HVX_ARCH__ >= 60 |
947 | /* ========================================================================== |
948 | Assembly Syntax: Vd32.b=vdeal(Vu32.b) |
949 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) |
950 | Instruction Type: CVI_VP |
951 | Execution Slots: SLOT0123 |
952 | ========================================================================== */ |
953 | |
954 | #define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) |
955 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
956 | |
957 | #if __HVX_ARCH__ >= 60 |
958 | /* ========================================================================== |
959 | Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) |
960 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
961 | Instruction Type: CVI_VP |
962 | Execution Slots: SLOT0123 |
963 | ========================================================================== */ |
964 | |
965 | #define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) |
966 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
967 | |
968 | #if __HVX_ARCH__ >= 60 |
969 | /* ========================================================================== |
970 | Assembly Syntax: Vd32.h=vdeal(Vu32.h) |
971 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) |
972 | Instruction Type: CVI_VP |
973 | Execution Slots: SLOT0123 |
974 | ========================================================================== */ |
975 | |
976 | #define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) |
977 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
978 | |
979 | #if __HVX_ARCH__ >= 60 |
980 | /* ========================================================================== |
981 | Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) |
982 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
983 | Instruction Type: CVI_VP_VS |
984 | Execution Slots: SLOT0123 |
985 | ========================================================================== */ |
986 | |
987 | #define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) |
988 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
989 | |
990 | #if __HVX_ARCH__ >= 60 |
991 | /* ========================================================================== |
992 | Assembly Syntax: Vd32=vdelta(Vu32,Vv32) |
993 | C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
994 | Instruction Type: CVI_VP |
995 | Execution Slots: SLOT0123 |
996 | ========================================================================== */ |
997 | |
998 | #define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) |
999 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1000 | |
1001 | #if __HVX_ARCH__ >= 60 |
1002 | /* ========================================================================== |
1003 | Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) |
1004 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
1005 | Instruction Type: CVI_VX |
1006 | Execution Slots: SLOT23 |
1007 | ========================================================================== */ |
1008 | |
1009 | #define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) |
1010 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1011 | |
1012 | #if __HVX_ARCH__ >= 60 |
1013 | /* ========================================================================== |
1014 | Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) |
1015 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
1016 | Instruction Type: CVI_VX |
1017 | Execution Slots: SLOT23 |
1018 | ========================================================================== */ |
1019 | |
1020 | #define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) |
1021 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1022 | |
1023 | #if __HVX_ARCH__ >= 60 |
1024 | /* ========================================================================== |
1025 | Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) |
1026 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
1027 | Instruction Type: CVI_VX_DV |
1028 | Execution Slots: SLOT23 |
1029 | ========================================================================== */ |
1030 | |
1031 | #define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) |
1032 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1033 | |
1034 | #if __HVX_ARCH__ >= 60 |
1035 | /* ========================================================================== |
1036 | Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) |
1037 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
1038 | Instruction Type: CVI_VX_DV |
1039 | Execution Slots: SLOT23 |
1040 | ========================================================================== */ |
1041 | |
1042 | #define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) |
1043 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1044 | |
1045 | #if __HVX_ARCH__ >= 60 |
1046 | /* ========================================================================== |
1047 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) |
1048 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) |
1049 | Instruction Type: CVI_VX |
1050 | Execution Slots: SLOT23 |
1051 | ========================================================================== */ |
1052 | |
1053 | #define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) |
1054 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1055 | |
1056 | #if __HVX_ARCH__ >= 60 |
1057 | /* ========================================================================== |
1058 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) |
1059 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
1060 | Instruction Type: CVI_VX |
1061 | Execution Slots: SLOT23 |
1062 | ========================================================================== */ |
1063 | |
1064 | #define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) |
1065 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1066 | |
1067 | #if __HVX_ARCH__ >= 60 |
1068 | /* ========================================================================== |
1069 | Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) |
1070 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
1071 | Instruction Type: CVI_VX_DV |
1072 | Execution Slots: SLOT23 |
1073 | ========================================================================== */ |
1074 | |
1075 | #define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) |
1076 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1077 | |
1078 | #if __HVX_ARCH__ >= 60 |
1079 | /* ========================================================================== |
1080 | Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) |
1081 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
1082 | Instruction Type: CVI_VX_DV |
1083 | Execution Slots: SLOT23 |
1084 | ========================================================================== */ |
1085 | |
1086 | #define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) |
1087 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1088 | |
1089 | #if __HVX_ARCH__ >= 60 |
1090 | /* ========================================================================== |
1091 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat |
1092 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) |
1093 | Instruction Type: CVI_VX_DV |
1094 | Execution Slots: SLOT23 |
1095 | ========================================================================== */ |
1096 | |
1097 | #define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) |
1098 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1099 | |
1100 | #if __HVX_ARCH__ >= 60 |
1101 | /* ========================================================================== |
1102 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat |
1103 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
1104 | Instruction Type: CVI_VX_DV |
1105 | Execution Slots: SLOT23 |
1106 | ========================================================================== */ |
1107 | |
1108 | #define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) |
1109 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1110 | |
1111 | #if __HVX_ARCH__ >= 60 |
1112 | /* ========================================================================== |
1113 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat |
1114 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) |
1115 | Instruction Type: CVI_VX |
1116 | Execution Slots: SLOT23 |
1117 | ========================================================================== */ |
1118 | |
1119 | #define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) |
1120 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1121 | |
1122 | #if __HVX_ARCH__ >= 60 |
1123 | /* ========================================================================== |
1124 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat |
1125 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
1126 | Instruction Type: CVI_VX |
1127 | Execution Slots: SLOT23 |
1128 | ========================================================================== */ |
1129 | |
1130 | #define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) |
1131 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1132 | |
1133 | #if __HVX_ARCH__ >= 60 |
1134 | /* ========================================================================== |
1135 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
1136 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) |
1137 | Instruction Type: CVI_VX_DV |
1138 | Execution Slots: SLOT23 |
1139 | ========================================================================== */ |
1140 | |
1141 | #define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) |
1142 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1143 | |
1144 | #if __HVX_ARCH__ >= 60 |
1145 | /* ========================================================================== |
1146 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
1147 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
1148 | Instruction Type: CVI_VX_DV |
1149 | Execution Slots: SLOT23 |
1150 | ========================================================================== */ |
1151 | |
1152 | #define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) |
1153 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1154 | |
1155 | #if __HVX_ARCH__ >= 60 |
1156 | /* ========================================================================== |
1157 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat |
1158 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) |
1159 | Instruction Type: CVI_VX |
1160 | Execution Slots: SLOT23 |
1161 | ========================================================================== */ |
1162 | |
1163 | #define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) |
1164 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1165 | |
1166 | #if __HVX_ARCH__ >= 60 |
1167 | /* ========================================================================== |
1168 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat |
1169 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
1170 | Instruction Type: CVI_VX |
1171 | Execution Slots: SLOT23 |
1172 | ========================================================================== */ |
1173 | |
1174 | #define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) |
1175 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1176 | |
1177 | #if __HVX_ARCH__ >= 60 |
1178 | /* ========================================================================== |
1179 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat |
1180 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
1181 | Instruction Type: CVI_VX |
1182 | Execution Slots: SLOT23 |
1183 | ========================================================================== */ |
1184 | |
1185 | #define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) |
1186 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1187 | |
1188 | #if __HVX_ARCH__ >= 60 |
1189 | /* ========================================================================== |
1190 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat |
1191 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
1192 | Instruction Type: CVI_VX_DV |
1193 | Execution Slots: SLOT23 |
1194 | ========================================================================== */ |
1195 | |
1196 | #define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) |
1197 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1198 | |
1199 | #if __HVX_ARCH__ >= 60 |
1200 | /* ========================================================================== |
1201 | Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) |
1202 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) |
1203 | Instruction Type: CVI_VX_DV |
1204 | Execution Slots: SLOT23 |
1205 | ========================================================================== */ |
1206 | |
1207 | #define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) |
1208 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1209 | |
1210 | #if __HVX_ARCH__ >= 60 |
1211 | /* ========================================================================== |
1212 | Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) |
1213 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
1214 | Instruction Type: CVI_VX_DV |
1215 | Execution Slots: SLOT23 |
1216 | ========================================================================== */ |
1217 | |
1218 | #define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) |
1219 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1220 | |
1221 | #if __HVX_ARCH__ >= 60 |
1222 | /* ========================================================================== |
1223 | Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) |
1224 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
1225 | Instruction Type: CVI_VA |
1226 | Execution Slots: SLOT0123 |
1227 | ========================================================================== */ |
1228 | |
1229 | #define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) |
1230 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1231 | |
1232 | #if __HVX_ARCH__ >= 60 |
1233 | /* ========================================================================== |
1234 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) |
1235 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1236 | Instruction Type: CVI_VA |
1237 | Execution Slots: SLOT0123 |
1238 | ========================================================================== */ |
1239 | |
1240 | #define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1241 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1242 | |
1243 | #if __HVX_ARCH__ >= 60 |
1244 | /* ========================================================================== |
1245 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) |
1246 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1247 | Instruction Type: CVI_VA |
1248 | Execution Slots: SLOT0123 |
1249 | ========================================================================== */ |
1250 | |
1251 | #define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1252 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1253 | |
1254 | #if __HVX_ARCH__ >= 60 |
1255 | /* ========================================================================== |
1256 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) |
1257 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1258 | Instruction Type: CVI_VA |
1259 | Execution Slots: SLOT0123 |
1260 | ========================================================================== */ |
1261 | |
1262 | #define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1263 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1264 | |
1265 | #if __HVX_ARCH__ >= 60 |
1266 | /* ========================================================================== |
1267 | Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) |
1268 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
1269 | Instruction Type: CVI_VA |
1270 | Execution Slots: SLOT0123 |
1271 | ========================================================================== */ |
1272 | |
1273 | #define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) |
1274 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1275 | |
1276 | #if __HVX_ARCH__ >= 60 |
1277 | /* ========================================================================== |
1278 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) |
1279 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1280 | Instruction Type: CVI_VA |
1281 | Execution Slots: SLOT0123 |
1282 | ========================================================================== */ |
1283 | |
1284 | #define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1285 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1286 | |
1287 | #if __HVX_ARCH__ >= 60 |
1288 | /* ========================================================================== |
1289 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) |
1290 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1291 | Instruction Type: CVI_VA |
1292 | Execution Slots: SLOT0123 |
1293 | ========================================================================== */ |
1294 | |
1295 | #define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1296 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1297 | |
1298 | #if __HVX_ARCH__ >= 60 |
1299 | /* ========================================================================== |
1300 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) |
1301 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1302 | Instruction Type: CVI_VA |
1303 | Execution Slots: SLOT0123 |
1304 | ========================================================================== */ |
1305 | |
1306 | #define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1307 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1308 | |
1309 | #if __HVX_ARCH__ >= 60 |
1310 | /* ========================================================================== |
1311 | Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) |
1312 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
1313 | Instruction Type: CVI_VA |
1314 | Execution Slots: SLOT0123 |
1315 | ========================================================================== */ |
1316 | |
1317 | #define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) |
1318 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1319 | |
1320 | #if __HVX_ARCH__ >= 60 |
1321 | /* ========================================================================== |
1322 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) |
1323 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1324 | Instruction Type: CVI_VA |
1325 | Execution Slots: SLOT0123 |
1326 | ========================================================================== */ |
1327 | |
1328 | #define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1329 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1330 | |
1331 | #if __HVX_ARCH__ >= 60 |
1332 | /* ========================================================================== |
1333 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) |
1334 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1335 | Instruction Type: CVI_VA |
1336 | Execution Slots: SLOT0123 |
1337 | ========================================================================== */ |
1338 | |
1339 | #define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1340 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1341 | |
1342 | #if __HVX_ARCH__ >= 60 |
1343 | /* ========================================================================== |
1344 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) |
1345 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1346 | Instruction Type: CVI_VA |
1347 | Execution Slots: SLOT0123 |
1348 | ========================================================================== */ |
1349 | |
1350 | #define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1351 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1352 | |
1353 | #if __HVX_ARCH__ >= 60 |
1354 | /* ========================================================================== |
1355 | Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) |
1356 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
1357 | Instruction Type: CVI_VA |
1358 | Execution Slots: SLOT0123 |
1359 | ========================================================================== */ |
1360 | |
1361 | #define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) |
1362 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1363 | |
1364 | #if __HVX_ARCH__ >= 60 |
1365 | /* ========================================================================== |
1366 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) |
1367 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1368 | Instruction Type: CVI_VA |
1369 | Execution Slots: SLOT0123 |
1370 | ========================================================================== */ |
1371 | |
1372 | #define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1373 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1374 | |
1375 | #if __HVX_ARCH__ >= 60 |
1376 | /* ========================================================================== |
1377 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) |
1378 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1379 | Instruction Type: CVI_VA |
1380 | Execution Slots: SLOT0123 |
1381 | ========================================================================== */ |
1382 | |
1383 | #define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1384 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1385 | |
1386 | #if __HVX_ARCH__ >= 60 |
1387 | /* ========================================================================== |
1388 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) |
1389 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1390 | Instruction Type: CVI_VA |
1391 | Execution Slots: SLOT0123 |
1392 | ========================================================================== */ |
1393 | |
1394 | #define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1395 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1396 | |
1397 | #if __HVX_ARCH__ >= 60 |
1398 | /* ========================================================================== |
1399 | Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) |
1400 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
1401 | Instruction Type: CVI_VA |
1402 | Execution Slots: SLOT0123 |
1403 | ========================================================================== */ |
1404 | |
1405 | #define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) |
1406 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1407 | |
1408 | #if __HVX_ARCH__ >= 60 |
1409 | /* ========================================================================== |
1410 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) |
1411 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1412 | Instruction Type: CVI_VA |
1413 | Execution Slots: SLOT0123 |
1414 | ========================================================================== */ |
1415 | |
1416 | #define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1417 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1418 | |
1419 | #if __HVX_ARCH__ >= 60 |
1420 | /* ========================================================================== |
1421 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) |
1422 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1423 | Instruction Type: CVI_VA |
1424 | Execution Slots: SLOT0123 |
1425 | ========================================================================== */ |
1426 | |
1427 | #define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1428 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1429 | |
1430 | #if __HVX_ARCH__ >= 60 |
1431 | /* ========================================================================== |
1432 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) |
1433 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1434 | Instruction Type: CVI_VA |
1435 | Execution Slots: SLOT0123 |
1436 | ========================================================================== */ |
1437 | |
1438 | #define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1439 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1440 | |
1441 | #if __HVX_ARCH__ >= 60 |
1442 | /* ========================================================================== |
1443 | Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) |
1444 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
1445 | Instruction Type: CVI_VA |
1446 | Execution Slots: SLOT0123 |
1447 | ========================================================================== */ |
1448 | |
1449 | #define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) |
1450 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1451 | |
1452 | #if __HVX_ARCH__ >= 60 |
1453 | /* ========================================================================== |
1454 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) |
1455 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1456 | Instruction Type: CVI_VA |
1457 | Execution Slots: SLOT0123 |
1458 | ========================================================================== */ |
1459 | |
1460 | #define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1461 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1462 | |
1463 | #if __HVX_ARCH__ >= 60 |
1464 | /* ========================================================================== |
1465 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) |
1466 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1467 | Instruction Type: CVI_VA |
1468 | Execution Slots: SLOT0123 |
1469 | ========================================================================== */ |
1470 | |
1471 | #define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1472 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1473 | |
1474 | #if __HVX_ARCH__ >= 60 |
1475 | /* ========================================================================== |
1476 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) |
1477 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1478 | Instruction Type: CVI_VA |
1479 | Execution Slots: SLOT0123 |
1480 | ========================================================================== */ |
1481 | |
1482 | #define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1483 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1484 | |
1485 | #if __HVX_ARCH__ >= 60 |
1486 | /* ========================================================================== |
1487 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) |
1488 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
1489 | Instruction Type: CVI_VA |
1490 | Execution Slots: SLOT0123 |
1491 | ========================================================================== */ |
1492 | |
1493 | #define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) |
1494 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1495 | |
1496 | #if __HVX_ARCH__ >= 60 |
1497 | /* ========================================================================== |
1498 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) |
1499 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1500 | Instruction Type: CVI_VA |
1501 | Execution Slots: SLOT0123 |
1502 | ========================================================================== */ |
1503 | |
1504 | #define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1505 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1506 | |
1507 | #if __HVX_ARCH__ >= 60 |
1508 | /* ========================================================================== |
1509 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) |
1510 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1511 | Instruction Type: CVI_VA |
1512 | Execution Slots: SLOT0123 |
1513 | ========================================================================== */ |
1514 | |
1515 | #define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1516 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1517 | |
1518 | #if __HVX_ARCH__ >= 60 |
1519 | /* ========================================================================== |
1520 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) |
1521 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1522 | Instruction Type: CVI_VA |
1523 | Execution Slots: SLOT0123 |
1524 | ========================================================================== */ |
1525 | |
1526 | #define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1527 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1528 | |
1529 | #if __HVX_ARCH__ >= 60 |
1530 | /* ========================================================================== |
1531 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) |
1532 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
1533 | Instruction Type: CVI_VA |
1534 | Execution Slots: SLOT0123 |
1535 | ========================================================================== */ |
1536 | |
1537 | #define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) |
1538 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1539 | |
1540 | #if __HVX_ARCH__ >= 60 |
1541 | /* ========================================================================== |
1542 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) |
1543 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1544 | Instruction Type: CVI_VA |
1545 | Execution Slots: SLOT0123 |
1546 | ========================================================================== */ |
1547 | |
1548 | #define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1549 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1550 | |
1551 | #if __HVX_ARCH__ >= 60 |
1552 | /* ========================================================================== |
1553 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) |
1554 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1555 | Instruction Type: CVI_VA |
1556 | Execution Slots: SLOT0123 |
1557 | ========================================================================== */ |
1558 | |
1559 | #define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1560 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1561 | |
1562 | #if __HVX_ARCH__ >= 60 |
1563 | /* ========================================================================== |
1564 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) |
1565 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1566 | Instruction Type: CVI_VA |
1567 | Execution Slots: SLOT0123 |
1568 | ========================================================================== */ |
1569 | |
1570 | #define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1571 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1572 | |
1573 | #if __HVX_ARCH__ >= 60 |
1574 | /* ========================================================================== |
1575 | Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) |
1576 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
1577 | Instruction Type: CVI_VA |
1578 | Execution Slots: SLOT0123 |
1579 | ========================================================================== */ |
1580 | |
1581 | #define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) |
1582 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1583 | |
1584 | #if __HVX_ARCH__ >= 60 |
1585 | /* ========================================================================== |
1586 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) |
1587 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1588 | Instruction Type: CVI_VA |
1589 | Execution Slots: SLOT0123 |
1590 | ========================================================================== */ |
1591 | |
1592 | #define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1593 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1594 | |
1595 | #if __HVX_ARCH__ >= 60 |
1596 | /* ========================================================================== |
1597 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) |
1598 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1599 | Instruction Type: CVI_VA |
1600 | Execution Slots: SLOT0123 |
1601 | ========================================================================== */ |
1602 | |
1603 | #define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1604 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1605 | |
1606 | #if __HVX_ARCH__ >= 60 |
1607 | /* ========================================================================== |
1608 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) |
1609 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
1610 | Instruction Type: CVI_VA |
1611 | Execution Slots: SLOT0123 |
1612 | ========================================================================== */ |
1613 | |
1614 | #define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
1615 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1616 | |
1617 | #if __HVX_ARCH__ >= 60 |
1618 | /* ========================================================================== |
1619 | Assembly Syntax: Vx32.w=vinsert(Rt32) |
1620 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) |
1621 | Instruction Type: CVI_VX_LATE |
1622 | Execution Slots: SLOT23 |
1623 | ========================================================================== */ |
1624 | |
1625 | #define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) |
1626 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1627 | |
1628 | #if __HVX_ARCH__ >= 60 |
1629 | /* ========================================================================== |
1630 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) |
1631 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
1632 | Instruction Type: CVI_VP |
1633 | Execution Slots: SLOT0123 |
1634 | ========================================================================== */ |
1635 | |
1636 | #define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) |
1637 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1638 | |
1639 | #if __HVX_ARCH__ >= 60 |
1640 | /* ========================================================================== |
1641 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) |
1642 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
1643 | Instruction Type: CVI_VP |
1644 | Execution Slots: SLOT0123 |
1645 | ========================================================================== */ |
1646 | |
1647 | #define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) |
1648 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1649 | |
1650 | #if __HVX_ARCH__ >= 60 |
1651 | /* ========================================================================== |
1652 | Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) |
1653 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) |
1654 | Instruction Type: CVI_VS |
1655 | Execution Slots: SLOT0123 |
1656 | ========================================================================== */ |
1657 | |
1658 | #define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) |
1659 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1660 | |
1661 | #if __HVX_ARCH__ >= 60 |
1662 | /* ========================================================================== |
1663 | Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) |
1664 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
1665 | Instruction Type: CVI_VS |
1666 | Execution Slots: SLOT0123 |
1667 | ========================================================================== */ |
1668 | |
1669 | #define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) |
1670 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1671 | |
1672 | #if __HVX_ARCH__ >= 60 |
1673 | /* ========================================================================== |
1674 | Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) |
1675 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) |
1676 | Instruction Type: CVI_VS |
1677 | Execution Slots: SLOT0123 |
1678 | ========================================================================== */ |
1679 | |
1680 | #define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) |
1681 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1682 | |
1683 | #if __HVX_ARCH__ >= 60 |
1684 | /* ========================================================================== |
1685 | Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) |
1686 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
1687 | Instruction Type: CVI_VS |
1688 | Execution Slots: SLOT0123 |
1689 | ========================================================================== */ |
1690 | |
1691 | #define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) |
1692 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1693 | |
1694 | #if __HVX_ARCH__ >= 60 |
1695 | /* ========================================================================== |
1696 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) |
1697 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
1698 | Instruction Type: CVI_VP |
1699 | Execution Slots: SLOT0123 |
1700 | ========================================================================== */ |
1701 | |
1702 | #define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) |
1703 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1704 | |
1705 | #if __HVX_ARCH__ >= 60 |
1706 | /* ========================================================================== |
1707 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) |
1708 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
1709 | Instruction Type: CVI_VP_VS |
1710 | Execution Slots: SLOT0123 |
1711 | ========================================================================== */ |
1712 | |
1713 | #define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) |
1714 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1715 | |
1716 | #if __HVX_ARCH__ >= 60 |
1717 | /* ========================================================================== |
1718 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) |
1719 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
1720 | Instruction Type: CVI_VP_VS |
1721 | Execution Slots: SLOT0123 |
1722 | ========================================================================== */ |
1723 | |
1724 | #define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) |
1725 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1726 | |
1727 | #if __HVX_ARCH__ >= 60 |
1728 | /* ========================================================================== |
1729 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) |
1730 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
1731 | Instruction Type: CVI_VP_VS |
1732 | Execution Slots: SLOT0123 |
1733 | ========================================================================== */ |
1734 | |
1735 | #define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) |
1736 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1737 | |
1738 | #if __HVX_ARCH__ >= 60 |
1739 | /* ========================================================================== |
1740 | Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) |
1741 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
1742 | Instruction Type: CVI_VA |
1743 | Execution Slots: SLOT0123 |
1744 | ========================================================================== */ |
1745 | |
1746 | #define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) |
1747 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1748 | |
1749 | #if __HVX_ARCH__ >= 60 |
1750 | /* ========================================================================== |
1751 | Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) |
1752 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
1753 | Instruction Type: CVI_VA |
1754 | Execution Slots: SLOT0123 |
1755 | ========================================================================== */ |
1756 | |
1757 | #define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) |
1758 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1759 | |
1760 | #if __HVX_ARCH__ >= 60 |
1761 | /* ========================================================================== |
1762 | Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) |
1763 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
1764 | Instruction Type: CVI_VA |
1765 | Execution Slots: SLOT0123 |
1766 | ========================================================================== */ |
1767 | |
1768 | #define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) |
1769 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1770 | |
1771 | #if __HVX_ARCH__ >= 60 |
1772 | /* ========================================================================== |
1773 | Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) |
1774 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
1775 | Instruction Type: CVI_VA |
1776 | Execution Slots: SLOT0123 |
1777 | ========================================================================== */ |
1778 | |
1779 | #define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) |
1780 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1781 | |
1782 | #if __HVX_ARCH__ >= 60 |
1783 | /* ========================================================================== |
1784 | Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) |
1785 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
1786 | Instruction Type: CVI_VA |
1787 | Execution Slots: SLOT0123 |
1788 | ========================================================================== */ |
1789 | |
1790 | #define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) |
1791 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1792 | |
1793 | #if __HVX_ARCH__ >= 60 |
1794 | /* ========================================================================== |
1795 | Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) |
1796 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
1797 | Instruction Type: CVI_VA |
1798 | Execution Slots: SLOT0123 |
1799 | ========================================================================== */ |
1800 | |
1801 | #define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) |
1802 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1803 | |
1804 | #if __HVX_ARCH__ >= 60 |
1805 | /* ========================================================================== |
1806 | Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) |
1807 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
1808 | Instruction Type: CVI_VA |
1809 | Execution Slots: SLOT0123 |
1810 | ========================================================================== */ |
1811 | |
1812 | #define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) |
1813 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1814 | |
1815 | #if __HVX_ARCH__ >= 60 |
1816 | /* ========================================================================== |
1817 | Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) |
1818 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
1819 | Instruction Type: CVI_VA |
1820 | Execution Slots: SLOT0123 |
1821 | ========================================================================== */ |
1822 | |
1823 | #define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) |
1824 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1825 | |
1826 | #if __HVX_ARCH__ >= 60 |
1827 | /* ========================================================================== |
1828 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) |
1829 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
1830 | Instruction Type: CVI_VX_DV |
1831 | Execution Slots: SLOT23 |
1832 | ========================================================================== */ |
1833 | |
1834 | #define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) |
1835 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1836 | |
1837 | #if __HVX_ARCH__ >= 60 |
1838 | /* ========================================================================== |
1839 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) |
1840 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
1841 | Instruction Type: CVI_VX_DV |
1842 | Execution Slots: SLOT23 |
1843 | ========================================================================== */ |
1844 | |
1845 | #define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) |
1846 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1847 | |
1848 | #if __HVX_ARCH__ >= 60 |
1849 | /* ========================================================================== |
1850 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) |
1851 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
1852 | Instruction Type: CVI_VX_DV |
1853 | Execution Slots: SLOT23 |
1854 | ========================================================================== */ |
1855 | |
1856 | #define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) |
1857 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1858 | |
1859 | #if __HVX_ARCH__ >= 60 |
1860 | /* ========================================================================== |
1861 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) |
1862 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
1863 | Instruction Type: CVI_VX_DV |
1864 | Execution Slots: SLOT23 |
1865 | ========================================================================== */ |
1866 | |
1867 | #define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) |
1868 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1869 | |
1870 | #if __HVX_ARCH__ >= 60 |
1871 | /* ========================================================================== |
1872 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) |
1873 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
1874 | Instruction Type: CVI_VX_DV |
1875 | Execution Slots: SLOT23 |
1876 | ========================================================================== */ |
1877 | |
1878 | #define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) |
1879 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1880 | |
1881 | #if __HVX_ARCH__ >= 60 |
1882 | /* ========================================================================== |
1883 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) |
1884 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
1885 | Instruction Type: CVI_VX_DV |
1886 | Execution Slots: SLOT23 |
1887 | ========================================================================== */ |
1888 | |
1889 | #define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) |
1890 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1891 | |
1892 | #if __HVX_ARCH__ >= 60 |
1893 | /* ========================================================================== |
1894 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) |
1895 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
1896 | Instruction Type: CVI_VX_DV |
1897 | Execution Slots: SLOT23 |
1898 | ========================================================================== */ |
1899 | |
1900 | #define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) |
1901 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1902 | |
1903 | #if __HVX_ARCH__ >= 60 |
1904 | /* ========================================================================== |
1905 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) |
1906 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
1907 | Instruction Type: CVI_VX_DV |
1908 | Execution Slots: SLOT23 |
1909 | ========================================================================== */ |
1910 | |
1911 | #define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) |
1912 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1913 | |
1914 | #if __HVX_ARCH__ >= 60 |
1915 | /* ========================================================================== |
1916 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) |
1917 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
1918 | Instruction Type: CVI_VX_DV |
1919 | Execution Slots: SLOT23 |
1920 | ========================================================================== */ |
1921 | |
1922 | #define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) |
1923 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1924 | |
1925 | #if __HVX_ARCH__ >= 60 |
1926 | /* ========================================================================== |
1927 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) |
1928 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
1929 | Instruction Type: CVI_VX_DV |
1930 | Execution Slots: SLOT23 |
1931 | ========================================================================== */ |
1932 | |
1933 | #define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) |
1934 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1935 | |
1936 | #if __HVX_ARCH__ >= 60 |
1937 | /* ========================================================================== |
1938 | Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) |
1939 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
1940 | Instruction Type: CVI_VX_DV |
1941 | Execution Slots: SLOT23 |
1942 | ========================================================================== */ |
1943 | |
1944 | #define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) |
1945 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1946 | |
1947 | #if __HVX_ARCH__ >= 60 |
1948 | /* ========================================================================== |
1949 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) |
1950 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
1951 | Instruction Type: CVI_VX_DV |
1952 | Execution Slots: SLOT23 |
1953 | ========================================================================== */ |
1954 | |
1955 | #define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) |
1956 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1957 | |
1958 | #if __HVX_ARCH__ >= 60 |
1959 | /* ========================================================================== |
1960 | Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) |
1961 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
1962 | Instruction Type: CVI_VX_DV |
1963 | Execution Slots: SLOT23 |
1964 | ========================================================================== */ |
1965 | |
1966 | #define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) |
1967 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1968 | |
1969 | #if __HVX_ARCH__ >= 60 |
1970 | /* ========================================================================== |
1971 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) |
1972 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) |
1973 | Instruction Type: CVI_VX_DV |
1974 | Execution Slots: SLOT23 |
1975 | ========================================================================== */ |
1976 | |
1977 | #define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) |
1978 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1979 | |
1980 | #if __HVX_ARCH__ >= 60 |
1981 | /* ========================================================================== |
1982 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat |
1983 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
1984 | Instruction Type: CVI_VX_DV |
1985 | Execution Slots: SLOT23 |
1986 | ========================================================================== */ |
1987 | |
1988 | #define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) |
1989 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
1990 | |
1991 | #if __HVX_ARCH__ >= 60 |
1992 | /* ========================================================================== |
1993 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat |
1994 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) |
1995 | Instruction Type: CVI_VX |
1996 | Execution Slots: SLOT23 |
1997 | ========================================================================== */ |
1998 | |
1999 | #define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) |
2000 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2001 | |
2002 | #if __HVX_ARCH__ >= 60 |
2003 | /* ========================================================================== |
2004 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat |
2005 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) |
2006 | Instruction Type: CVI_VX |
2007 | Execution Slots: SLOT23 |
2008 | ========================================================================== */ |
2009 | |
2010 | #define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) |
2011 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2012 | |
2013 | #if __HVX_ARCH__ >= 60 |
2014 | /* ========================================================================== |
2015 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) |
2016 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) |
2017 | Instruction Type: CVI_VX_DV |
2018 | Execution Slots: SLOT23 |
2019 | ========================================================================== */ |
2020 | |
2021 | #define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) |
2022 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2023 | |
2024 | #if __HVX_ARCH__ >= 60 |
2025 | /* ========================================================================== |
2026 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) |
2027 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
2028 | Instruction Type: CVI_VX_DV |
2029 | Execution Slots: SLOT23 |
2030 | ========================================================================== */ |
2031 | |
2032 | #define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) |
2033 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2034 | |
2035 | #if __HVX_ARCH__ >= 60 |
2036 | /* ========================================================================== |
2037 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) |
2038 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2039 | Instruction Type: CVI_VX_DV |
2040 | Execution Slots: SLOT23 |
2041 | ========================================================================== */ |
2042 | |
2043 | #define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) |
2044 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2045 | |
2046 | #if __HVX_ARCH__ >= 60 |
2047 | /* ========================================================================== |
2048 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) |
2049 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
2050 | Instruction Type: CVI_VX_DV |
2051 | Execution Slots: SLOT23 |
2052 | ========================================================================== */ |
2053 | |
2054 | #define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) |
2055 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2056 | |
2057 | #if __HVX_ARCH__ >= 60 |
2058 | /* ========================================================================== |
2059 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat |
2060 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
2061 | Instruction Type: CVI_VX |
2062 | Execution Slots: SLOT23 |
2063 | ========================================================================== */ |
2064 | |
2065 | #define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) |
2066 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2067 | |
2068 | #if __HVX_ARCH__ >= 60 |
2069 | /* ========================================================================== |
2070 | Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) |
2071 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2072 | Instruction Type: CVI_VX |
2073 | Execution Slots: SLOT23 |
2074 | ========================================================================== */ |
2075 | |
2076 | #define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) |
2077 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2078 | |
2079 | #if __HVX_ARCH__ >= 60 |
2080 | /* ========================================================================== |
2081 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) |
2082 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2083 | Instruction Type: CVI_VX_DV |
2084 | Execution Slots: SLOT23 |
2085 | ========================================================================== */ |
2086 | |
2087 | #define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) |
2088 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2089 | |
2090 | #if __HVX_ARCH__ >= 60 |
2091 | /* ========================================================================== |
2092 | Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) |
2093 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
2094 | Instruction Type: CVI_VX_DV |
2095 | Execution Slots: SLOT23 |
2096 | ========================================================================== */ |
2097 | |
2098 | #define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) |
2099 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2100 | |
2101 | #if __HVX_ARCH__ >= 60 |
2102 | /* ========================================================================== |
2103 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) |
2104 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2105 | Instruction Type: CVI_VX_DV |
2106 | Execution Slots: SLOT23 |
2107 | ========================================================================== */ |
2108 | |
2109 | #define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) |
2110 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2111 | |
2112 | #if __HVX_ARCH__ >= 60 |
2113 | /* ========================================================================== |
2114 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) |
2115 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2116 | Instruction Type: CVI_VX_DV |
2117 | Execution Slots: SLOT23 |
2118 | ========================================================================== */ |
2119 | |
2120 | #define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) |
2121 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2122 | |
2123 | #if __HVX_ARCH__ >= 60 |
2124 | /* ========================================================================== |
2125 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) |
2126 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2127 | Instruction Type: CVI_VX_DV |
2128 | Execution Slots: SLOT23 |
2129 | ========================================================================== */ |
2130 | |
2131 | #define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) |
2132 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2133 | |
2134 | #if __HVX_ARCH__ >= 60 |
2135 | /* ========================================================================== |
2136 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) |
2137 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) |
2138 | Instruction Type: CVI_VX |
2139 | Execution Slots: SLOT23 |
2140 | ========================================================================== */ |
2141 | |
2142 | #define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) |
2143 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2144 | |
2145 | #if __HVX_ARCH__ >= 60 |
2146 | /* ========================================================================== |
2147 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) |
2148 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
2149 | Instruction Type: CVI_VX |
2150 | Execution Slots: SLOT23 |
2151 | ========================================================================== */ |
2152 | |
2153 | #define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) |
2154 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2155 | |
2156 | #if __HVX_ARCH__ >= 60 |
2157 | /* ========================================================================== |
2158 | Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) |
2159 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) |
2160 | Instruction Type: CVI_VX_DV |
2161 | Execution Slots: SLOT23 |
2162 | ========================================================================== */ |
2163 | |
2164 | #define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) |
2165 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2166 | |
2167 | #if __HVX_ARCH__ >= 60 |
2168 | /* ========================================================================== |
2169 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) |
2170 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) |
2171 | Instruction Type: CVI_VX |
2172 | Execution Slots: SLOT23 |
2173 | ========================================================================== */ |
2174 | |
2175 | #define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) |
2176 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2177 | |
2178 | #if __HVX_ARCH__ >= 60 |
2179 | /* ========================================================================== |
2180 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) |
2181 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
2182 | Instruction Type: CVI_VX |
2183 | Execution Slots: SLOT23 |
2184 | ========================================================================== */ |
2185 | |
2186 | #define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) |
2187 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2188 | |
2189 | #if __HVX_ARCH__ >= 60 |
2190 | /* ========================================================================== |
2191 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) |
2192 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) |
2193 | Instruction Type: CVI_VX_DV |
2194 | Execution Slots: SLOT23 |
2195 | ========================================================================== */ |
2196 | |
2197 | #define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) |
2198 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2199 | |
2200 | #if __HVX_ARCH__ >= 60 |
2201 | /* ========================================================================== |
2202 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) |
2203 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
2204 | Instruction Type: CVI_VX_DV |
2205 | Execution Slots: SLOT23 |
2206 | ========================================================================== */ |
2207 | |
2208 | #define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) |
2209 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2210 | |
2211 | #if __HVX_ARCH__ >= 60 |
2212 | /* ========================================================================== |
2213 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat |
2214 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) |
2215 | Instruction Type: CVI_VX_DV |
2216 | Execution Slots: SLOT23 |
2217 | ========================================================================== */ |
2218 | |
2219 | #define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) |
2220 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2221 | |
2222 | #if __HVX_ARCH__ >= 60 |
2223 | /* ========================================================================== |
2224 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat |
2225 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
2226 | Instruction Type: CVI_VX_DV |
2227 | Execution Slots: SLOT23 |
2228 | ========================================================================== */ |
2229 | |
2230 | #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) |
2231 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2232 | |
2233 | #if __HVX_ARCH__ >= 60 |
2234 | /* ========================================================================== |
2235 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift |
2236 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2237 | Instruction Type: CVI_VX_DV |
2238 | Execution Slots: SLOT23 |
2239 | ========================================================================== */ |
2240 | |
2241 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) |
2242 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2243 | |
2244 | #if __HVX_ARCH__ >= 60 |
2245 | /* ========================================================================== |
2246 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift |
2247 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2248 | Instruction Type: CVI_VX_DV |
2249 | Execution Slots: SLOT23 |
2250 | ========================================================================== */ |
2251 | |
2252 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) |
2253 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2254 | |
2255 | #if __HVX_ARCH__ >= 60 |
2256 | /* ========================================================================== |
2257 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) |
2258 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
2259 | Instruction Type: CVI_VX_DV |
2260 | Execution Slots: SLOT23 |
2261 | ========================================================================== */ |
2262 | |
2263 | #define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) |
2264 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2265 | |
2266 | #if __HVX_ARCH__ >= 60 |
2267 | /* ========================================================================== |
2268 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) |
2269 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
2270 | Instruction Type: CVI_VX_DV |
2271 | Execution Slots: SLOT23 |
2272 | ========================================================================== */ |
2273 | |
2274 | #define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) |
2275 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2276 | |
2277 | #if __HVX_ARCH__ >= 60 |
2278 | /* ========================================================================== |
2279 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) |
2280 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
2281 | Instruction Type: CVI_VX_DV |
2282 | Execution Slots: SLOT23 |
2283 | ========================================================================== */ |
2284 | |
2285 | #define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) |
2286 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2287 | |
2288 | #if __HVX_ARCH__ >= 60 |
2289 | /* ========================================================================== |
2290 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) |
2291 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
2292 | Instruction Type: CVI_VX_DV |
2293 | Execution Slots: SLOT23 |
2294 | ========================================================================== */ |
2295 | |
2296 | #define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) |
2297 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2298 | |
2299 | #if __HVX_ARCH__ >= 60 |
2300 | /* ========================================================================== |
2301 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) |
2302 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) |
2303 | Instruction Type: CVI_VX_DV |
2304 | Execution Slots: SLOT23 |
2305 | ========================================================================== */ |
2306 | |
2307 | #define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) |
2308 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2309 | |
2310 | #if __HVX_ARCH__ >= 60 |
2311 | /* ========================================================================== |
2312 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) |
2313 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
2314 | Instruction Type: CVI_VX_DV |
2315 | Execution Slots: SLOT23 |
2316 | ========================================================================== */ |
2317 | |
2318 | #define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) |
2319 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2320 | |
2321 | #if __HVX_ARCH__ >= 60 |
2322 | /* ========================================================================== |
2323 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) |
2324 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
2325 | Instruction Type: CVI_VX_DV |
2326 | Execution Slots: SLOT23 |
2327 | ========================================================================== */ |
2328 | |
2329 | #define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) |
2330 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2331 | |
2332 | #if __HVX_ARCH__ >= 60 |
2333 | /* ========================================================================== |
2334 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) |
2335 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
2336 | Instruction Type: CVI_VX_DV |
2337 | Execution Slots: SLOT23 |
2338 | ========================================================================== */ |
2339 | |
2340 | #define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) |
2341 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2342 | |
2343 | #if __HVX_ARCH__ >= 60 |
2344 | /* ========================================================================== |
2345 | Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) |
2346 | C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
2347 | Instruction Type: CVI_VA |
2348 | Execution Slots: SLOT0123 |
2349 | ========================================================================== */ |
2350 | |
2351 | #define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) |
2352 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2353 | |
2354 | #if __HVX_ARCH__ >= 60 |
2355 | /* ========================================================================== |
2356 | Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) |
2357 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2358 | Instruction Type: CVI_VA |
2359 | Execution Slots: SLOT0123 |
2360 | ========================================================================== */ |
2361 | |
2362 | #define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) |
2363 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2364 | |
2365 | #if __HVX_ARCH__ >= 60 |
2366 | /* ========================================================================== |
2367 | Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) |
2368 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
2369 | Instruction Type: CVI_VA |
2370 | Execution Slots: SLOT0123 |
2371 | ========================================================================== */ |
2372 | |
2373 | #define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) |
2374 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2375 | |
2376 | #if __HVX_ARCH__ >= 60 |
2377 | /* ========================================================================== |
2378 | Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) |
2379 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
2380 | Instruction Type: CVI_VA |
2381 | Execution Slots: SLOT0123 |
2382 | ========================================================================== */ |
2383 | |
2384 | #define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) |
2385 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2386 | |
2387 | #if __HVX_ARCH__ >= 60 |
2388 | /* ========================================================================== |
2389 | Assembly Syntax: Vd32.h=vnormamt(Vu32.h) |
2390 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) |
2391 | Instruction Type: CVI_VS |
2392 | Execution Slots: SLOT0123 |
2393 | ========================================================================== */ |
2394 | |
2395 | #define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) |
2396 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2397 | |
2398 | #if __HVX_ARCH__ >= 60 |
2399 | /* ========================================================================== |
2400 | Assembly Syntax: Vd32.w=vnormamt(Vu32.w) |
2401 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) |
2402 | Instruction Type: CVI_VS |
2403 | Execution Slots: SLOT0123 |
2404 | ========================================================================== */ |
2405 | |
2406 | #define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) |
2407 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2408 | |
2409 | #if __HVX_ARCH__ >= 60 |
2410 | /* ========================================================================== |
2411 | Assembly Syntax: Vd32=vnot(Vu32) |
2412 | C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) |
2413 | Instruction Type: CVI_VA |
2414 | Execution Slots: SLOT0123 |
2415 | ========================================================================== */ |
2416 | |
2417 | #define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) |
2418 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2419 | |
2420 | #if __HVX_ARCH__ >= 60 |
2421 | /* ========================================================================== |
2422 | Assembly Syntax: Vd32=vor(Vu32,Vv32) |
2423 | C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) |
2424 | Instruction Type: CVI_VA |
2425 | Execution Slots: SLOT0123 |
2426 | ========================================================================== */ |
2427 | |
2428 | #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) |
2429 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2430 | |
2431 | #if __HVX_ARCH__ >= 60 |
2432 | /* ========================================================================== |
2433 | Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) |
2434 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2435 | Instruction Type: CVI_VP |
2436 | Execution Slots: SLOT0123 |
2437 | ========================================================================== */ |
2438 | |
2439 | #define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) |
2440 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2441 | |
2442 | #if __HVX_ARCH__ >= 60 |
2443 | /* ========================================================================== |
2444 | Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) |
2445 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
2446 | Instruction Type: CVI_VP |
2447 | Execution Slots: SLOT0123 |
2448 | ========================================================================== */ |
2449 | |
2450 | #define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) |
2451 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2452 | |
2453 | #if __HVX_ARCH__ >= 60 |
2454 | /* ========================================================================== |
2455 | Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat |
2456 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
2457 | Instruction Type: CVI_VP |
2458 | Execution Slots: SLOT0123 |
2459 | ========================================================================== */ |
2460 | |
2461 | #define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) |
2462 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2463 | |
2464 | #if __HVX_ARCH__ >= 60 |
2465 | /* ========================================================================== |
2466 | Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat |
2467 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
2468 | Instruction Type: CVI_VP |
2469 | Execution Slots: SLOT0123 |
2470 | ========================================================================== */ |
2471 | |
2472 | #define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) |
2473 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2474 | |
2475 | #if __HVX_ARCH__ >= 60 |
2476 | /* ========================================================================== |
2477 | Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) |
2478 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2479 | Instruction Type: CVI_VP |
2480 | Execution Slots: SLOT0123 |
2481 | ========================================================================== */ |
2482 | |
2483 | #define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) |
2484 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2485 | |
2486 | #if __HVX_ARCH__ >= 60 |
2487 | /* ========================================================================== |
2488 | Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) |
2489 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
2490 | Instruction Type: CVI_VP |
2491 | Execution Slots: SLOT0123 |
2492 | ========================================================================== */ |
2493 | |
2494 | #define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) |
2495 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2496 | |
2497 | #if __HVX_ARCH__ >= 60 |
2498 | /* ========================================================================== |
2499 | Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat |
2500 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
2501 | Instruction Type: CVI_VP |
2502 | Execution Slots: SLOT0123 |
2503 | ========================================================================== */ |
2504 | |
2505 | #define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) |
2506 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2507 | |
2508 | #if __HVX_ARCH__ >= 60 |
2509 | /* ========================================================================== |
2510 | Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat |
2511 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
2512 | Instruction Type: CVI_VP |
2513 | Execution Slots: SLOT0123 |
2514 | ========================================================================== */ |
2515 | |
2516 | #define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) |
2517 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2518 | |
2519 | #if __HVX_ARCH__ >= 60 |
2520 | /* ========================================================================== |
2521 | Assembly Syntax: Vd32.h=vpopcount(Vu32.h) |
2522 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) |
2523 | Instruction Type: CVI_VS |
2524 | Execution Slots: SLOT0123 |
2525 | ========================================================================== */ |
2526 | |
2527 | #define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) |
2528 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2529 | |
2530 | #if __HVX_ARCH__ >= 60 |
2531 | /* ========================================================================== |
2532 | Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) |
2533 | C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
2534 | Instruction Type: CVI_VP |
2535 | Execution Slots: SLOT0123 |
2536 | ========================================================================== */ |
2537 | |
2538 | #define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) |
2539 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2540 | |
2541 | #if __HVX_ARCH__ >= 60 |
2542 | /* ========================================================================== |
2543 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) |
2544 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
2545 | Instruction Type: CVI_VX |
2546 | Execution Slots: SLOT23 |
2547 | ========================================================================== */ |
2548 | |
2549 | #define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) |
2550 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2551 | |
2552 | #if __HVX_ARCH__ >= 60 |
2553 | /* ========================================================================== |
2554 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) |
2555 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
2556 | Instruction Type: CVI_VX |
2557 | Execution Slots: SLOT23 |
2558 | ========================================================================== */ |
2559 | |
2560 | #define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) |
2561 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2562 | |
2563 | #if __HVX_ARCH__ >= 60 |
2564 | /* ========================================================================== |
2565 | Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) |
2566 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2567 | Instruction Type: CVI_VX_DV |
2568 | Execution Slots: SLOT23 |
2569 | ========================================================================== */ |
2570 | |
2571 | #define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) |
2572 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2573 | |
2574 | #if __HVX_ARCH__ >= 60 |
2575 | /* ========================================================================== |
2576 | Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) |
2577 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2578 | Instruction Type: CVI_VX_DV |
2579 | Execution Slots: SLOT23 |
2580 | ========================================================================== */ |
2581 | |
2582 | #define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) |
2583 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2584 | |
2585 | #if __HVX_ARCH__ >= 60 |
2586 | /* ========================================================================== |
2587 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) |
2588 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
2589 | Instruction Type: CVI_VX |
2590 | Execution Slots: SLOT23 |
2591 | ========================================================================== */ |
2592 | |
2593 | #define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) |
2594 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2595 | |
2596 | #if __HVX_ARCH__ >= 60 |
2597 | /* ========================================================================== |
2598 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) |
2599 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2600 | Instruction Type: CVI_VX |
2601 | Execution Slots: SLOT23 |
2602 | ========================================================================== */ |
2603 | |
2604 | #define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) |
2605 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2606 | |
2607 | #if __HVX_ARCH__ >= 60 |
2608 | /* ========================================================================== |
2609 | Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) |
2610 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
2611 | Instruction Type: CVI_VX |
2612 | Execution Slots: SLOT23 |
2613 | ========================================================================== */ |
2614 | |
2615 | #define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) |
2616 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2617 | |
2618 | #if __HVX_ARCH__ >= 60 |
2619 | /* ========================================================================== |
2620 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) |
2621 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2622 | Instruction Type: CVI_VX |
2623 | Execution Slots: SLOT23 |
2624 | ========================================================================== */ |
2625 | |
2626 | #define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) |
2627 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2628 | |
2629 | #if __HVX_ARCH__ >= 60 |
2630 | /* ========================================================================== |
2631 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) |
2632 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
2633 | Instruction Type: CVI_VX |
2634 | Execution Slots: SLOT23 |
2635 | ========================================================================== */ |
2636 | |
2637 | #define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) |
2638 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2639 | |
2640 | #if __HVX_ARCH__ >= 60 |
2641 | /* ========================================================================== |
2642 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) |
2643 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
2644 | Instruction Type: CVI_VX |
2645 | Execution Slots: SLOT23 |
2646 | ========================================================================== */ |
2647 | |
2648 | #define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) |
2649 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2650 | |
2651 | #if __HVX_ARCH__ >= 60 |
2652 | /* ========================================================================== |
2653 | Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
2654 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2655 | Instruction Type: CVI_VX_DV |
2656 | Execution Slots: SLOT23 |
2657 | ========================================================================== */ |
2658 | |
2659 | #define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) |
2660 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2661 | |
2662 | #if __HVX_ARCH__ >= 60 |
2663 | /* ========================================================================== |
2664 | Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
2665 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2666 | Instruction Type: CVI_VX_DV |
2667 | Execution Slots: SLOT23 |
2668 | ========================================================================== */ |
2669 | |
2670 | #define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) |
2671 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2672 | |
2673 | #if __HVX_ARCH__ >= 60 |
2674 | /* ========================================================================== |
2675 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) |
2676 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
2677 | Instruction Type: CVI_VX |
2678 | Execution Slots: SLOT23 |
2679 | ========================================================================== */ |
2680 | |
2681 | #define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) |
2682 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2683 | |
2684 | #if __HVX_ARCH__ >= 60 |
2685 | /* ========================================================================== |
2686 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) |
2687 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
2688 | Instruction Type: CVI_VX |
2689 | Execution Slots: SLOT23 |
2690 | ========================================================================== */ |
2691 | |
2692 | #define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) |
2693 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2694 | |
2695 | #if __HVX_ARCH__ >= 60 |
2696 | /* ========================================================================== |
2697 | Assembly Syntax: Vd32=vror(Vu32,Rt32) |
2698 | C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) |
2699 | Instruction Type: CVI_VP |
2700 | Execution Slots: SLOT0123 |
2701 | ========================================================================== */ |
2702 | |
2703 | #define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) |
2704 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2705 | |
2706 | #if __HVX_ARCH__ >= 60 |
2707 | /* ========================================================================== |
2708 | Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat |
2709 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
2710 | Instruction Type: CVI_VS |
2711 | Execution Slots: SLOT0123 |
2712 | ========================================================================== */ |
2713 | |
2714 | #define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) |
2715 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2716 | |
2717 | #if __HVX_ARCH__ >= 60 |
2718 | /* ========================================================================== |
2719 | Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat |
2720 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
2721 | Instruction Type: CVI_VS |
2722 | Execution Slots: SLOT0123 |
2723 | ========================================================================== */ |
2724 | |
2725 | #define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) |
2726 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2727 | |
2728 | #if __HVX_ARCH__ >= 60 |
2729 | /* ========================================================================== |
2730 | Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat |
2731 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
2732 | Instruction Type: CVI_VS |
2733 | Execution Slots: SLOT0123 |
2734 | ========================================================================== */ |
2735 | |
2736 | #define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) |
2737 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2738 | |
2739 | #if __HVX_ARCH__ >= 60 |
2740 | /* ========================================================================== |
2741 | Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat |
2742 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
2743 | Instruction Type: CVI_VS |
2744 | Execution Slots: SLOT0123 |
2745 | ========================================================================== */ |
2746 | |
2747 | #define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) |
2748 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2749 | |
2750 | #if __HVX_ARCH__ >= 60 |
2751 | /* ========================================================================== |
2752 | Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) |
2753 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2754 | Instruction Type: CVI_VX_DV |
2755 | Execution Slots: SLOT23 |
2756 | ========================================================================== */ |
2757 | |
2758 | #define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) |
2759 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2760 | |
2761 | #if __HVX_ARCH__ >= 60 |
2762 | /* ========================================================================== |
2763 | Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) |
2764 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
2765 | Instruction Type: CVI_VX_DV |
2766 | Execution Slots: SLOT23 |
2767 | ========================================================================== */ |
2768 | |
2769 | #define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) |
2770 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2771 | |
2772 | #if __HVX_ARCH__ >= 60 |
2773 | /* ========================================================================== |
2774 | Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) |
2775 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2776 | Instruction Type: CVI_VA |
2777 | Execution Slots: SLOT0123 |
2778 | ========================================================================== */ |
2779 | |
2780 | #define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) |
2781 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2782 | |
2783 | #if __HVX_ARCH__ >= 60 |
2784 | /* ========================================================================== |
2785 | Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) |
2786 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
2787 | Instruction Type: CVI_VA |
2788 | Execution Slots: SLOT0123 |
2789 | ========================================================================== */ |
2790 | |
2791 | #define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) |
2792 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2793 | |
2794 | #if __HVX_ARCH__ >= 60 |
2795 | /* ========================================================================== |
2796 | Assembly Syntax: Vdd32.h=vsxt(Vu32.b) |
2797 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) |
2798 | Instruction Type: CVI_VA_DV |
2799 | Execution Slots: SLOT0123 |
2800 | ========================================================================== */ |
2801 | |
2802 | #define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) |
2803 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2804 | |
2805 | #if __HVX_ARCH__ >= 60 |
2806 | /* ========================================================================== |
2807 | Assembly Syntax: Vdd32.w=vsxt(Vu32.h) |
2808 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) |
2809 | Instruction Type: CVI_VA_DV |
2810 | Execution Slots: SLOT0123 |
2811 | ========================================================================== */ |
2812 | |
2813 | #define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) |
2814 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2815 | |
2816 | #if __HVX_ARCH__ >= 60 |
2817 | /* ========================================================================== |
2818 | Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) |
2819 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2820 | Instruction Type: CVI_VA |
2821 | Execution Slots: SLOT0123 |
2822 | ========================================================================== */ |
2823 | |
2824 | #define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) |
2825 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2826 | |
2827 | #if __HVX_ARCH__ >= 60 |
2828 | /* ========================================================================== |
2829 | Assembly Syntax: Vd32.b=vshuff(Vu32.b) |
2830 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) |
2831 | Instruction Type: CVI_VP |
2832 | Execution Slots: SLOT0123 |
2833 | ========================================================================== */ |
2834 | |
2835 | #define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) |
2836 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2837 | |
2838 | #if __HVX_ARCH__ >= 60 |
2839 | /* ========================================================================== |
2840 | Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) |
2841 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
2842 | Instruction Type: CVI_VA |
2843 | Execution Slots: SLOT0123 |
2844 | ========================================================================== */ |
2845 | |
2846 | #define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) |
2847 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2848 | |
2849 | #if __HVX_ARCH__ >= 60 |
2850 | /* ========================================================================== |
2851 | Assembly Syntax: Vd32.h=vshuff(Vu32.h) |
2852 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) |
2853 | Instruction Type: CVI_VP |
2854 | Execution Slots: SLOT0123 |
2855 | ========================================================================== */ |
2856 | |
2857 | #define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) |
2858 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2859 | |
2860 | #if __HVX_ARCH__ >= 60 |
2861 | /* ========================================================================== |
2862 | Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) |
2863 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
2864 | Instruction Type: CVI_VA |
2865 | Execution Slots: SLOT0123 |
2866 | ========================================================================== */ |
2867 | |
2868 | #define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) |
2869 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2870 | |
2871 | #if __HVX_ARCH__ >= 60 |
2872 | /* ========================================================================== |
2873 | Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) |
2874 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
2875 | Instruction Type: CVI_VP_VS |
2876 | Execution Slots: SLOT0123 |
2877 | ========================================================================== */ |
2878 | |
2879 | #define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) |
2880 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2881 | |
2882 | #if __HVX_ARCH__ >= 60 |
2883 | /* ========================================================================== |
2884 | Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) |
2885 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
2886 | Instruction Type: CVI_VA_DV |
2887 | Execution Slots: SLOT0123 |
2888 | ========================================================================== */ |
2889 | |
2890 | #define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) |
2891 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2892 | |
2893 | #if __HVX_ARCH__ >= 60 |
2894 | /* ========================================================================== |
2895 | Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) |
2896 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2897 | Instruction Type: CVI_VA_DV |
2898 | Execution Slots: SLOT0123 |
2899 | ========================================================================== */ |
2900 | |
2901 | #define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) |
2902 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2903 | |
2904 | #if __HVX_ARCH__ >= 60 |
2905 | /* ========================================================================== |
2906 | Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) |
2907 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2908 | Instruction Type: CVI_VA |
2909 | Execution Slots: SLOT0123 |
2910 | ========================================================================== */ |
2911 | |
2912 | #define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) |
2913 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2914 | |
2915 | #if __HVX_ARCH__ >= 60 |
2916 | /* ========================================================================== |
2917 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) |
2918 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
2919 | Instruction Type: CVI_VA |
2920 | Execution Slots: SLOT0123 |
2921 | ========================================================================== */ |
2922 | |
2923 | #define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) |
2924 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2925 | |
2926 | #if __HVX_ARCH__ >= 60 |
2927 | /* ========================================================================== |
2928 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) |
2929 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
2930 | Instruction Type: CVI_VA_DV |
2931 | Execution Slots: SLOT0123 |
2932 | ========================================================================== */ |
2933 | |
2934 | #define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) |
2935 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2936 | |
2937 | #if __HVX_ARCH__ >= 60 |
2938 | /* ========================================================================== |
2939 | Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b |
2940 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
2941 | Instruction Type: CVI_VA |
2942 | Execution Slots: SLOT0123 |
2943 | ========================================================================== */ |
2944 | |
2945 | #define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
2946 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2947 | |
2948 | #if __HVX_ARCH__ >= 60 |
2949 | /* ========================================================================== |
2950 | Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b |
2951 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
2952 | Instruction Type: CVI_VA |
2953 | Execution Slots: SLOT0123 |
2954 | ========================================================================== */ |
2955 | |
2956 | #define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
2957 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2958 | |
2959 | #if __HVX_ARCH__ >= 60 |
2960 | /* ========================================================================== |
2961 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) |
2962 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
2963 | Instruction Type: CVI_VA |
2964 | Execution Slots: SLOT0123 |
2965 | ========================================================================== */ |
2966 | |
2967 | #define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) |
2968 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2969 | |
2970 | #if __HVX_ARCH__ >= 60 |
2971 | /* ========================================================================== |
2972 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) |
2973 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
2974 | Instruction Type: CVI_VA_DV |
2975 | Execution Slots: SLOT0123 |
2976 | ========================================================================== */ |
2977 | |
2978 | #define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) |
2979 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2980 | |
2981 | #if __HVX_ARCH__ >= 60 |
2982 | /* ========================================================================== |
2983 | Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h |
2984 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
2985 | Instruction Type: CVI_VA |
2986 | Execution Slots: SLOT0123 |
2987 | ========================================================================== */ |
2988 | |
2989 | #define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
2990 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
2991 | |
2992 | #if __HVX_ARCH__ >= 60 |
2993 | /* ========================================================================== |
2994 | Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h |
2995 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
2996 | Instruction Type: CVI_VA |
2997 | Execution Slots: SLOT0123 |
2998 | ========================================================================== */ |
2999 | |
3000 | #define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
3001 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3002 | |
3003 | #if __HVX_ARCH__ >= 60 |
3004 | /* ========================================================================== |
3005 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat |
3006 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
3007 | Instruction Type: CVI_VA |
3008 | Execution Slots: SLOT0123 |
3009 | ========================================================================== */ |
3010 | |
3011 | #define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) |
3012 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3013 | |
3014 | #if __HVX_ARCH__ >= 60 |
3015 | /* ========================================================================== |
3016 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat |
3017 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3018 | Instruction Type: CVI_VA_DV |
3019 | Execution Slots: SLOT0123 |
3020 | ========================================================================== */ |
3021 | |
3022 | #define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) |
3023 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3024 | |
3025 | #if __HVX_ARCH__ >= 60 |
3026 | /* ========================================================================== |
3027 | Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) |
3028 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
3029 | Instruction Type: CVI_VX_DV |
3030 | Execution Slots: SLOT23 |
3031 | ========================================================================== */ |
3032 | |
3033 | #define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) |
3034 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3035 | |
3036 | #if __HVX_ARCH__ >= 60 |
3037 | /* ========================================================================== |
3038 | Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) |
3039 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
3040 | Instruction Type: CVI_VX_DV |
3041 | Execution Slots: SLOT23 |
3042 | ========================================================================== */ |
3043 | |
3044 | #define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) |
3045 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3046 | |
3047 | #if __HVX_ARCH__ >= 60 |
3048 | /* ========================================================================== |
3049 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat |
3050 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
3051 | Instruction Type: CVI_VA |
3052 | Execution Slots: SLOT0123 |
3053 | ========================================================================== */ |
3054 | |
3055 | #define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) |
3056 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3057 | |
3058 | #if __HVX_ARCH__ >= 60 |
3059 | /* ========================================================================== |
3060 | Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat |
3061 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3062 | Instruction Type: CVI_VA_DV |
3063 | Execution Slots: SLOT0123 |
3064 | ========================================================================== */ |
3065 | |
3066 | #define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) |
3067 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3068 | |
3069 | #if __HVX_ARCH__ >= 60 |
3070 | /* ========================================================================== |
3071 | Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat |
3072 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
3073 | Instruction Type: CVI_VA |
3074 | Execution Slots: SLOT0123 |
3075 | ========================================================================== */ |
3076 | |
3077 | #define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) |
3078 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3079 | |
3080 | #if __HVX_ARCH__ >= 60 |
3081 | /* ========================================================================== |
3082 | Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat |
3083 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3084 | Instruction Type: CVI_VA_DV |
3085 | Execution Slots: SLOT0123 |
3086 | ========================================================================== */ |
3087 | |
3088 | #define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) |
3089 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3090 | |
3091 | #if __HVX_ARCH__ >= 60 |
3092 | /* ========================================================================== |
3093 | Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) |
3094 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
3095 | Instruction Type: CVI_VX_DV |
3096 | Execution Slots: SLOT23 |
3097 | ========================================================================== */ |
3098 | |
3099 | #define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) |
3100 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3101 | |
3102 | #if __HVX_ARCH__ >= 60 |
3103 | /* ========================================================================== |
3104 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) |
3105 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
3106 | Instruction Type: CVI_VA |
3107 | Execution Slots: SLOT0123 |
3108 | ========================================================================== */ |
3109 | |
3110 | #define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) |
3111 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3112 | |
3113 | #if __HVX_ARCH__ >= 60 |
3114 | /* ========================================================================== |
3115 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) |
3116 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3117 | Instruction Type: CVI_VA_DV |
3118 | Execution Slots: SLOT0123 |
3119 | ========================================================================== */ |
3120 | |
3121 | #define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) |
3122 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3123 | |
3124 | #if __HVX_ARCH__ >= 60 |
3125 | /* ========================================================================== |
3126 | Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w |
3127 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
3128 | Instruction Type: CVI_VA |
3129 | Execution Slots: SLOT0123 |
3130 | ========================================================================== */ |
3131 | |
3132 | #define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
3133 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3134 | |
3135 | #if __HVX_ARCH__ >= 60 |
3136 | /* ========================================================================== |
3137 | Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w |
3138 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
3139 | Instruction Type: CVI_VA |
3140 | Execution Slots: SLOT0123 |
3141 | ========================================================================== */ |
3142 | |
3143 | #define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) |
3144 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3145 | |
3146 | #if __HVX_ARCH__ >= 60 |
3147 | /* ========================================================================== |
3148 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat |
3149 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
3150 | Instruction Type: CVI_VA |
3151 | Execution Slots: SLOT0123 |
3152 | ========================================================================== */ |
3153 | |
3154 | #define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) |
3155 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3156 | |
3157 | #if __HVX_ARCH__ >= 60 |
3158 | /* ========================================================================== |
3159 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat |
3160 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3161 | Instruction Type: CVI_VA_DV |
3162 | Execution Slots: SLOT0123 |
3163 | ========================================================================== */ |
3164 | |
3165 | #define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) |
3166 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3167 | |
3168 | #if __HVX_ARCH__ >= 60 |
3169 | /* ========================================================================== |
3170 | Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) |
3171 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
3172 | Instruction Type: CVI_VA_DV |
3173 | Execution Slots: SLOT0123 |
3174 | ========================================================================== */ |
3175 | |
3176 | #define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) |
3177 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3178 | |
3179 | #if __HVX_ARCH__ >= 60 |
3180 | /* ========================================================================== |
3181 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) |
3182 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) |
3183 | Instruction Type: CVI_VX_DV |
3184 | Execution Slots: SLOT23 |
3185 | ========================================================================== */ |
3186 | |
3187 | #define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) |
3188 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3189 | |
3190 | #if __HVX_ARCH__ >= 60 |
3191 | /* ========================================================================== |
3192 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) |
3193 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
3194 | Instruction Type: CVI_VX_DV |
3195 | Execution Slots: SLOT23 |
3196 | ========================================================================== */ |
3197 | |
3198 | #define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) |
3199 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3200 | |
3201 | #if __HVX_ARCH__ >= 60 |
3202 | /* ========================================================================== |
3203 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) |
3204 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
3205 | Instruction Type: CVI_VX_DV |
3206 | Execution Slots: SLOT23 |
3207 | ========================================================================== */ |
3208 | |
3209 | #define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) |
3210 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3211 | |
3212 | #if __HVX_ARCH__ >= 60 |
3213 | /* ========================================================================== |
3214 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) |
3215 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
3216 | Instruction Type: CVI_VX_DV |
3217 | Execution Slots: SLOT23 |
3218 | ========================================================================== */ |
3219 | |
3220 | #define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) |
3221 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3222 | |
3223 | #if __HVX_ARCH__ >= 60 |
3224 | /* ========================================================================== |
3225 | Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) |
3226 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
3227 | Instruction Type: CVI_VX_DV |
3228 | Execution Slots: SLOT23 |
3229 | ========================================================================== */ |
3230 | |
3231 | #define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) |
3232 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3233 | |
3234 | #if __HVX_ARCH__ >= 60 |
3235 | /* ========================================================================== |
3236 | Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) |
3237 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
3238 | Instruction Type: CVI_VX_DV |
3239 | Execution Slots: SLOT23 |
3240 | ========================================================================== */ |
3241 | |
3242 | #define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) |
3243 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3244 | |
3245 | #if __HVX_ARCH__ >= 60 |
3246 | /* ========================================================================== |
3247 | Assembly Syntax: Vdd32.h=vunpack(Vu32.b) |
3248 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) |
3249 | Instruction Type: CVI_VP_VS |
3250 | Execution Slots: SLOT0123 |
3251 | ========================================================================== */ |
3252 | |
3253 | #define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) |
3254 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3255 | |
3256 | #if __HVX_ARCH__ >= 60 |
3257 | /* ========================================================================== |
3258 | Assembly Syntax: Vdd32.w=vunpack(Vu32.h) |
3259 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) |
3260 | Instruction Type: CVI_VP_VS |
3261 | Execution Slots: SLOT0123 |
3262 | ========================================================================== */ |
3263 | |
3264 | #define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) |
3265 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3266 | |
3267 | #if __HVX_ARCH__ >= 60 |
3268 | /* ========================================================================== |
3269 | Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) |
3270 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) |
3271 | Instruction Type: CVI_VP_VS |
3272 | Execution Slots: SLOT0123 |
3273 | ========================================================================== */ |
3274 | |
3275 | #define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) |
3276 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3277 | |
3278 | #if __HVX_ARCH__ >= 60 |
3279 | /* ========================================================================== |
3280 | Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) |
3281 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) |
3282 | Instruction Type: CVI_VP_VS |
3283 | Execution Slots: SLOT0123 |
3284 | ========================================================================== */ |
3285 | |
3286 | #define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) |
3287 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3288 | |
3289 | #if __HVX_ARCH__ >= 60 |
3290 | /* ========================================================================== |
3291 | Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) |
3292 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) |
3293 | Instruction Type: CVI_VP_VS |
3294 | Execution Slots: SLOT0123 |
3295 | ========================================================================== */ |
3296 | |
3297 | #define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) |
3298 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3299 | |
3300 | #if __HVX_ARCH__ >= 60 |
3301 | /* ========================================================================== |
3302 | Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) |
3303 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) |
3304 | Instruction Type: CVI_VP_VS |
3305 | Execution Slots: SLOT0123 |
3306 | ========================================================================== */ |
3307 | |
3308 | #define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) |
3309 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3310 | |
3311 | #if __HVX_ARCH__ >= 60 |
3312 | /* ========================================================================== |
3313 | Assembly Syntax: Vd32=vxor(Vu32,Vv32) |
3314 | C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) |
3315 | Instruction Type: CVI_VA |
3316 | Execution Slots: SLOT0123 |
3317 | ========================================================================== */ |
3318 | |
3319 | #define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) |
3320 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3321 | |
3322 | #if __HVX_ARCH__ >= 60 |
3323 | /* ========================================================================== |
3324 | Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) |
3325 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) |
3326 | Instruction Type: CVI_VA_DV |
3327 | Execution Slots: SLOT0123 |
3328 | ========================================================================== */ |
3329 | |
3330 | #define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) |
3331 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3332 | |
3333 | #if __HVX_ARCH__ >= 60 |
3334 | /* ========================================================================== |
3335 | Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) |
3336 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) |
3337 | Instruction Type: CVI_VA_DV |
3338 | Execution Slots: SLOT0123 |
3339 | ========================================================================== */ |
3340 | |
3341 | #define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) |
3342 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
3343 | |
3344 | #if __HVX_ARCH__ >= 62 |
3345 | /* ========================================================================== |
3346 | Assembly Syntax: Vd32.b=vsplat(Rt32) |
3347 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) |
3348 | Instruction Type: CVI_VX_LATE |
3349 | Execution Slots: SLOT23 |
3350 | ========================================================================== */ |
3351 | |
3352 | #define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) |
3353 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3354 | |
3355 | #if __HVX_ARCH__ >= 62 |
3356 | /* ========================================================================== |
3357 | Assembly Syntax: Vd32.h=vsplat(Rt32) |
3358 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) |
3359 | Instruction Type: CVI_VX_LATE |
3360 | Execution Slots: SLOT23 |
3361 | ========================================================================== */ |
3362 | |
3363 | #define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) |
3364 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3365 | |
3366 | #if __HVX_ARCH__ >= 62 |
3367 | /* ========================================================================== |
3368 | Assembly Syntax: Qd4=vsetq2(Rt32) |
3369 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) |
3370 | Instruction Type: CVI_VP |
3371 | Execution Slots: SLOT0123 |
3372 | ========================================================================== */ |
3373 | |
3374 | #define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) |
3375 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3376 | |
3377 | #if __HVX_ARCH__ >= 62 |
3378 | /* ========================================================================== |
3379 | Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) |
3380 | C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) |
3381 | Instruction Type: CVI_VA_DV |
3382 | Execution Slots: SLOT0123 |
3383 | ========================================================================== */ |
3384 | |
3385 | #define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
3386 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3387 | |
3388 | #if __HVX_ARCH__ >= 62 |
3389 | /* ========================================================================== |
3390 | Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) |
3391 | C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) |
3392 | Instruction Type: CVI_VA_DV |
3393 | Execution Slots: SLOT0123 |
3394 | ========================================================================== */ |
3395 | |
3396 | #define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) |
3397 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3398 | |
3399 | #if __HVX_ARCH__ >= 62 |
3400 | /* ========================================================================== |
3401 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat |
3402 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
3403 | Instruction Type: CVI_VA |
3404 | Execution Slots: SLOT0123 |
3405 | ========================================================================== */ |
3406 | |
3407 | #define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) |
3408 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3409 | |
3410 | #if __HVX_ARCH__ >= 62 |
3411 | /* ========================================================================== |
3412 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat |
3413 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3414 | Instruction Type: CVI_VA_DV |
3415 | Execution Slots: SLOT0123 |
3416 | ========================================================================== */ |
3417 | |
3418 | #define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) |
3419 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3420 | |
3421 | #if __HVX_ARCH__ >= 62 |
3422 | /* ========================================================================== |
3423 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry |
3424 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
3425 | Instruction Type: CVI_VA |
3426 | Execution Slots: SLOT0123 |
3427 | ========================================================================== */ |
3428 | |
3429 | #define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) |
3430 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3431 | |
3432 | #if __HVX_ARCH__ >= 62 |
3433 | /* ========================================================================== |
3434 | Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) |
3435 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
3436 | Instruction Type: CVI_VS |
3437 | Execution Slots: SLOT0123 |
3438 | ========================================================================== */ |
3439 | |
3440 | #define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) |
3441 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3442 | |
3443 | #if __HVX_ARCH__ >= 62 |
3444 | /* ========================================================================== |
3445 | Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) |
3446 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
3447 | Instruction Type: CVI_VS |
3448 | Execution Slots: SLOT0123 |
3449 | ========================================================================== */ |
3450 | |
3451 | #define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) |
3452 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3453 | |
3454 | #if __HVX_ARCH__ >= 62 |
3455 | /* ========================================================================== |
3456 | Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) |
3457 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
3458 | Instruction Type: CVI_VX_DV |
3459 | Execution Slots: SLOT23 |
3460 | ========================================================================== */ |
3461 | |
3462 | #define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) |
3463 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3464 | |
3465 | #if __HVX_ARCH__ >= 62 |
3466 | /* ========================================================================== |
3467 | Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) |
3468 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
3469 | Instruction Type: CVI_VX_DV |
3470 | Execution Slots: SLOT23 |
3471 | ========================================================================== */ |
3472 | |
3473 | #define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) |
3474 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3475 | |
3476 | #if __HVX_ARCH__ >= 62 |
3477 | /* ========================================================================== |
3478 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat |
3479 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
3480 | Instruction Type: CVI_VA |
3481 | Execution Slots: SLOT0123 |
3482 | ========================================================================== */ |
3483 | |
3484 | #define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) |
3485 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3486 | |
3487 | #if __HVX_ARCH__ >= 62 |
3488 | /* ========================================================================== |
3489 | Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) |
3490 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
3491 | Instruction Type: CVI_VX_DV |
3492 | Execution Slots: SLOT23 |
3493 | ========================================================================== */ |
3494 | |
3495 | #define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) |
3496 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3497 | |
3498 | #if __HVX_ARCH__ >= 62 |
3499 | /* ========================================================================== |
3500 | Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat |
3501 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
3502 | Instruction Type: CVI_VA |
3503 | Execution Slots: SLOT0123 |
3504 | ========================================================================== */ |
3505 | |
3506 | #define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) |
3507 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3508 | |
3509 | #if __HVX_ARCH__ >= 62 |
3510 | /* ========================================================================== |
3511 | Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat |
3512 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3513 | Instruction Type: CVI_VA_DV |
3514 | Execution Slots: SLOT0123 |
3515 | ========================================================================== */ |
3516 | |
3517 | #define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) |
3518 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3519 | |
3520 | #if __HVX_ARCH__ >= 62 |
3521 | /* ========================================================================== |
3522 | Assembly Syntax: Vd32=vand(!Qu4,Rt32) |
3523 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) |
3524 | Instruction Type: CVI_VX_LATE |
3525 | Execution Slots: SLOT23 |
3526 | ========================================================================== */ |
3527 | |
3528 | #define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
3529 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3530 | |
3531 | #if __HVX_ARCH__ >= 62 |
3532 | /* ========================================================================== |
3533 | Assembly Syntax: Vx32|=vand(!Qu4,Rt32) |
3534 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
3535 | Instruction Type: CVI_VX_LATE |
3536 | Execution Slots: SLOT23 |
3537 | ========================================================================== */ |
3538 | |
3539 | #define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) |
3540 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3541 | |
3542 | #if __HVX_ARCH__ >= 62 |
3543 | /* ========================================================================== |
3544 | Assembly Syntax: Vd32=vand(!Qv4,Vu32) |
3545 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) |
3546 | Instruction Type: CVI_VA |
3547 | Execution Slots: SLOT0123 |
3548 | ========================================================================== */ |
3549 | |
3550 | #define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) |
3551 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3552 | |
3553 | #if __HVX_ARCH__ >= 62 |
3554 | /* ========================================================================== |
3555 | Assembly Syntax: Vd32=vand(Qv4,Vu32) |
3556 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) |
3557 | Instruction Type: CVI_VA |
3558 | Execution Slots: SLOT0123 |
3559 | ========================================================================== */ |
3560 | |
3561 | #define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) |
3562 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3563 | |
3564 | #if __HVX_ARCH__ >= 62 |
3565 | /* ========================================================================== |
3566 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat |
3567 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3568 | Instruction Type: CVI_VS |
3569 | Execution Slots: SLOT0123 |
3570 | ========================================================================== */ |
3571 | |
3572 | #define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) |
3573 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3574 | |
3575 | #if __HVX_ARCH__ >= 62 |
3576 | /* ========================================================================== |
3577 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat |
3578 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3579 | Instruction Type: CVI_VS |
3580 | Execution Slots: SLOT0123 |
3581 | ========================================================================== */ |
3582 | |
3583 | #define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) |
3584 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3585 | |
3586 | #if __HVX_ARCH__ >= 62 |
3587 | /* ========================================================================== |
3588 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
3589 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3590 | Instruction Type: CVI_VS |
3591 | Execution Slots: SLOT0123 |
3592 | ========================================================================== */ |
3593 | |
3594 | #define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) |
3595 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3596 | |
3597 | #if __HVX_ARCH__ >= 62 |
3598 | /* ========================================================================== |
3599 | Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) |
3600 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) |
3601 | Instruction Type: CVI_VS |
3602 | Execution Slots: SLOT0123 |
3603 | ========================================================================== */ |
3604 | |
3605 | #define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) |
3606 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3607 | |
3608 | #if __HVX_ARCH__ >= 62 |
3609 | /* ========================================================================== |
3610 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch |
3611 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3612 | Instruction Type: CVI_VP |
3613 | Execution Slots: SLOT0123 |
3614 | ========================================================================== */ |
3615 | |
3616 | #define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) |
3617 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3618 | |
3619 | #if __HVX_ARCH__ >= 62 |
3620 | /* ========================================================================== |
3621 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) |
3622 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
3623 | Instruction Type: CVI_VP_VS |
3624 | Execution Slots: SLOT0123 |
3625 | ========================================================================== */ |
3626 | |
3627 | #define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) |
3628 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3629 | |
3630 | #if __HVX_ARCH__ >= 62 |
3631 | /* ========================================================================== |
3632 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) |
3633 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
3634 | Instruction Type: CVI_VP |
3635 | Execution Slots: SLOT0123 |
3636 | ========================================================================== */ |
3637 | |
3638 | #define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) |
3639 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3640 | |
3641 | #if __HVX_ARCH__ >= 62 |
3642 | /* ========================================================================== |
3643 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch |
3644 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3645 | Instruction Type: CVI_VP_VS |
3646 | Execution Slots: SLOT0123 |
3647 | ========================================================================== */ |
3648 | |
3649 | #define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) |
3650 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3651 | |
3652 | #if __HVX_ARCH__ >= 62 |
3653 | /* ========================================================================== |
3654 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) |
3655 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
3656 | Instruction Type: CVI_VP_VS |
3657 | Execution Slots: SLOT0123 |
3658 | ========================================================================== */ |
3659 | |
3660 | #define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) |
3661 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3662 | |
3663 | #if __HVX_ARCH__ >= 62 |
3664 | /* ========================================================================== |
3665 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) |
3666 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
3667 | Instruction Type: CVI_VP_VS |
3668 | Execution Slots: SLOT0123 |
3669 | ========================================================================== */ |
3670 | |
3671 | #define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) |
3672 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3673 | |
3674 | #if __HVX_ARCH__ >= 62 |
3675 | /* ========================================================================== |
3676 | Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) |
3677 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
3678 | Instruction Type: CVI_VA |
3679 | Execution Slots: SLOT0123 |
3680 | ========================================================================== */ |
3681 | |
3682 | #define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) |
3683 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3684 | |
3685 | #if __HVX_ARCH__ >= 62 |
3686 | /* ========================================================================== |
3687 | Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) |
3688 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
3689 | Instruction Type: CVI_VA |
3690 | Execution Slots: SLOT0123 |
3691 | ========================================================================== */ |
3692 | |
3693 | #define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) |
3694 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3695 | |
3696 | #if __HVX_ARCH__ >= 62 |
3697 | /* ========================================================================== |
3698 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) |
3699 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) |
3700 | Instruction Type: CVI_VX_DV |
3701 | Execution Slots: SLOT23 |
3702 | ========================================================================== */ |
3703 | |
3704 | #define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) |
3705 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3706 | |
3707 | #if __HVX_ARCH__ >= 62 |
3708 | /* ========================================================================== |
3709 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) |
3710 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
3711 | Instruction Type: CVI_VX_DV |
3712 | Execution Slots: SLOT23 |
3713 | ========================================================================== */ |
3714 | |
3715 | #define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) |
3716 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3717 | |
3718 | #if __HVX_ARCH__ >= 62 |
3719 | /* ========================================================================== |
3720 | Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) |
3721 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
3722 | Instruction Type: CVI_VX_DV |
3723 | Execution Slots: SLOT23 |
3724 | ========================================================================== */ |
3725 | |
3726 | #define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) |
3727 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3728 | |
3729 | #if __HVX_ARCH__ >= 62 |
3730 | /* ========================================================================== |
3731 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) |
3732 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) |
3733 | Instruction Type: CVI_VX |
3734 | Execution Slots: SLOT23 |
3735 | ========================================================================== */ |
3736 | |
3737 | #define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) |
3738 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3739 | |
3740 | #if __HVX_ARCH__ >= 62 |
3741 | /* ========================================================================== |
3742 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) |
3743 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
3744 | Instruction Type: CVI_VX |
3745 | Execution Slots: SLOT23 |
3746 | ========================================================================== */ |
3747 | |
3748 | #define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) |
3749 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3750 | |
3751 | #if __HVX_ARCH__ >= 62 |
3752 | /* ========================================================================== |
3753 | Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) |
3754 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
3755 | Instruction Type: CVI_VX_DV |
3756 | Execution Slots: SLOT23 |
3757 | ========================================================================== */ |
3758 | |
3759 | #define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) |
3760 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3761 | |
3762 | #if __HVX_ARCH__ >= 62 |
3763 | /* ========================================================================== |
3764 | Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat |
3765 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
3766 | Instruction Type: CVI_VS |
3767 | Execution Slots: SLOT0123 |
3768 | ========================================================================== */ |
3769 | |
3770 | #define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) |
3771 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3772 | |
3773 | #if __HVX_ARCH__ >= 62 |
3774 | /* ========================================================================== |
3775 | Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat |
3776 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
3777 | Instruction Type: CVI_VS |
3778 | Execution Slots: SLOT0123 |
3779 | ========================================================================== */ |
3780 | |
3781 | #define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) |
3782 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3783 | |
3784 | #if __HVX_ARCH__ >= 62 |
3785 | /* ========================================================================== |
3786 | Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) |
3787 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
3788 | Instruction Type: CVI_VA |
3789 | Execution Slots: SLOT0123 |
3790 | ========================================================================== */ |
3791 | |
3792 | #define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) |
3793 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3794 | |
3795 | #if __HVX_ARCH__ >= 62 |
3796 | /* ========================================================================== |
3797 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat |
3798 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
3799 | Instruction Type: CVI_VA |
3800 | Execution Slots: SLOT0123 |
3801 | ========================================================================== */ |
3802 | |
3803 | #define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) |
3804 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3805 | |
3806 | #if __HVX_ARCH__ >= 62 |
3807 | /* ========================================================================== |
3808 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat |
3809 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3810 | Instruction Type: CVI_VA_DV |
3811 | Execution Slots: SLOT0123 |
3812 | ========================================================================== */ |
3813 | |
3814 | #define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) |
3815 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3816 | |
3817 | #if __HVX_ARCH__ >= 62 |
3818 | /* ========================================================================== |
3819 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry |
3820 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
3821 | Instruction Type: CVI_VA |
3822 | Execution Slots: SLOT0123 |
3823 | ========================================================================== */ |
3824 | |
3825 | #define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) |
3826 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3827 | |
3828 | #if __HVX_ARCH__ >= 62 |
3829 | /* ========================================================================== |
3830 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat |
3831 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
3832 | Instruction Type: CVI_VA |
3833 | Execution Slots: SLOT0123 |
3834 | ========================================================================== */ |
3835 | |
3836 | #define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) |
3837 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3838 | |
3839 | #if __HVX_ARCH__ >= 62 |
3840 | /* ========================================================================== |
3841 | Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat |
3842 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
3843 | Instruction Type: CVI_VA |
3844 | Execution Slots: SLOT0123 |
3845 | ========================================================================== */ |
3846 | |
3847 | #define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) |
3848 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3849 | |
3850 | #if __HVX_ARCH__ >= 62 |
3851 | /* ========================================================================== |
3852 | Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat |
3853 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
3854 | Instruction Type: CVI_VA_DV |
3855 | Execution Slots: SLOT0123 |
3856 | ========================================================================== */ |
3857 | |
3858 | #define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) |
3859 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
3860 | |
3861 | #if __HVX_ARCH__ >= 65 |
3862 | /* ========================================================================== |
3863 | Assembly Syntax: Vd32.b=vabs(Vu32.b) |
3864 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) |
3865 | Instruction Type: CVI_VA |
3866 | Execution Slots: SLOT0123 |
3867 | ========================================================================== */ |
3868 | |
3869 | #define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) |
3870 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3871 | |
3872 | #if __HVX_ARCH__ >= 65 |
3873 | /* ========================================================================== |
3874 | Assembly Syntax: Vd32.b=vabs(Vu32.b):sat |
3875 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) |
3876 | Instruction Type: CVI_VA |
3877 | Execution Slots: SLOT0123 |
3878 | ========================================================================== */ |
3879 | |
3880 | #define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) |
3881 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3882 | |
3883 | #if __HVX_ARCH__ >= 65 |
3884 | /* ========================================================================== |
3885 | Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) |
3886 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
3887 | Instruction Type: CVI_VS |
3888 | Execution Slots: SLOT0123 |
3889 | ========================================================================== */ |
3890 | |
3891 | #define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) |
3892 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3893 | |
3894 | #if __HVX_ARCH__ >= 65 |
3895 | /* ========================================================================== |
3896 | Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) |
3897 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
3898 | Instruction Type: CVI_VS |
3899 | Execution Slots: SLOT0123 |
3900 | ========================================================================== */ |
3901 | |
3902 | #define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) |
3903 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3904 | |
3905 | #if __HVX_ARCH__ >= 65 |
3906 | /* ========================================================================== |
3907 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat |
3908 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3909 | Instruction Type: CVI_VS |
3910 | Execution Slots: SLOT0123 |
3911 | ========================================================================== */ |
3912 | |
3913 | #define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) |
3914 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3915 | |
3916 | #if __HVX_ARCH__ >= 65 |
3917 | /* ========================================================================== |
3918 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat |
3919 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3920 | Instruction Type: CVI_VS |
3921 | Execution Slots: SLOT0123 |
3922 | ========================================================================== */ |
3923 | |
3924 | #define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) |
3925 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3926 | |
3927 | #if __HVX_ARCH__ >= 65 |
3928 | /* ========================================================================== |
3929 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat |
3930 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
3931 | Instruction Type: CVI_VS |
3932 | Execution Slots: SLOT0123 |
3933 | ========================================================================== */ |
3934 | |
3935 | #define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) |
3936 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3937 | |
3938 | #if __HVX_ARCH__ >= 65 |
3939 | /* ========================================================================== |
3940 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) |
3941 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
3942 | Instruction Type: CVI_VA |
3943 | Execution Slots: SLOT0123 |
3944 | ========================================================================== */ |
3945 | |
3946 | #define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) |
3947 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3948 | |
3949 | #if __HVX_ARCH__ >= 65 |
3950 | /* ========================================================================== |
3951 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd |
3952 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) |
3953 | Instruction Type: CVI_VA |
3954 | Execution Slots: SLOT0123 |
3955 | ========================================================================== */ |
3956 | |
3957 | #define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) |
3958 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3959 | |
3960 | #if __HVX_ARCH__ >= 65 |
3961 | /* ========================================================================== |
3962 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) |
3963 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
3964 | Instruction Type: CVI_VA |
3965 | Execution Slots: SLOT0123 |
3966 | ========================================================================== */ |
3967 | |
3968 | #define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) |
3969 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3970 | |
3971 | #if __HVX_ARCH__ >= 65 |
3972 | /* ========================================================================== |
3973 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd |
3974 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
3975 | Instruction Type: CVI_VA |
3976 | Execution Slots: SLOT0123 |
3977 | ========================================================================== */ |
3978 | |
3979 | #define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) |
3980 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3981 | |
3982 | #if __HVX_ARCH__ >= 65 |
3983 | /* ========================================================================== |
3984 | Assembly Syntax: Vdd32=#0 |
3985 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() |
3986 | Instruction Type: MAPPING |
3987 | Execution Slots: SLOT0123 |
3988 | ========================================================================== */ |
3989 | |
3990 | #define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() |
3991 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
3992 | |
3993 | #if __HVX_ARCH__ >= 65 |
3994 | /* ========================================================================== |
3995 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
3996 | C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
3997 | Instruction Type: CVI_GATHER |
3998 | Execution Slots: SLOT01 |
3999 | ========================================================================== */ |
4000 | |
4001 | #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) |
4002 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4003 | |
4004 | #if __HVX_ARCH__ >= 65 |
4005 | /* ========================================================================== |
4006 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
4007 | C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
4008 | Instruction Type: CVI_GATHER |
4009 | Execution Slots: SLOT01 |
4010 | ========================================================================== */ |
4011 | |
4012 | #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) |
4013 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4014 | |
4015 | #if __HVX_ARCH__ >= 65 |
4016 | /* ========================================================================== |
4017 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
4018 | C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
4019 | Instruction Type: CVI_GATHER_DV |
4020 | Execution Slots: SLOT01 |
4021 | ========================================================================== */ |
4022 | |
4023 | #define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) |
4024 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4025 | |
4026 | #if __HVX_ARCH__ >= 65 |
4027 | /* ========================================================================== |
4028 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
4029 | C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
4030 | Instruction Type: CVI_GATHER_DV |
4031 | Execution Slots: SLOT01 |
4032 | ========================================================================== */ |
4033 | |
4034 | #define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) |
4035 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4036 | |
4037 | #if __HVX_ARCH__ >= 65 |
4038 | /* ========================================================================== |
4039 | Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
4040 | C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
4041 | Instruction Type: CVI_GATHER |
4042 | Execution Slots: SLOT01 |
4043 | ========================================================================== */ |
4044 | |
4045 | #define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) |
4046 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4047 | |
4048 | #if __HVX_ARCH__ >= 65 |
4049 | /* ========================================================================== |
4050 | Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
4051 | C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
4052 | Instruction Type: CVI_GATHER |
4053 | Execution Slots: SLOT01 |
4054 | ========================================================================== */ |
4055 | |
4056 | #define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) |
4057 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4058 | |
4059 | #if __HVX_ARCH__ >= 65 |
4060 | /* ========================================================================== |
4061 | Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) |
4062 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) |
4063 | Instruction Type: CVI_VX_DV |
4064 | Execution Slots: SLOT2 |
4065 | ========================================================================== */ |
4066 | |
4067 | #define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) |
4068 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4069 | |
4070 | #if __HVX_ARCH__ >= 65 |
4071 | /* ========================================================================== |
4072 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) |
4073 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) |
4074 | Instruction Type: CVI_VX_DV |
4075 | Execution Slots: SLOT23 |
4076 | ========================================================================== */ |
4077 | |
4078 | #define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) |
4079 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4080 | |
4081 | #if __HVX_ARCH__ >= 65 |
4082 | /* ========================================================================== |
4083 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) |
4084 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
4085 | Instruction Type: CVI_VX_DV |
4086 | Execution Slots: SLOT23 |
4087 | ========================================================================== */ |
4088 | |
4089 | #define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) |
4090 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4091 | |
4092 | #if __HVX_ARCH__ >= 65 |
4093 | /* ========================================================================== |
4094 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat |
4095 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
4096 | Instruction Type: CVI_VX_DV |
4097 | Execution Slots: SLOT2 |
4098 | ========================================================================== */ |
4099 | |
4100 | #define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) |
4101 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4102 | |
4103 | #if __HVX_ARCH__ >= 65 |
4104 | /* ========================================================================== |
4105 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat |
4106 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
4107 | Instruction Type: CVI_VX_DV |
4108 | Execution Slots: SLOT2 |
4109 | ========================================================================== */ |
4110 | |
4111 | #define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) |
4112 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4113 | |
4114 | #if __HVX_ARCH__ >= 65 |
4115 | /* ========================================================================== |
4116 | Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat |
4117 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
4118 | Instruction Type: CVI_VX_DV |
4119 | Execution Slots: SLOT2 |
4120 | ========================================================================== */ |
4121 | |
4122 | #define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) |
4123 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4124 | |
4125 | #if __HVX_ARCH__ >= 65 |
4126 | /* ========================================================================== |
4127 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) |
4128 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
4129 | Instruction Type: CVI_VX_DV |
4130 | Execution Slots: SLOT23 |
4131 | ========================================================================== */ |
4132 | |
4133 | #define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) |
4134 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4135 | |
4136 | #if __HVX_ARCH__ >= 65 |
4137 | /* ========================================================================== |
4138 | Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) |
4139 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) |
4140 | Instruction Type: CVI_VX |
4141 | Execution Slots: SLOT23 |
4142 | ========================================================================== */ |
4143 | |
4144 | #define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) |
4145 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4146 | |
4147 | #if __HVX_ARCH__ >= 65 |
4148 | /* ========================================================================== |
4149 | Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) |
4150 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
4151 | Instruction Type: CVI_VX |
4152 | Execution Slots: SLOT23 |
4153 | ========================================================================== */ |
4154 | |
4155 | #define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) |
4156 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4157 | |
4158 | #if __HVX_ARCH__ >= 65 |
4159 | /* ========================================================================== |
4160 | Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) |
4161 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
4162 | Instruction Type: CVI_VA |
4163 | Execution Slots: SLOT0123 |
4164 | ========================================================================== */ |
4165 | |
4166 | #define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) |
4167 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4168 | |
4169 | #if __HVX_ARCH__ >= 65 |
4170 | /* ========================================================================== |
4171 | Assembly Syntax: Vd32.b=prefixsum(Qv4) |
4172 | C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) |
4173 | Instruction Type: CVI_VS |
4174 | Execution Slots: SLOT0123 |
4175 | ========================================================================== */ |
4176 | |
4177 | #define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
4178 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4179 | |
4180 | #if __HVX_ARCH__ >= 65 |
4181 | /* ========================================================================== |
4182 | Assembly Syntax: Vd32.h=prefixsum(Qv4) |
4183 | C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) |
4184 | Instruction Type: CVI_VS |
4185 | Execution Slots: SLOT0123 |
4186 | ========================================================================== */ |
4187 | |
4188 | #define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
4189 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4190 | |
4191 | #if __HVX_ARCH__ >= 65 |
4192 | /* ========================================================================== |
4193 | Assembly Syntax: Vd32.w=prefixsum(Qv4) |
4194 | C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) |
4195 | Instruction Type: CVI_VS |
4196 | Execution Slots: SLOT0123 |
4197 | ========================================================================== */ |
4198 | |
4199 | #define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) |
4200 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4201 | |
4202 | #if __HVX_ARCH__ >= 65 |
4203 | /* ========================================================================== |
4204 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
4205 | C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4206 | Instruction Type: CVI_SCATTER |
4207 | Execution Slots: SLOT0 |
4208 | ========================================================================== */ |
4209 | |
4210 | #define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) |
4211 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4212 | |
4213 | #if __HVX_ARCH__ >= 65 |
4214 | /* ========================================================================== |
4215 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 |
4216 | C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4217 | Instruction Type: CVI_SCATTER |
4218 | Execution Slots: SLOT0 |
4219 | ========================================================================== */ |
4220 | |
4221 | #define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) |
4222 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4223 | |
4224 | #if __HVX_ARCH__ >= 65 |
4225 | /* ========================================================================== |
4226 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
4227 | C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4228 | Instruction Type: CVI_SCATTER |
4229 | Execution Slots: SLOT0 |
4230 | ========================================================================== */ |
4231 | |
4232 | #define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) |
4233 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4234 | |
4235 | #if __HVX_ARCH__ >= 65 |
4236 | /* ========================================================================== |
4237 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
4238 | C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
4239 | Instruction Type: CVI_SCATTER_DV |
4240 | Execution Slots: SLOT0 |
4241 | ========================================================================== */ |
4242 | |
4243 | #define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) |
4244 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4245 | |
4246 | #if __HVX_ARCH__ >= 65 |
4247 | /* ========================================================================== |
4248 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 |
4249 | C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
4250 | Instruction Type: CVI_SCATTER_DV |
4251 | Execution Slots: SLOT0 |
4252 | ========================================================================== */ |
4253 | |
4254 | #define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) |
4255 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4256 | |
4257 | #if __HVX_ARCH__ >= 65 |
4258 | /* ========================================================================== |
4259 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
4260 | C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
4261 | Instruction Type: CVI_SCATTER_DV |
4262 | Execution Slots: SLOT0 |
4263 | ========================================================================== */ |
4264 | |
4265 | #define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) |
4266 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4267 | |
4268 | #if __HVX_ARCH__ >= 65 |
4269 | /* ========================================================================== |
4270 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
4271 | C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4272 | Instruction Type: CVI_SCATTER |
4273 | Execution Slots: SLOT0 |
4274 | ========================================================================== */ |
4275 | |
4276 | #define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) |
4277 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4278 | |
4279 | #if __HVX_ARCH__ >= 65 |
4280 | /* ========================================================================== |
4281 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 |
4282 | C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4283 | Instruction Type: CVI_SCATTER |
4284 | Execution Slots: SLOT0 |
4285 | ========================================================================== */ |
4286 | |
4287 | #define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) |
4288 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4289 | |
4290 | #if __HVX_ARCH__ >= 65 |
4291 | /* ========================================================================== |
4292 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
4293 | C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
4294 | Instruction Type: CVI_SCATTER |
4295 | Execution Slots: SLOT0 |
4296 | ========================================================================== */ |
4297 | |
4298 | #define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) |
4299 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
4300 | |
4301 | #if __HVX_ARCH__ >= 66 |
4302 | /* ========================================================================== |
4303 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat |
4304 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) |
4305 | Instruction Type: CVI_VA |
4306 | Execution Slots: SLOT0123 |
4307 | ========================================================================== */ |
4308 | |
4309 | #define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) |
4310 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
4311 | |
4312 | #if __HVX_ARCH__ >= 66 |
4313 | /* ========================================================================== |
4314 | Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) |
4315 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
4316 | Instruction Type: CVI_VP_VS |
4317 | Execution Slots: SLOT0123 |
4318 | ========================================================================== */ |
4319 | |
4320 | #define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) |
4321 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
4322 | |
4323 | #if __HVX_ARCH__ >= 66 |
4324 | /* ========================================================================== |
4325 | Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) |
4326 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
4327 | Instruction Type: CVI_VS |
4328 | Execution Slots: SLOT0123 |
4329 | ========================================================================== */ |
4330 | |
4331 | #define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) |
4332 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
4333 | |
4334 | #if __HVX_ARCH__ >= 66 |
4335 | /* ========================================================================== |
4336 | Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) |
4337 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
4338 | Instruction Type: CVI_VA |
4339 | Execution Slots: SLOT0123 |
4340 | ========================================================================== */ |
4341 | |
4342 | #define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) |
4343 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
4344 | |
4345 | #if __HVX_ARCH__ >= 68 |
4346 | /* ========================================================================== |
4347 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
4348 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
4349 | Instruction Type: CVI_VX_DV |
4350 | Execution Slots: SLOT23 |
4351 | ========================================================================== */ |
4352 | |
4353 | #define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) |
4354 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4355 | |
4356 | #if __HVX_ARCH__ >= 68 |
4357 | /* ========================================================================== |
4358 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
4359 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
4360 | Instruction Type: CVI_VX_DV |
4361 | Execution Slots: SLOT23 |
4362 | ========================================================================== */ |
4363 | |
4364 | #define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) |
4365 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4366 | |
4367 | #if __HVX_ARCH__ >= 68 |
4368 | /* ========================================================================== |
4369 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
4370 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
4371 | Instruction Type: CVI_VX_DV |
4372 | Execution Slots: SLOT23 |
4373 | ========================================================================== */ |
4374 | |
4375 | #define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) |
4376 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4377 | |
4378 | #if __HVX_ARCH__ >= 68 |
4379 | /* ========================================================================== |
4380 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
4381 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
4382 | Instruction Type: CVI_VX_DV |
4383 | Execution Slots: SLOT23 |
4384 | ========================================================================== */ |
4385 | |
4386 | #define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) |
4387 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4388 | |
4389 | #if __HVX_ARCH__ >= 68 |
4390 | /* ========================================================================== |
4391 | Assembly Syntax: Vd32.hf=vabs(Vu32.hf) |
4392 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) |
4393 | Instruction Type: CVI_VX_LATE |
4394 | Execution Slots: SLOT23 |
4395 | ========================================================================== */ |
4396 | |
4397 | #define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) |
4398 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4399 | |
4400 | #if __HVX_ARCH__ >= 68 |
4401 | /* ========================================================================== |
4402 | Assembly Syntax: Vd32.sf=vabs(Vu32.sf) |
4403 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) |
4404 | Instruction Type: CVI_VX_LATE |
4405 | Execution Slots: SLOT23 |
4406 | ========================================================================== */ |
4407 | |
4408 | #define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) |
4409 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4410 | |
4411 | #if __HVX_ARCH__ >= 68 |
4412 | /* ========================================================================== |
4413 | Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) |
4414 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4415 | Instruction Type: CVI_VS |
4416 | Execution Slots: SLOT0123 |
4417 | ========================================================================== */ |
4418 | |
4419 | #define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) |
4420 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4421 | |
4422 | #if __HVX_ARCH__ >= 68 |
4423 | /* ========================================================================== |
4424 | Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) |
4425 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4426 | Instruction Type: CVI_VX |
4427 | Execution Slots: SLOT23 |
4428 | ========================================================================== */ |
4429 | |
4430 | #define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) |
4431 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4432 | |
4433 | #if __HVX_ARCH__ >= 68 |
4434 | /* ========================================================================== |
4435 | Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) |
4436 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
4437 | Instruction Type: CVI_VS |
4438 | Execution Slots: SLOT0123 |
4439 | ========================================================================== */ |
4440 | |
4441 | #define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) |
4442 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4443 | |
4444 | #if __HVX_ARCH__ >= 68 |
4445 | /* ========================================================================== |
4446 | Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) |
4447 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
4448 | Instruction Type: CVI_VS |
4449 | Execution Slots: SLOT0123 |
4450 | ========================================================================== */ |
4451 | |
4452 | #define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) |
4453 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4454 | |
4455 | #if __HVX_ARCH__ >= 68 |
4456 | /* ========================================================================== |
4457 | Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) |
4458 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
4459 | Instruction Type: CVI_VS |
4460 | Execution Slots: SLOT0123 |
4461 | ========================================================================== */ |
4462 | |
4463 | #define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) |
4464 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4465 | |
4466 | #if __HVX_ARCH__ >= 68 |
4467 | /* ========================================================================== |
4468 | Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) |
4469 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) |
4470 | Instruction Type: CVI_VS |
4471 | Execution Slots: SLOT0123 |
4472 | ========================================================================== */ |
4473 | |
4474 | #define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) |
4475 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4476 | |
4477 | #if __HVX_ARCH__ >= 68 |
4478 | /* ========================================================================== |
4479 | Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) |
4480 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4481 | Instruction Type: CVI_VS |
4482 | Execution Slots: SLOT0123 |
4483 | ========================================================================== */ |
4484 | |
4485 | #define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) |
4486 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4487 | |
4488 | #if __HVX_ARCH__ >= 68 |
4489 | /* ========================================================================== |
4490 | Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) |
4491 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4492 | Instruction Type: CVI_VX_DV |
4493 | Execution Slots: SLOT23 |
4494 | ========================================================================== */ |
4495 | |
4496 | #define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) |
4497 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4498 | |
4499 | #if __HVX_ARCH__ >= 68 |
4500 | /* ========================================================================== |
4501 | Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) |
4502 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4503 | Instruction Type: CVI_VX |
4504 | Execution Slots: SLOT23 |
4505 | ========================================================================== */ |
4506 | |
4507 | #define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) |
4508 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4509 | |
4510 | #if __HVX_ARCH__ >= 68 |
4511 | /* ========================================================================== |
4512 | Assembly Syntax: Vd32.w=vfmv(Vu32.w) |
4513 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) |
4514 | Instruction Type: CVI_VX_LATE |
4515 | Execution Slots: SLOT23 |
4516 | ========================================================================== */ |
4517 | |
4518 | #define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) |
4519 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4520 | |
4521 | #if __HVX_ARCH__ >= 68 |
4522 | /* ========================================================================== |
4523 | Assembly Syntax: Vd32.hf=Vu32.qf16 |
4524 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) |
4525 | Instruction Type: CVI_VS |
4526 | Execution Slots: SLOT0123 |
4527 | ========================================================================== */ |
4528 | |
4529 | #define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) |
4530 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4531 | |
4532 | #if __HVX_ARCH__ >= 68 |
4533 | /* ========================================================================== |
4534 | Assembly Syntax: Vd32.hf=Vuu32.qf32 |
4535 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) |
4536 | Instruction Type: CVI_VS |
4537 | Execution Slots: SLOT0123 |
4538 | ========================================================================== */ |
4539 | |
4540 | #define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) |
4541 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4542 | |
4543 | #if __HVX_ARCH__ >= 68 |
4544 | /* ========================================================================== |
4545 | Assembly Syntax: Vd32.sf=Vu32.qf32 |
4546 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) |
4547 | Instruction Type: CVI_VS |
4548 | Execution Slots: SLOT0123 |
4549 | ========================================================================== */ |
4550 | |
4551 | #define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) |
4552 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4553 | |
4554 | #if __HVX_ARCH__ >= 68 |
4555 | /* ========================================================================== |
4556 | Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) |
4557 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4558 | Instruction Type: CVI_VX |
4559 | Execution Slots: SLOT23 |
4560 | ========================================================================== */ |
4561 | |
4562 | #define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) |
4563 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4564 | |
4565 | #if __HVX_ARCH__ >= 68 |
4566 | /* ========================================================================== |
4567 | Assembly Syntax: Vd32.h=vcvt(Vu32.hf) |
4568 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) |
4569 | Instruction Type: CVI_VX |
4570 | Execution Slots: SLOT23 |
4571 | ========================================================================== */ |
4572 | |
4573 | #define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) |
4574 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4575 | |
4576 | #if __HVX_ARCH__ >= 68 |
4577 | /* ========================================================================== |
4578 | Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) |
4579 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) |
4580 | Instruction Type: CVI_VX_DV |
4581 | Execution Slots: SLOT23 |
4582 | ========================================================================== */ |
4583 | |
4584 | #define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) |
4585 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4586 | |
4587 | #if __HVX_ARCH__ >= 68 |
4588 | /* ========================================================================== |
4589 | Assembly Syntax: Vd32.hf=vcvt(Vu32.h) |
4590 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) |
4591 | Instruction Type: CVI_VX |
4592 | Execution Slots: SLOT23 |
4593 | ========================================================================== */ |
4594 | |
4595 | #define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) |
4596 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4597 | |
4598 | #if __HVX_ARCH__ >= 68 |
4599 | /* ========================================================================== |
4600 | Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) |
4601 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4602 | Instruction Type: CVI_VX |
4603 | Execution Slots: SLOT23 |
4604 | ========================================================================== */ |
4605 | |
4606 | #define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) |
4607 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4608 | |
4609 | #if __HVX_ARCH__ >= 68 |
4610 | /* ========================================================================== |
4611 | Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) |
4612 | C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) |
4613 | Instruction Type: CVI_VX_DV |
4614 | Execution Slots: SLOT23 |
4615 | ========================================================================== */ |
4616 | |
4617 | #define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) |
4618 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4619 | |
4620 | #if __HVX_ARCH__ >= 68 |
4621 | /* ========================================================================== |
4622 | Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) |
4623 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) |
4624 | Instruction Type: CVI_VX |
4625 | Execution Slots: SLOT23 |
4626 | ========================================================================== */ |
4627 | |
4628 | #define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) |
4629 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4630 | |
4631 | #if __HVX_ARCH__ >= 68 |
4632 | /* ========================================================================== |
4633 | Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) |
4634 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) |
4635 | Instruction Type: CVI_VX_DV |
4636 | Execution Slots: SLOT23 |
4637 | ========================================================================== */ |
4638 | |
4639 | #define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) |
4640 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4641 | |
4642 | #if __HVX_ARCH__ >= 68 |
4643 | /* ========================================================================== |
4644 | Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) |
4645 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4646 | Instruction Type: CVI_VX |
4647 | Execution Slots: SLOT23 |
4648 | ========================================================================== */ |
4649 | |
4650 | #define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) |
4651 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4652 | |
4653 | #if __HVX_ARCH__ >= 68 |
4654 | /* ========================================================================== |
4655 | Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) |
4656 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) |
4657 | Instruction Type: CVI_VX |
4658 | Execution Slots: SLOT23 |
4659 | ========================================================================== */ |
4660 | |
4661 | #define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) |
4662 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4663 | |
4664 | #if __HVX_ARCH__ >= 68 |
4665 | /* ========================================================================== |
4666 | Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) |
4667 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4668 | Instruction Type: CVI_VX |
4669 | Execution Slots: SLOT23 |
4670 | ========================================================================== */ |
4671 | |
4672 | #define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) |
4673 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4674 | |
4675 | #if __HVX_ARCH__ >= 68 |
4676 | /* ========================================================================== |
4677 | Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) |
4678 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
4679 | Instruction Type: CVI_VX |
4680 | Execution Slots: SLOT23 |
4681 | ========================================================================== */ |
4682 | |
4683 | #define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) |
4684 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4685 | |
4686 | #if __HVX_ARCH__ >= 68 |
4687 | /* ========================================================================== |
4688 | Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) |
4689 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4690 | Instruction Type: CVI_VX_LATE |
4691 | Execution Slots: SLOT23 |
4692 | ========================================================================== */ |
4693 | |
4694 | #define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) |
4695 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4696 | |
4697 | #if __HVX_ARCH__ >= 68 |
4698 | /* ========================================================================== |
4699 | Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) |
4700 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4701 | Instruction Type: CVI_VX_LATE |
4702 | Execution Slots: SLOT23 |
4703 | ========================================================================== */ |
4704 | |
4705 | #define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) |
4706 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4707 | |
4708 | #if __HVX_ARCH__ >= 68 |
4709 | /* ========================================================================== |
4710 | Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) |
4711 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4712 | Instruction Type: CVI_VX_LATE |
4713 | Execution Slots: SLOT23 |
4714 | ========================================================================== */ |
4715 | |
4716 | #define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) |
4717 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4718 | |
4719 | #if __HVX_ARCH__ >= 68 |
4720 | /* ========================================================================== |
4721 | Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) |
4722 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4723 | Instruction Type: CVI_VX_LATE |
4724 | Execution Slots: SLOT23 |
4725 | ========================================================================== */ |
4726 | |
4727 | #define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) |
4728 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4729 | |
4730 | #if __HVX_ARCH__ >= 68 |
4731 | /* ========================================================================== |
4732 | Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) |
4733 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) |
4734 | Instruction Type: CVI_VX_LATE |
4735 | Execution Slots: SLOT23 |
4736 | ========================================================================== */ |
4737 | |
4738 | #define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) |
4739 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4740 | |
4741 | #if __HVX_ARCH__ >= 68 |
4742 | /* ========================================================================== |
4743 | Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) |
4744 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) |
4745 | Instruction Type: CVI_VX_LATE |
4746 | Execution Slots: SLOT23 |
4747 | ========================================================================== */ |
4748 | |
4749 | #define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) |
4750 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4751 | |
4752 | #if __HVX_ARCH__ >= 68 |
4753 | /* ========================================================================== |
4754 | Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) |
4755 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4756 | Instruction Type: CVI_VA |
4757 | Execution Slots: SLOT0123 |
4758 | ========================================================================== */ |
4759 | |
4760 | #define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) |
4761 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4762 | |
4763 | #if __HVX_ARCH__ >= 68 |
4764 | /* ========================================================================== |
4765 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) |
4766 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4767 | Instruction Type: CVI_VA |
4768 | Execution Slots: SLOT0123 |
4769 | ========================================================================== */ |
4770 | |
4771 | #define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4772 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4773 | |
4774 | #if __HVX_ARCH__ >= 68 |
4775 | /* ========================================================================== |
4776 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) |
4777 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4778 | Instruction Type: CVI_VA |
4779 | Execution Slots: SLOT0123 |
4780 | ========================================================================== */ |
4781 | |
4782 | #define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4783 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4784 | |
4785 | #if __HVX_ARCH__ >= 68 |
4786 | /* ========================================================================== |
4787 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) |
4788 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4789 | Instruction Type: CVI_VA |
4790 | Execution Slots: SLOT0123 |
4791 | ========================================================================== */ |
4792 | |
4793 | #define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4794 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4795 | |
4796 | #if __HVX_ARCH__ >= 68 |
4797 | /* ========================================================================== |
4798 | Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) |
4799 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4800 | Instruction Type: CVI_VA |
4801 | Execution Slots: SLOT0123 |
4802 | ========================================================================== */ |
4803 | |
4804 | #define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) |
4805 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4806 | |
4807 | #if __HVX_ARCH__ >= 68 |
4808 | /* ========================================================================== |
4809 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) |
4810 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4811 | Instruction Type: CVI_VA |
4812 | Execution Slots: SLOT0123 |
4813 | ========================================================================== */ |
4814 | |
4815 | #define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4816 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4817 | |
4818 | #if __HVX_ARCH__ >= 68 |
4819 | /* ========================================================================== |
4820 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) |
4821 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4822 | Instruction Type: CVI_VA |
4823 | Execution Slots: SLOT0123 |
4824 | ========================================================================== */ |
4825 | |
4826 | #define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4827 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4828 | |
4829 | #if __HVX_ARCH__ >= 68 |
4830 | /* ========================================================================== |
4831 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) |
4832 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
4833 | Instruction Type: CVI_VA |
4834 | Execution Slots: SLOT0123 |
4835 | ========================================================================== */ |
4836 | |
4837 | #define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) |
4838 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4839 | |
4840 | #if __HVX_ARCH__ >= 68 |
4841 | /* ========================================================================== |
4842 | Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) |
4843 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4844 | Instruction Type: CVI_VA |
4845 | Execution Slots: SLOT0123 |
4846 | ========================================================================== */ |
4847 | |
4848 | #define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) |
4849 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4850 | |
4851 | #if __HVX_ARCH__ >= 68 |
4852 | /* ========================================================================== |
4853 | Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) |
4854 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4855 | Instruction Type: CVI_VA |
4856 | Execution Slots: SLOT0123 |
4857 | ========================================================================== */ |
4858 | |
4859 | #define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) |
4860 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4861 | |
4862 | #if __HVX_ARCH__ >= 68 |
4863 | /* ========================================================================== |
4864 | Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) |
4865 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4866 | Instruction Type: CVI_VA |
4867 | Execution Slots: SLOT0123 |
4868 | ========================================================================== */ |
4869 | |
4870 | #define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) |
4871 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4872 | |
4873 | #if __HVX_ARCH__ >= 68 |
4874 | /* ========================================================================== |
4875 | Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) |
4876 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4877 | Instruction Type: CVI_VA |
4878 | Execution Slots: SLOT0123 |
4879 | ========================================================================== */ |
4880 | |
4881 | #define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) |
4882 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4883 | |
4884 | #if __HVX_ARCH__ >= 68 |
4885 | /* ========================================================================== |
4886 | Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) |
4887 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4888 | Instruction Type: CVI_VX |
4889 | Execution Slots: SLOT23 |
4890 | ========================================================================== */ |
4891 | |
4892 | #define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) |
4893 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4894 | |
4895 | #if __HVX_ARCH__ >= 68 |
4896 | /* ========================================================================== |
4897 | Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) |
4898 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
4899 | Instruction Type: CVI_VX |
4900 | Execution Slots: SLOT23 |
4901 | ========================================================================== */ |
4902 | |
4903 | #define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) |
4904 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4905 | |
4906 | #if __HVX_ARCH__ >= 68 |
4907 | /* ========================================================================== |
4908 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) |
4909 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
4910 | Instruction Type: CVI_VX_DV |
4911 | Execution Slots: SLOT23 |
4912 | ========================================================================== */ |
4913 | |
4914 | #define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) |
4915 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4916 | |
4917 | #if __HVX_ARCH__ >= 68 |
4918 | /* ========================================================================== |
4919 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) |
4920 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4921 | Instruction Type: CVI_VX_DV |
4922 | Execution Slots: SLOT23 |
4923 | ========================================================================== */ |
4924 | |
4925 | #define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) |
4926 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4927 | |
4928 | #if __HVX_ARCH__ >= 68 |
4929 | /* ========================================================================== |
4930 | Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) |
4931 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
4932 | Instruction Type: CVI_VX_DV |
4933 | Execution Slots: SLOT23 |
4934 | ========================================================================== */ |
4935 | |
4936 | #define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) |
4937 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4938 | |
4939 | #if __HVX_ARCH__ >= 68 |
4940 | /* ========================================================================== |
4941 | Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) |
4942 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
4943 | Instruction Type: CVI_VX_DV |
4944 | Execution Slots: SLOT23 |
4945 | ========================================================================== */ |
4946 | |
4947 | #define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) |
4948 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4949 | |
4950 | #if __HVX_ARCH__ >= 68 |
4951 | /* ========================================================================== |
4952 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) |
4953 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4954 | Instruction Type: CVI_VX_DV |
4955 | Execution Slots: SLOT23 |
4956 | ========================================================================== */ |
4957 | |
4958 | #define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) |
4959 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4960 | |
4961 | #if __HVX_ARCH__ >= 68 |
4962 | /* ========================================================================== |
4963 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) |
4964 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
4965 | Instruction Type: CVI_VX_DV |
4966 | Execution Slots: SLOT23 |
4967 | ========================================================================== */ |
4968 | |
4969 | #define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) |
4970 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4971 | |
4972 | #if __HVX_ARCH__ >= 68 |
4973 | /* ========================================================================== |
4974 | Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) |
4975 | C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
4976 | Instruction Type: CVI_VX_DV |
4977 | Execution Slots: SLOT23 |
4978 | ========================================================================== */ |
4979 | |
4980 | #define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) |
4981 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4982 | |
4983 | #if __HVX_ARCH__ >= 68 |
4984 | /* ========================================================================== |
4985 | Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) |
4986 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
4987 | Instruction Type: CVI_VX_DV |
4988 | Execution Slots: SLOT23 |
4989 | ========================================================================== */ |
4990 | |
4991 | #define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) |
4992 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
4993 | |
4994 | #if __HVX_ARCH__ >= 68 |
4995 | /* ========================================================================== |
4996 | Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) |
4997 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
4998 | Instruction Type: CVI_VX_DV |
4999 | Execution Slots: SLOT23 |
5000 | ========================================================================== */ |
5001 | |
5002 | #define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) |
5003 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5004 | |
5005 | #if __HVX_ARCH__ >= 68 |
5006 | /* ========================================================================== |
5007 | Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) |
5008 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
5009 | Instruction Type: CVI_VX_DV |
5010 | Execution Slots: SLOT23 |
5011 | ========================================================================== */ |
5012 | |
5013 | #define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) |
5014 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5015 | |
5016 | #if __HVX_ARCH__ >= 68 |
5017 | /* ========================================================================== |
5018 | Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) |
5019 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
5020 | Instruction Type: CVI_VX_DV |
5021 | Execution Slots: SLOT23 |
5022 | ========================================================================== */ |
5023 | |
5024 | #define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) |
5025 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5026 | |
5027 | #if __HVX_ARCH__ >= 68 |
5028 | /* ========================================================================== |
5029 | Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) |
5030 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
5031 | Instruction Type: CVI_VS |
5032 | Execution Slots: SLOT0123 |
5033 | ========================================================================== */ |
5034 | |
5035 | #define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) |
5036 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5037 | |
5038 | #if __HVX_ARCH__ >= 68 |
5039 | /* ========================================================================== |
5040 | Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) |
5041 | C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
5042 | Instruction Type: CVI_VX |
5043 | Execution Slots: SLOT23 |
5044 | ========================================================================== */ |
5045 | |
5046 | #define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) |
5047 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5048 | |
5049 | #if __HVX_ARCH__ >= 68 |
5050 | /* ========================================================================== |
5051 | Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) |
5052 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) |
5053 | Instruction Type: CVI_VS |
5054 | Execution Slots: SLOT0123 |
5055 | ========================================================================== */ |
5056 | |
5057 | #define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) |
5058 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5059 | |
5060 | #if __HVX_ARCH__ >= 68 |
5061 | /* ========================================================================== |
5062 | Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) |
5063 | C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) |
5064 | Instruction Type: CVI_VS |
5065 | Execution Slots: SLOT0123 |
5066 | ========================================================================== */ |
5067 | |
5068 | #define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) |
5069 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5070 | |
5071 | #if __HVX_ARCH__ >= 68 |
5072 | /* ========================================================================== |
5073 | Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) |
5074 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) |
5075 | Instruction Type: CVI_VS |
5076 | Execution Slots: SLOT0123 |
5077 | ========================================================================== */ |
5078 | |
5079 | #define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) |
5080 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5081 | |
5082 | #if __HVX_ARCH__ >= 68 |
5083 | /* ========================================================================== |
5084 | Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) |
5085 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) |
5086 | Instruction Type: CVI_VS |
5087 | Execution Slots: SLOT0123 |
5088 | ========================================================================== */ |
5089 | |
5090 | #define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) |
5091 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5092 | |
5093 | #if __HVX_ARCH__ >= 68 |
5094 | /* ========================================================================== |
5095 | Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) |
5096 | C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
5097 | Instruction Type: CVI_VS |
5098 | Execution Slots: SLOT0123 |
5099 | ========================================================================== */ |
5100 | |
5101 | #define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) |
5102 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5103 | |
5104 | #if __HVX_ARCH__ >= 68 |
5105 | /* ========================================================================== |
5106 | Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) |
5107 | C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) |
5108 | Instruction Type: CVI_VX_DV |
5109 | Execution Slots: SLOT23 |
5110 | ========================================================================== */ |
5111 | |
5112 | #define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) |
5113 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5114 | |
5115 | #if __HVX_ARCH__ >= 68 |
5116 | /* ========================================================================== |
5117 | Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) |
5118 | C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) |
5119 | Instruction Type: CVI_VX |
5120 | Execution Slots: SLOT23 |
5121 | ========================================================================== */ |
5122 | |
5123 | #define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) |
5124 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
5125 | |
5126 | #if __HVX_ARCH__ >= 69 |
5127 | /* ========================================================================== |
5128 | Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat |
5129 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
5130 | Instruction Type: CVI_VS |
5131 | Execution Slots: SLOT0123 |
5132 | ========================================================================== */ |
5133 | |
5134 | #define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) |
5135 | #endif /* __HEXAGON_ARCH___ >= 69 */ |
5136 | |
5137 | #if __HVX_ARCH__ >= 69 |
5138 | /* ========================================================================== |
5139 | Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat |
5140 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
5141 | Instruction Type: CVI_VS |
5142 | Execution Slots: SLOT0123 |
5143 | ========================================================================== */ |
5144 | |
5145 | #define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) |
5146 | #endif /* __HEXAGON_ARCH___ >= 69 */ |
5147 | |
5148 | #if __HVX_ARCH__ >= 69 |
5149 | /* ========================================================================== |
5150 | Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat |
5151 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
5152 | Instruction Type: CVI_VS |
5153 | Execution Slots: SLOT0123 |
5154 | ========================================================================== */ |
5155 | |
5156 | #define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) |
5157 | #endif /* __HEXAGON_ARCH___ >= 69 */ |
5158 | |
5159 | #if __HVX_ARCH__ >= 69 |
5160 | /* ========================================================================== |
5161 | Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat |
5162 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) |
5163 | Instruction Type: CVI_VS |
5164 | Execution Slots: SLOT0123 |
5165 | ========================================================================== */ |
5166 | |
5167 | #define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) |
5168 | #endif /* __HEXAGON_ARCH___ >= 69 */ |
5169 | |
5170 | #if __HVX_ARCH__ >= 69 |
5171 | /* ========================================================================== |
5172 | Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 |
5173 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) |
5174 | Instruction Type: CVI_VX |
5175 | Execution Slots: SLOT23 |
5176 | ========================================================================== */ |
5177 | |
5178 | #define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) |
5179 | #endif /* __HEXAGON_ARCH___ >= 69 */ |
5180 | |
5181 | #endif /* __HVX__ */ |
5182 | |
5183 | #endif |
5184 |
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