1 | //===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | /// \file |
9 | /// |
10 | /// InOrderIssueStage implements an in-order execution pipeline. |
11 | /// |
12 | //===----------------------------------------------------------------------===// |
13 | |
14 | #ifndef LLVM_MCA_STAGES_INORDERISSUESTAGE_H |
15 | #define LLVM_MCA_STAGES_INORDERISSUESTAGE_H |
16 | |
17 | #include "llvm/MCA/CustomBehaviour.h" |
18 | #include "llvm/MCA/HardwareUnits/ResourceManager.h" |
19 | #include "llvm/MCA/SourceMgr.h" |
20 | #include "llvm/MCA/Stages/Stage.h" |
21 | |
22 | namespace llvm { |
23 | namespace mca { |
24 | class LSUnit; |
25 | class RegisterFile; |
26 | |
27 | struct StallInfo { |
28 | enum class StallKind { |
29 | DEFAULT, |
30 | REGISTER_DEPS, |
31 | DISPATCH, |
32 | DELAY, |
33 | LOAD_STORE, |
34 | CUSTOM_STALL |
35 | }; |
36 | |
37 | InstRef IR; |
38 | unsigned CyclesLeft = 0; |
39 | StallKind Kind = StallKind::DEFAULT; |
40 | |
41 | StallInfo() = default; |
42 | |
43 | StallKind getStallKind() const { return Kind; } |
44 | unsigned getCyclesLeft() const { return CyclesLeft; } |
45 | const InstRef &getInstruction() const { return IR; } |
46 | InstRef &getInstruction() { return IR; } |
47 | |
48 | bool isValid() const { return (bool)IR; } |
49 | void clear(); |
50 | void update(const InstRef &Inst, unsigned Cycles, StallKind SK); |
51 | void cycleEnd(); |
52 | }; |
53 | |
54 | class InOrderIssueStage final : public Stage { |
55 | const MCSubtargetInfo &STI; |
56 | RegisterFile &PRF; |
57 | ResourceManager RM; |
58 | CustomBehaviour &CB; |
59 | LSUnit &LSU; |
60 | |
61 | /// Instructions that were issued, but not executed yet. |
62 | SmallVector<InstRef, 4> IssuedInst; |
63 | |
64 | /// Number of instructions issued in the current cycle. |
65 | unsigned NumIssued; |
66 | |
67 | StallInfo SI; |
68 | |
69 | /// Instruction that is issued in more than 1 cycle. |
70 | InstRef CarriedOver; |
71 | /// Number of CarriedOver uops left to issue. |
72 | unsigned CarryOver; |
73 | |
74 | /// Number of instructions that can be issued in the current cycle. |
75 | unsigned Bandwidth; |
76 | |
77 | /// Number of cycles (counted from the current cycle) until the last write is |
78 | /// committed. This is taken into account to ensure that writes commit in the |
79 | /// program order. |
80 | unsigned LastWriteBackCycle; |
81 | |
82 | InOrderIssueStage(const InOrderIssueStage &Other) = delete; |
83 | InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete; |
84 | |
85 | /// Returns true if IR can execute during this cycle. |
86 | /// In case of stall, it updates SI with information about the stalled |
87 | /// instruction and the stall reason. |
88 | bool canExecute(const InstRef &IR); |
89 | |
90 | /// Issue the instruction, or update the StallInfo. |
91 | Error tryIssue(InstRef &IR); |
92 | |
93 | /// Update status of instructions from IssuedInst. |
94 | void updateIssuedInst(); |
95 | |
96 | /// Continue to issue the CarriedOver instruction. |
97 | void updateCarriedOver(); |
98 | |
99 | /// Notifies a stall event to the Stage listener. Stall information is |
100 | /// obtained from the internal StallInfo field. |
101 | void notifyStallEvent(); |
102 | |
103 | void notifyInstructionIssued(const InstRef &IR, |
104 | ArrayRef<ResourceUse> UsedRes); |
105 | void notifyInstructionDispatched(const InstRef &IR, unsigned Ops, |
106 | ArrayRef<unsigned> UsedRegs); |
107 | void notifyInstructionExecuted(const InstRef &IR); |
108 | void notifyInstructionRetired(const InstRef &IR, |
109 | ArrayRef<unsigned> FreedRegs); |
110 | |
111 | /// Retire instruction once it is executed. |
112 | void retireInstruction(InstRef &IR); |
113 | |
114 | public: |
115 | InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF, |
116 | CustomBehaviour &CB, LSUnit &LSU); |
117 | |
118 | unsigned getIssueWidth() const; |
119 | bool isAvailable(const InstRef &) const override; |
120 | bool hasWorkToComplete() const override; |
121 | Error execute(InstRef &IR) override; |
122 | Error cycleStart() override; |
123 | Error cycleEnd() override; |
124 | }; |
125 | |
126 | } // namespace mca |
127 | } // namespace llvm |
128 | |
129 | #endif // LLVM_MCA_STAGES_INORDERISSUESTAGE_H |
130 | |