1//===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format MIPS assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAsmPrinter.h"
15#include "MCTargetDesc/MipsABIInfo.h"
16#include "MCTargetDesc/MipsBaseInfo.h"
17#include "MCTargetDesc/MipsInstPrinter.h"
18#include "MCTargetDesc/MipsMCNaCl.h"
19#include "MCTargetDesc/MipsMCTargetDesc.h"
20#include "Mips.h"
21#include "MipsMCInstLower.h"
22#include "MipsMachineFunction.h"
23#include "MipsSubtarget.h"
24#include "MipsTargetMachine.h"
25#include "MipsTargetStreamer.h"
26#include "TargetInfo/MipsTargetInfo.h"
27#include "llvm/ADT/SmallString.h"
28#include "llvm/ADT/StringRef.h"
29#include "llvm/ADT/Twine.h"
30#include "llvm/BinaryFormat/ELF.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineConstantPool.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineJumpTableInfo.h"
37#include "llvm/CodeGen/MachineOperand.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/BasicBlock.h"
42#include "llvm/IR/DataLayout.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/InlineAsm.h"
45#include "llvm/IR/Instructions.h"
46#include "llvm/MC/MCContext.h"
47#include "llvm/MC/MCExpr.h"
48#include "llvm/MC/MCInst.h"
49#include "llvm/MC/MCInstBuilder.h"
50#include "llvm/MC/MCObjectFileInfo.h"
51#include "llvm/MC/MCSectionELF.h"
52#include "llvm/MC/MCSymbol.h"
53#include "llvm/MC/MCSymbolELF.h"
54#include "llvm/MC/TargetRegistry.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/ErrorHandling.h"
57#include "llvm/Support/raw_ostream.h"
58#include "llvm/Target/TargetLoweringObjectFile.h"
59#include "llvm/Target/TargetMachine.h"
60#include "llvm/TargetParser/Triple.h"
61#include <cassert>
62#include <cstdint>
63#include <map>
64#include <memory>
65#include <string>
66#include <vector>
67
68using namespace llvm;
69
70#define DEBUG_TYPE "mips-asm-printer"
71
72extern cl::opt<bool> EmitJalrReloc;
73
74MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
75 return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
76}
77
78bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
79 Subtarget = &MF.getSubtarget<MipsSubtarget>();
80
81 MipsFI = MF.getInfo<MipsFunctionInfo>();
82 if (Subtarget->inMips16Mode())
83 for (const auto &I : MipsFI->StubsNeeded) {
84 const char *Symbol = I.first;
85 const Mips16HardFloatInfo::FuncSignature *Signature = I.second;
86 if (StubsNeeded.find(x: Symbol) == StubsNeeded.end())
87 StubsNeeded[Symbol] = Signature;
88 }
89 MCP = MF.getConstantPool();
90
91 // In NaCl, all indirect jump targets must be aligned to bundle size.
92 if (Subtarget->isTargetNaCl())
93 NaClAlignIndirectJumpTargets(MF);
94
95 AsmPrinter::runOnMachineFunction(MF);
96
97 emitXRayTable();
98
99 return true;
100}
101
102bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
103 MCOp = MCInstLowering.LowerOperand(MO);
104 return MCOp.isValid();
105}
106
107#include "MipsGenMCPseudoLowering.inc"
108
109// Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
110// JALR, or JALR64 as appropriate for the target.
111void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
112 const MachineInstr *MI) {
113 bool HasLinkReg = false;
114 bool InMicroMipsMode = Subtarget->inMicroMipsMode();
115 MCInst TmpInst0;
116
117 if (Subtarget->hasMips64r6()) {
118 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
119 TmpInst0.setOpcode(Mips::JALR64);
120 HasLinkReg = true;
121 } else if (Subtarget->hasMips32r6()) {
122 // MIPS32r6 should use (JALR ZERO, $rs)
123 if (InMicroMipsMode)
124 TmpInst0.setOpcode(Mips::JRC16_MMR6);
125 else {
126 TmpInst0.setOpcode(Mips::JALR);
127 HasLinkReg = true;
128 }
129 } else if (Subtarget->inMicroMipsMode())
130 // microMIPS should use (JR_MM $rs)
131 TmpInst0.setOpcode(Mips::JR_MM);
132 else {
133 // Everything else should use (JR $rs)
134 TmpInst0.setOpcode(Mips::JR);
135 }
136
137 MCOperand MCOp;
138
139 if (HasLinkReg) {
140 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
141 TmpInst0.addOperand(Op: MCOperand::createReg(Reg: ZeroReg));
142 }
143
144 lowerOperand(MO: MI->getOperand(i: 0), MCOp);
145 TmpInst0.addOperand(Op: MCOp);
146
147 EmitToStreamer(S&: OutStreamer, Inst: TmpInst0);
148}
149
150// If there is an MO_JALR operand, insert:
151//
152// .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
153// tmplabel:
154//
155// This is an optimization hint for the linker which may then replace
156// an indirect call with a direct branch.
157static void emitDirectiveRelocJalr(const MachineInstr &MI,
158 MCContext &OutContext,
159 TargetMachine &TM,
160 MCStreamer &OutStreamer,
161 const MipsSubtarget &Subtarget) {
162 for (const MachineOperand &MO :
163 llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands())) {
164 if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)) {
165 MCSymbol *Callee = MO.getMCSymbol();
166 if (Callee && !Callee->getName().empty()) {
167 MCSymbol *OffsetLabel = OutContext.createTempSymbol();
168 const MCExpr *OffsetExpr =
169 MCSymbolRefExpr::create(Symbol: OffsetLabel, Ctx&: OutContext);
170 const MCExpr *CaleeExpr =
171 MCSymbolRefExpr::create(Symbol: Callee, Ctx&: OutContext);
172 OutStreamer.emitRelocDirective(
173 Offset: *OffsetExpr,
174 Name: Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
175 Expr: CaleeExpr, Loc: SMLoc(), STI: *TM.getMCSubtargetInfo());
176 OutStreamer.emitLabel(Symbol: OffsetLabel);
177 return;
178 }
179 }
180 }
181}
182
183void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) {
184 // FIXME: Enable feature predicate checks once all the test pass.
185 // Mips_MC::verifyInstructionPredicates(MI->getOpcode(),
186 // getSubtargetInfo().getFeatureBits());
187
188 MipsTargetStreamer &TS = getTargetStreamer();
189 unsigned Opc = MI->getOpcode();
190 TS.forbidModuleDirective();
191
192 if (MI->isDebugValue()) {
193 SmallString<128> Str;
194 raw_svector_ostream OS(Str);
195
196 PrintDebugValueComment(MI, OS);
197 return;
198 }
199 if (MI->isDebugLabel())
200 return;
201
202 // If we just ended a constant pool, mark it as such.
203 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
204 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
205 InConstantPool = false;
206 }
207 if (Opc == Mips::CONSTPOOL_ENTRY) {
208 // CONSTPOOL_ENTRY - This instruction represents a floating
209 // constant pool in the function. The first operand is the ID#
210 // for this instruction, the second is the index into the
211 // MachineConstantPool that this is, the third is the size in
212 // bytes of this constant pool entry.
213 // The required alignment is specified on the basic block holding this MI.
214 //
215 unsigned LabelId = (unsigned)MI->getOperand(i: 0).getImm();
216 unsigned CPIdx = (unsigned)MI->getOperand(i: 1).getIndex();
217
218 // If this is the first entry of the pool, mark it.
219 if (!InConstantPool) {
220 OutStreamer->emitDataRegion(Kind: MCDR_DataRegion);
221 InConstantPool = true;
222 }
223
224 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: LabelId));
225
226 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
227 if (MCPE.isMachineConstantPoolEntry())
228 emitMachineConstantPoolValue(MCPV: MCPE.Val.MachineCPVal);
229 else
230 emitGlobalConstant(DL: MF->getDataLayout(), CV: MCPE.Val.ConstVal);
231 return;
232 }
233
234 switch (Opc) {
235 case Mips::PATCHABLE_FUNCTION_ENTER:
236 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI);
237 return;
238 case Mips::PATCHABLE_FUNCTION_EXIT:
239 LowerPATCHABLE_FUNCTION_EXIT(MI: *MI);
240 return;
241 case Mips::PATCHABLE_TAIL_CALL:
242 LowerPATCHABLE_TAIL_CALL(MI: *MI);
243 return;
244 }
245
246 if (EmitJalrReloc &&
247 (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) {
248 emitDirectiveRelocJalr(MI: *MI, OutContext, TM, OutStreamer&: *OutStreamer, Subtarget: *Subtarget);
249 }
250
251 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
252 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
253
254 do {
255 // Do any auto-generated pseudo lowerings.
256 if (emitPseudoExpansionLowering(OutStreamer&: *OutStreamer, MI: &*I))
257 continue;
258
259 // Skip the BUNDLE pseudo instruction and lower the contents
260 if (I->isBundle())
261 continue;
262
263 if (I->getOpcode() == Mips::PseudoReturn ||
264 I->getOpcode() == Mips::PseudoReturn64 ||
265 I->getOpcode() == Mips::PseudoIndirectBranch ||
266 I->getOpcode() == Mips::PseudoIndirectBranch64 ||
267 I->getOpcode() == Mips::TAILCALLREG ||
268 I->getOpcode() == Mips::TAILCALLREG64) {
269 emitPseudoIndirectBranch(OutStreamer&: *OutStreamer, MI: &*I);
270 continue;
271 }
272
273 // The inMips16Mode() test is not permanent.
274 // Some instructions are marked as pseudo right now which
275 // would make the test fail for the wrong reason but
276 // that will be fixed soon. We need this here because we are
277 // removing another test for this situation downstream in the
278 // callchain.
279 //
280 if (I->isPseudo() && !Subtarget->inMips16Mode()
281 && !isLongBranchPseudo(Opcode: I->getOpcode()))
282 llvm_unreachable("Pseudo opcode found in emitInstruction()");
283
284 MCInst TmpInst0;
285 MCInstLowering.Lower(MI: &*I, OutMI&: TmpInst0);
286 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst0);
287 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
288}
289
290//===----------------------------------------------------------------------===//
291//
292// Mips Asm Directives
293//
294// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
295// Describe the stack frame.
296//
297// -- Mask directives "(f)mask bitmask, offset"
298// Tells the assembler which registers are saved and where.
299// bitmask - contain a little endian bitset indicating which registers are
300// saved on function prologue (e.g. with a 0x80000000 mask, the
301// assembler knows the register 31 (RA) is saved at prologue.
302// offset - the position before stack pointer subtraction indicating where
303// the first saved register on prologue is located. (e.g. with a
304//
305// Consider the following function prologue:
306//
307// .frame $fp,48,$ra
308// .mask 0xc0000000,-8
309// addiu $sp, $sp, -48
310// sw $ra, 40($sp)
311// sw $fp, 36($sp)
312//
313// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
314// 30 (FP) are saved at prologue. As the save order on prologue is from
315// left to right, RA is saved first. A -8 offset means that after the
316// stack pointer subtration, the first register in the mask (RA) will be
317// saved at address 48-8=40.
318//
319//===----------------------------------------------------------------------===//
320
321//===----------------------------------------------------------------------===//
322// Mask directives
323//===----------------------------------------------------------------------===//
324
325// Create a bitmask with all callee saved registers for CPU or Floating Point
326// registers. For CPU registers consider RA, GP and FP for saving if necessary.
327void MipsAsmPrinter::printSavedRegsBitmask() {
328 // CPU and FPU Saved Registers Bitmasks
329 unsigned CPUBitmask = 0, FPUBitmask = 0;
330 int CPUTopSavedRegOff, FPUTopSavedRegOff;
331
332 // Set the CPU and FPU Bitmasks
333 const MachineFrameInfo &MFI = MF->getFrameInfo();
334 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
335 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
336 // size of stack area to which FP callee-saved regs are saved.
337 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
338 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
339 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
340 bool HasAFGR64Reg = false;
341 unsigned CSFPRegsSize = 0;
342
343 for (const auto &I : CSI) {
344 Register Reg = I.getReg();
345 unsigned RegNum = TRI->getEncodingValue(RegNo: Reg);
346
347 // If it's a floating point register, set the FPU Bitmask.
348 // If it's a general purpose register, set the CPU Bitmask.
349 if (Mips::FGR32RegClass.contains(Reg)) {
350 FPUBitmask |= (1 << RegNum);
351 CSFPRegsSize += FGR32RegSize;
352 } else if (Mips::AFGR64RegClass.contains(Reg)) {
353 FPUBitmask |= (3 << RegNum);
354 CSFPRegsSize += AFGR64RegSize;
355 HasAFGR64Reg = true;
356 } else if (Mips::GPR32RegClass.contains(Reg))
357 CPUBitmask |= (1 << RegNum);
358 }
359
360 // FP Regs are saved right below where the virtual frame pointer points to.
361 FPUTopSavedRegOff = FPUBitmask ?
362 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
363
364 // CPU Regs are saved below FP Regs.
365 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
366
367 MipsTargetStreamer &TS = getTargetStreamer();
368 // Print CPUBitmask
369 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
370
371 // Print FPUBitmask
372 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
373}
374
375//===----------------------------------------------------------------------===//
376// Frame and Set directives
377//===----------------------------------------------------------------------===//
378
379/// Frame Directive
380void MipsAsmPrinter::emitFrameDirective() {
381 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
382
383 Register stackReg = RI.getFrameRegister(MF: *MF);
384 unsigned returnReg = RI.getRARegister();
385 unsigned stackSize = MF->getFrameInfo().getStackSize();
386
387 getTargetStreamer().emitFrame(StackReg: stackReg, StackSize: stackSize, ReturnReg: returnReg);
388}
389
390/// Emit Set directives.
391const char *MipsAsmPrinter::getCurrentABIString() const {
392 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
393 case MipsABIInfo::ABI::O32: return "abi32";
394 case MipsABIInfo::ABI::N32: return "abiN32";
395 case MipsABIInfo::ABI::N64: return "abi64";
396 default: llvm_unreachable("Unknown Mips ABI");
397 }
398}
399
400void MipsAsmPrinter::emitFunctionEntryLabel() {
401 MipsTargetStreamer &TS = getTargetStreamer();
402
403 // NaCl sandboxing requires that indirect call instructions are masked.
404 // This means that function entry points should be bundle-aligned.
405 if (Subtarget->isTargetNaCl())
406 emitAlignment(Alignment: std::max(a: MF->getAlignment(), b: MIPS_NACL_BUNDLE_ALIGN));
407
408 if (Subtarget->inMicroMipsMode()) {
409 TS.emitDirectiveSetMicroMips();
410 TS.setUsesMicroMips();
411 TS.updateABIInfo(P: *Subtarget);
412 } else
413 TS.emitDirectiveSetNoMicroMips();
414
415 if (Subtarget->inMips16Mode())
416 TS.emitDirectiveSetMips16();
417 else
418 TS.emitDirectiveSetNoMips16();
419
420 TS.emitDirectiveEnt(Symbol: *CurrentFnSym);
421 OutStreamer->emitLabel(Symbol: CurrentFnSym);
422}
423
424/// EmitFunctionBodyStart - Targets can override this to emit stuff before
425/// the first basic block in the function.
426void MipsAsmPrinter::emitFunctionBodyStart() {
427 MipsTargetStreamer &TS = getTargetStreamer();
428
429 MCInstLowering.Initialize(C: &MF->getContext());
430
431 bool IsNakedFunction = MF->getFunction().hasFnAttribute(Attribute::Naked);
432 if (!IsNakedFunction)
433 emitFrameDirective();
434
435 if (!IsNakedFunction)
436 printSavedRegsBitmask();
437
438 if (!Subtarget->inMips16Mode()) {
439 TS.emitDirectiveSetNoReorder();
440 TS.emitDirectiveSetNoMacro();
441 TS.emitDirectiveSetNoAt();
442 }
443}
444
445/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
446/// the last basic block in the function.
447void MipsAsmPrinter::emitFunctionBodyEnd() {
448 MipsTargetStreamer &TS = getTargetStreamer();
449
450 // There are instruction for this macros, but they must
451 // always be at the function end, and we can't emit and
452 // break with BB logic.
453 if (!Subtarget->inMips16Mode()) {
454 TS.emitDirectiveSetAt();
455 TS.emitDirectiveSetMacro();
456 TS.emitDirectiveSetReorder();
457 }
458 TS.emitDirectiveEnd(Name: CurrentFnSym->getName());
459 // Make sure to terminate any constant pools that were at the end
460 // of the function.
461 if (!InConstantPool)
462 return;
463 InConstantPool = false;
464 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
465}
466
467void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) {
468 AsmPrinter::emitBasicBlockEnd(MBB);
469 MipsTargetStreamer &TS = getTargetStreamer();
470 if (MBB.empty())
471 TS.emitDirectiveInsn();
472}
473
474// Print out an operand for an inline asm expression.
475bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
476 const char *ExtraCode, raw_ostream &O) {
477 // Does this asm operand have a single letter operand modifier?
478 if (ExtraCode && ExtraCode[0]) {
479 if (ExtraCode[1] != 0) return true; // Unknown modifier.
480
481 const MachineOperand &MO = MI->getOperand(i: OpNum);
482 switch (ExtraCode[0]) {
483 default:
484 // See if this is a generic print operand
485 return AsmPrinter::PrintAsmOperand(MI, OpNo: OpNum, ExtraCode, OS&: O);
486 case 'X': // hex const int
487 if (!MO.isImm())
488 return true;
489 O << "0x" << Twine::utohexstr(Val: MO.getImm());
490 return false;
491 case 'x': // hex const int (low 16 bits)
492 if (!MO.isImm())
493 return true;
494 O << "0x" << Twine::utohexstr(Val: MO.getImm() & 0xffff);
495 return false;
496 case 'd': // decimal const int
497 if (!MO.isImm())
498 return true;
499 O << MO.getImm();
500 return false;
501 case 'm': // decimal const int minus 1
502 if (!MO.isImm())
503 return true;
504 O << MO.getImm() - 1;
505 return false;
506 case 'y': // exact log2
507 if (!MO.isImm())
508 return true;
509 if (!isPowerOf2_64(Value: MO.getImm()))
510 return true;
511 O << Log2_64(Value: MO.getImm());
512 return false;
513 case 'z':
514 // $0 if zero, regular printing otherwise
515 if (MO.isImm() && MO.getImm() == 0) {
516 O << "$0";
517 return false;
518 }
519 // If not, call printOperand as normal.
520 break;
521 case 'D': // Second part of a double word register operand
522 case 'L': // Low order register of a double word register operand
523 case 'M': // High order register of a double word register operand
524 {
525 if (OpNum == 0)
526 return true;
527 const MachineOperand &FlagsOP = MI->getOperand(i: OpNum - 1);
528 if (!FlagsOP.isImm())
529 return true;
530 const InlineAsm::Flag Flags(FlagsOP.getImm());
531 const unsigned NumVals = Flags.getNumOperandRegisters();
532 // Number of registers represented by this operand. We are looking
533 // for 2 for 32 bit mode and 1 for 64 bit mode.
534 if (NumVals != 2) {
535 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
536 Register Reg = MO.getReg();
537 O << '$' << MipsInstPrinter::getRegisterName(Reg);
538 return false;
539 }
540 return true;
541 }
542
543 unsigned RegOp = OpNum;
544 if (!Subtarget->isGP64bit()){
545 // Endianness reverses which register holds the high or low value
546 // between M and L.
547 switch(ExtraCode[0]) {
548 case 'M':
549 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
550 break;
551 case 'L':
552 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
553 break;
554 case 'D': // Always the second part
555 RegOp = OpNum + 1;
556 }
557 if (RegOp >= MI->getNumOperands())
558 return true;
559 const MachineOperand &MO = MI->getOperand(i: RegOp);
560 if (!MO.isReg())
561 return true;
562 Register Reg = MO.getReg();
563 O << '$' << MipsInstPrinter::getRegisterName(Reg);
564 return false;
565 }
566 break;
567 }
568 case 'w':
569 // Print MSA registers for the 'f' constraint
570 // In LLVM, the 'w' modifier doesn't need to do anything.
571 // We can just call printOperand as normal.
572 break;
573 }
574 }
575
576 printOperand(MI, opNum: OpNum, O);
577 return false;
578}
579
580bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
581 unsigned OpNum,
582 const char *ExtraCode,
583 raw_ostream &O) {
584 assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
585 const MachineOperand &BaseMO = MI->getOperand(i: OpNum);
586 const MachineOperand &OffsetMO = MI->getOperand(i: OpNum + 1);
587 assert(BaseMO.isReg() &&
588 "Unexpected base pointer for inline asm memory operand.");
589 assert(OffsetMO.isImm() &&
590 "Unexpected offset for inline asm memory operand.");
591 int Offset = OffsetMO.getImm();
592
593 // Currently we are expecting either no ExtraCode or 'D','M','L'.
594 if (ExtraCode) {
595 switch (ExtraCode[0]) {
596 case 'D':
597 Offset += 4;
598 break;
599 case 'M':
600 if (Subtarget->isLittle())
601 Offset += 4;
602 break;
603 case 'L':
604 if (!Subtarget->isLittle())
605 Offset += 4;
606 break;
607 default:
608 return true; // Unknown modifier.
609 }
610 }
611
612 O << Offset << "($" << MipsInstPrinter::getRegisterName(Reg: BaseMO.getReg())
613 << ")";
614
615 return false;
616}
617
618void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
619 raw_ostream &O) {
620 const MachineOperand &MO = MI->getOperand(i: opNum);
621 bool closeP = false;
622
623 if (MO.getTargetFlags())
624 closeP = true;
625
626 switch(MO.getTargetFlags()) {
627 case MipsII::MO_GPREL: O << "%gp_rel("; break;
628 case MipsII::MO_GOT_CALL: O << "%call16("; break;
629 case MipsII::MO_GOT: O << "%got("; break;
630 case MipsII::MO_ABS_HI: O << "%hi("; break;
631 case MipsII::MO_ABS_LO: O << "%lo("; break;
632 case MipsII::MO_HIGHER: O << "%higher("; break;
633 case MipsII::MO_HIGHEST: O << "%highest(("; break;
634 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
635 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
636 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
637 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
638 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
639 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
640 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
641 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
642 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
643 }
644
645 switch (MO.getType()) {
646 case MachineOperand::MO_Register:
647 O << '$'
648 << StringRef(MipsInstPrinter::getRegisterName(Reg: MO.getReg())).lower();
649 break;
650
651 case MachineOperand::MO_Immediate:
652 O << MO.getImm();
653 break;
654
655 case MachineOperand::MO_MachineBasicBlock:
656 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
657 return;
658
659 case MachineOperand::MO_GlobalAddress:
660 PrintSymbolOperand(MO, OS&: O);
661 break;
662
663 case MachineOperand::MO_BlockAddress: {
664 MCSymbol *BA = GetBlockAddressSymbol(BA: MO.getBlockAddress());
665 O << BA->getName();
666 break;
667 }
668
669 case MachineOperand::MO_ConstantPoolIndex:
670 O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
671 << getFunctionNumber() << "_" << MO.getIndex();
672 if (MO.getOffset())
673 O << "+" << MO.getOffset();
674 break;
675
676 default:
677 llvm_unreachable("<unknown operand type>");
678 }
679
680 if (closeP) O << ")";
681}
682
683void MipsAsmPrinter::
684printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
685 // Load/Store memory operands -- imm($reg)
686 // If PIC target the target is loaded as the
687 // pattern lw $25,%call16($28)
688
689 // opNum can be invalid if instruction has reglist as operand.
690 // MemOperand is always last operand of instruction (base + offset).
691 switch (MI->getOpcode()) {
692 default:
693 break;
694 case Mips::SWM32_MM:
695 case Mips::LWM32_MM:
696 opNum = MI->getNumOperands() - 2;
697 break;
698 }
699
700 printOperand(MI, opNum: opNum+1, O);
701 O << "(";
702 printOperand(MI, opNum, O);
703 O << ")";
704}
705
706void MipsAsmPrinter::
707printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
708 // when using stack locations for not load/store instructions
709 // print the same way as all normal 3 operand instructions.
710 printOperand(MI, opNum, O);
711 O << ", ";
712 printOperand(MI, opNum: opNum+1, O);
713}
714
715void MipsAsmPrinter::
716printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
717 const char *Modifier) {
718 const MachineOperand &MO = MI->getOperand(i: opNum);
719 O << Mips::MipsFCCToString(CC: (Mips::CondCode)MO.getImm());
720}
721
722void MipsAsmPrinter::
723printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
724 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
725 if (i != opNum) O << ", ";
726 printOperand(MI, opNum: i, O);
727 }
728}
729
730void MipsAsmPrinter::emitStartOfAsmFile(Module &M) {
731 MipsTargetStreamer &TS = getTargetStreamer();
732
733 // MipsTargetStreamer has an initialization order problem when emitting an
734 // object file directly (see MipsTargetELFStreamer for full details). Work
735 // around it by re-initializing the PIC state here.
736 TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
737
738 // Try to get target-features from the first function.
739 StringRef FS = TM.getTargetFeatureString();
740 Module::iterator F = M.begin();
741 if (FS.empty() && M.size() && F->hasFnAttribute(Kind: "target-features"))
742 FS = F->getFnAttribute(Kind: "target-features").getValueAsString();
743
744 // Compute MIPS architecture attributes based on the default subtarget
745 // that we'd have constructed.
746 // FIXME: For ifunc related functions we could iterate over and look
747 // for a feature string that doesn't match the default one.
748 const Triple &TT = TM.getTargetTriple();
749 StringRef CPU = MIPS_MC::selectMipsCPU(TT, CPU: TM.getTargetCPU());
750 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
751 const MipsSubtarget STI(TT, CPU, FS, MTM.isLittleEndian(), MTM, std::nullopt);
752
753 bool IsABICalls = STI.isABICalls();
754 const MipsABIInfo &ABI = MTM.getABI();
755 if (IsABICalls) {
756 TS.emitDirectiveAbiCalls();
757 // FIXME: This condition should be a lot more complicated that it is here.
758 // Ideally it should test for properties of the ABI and not the ABI
759 // itself.
760 // For the moment, I'm only correcting enough to make MIPS-IV work.
761 if (!isPositionIndependent() && STI.hasSym32())
762 TS.emitDirectiveOptionPic0();
763 }
764
765 // Tell the assembler which ABI we are using
766 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
767 OutStreamer->switchSection(
768 Section: OutContext.getELFSection(Section: SectionName, Type: ELF::SHT_PROGBITS, Flags: 0));
769
770 // NaN: At the moment we only support:
771 // 1. .nan legacy (default)
772 // 2. .nan 2008
773 STI.isNaN2008() ? TS.emitDirectiveNaN2008()
774 : TS.emitDirectiveNaNLegacy();
775
776 // TODO: handle O64 ABI
777
778 TS.updateABIInfo(P: STI);
779
780 // We should always emit a '.module fp=...' but binutils 2.24 does not accept
781 // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
782 // -mfp64) and omit it otherwise.
783 if ((ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) ||
784 STI.useSoftFloat())
785 TS.emitDirectiveModuleFP();
786
787 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
788 // accept it. We therefore emit it when it contradicts the default or an
789 // option has changed the default (i.e. FPXX) and omit it otherwise.
790 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
791 TS.emitDirectiveModuleOddSPReg();
792
793 // Switch to the .text section.
794 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection());
795}
796
797void MipsAsmPrinter::emitInlineAsmStart() const {
798 MipsTargetStreamer &TS = getTargetStreamer();
799
800 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
801 // and 'reorder') is different from LLVM's choice for generated code ('noat',
802 // 'nomacro' and 'noreorder').
803 // In order to maintain compatibility with inline assembly code which depends
804 // on GCC's assembler options being used, we have to switch to those options
805 // for the duration of the inline assembly block and then switch back.
806 TS.emitDirectiveSetPush();
807 TS.emitDirectiveSetAt();
808 TS.emitDirectiveSetMacro();
809 TS.emitDirectiveSetReorder();
810 OutStreamer->addBlankLine();
811}
812
813void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
814 const MCSubtargetInfo *EndInfo) const {
815 OutStreamer->addBlankLine();
816 getTargetStreamer().emitDirectiveSetPop();
817}
818
819void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
820 MCInst I;
821 I.setOpcode(Mips::JAL);
822 I.addOperand(
823 Op: MCOperand::createExpr(Val: MCSymbolRefExpr::create(Symbol, Ctx&: OutContext)));
824 OutStreamer->emitInstruction(Inst: I, STI);
825}
826
827void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
828 unsigned Reg) {
829 MCInst I;
830 I.setOpcode(Opcode);
831 I.addOperand(Op: MCOperand::createReg(Reg));
832 OutStreamer->emitInstruction(Inst: I, STI);
833}
834
835void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
836 unsigned Opcode, unsigned Reg1,
837 unsigned Reg2) {
838 MCInst I;
839 //
840 // Because of the current td files for Mips32, the operands for MTC1
841 // appear backwards from their normal assembly order. It's not a trivial
842 // change to fix this in the td file so we adjust for it here.
843 //
844 if (Opcode == Mips::MTC1) {
845 unsigned Temp = Reg1;
846 Reg1 = Reg2;
847 Reg2 = Temp;
848 }
849 I.setOpcode(Opcode);
850 I.addOperand(Op: MCOperand::createReg(Reg: Reg1));
851 I.addOperand(Op: MCOperand::createReg(Reg: Reg2));
852 OutStreamer->emitInstruction(Inst: I, STI);
853}
854
855void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
856 unsigned Opcode, unsigned Reg1,
857 unsigned Reg2, unsigned Reg3) {
858 MCInst I;
859 I.setOpcode(Opcode);
860 I.addOperand(Op: MCOperand::createReg(Reg: Reg1));
861 I.addOperand(Op: MCOperand::createReg(Reg: Reg2));
862 I.addOperand(Op: MCOperand::createReg(Reg: Reg3));
863 OutStreamer->emitInstruction(Inst: I, STI);
864}
865
866void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
867 unsigned MovOpc, unsigned Reg1,
868 unsigned Reg2, unsigned FPReg1,
869 unsigned FPReg2, bool LE) {
870 if (!LE) {
871 unsigned temp = Reg1;
872 Reg1 = Reg2;
873 Reg2 = temp;
874 }
875 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1, Reg2: FPReg1);
876 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Reg2, Reg2: FPReg2);
877}
878
879void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
880 Mips16HardFloatInfo::FPParamVariant PV,
881 bool LE, bool ToFP) {
882 using namespace Mips16HardFloatInfo;
883
884 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
885 switch (PV) {
886 case FSig:
887 EmitInstrRegReg(STI, Opcode: MovOpc, Mips::Reg1: A0, Mips::Reg2: F12);
888 break;
889 case FFSig:
890 EmitMovFPIntPair(STI, MovOpc, Mips::Reg1: A0, Mips::Reg2: A1, Mips::FPReg1: F12, Mips::FPReg2: F14, LE);
891 break;
892 case FDSig:
893 EmitInstrRegReg(STI, Opcode: MovOpc, Mips::Reg1: A0, Mips::Reg2: F12);
894 EmitMovFPIntPair(STI, MovOpc, Mips::Reg1: A2, Mips::Reg2: A3, Mips::FPReg1: F14, Mips::FPReg2: F15, LE);
895 break;
896 case DSig:
897 EmitMovFPIntPair(STI, MovOpc, Mips::Reg1: A0, Mips::Reg2: A1, Mips::FPReg1: F12, Mips::FPReg2: F13, LE);
898 break;
899 case DDSig:
900 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
901 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
902 break;
903 case DFSig:
904 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
905 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
906 break;
907 case NoSig:
908 return;
909 }
910}
911
912void MipsAsmPrinter::EmitSwapFPIntRetval(
913 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
914 bool LE) {
915 using namespace Mips16HardFloatInfo;
916
917 unsigned MovOpc = Mips::MFC1;
918 switch (RV) {
919 case FRet:
920 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
921 break;
922 case DRet:
923 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
924 break;
925 case CFRet:
926 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
927 break;
928 case CDRet:
929 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
930 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
931 break;
932 case NoFPRet:
933 break;
934 }
935}
936
937void MipsAsmPrinter::EmitFPCallStub(
938 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
939 using namespace Mips16HardFloatInfo;
940
941 MCSymbol *MSymbol = OutContext.getOrCreateSymbol(Name: StringRef(Symbol));
942 bool LE = getDataLayout().isLittleEndian();
943 // Construct a local MCSubtargetInfo here.
944 // This is because the MachineFunction won't exist (but have not yet been
945 // freed) and since we're at the global level we can use the default
946 // constructed subtarget.
947 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
948 TheTriple: TM.getTargetTriple().str(), CPU: TM.getTargetCPU(),
949 Features: TM.getTargetFeatureString()));
950
951 //
952 // .global xxxx
953 //
954 OutStreamer->emitSymbolAttribute(Symbol: MSymbol, Attribute: MCSA_Global);
955 const char *RetType;
956 //
957 // make the comment field identifying the return and parameter
958 // types of the floating point stub
959 // # Stub function to call rettype xxxx (params)
960 //
961 switch (Signature->RetSig) {
962 case FRet:
963 RetType = "float";
964 break;
965 case DRet:
966 RetType = "double";
967 break;
968 case CFRet:
969 RetType = "complex";
970 break;
971 case CDRet:
972 RetType = "double complex";
973 break;
974 case NoFPRet:
975 RetType = "";
976 break;
977 }
978 const char *Parms;
979 switch (Signature->ParamSig) {
980 case FSig:
981 Parms = "float";
982 break;
983 case FFSig:
984 Parms = "float, float";
985 break;
986 case FDSig:
987 Parms = "float, double";
988 break;
989 case DSig:
990 Parms = "double";
991 break;
992 case DDSig:
993 Parms = "double, double";
994 break;
995 case DFSig:
996 Parms = "double, float";
997 break;
998 case NoSig:
999 Parms = "";
1000 break;
1001 }
1002 OutStreamer->AddComment(T: "\t# Stub function to call " + Twine(RetType) + " " +
1003 Twine(Symbol) + " (" + Twine(Parms) + ")");
1004 //
1005 // probably not necessary but we save and restore the current section state
1006 //
1007 OutStreamer->pushSection();
1008 //
1009 // .section mips16.call.fpxxxx,"ax",@progbits
1010 //
1011 MCSectionELF *M = OutContext.getELFSection(
1012 Section: ".mips16.call.fp." + std::string(Symbol), Type: ELF::SHT_PROGBITS,
1013 Flags: ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
1014 OutStreamer->switchSection(Section: M, Subsection: nullptr);
1015 //
1016 // .align 2
1017 //
1018 OutStreamer->emitValueToAlignment(Alignment: Align(4));
1019 MipsTargetStreamer &TS = getTargetStreamer();
1020 //
1021 // .set nomips16
1022 // .set nomicromips
1023 //
1024 TS.emitDirectiveSetNoMips16();
1025 TS.emitDirectiveSetNoMicroMips();
1026 //
1027 // .ent __call_stub_fp_xxxx
1028 // .type __call_stub_fp_xxxx,@function
1029 // __call_stub_fp_xxxx:
1030 //
1031 std::string x = "__call_stub_fp_" + std::string(Symbol);
1032 MCSymbolELF *Stub =
1033 cast<MCSymbolELF>(Val: OutContext.getOrCreateSymbol(Name: StringRef(x)));
1034 TS.emitDirectiveEnt(Symbol: *Stub);
1035 MCSymbol *MType =
1036 OutContext.getOrCreateSymbol(Name: "__call_stub_fp_" + Twine(Symbol));
1037 OutStreamer->emitSymbolAttribute(Symbol: MType, Attribute: MCSA_ELF_TypeFunction);
1038 OutStreamer->emitLabel(Symbol: Stub);
1039
1040 // Only handle non-pic for now.
1041 assert(!isPositionIndependent() &&
1042 "should not be here if we are compiling pic");
1043 TS.emitDirectiveSetReorder();
1044 //
1045 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1046 // stubs without raw text but this current patch is for compiler generated
1047 // functions and they all return some value.
1048 // The calling sequence for non pic is different in that case and we need
1049 // to implement %lo and %hi in order to handle the case of no return value
1050 // See the corresponding method in Mips16HardFloat for details.
1051 //
1052 // mov the return address to S2.
1053 // we have no stack space to store it and we are about to make another call.
1054 // We need to make sure that the enclosing function knows to save S2
1055 // This should have already been handled.
1056 //
1057 // Mov $18, $31
1058
1059 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1060
1061 EmitSwapFPIntParams(STI: *STI, PV: Signature->ParamSig, LE, ToFP: true);
1062
1063 // Jal xxxx
1064 //
1065 EmitJal(STI: *STI, Symbol: MSymbol);
1066
1067 // fix return values
1068 EmitSwapFPIntRetval(STI: *STI, RV: Signature->RetSig, LE);
1069 //
1070 // do the return
1071 // if (Signature->RetSig == NoFPRet)
1072 // llvm_unreachable("should not be any stubs here with no return value");
1073 // else
1074 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1075
1076 MCSymbol *Tmp = OutContext.createTempSymbol();
1077 OutStreamer->emitLabel(Symbol: Tmp);
1078 const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Symbol: Stub, Ctx&: OutContext);
1079 const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Symbol: Tmp, Ctx&: OutContext);
1080 const MCExpr *T_min_E = MCBinaryExpr::createSub(LHS: T, RHS: E, Ctx&: OutContext);
1081 OutStreamer->emitELFSize(Symbol: Stub, Value: T_min_E);
1082 TS.emitDirectiveEnd(Name: x);
1083 OutStreamer->popSection();
1084}
1085
1086void MipsAsmPrinter::emitEndOfAsmFile(Module &M) {
1087 // Emit needed stubs
1088 //
1089 for (std::map<
1090 const char *,
1091 const Mips16HardFloatInfo::FuncSignature *>::const_iterator
1092 it = StubsNeeded.begin();
1093 it != StubsNeeded.end(); ++it) {
1094 const char *Symbol = it->first;
1095 const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1096 EmitFPCallStub(Symbol, Signature);
1097 }
1098 // return to the text section
1099 OutStreamer->switchSection(Section: OutContext.getObjectFileInfo()->getTextSection());
1100}
1101
1102void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1103 const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1104 // For mips32 we want to emit the following pattern:
1105 //
1106 // .Lxray_sled_N:
1107 // ALIGN
1108 // B .tmpN
1109 // 11 NOP instructions (44 bytes)
1110 // ADDIU T9, T9, 52
1111 // .tmpN
1112 //
1113 // We need the 44 bytes (11 instructions) because at runtime, we'd
1114 // be patching over the full 48 bytes (12 instructions) with the following
1115 // pattern:
1116 //
1117 // ADDIU SP, SP, -8
1118 // NOP
1119 // SW RA, 4(SP)
1120 // SW T9, 0(SP)
1121 // LUI T9, %hi(__xray_FunctionEntry/Exit)
1122 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1123 // LUI T0, %hi(function_id)
1124 // JALR T9
1125 // ORI T0, T0, %lo(function_id)
1126 // LW T9, 0(SP)
1127 // LW RA, 4(SP)
1128 // ADDIU SP, SP, 8
1129 //
1130 // We add 52 bytes to t9 because we want to adjust the function pointer to
1131 // the actual start of function i.e. the address just after the noop sled.
1132 // We do this because gp displacement relocation is emitted at the start of
1133 // of the function i.e after the nop sled and to correctly calculate the
1134 // global offset table address, t9 must hold the address of the instruction
1135 // containing the gp displacement relocation.
1136 // FIXME: Is this correct for the static relocation model?
1137 //
1138 // For mips64 we want to emit the following pattern:
1139 //
1140 // .Lxray_sled_N:
1141 // ALIGN
1142 // B .tmpN
1143 // 15 NOP instructions (60 bytes)
1144 // .tmpN
1145 //
1146 // We need the 60 bytes (15 instructions) because at runtime, we'd
1147 // be patching over the full 64 bytes (16 instructions) with the following
1148 // pattern:
1149 //
1150 // DADDIU SP, SP, -16
1151 // NOP
1152 // SD RA, 8(SP)
1153 // SD T9, 0(SP)
1154 // LUI T9, %highest(__xray_FunctionEntry/Exit)
1155 // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1156 // DSLL T9, T9, 16
1157 // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1158 // DSLL T9, T9, 16
1159 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1160 // LUI T0, %hi(function_id)
1161 // JALR T9
1162 // ADDIU T0, T0, %lo(function_id)
1163 // LD T9, 0(SP)
1164 // LD RA, 8(SP)
1165 // DADDIU SP, SP, 16
1166 //
1167 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: &getSubtargetInfo());
1168 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1169 OutStreamer->emitLabel(Symbol: CurSled);
1170 auto Target = OutContext.createTempSymbol();
1171
1172 // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1173 // start of function
1174 const MCExpr *TargetExpr = MCSymbolRefExpr::create(
1175 Symbol: Target, Kind: MCSymbolRefExpr::VariantKind::VK_None, Ctx&: OutContext);
1176 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1177 .addReg(Mips::ZERO)
1178 .addReg(Mips::ZERO)
1179 .addExpr(TargetExpr));
1180
1181 for (int8_t I = 0; I < NoopsInSledCount; I++)
1182 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1183 .addReg(Mips::ZERO)
1184 .addReg(Mips::ZERO)
1185 .addImm(0));
1186
1187 OutStreamer->emitLabel(Symbol: Target);
1188
1189 if (!Subtarget->isGP64bit()) {
1190 EmitToStreamer(*OutStreamer,
1191 MCInstBuilder(Mips::ADDiu)
1192 .addReg(Mips::T9)
1193 .addReg(Mips::T9)
1194 .addImm(0x34));
1195 }
1196
1197 recordSled(Sled: CurSled, MI, Kind, Version: 2);
1198}
1199
1200void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1201 EmitSled(MI, Kind: SledKind::FUNCTION_ENTER);
1202}
1203
1204void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1205 EmitSled(MI, Kind: SledKind::FUNCTION_EXIT);
1206}
1207
1208void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1209 EmitSled(MI, Kind: SledKind::TAIL_CALL);
1210}
1211
1212void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1213 raw_ostream &OS) {
1214 // TODO: implement
1215}
1216
1217// Emit .dtprelword or .dtpreldword directive
1218// and value for debug thread local expression.
1219void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const {
1220 if (auto *MipsExpr = dyn_cast<MipsMCExpr>(Val: Value)) {
1221 if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) {
1222 switch (Size) {
1223 case 4:
1224 OutStreamer->emitDTPRel32Value(Value: MipsExpr->getSubExpr());
1225 break;
1226 case 8:
1227 OutStreamer->emitDTPRel64Value(Value: MipsExpr->getSubExpr());
1228 break;
1229 default:
1230 llvm_unreachable("Unexpected size of expression value.");
1231 }
1232 return;
1233 }
1234 }
1235 AsmPrinter::emitDebugValue(Value, Size);
1236}
1237
1238// Align all targets of indirect branches on bundle size. Used only if target
1239// is NaCl.
1240void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
1241 // Align all blocks that are jumped to through jump table.
1242 if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
1243 const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
1244 for (const auto &I : JT) {
1245 const std::vector<MachineBasicBlock *> &MBBs = I.MBBs;
1246
1247 for (MachineBasicBlock *MBB : MBBs)
1248 MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1249 }
1250 }
1251
1252 // If basic block address is taken, block can be target of indirect branch.
1253 for (auto &MBB : MF) {
1254 if (MBB.hasAddressTaken())
1255 MBB.setAlignment(MIPS_NACL_BUNDLE_ALIGN);
1256 }
1257}
1258
1259bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1260 return (Opcode == Mips::LONG_BRANCH_LUi
1261 || Opcode == Mips::LONG_BRANCH_LUi2Op
1262 || Opcode == Mips::LONG_BRANCH_LUi2Op_64
1263 || Opcode == Mips::LONG_BRANCH_ADDiu
1264 || Opcode == Mips::LONG_BRANCH_ADDiu2Op
1265 || Opcode == Mips::LONG_BRANCH_DADDiu
1266 || Opcode == Mips::LONG_BRANCH_DADDiu2Op);
1267}
1268
1269// Force static initialization.
1270extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsAsmPrinter() {
1271 RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget());
1272 RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget());
1273 RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target());
1274 RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget());
1275}
1276

source code of llvm/lib/Target/Mips/MipsAsmPrinter.cpp