1 | //===- llvm/CodeGen/MachineRegisterInfo.h -----------------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file defines the MachineRegisterInfo class. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H |
14 | #define LLVM_CODEGEN_MACHINEREGISTERINFO_H |
15 | |
16 | #include "llvm/ADT/ArrayRef.h" |
17 | #include "llvm/ADT/BitVector.h" |
18 | #include "llvm/ADT/IndexedMap.h" |
19 | #include "llvm/ADT/PointerUnion.h" |
20 | #include "llvm/ADT/SmallPtrSet.h" |
21 | #include "llvm/ADT/SmallVector.h" |
22 | #include "llvm/ADT/StringSet.h" |
23 | #include "llvm/ADT/iterator_range.h" |
24 | #include "llvm/CodeGen/MachineBasicBlock.h" |
25 | #include "llvm/CodeGen/MachineFunction.h" |
26 | #include "llvm/CodeGen/MachineInstrBundle.h" |
27 | #include "llvm/CodeGen/MachineOperand.h" |
28 | #include "llvm/CodeGen/RegisterBank.h" |
29 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
30 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
31 | #include "llvm/MC/LaneBitmask.h" |
32 | #include <cassert> |
33 | #include <cstddef> |
34 | #include <cstdint> |
35 | #include <iterator> |
36 | #include <memory> |
37 | #include <utility> |
38 | #include <vector> |
39 | |
40 | namespace llvm { |
41 | |
42 | class PSetIterator; |
43 | |
44 | /// Convenient type to represent either a register class or a register bank. |
45 | using RegClassOrRegBank = |
46 | PointerUnion<const TargetRegisterClass *, const RegisterBank *>; |
47 | |
48 | /// MachineRegisterInfo - Keep track of information for virtual and physical |
49 | /// registers, including vreg register classes, use/def chains for registers, |
50 | /// etc. |
51 | class MachineRegisterInfo { |
52 | public: |
53 | class Delegate { |
54 | virtual void anchor(); |
55 | |
56 | public: |
57 | virtual ~Delegate() = default; |
58 | |
59 | virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0; |
60 | virtual void MRI_NoteCloneVirtualRegister(Register NewReg, |
61 | Register SrcReg) { |
62 | MRI_NoteNewVirtualRegister(Reg: NewReg); |
63 | } |
64 | }; |
65 | |
66 | private: |
67 | MachineFunction *MF; |
68 | SmallPtrSet<Delegate *, 1> TheDelegates; |
69 | |
70 | /// True if subregister liveness is tracked. |
71 | const bool TracksSubRegLiveness; |
72 | |
73 | /// VRegInfo - Information we keep for each virtual register. |
74 | /// |
75 | /// Each element in this list contains the register class of the vreg and the |
76 | /// start of the use/def list for the register. |
77 | IndexedMap<std::pair<RegClassOrRegBank, MachineOperand *>, |
78 | VirtReg2IndexFunctor> |
79 | VRegInfo; |
80 | |
81 | /// Map for recovering vreg name from vreg number. |
82 | /// This map is used by the MIR Printer. |
83 | IndexedMap<std::string, VirtReg2IndexFunctor> VReg2Name; |
84 | |
85 | /// StringSet that is used to unique vreg names. |
86 | StringSet<> VRegNames; |
87 | |
88 | /// The flag is true upon \p UpdatedCSRs initialization |
89 | /// and false otherwise. |
90 | bool IsUpdatedCSRsInitialized = false; |
91 | |
92 | /// Contains the updated callee saved register list. |
93 | /// As opposed to the static list defined in register info, |
94 | /// all registers that were disabled are removed from the list. |
95 | SmallVector<MCPhysReg, 16> UpdatedCSRs; |
96 | |
97 | /// RegAllocHints - This vector records register allocation hints for |
98 | /// virtual registers. For each virtual register, it keeps a pair of hint |
99 | /// type and hints vector making up the allocation hints. Only the first |
100 | /// hint may be target specific, and in that case this is reflected by the |
101 | /// first member of the pair being non-zero. If the hinted register is |
102 | /// virtual, it means the allocator should prefer the physical register |
103 | /// allocated to it if any. |
104 | IndexedMap<std::pair<unsigned, SmallVector<Register, 4>>, |
105 | VirtReg2IndexFunctor> |
106 | RegAllocHints; |
107 | |
108 | /// PhysRegUseDefLists - This is an array of the head of the use/def list for |
109 | /// physical registers. |
110 | std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists; |
111 | |
112 | /// getRegUseDefListHead - Return the head pointer for the register use/def |
113 | /// list for the specified virtual or physical register. |
114 | MachineOperand *&getRegUseDefListHead(Register RegNo) { |
115 | if (RegNo.isVirtual()) |
116 | return VRegInfo[RegNo.id()].second; |
117 | return PhysRegUseDefLists[RegNo.id()]; |
118 | } |
119 | |
120 | MachineOperand *getRegUseDefListHead(Register RegNo) const { |
121 | if (RegNo.isVirtual()) |
122 | return VRegInfo[RegNo.id()].second; |
123 | return PhysRegUseDefLists[RegNo.id()]; |
124 | } |
125 | |
126 | /// Get the next element in the use-def chain. |
127 | static MachineOperand *getNextOperandForReg(const MachineOperand *MO) { |
128 | assert(MO && MO->isReg() && "This is not a register operand!" ); |
129 | return MO->Contents.Reg.Next; |
130 | } |
131 | |
132 | /// UsedPhysRegMask - Additional used physregs including aliases. |
133 | /// This bit vector represents all the registers clobbered by function calls. |
134 | BitVector UsedPhysRegMask; |
135 | |
136 | /// ReservedRegs - This is a bit vector of reserved registers. The target |
137 | /// may change its mind about which registers should be reserved. This |
138 | /// vector is the frozen set of reserved registers when register allocation |
139 | /// started. |
140 | BitVector ReservedRegs; |
141 | |
142 | using VRegToTypeMap = IndexedMap<LLT, VirtReg2IndexFunctor>; |
143 | /// Map generic virtual registers to their low-level type. |
144 | VRegToTypeMap VRegToType; |
145 | |
146 | /// Keep track of the physical registers that are live in to the function. |
147 | /// Live in values are typically arguments in registers. LiveIn values are |
148 | /// allowed to have virtual registers associated with them, stored in the |
149 | /// second element. |
150 | std::vector<std::pair<MCRegister, Register>> LiveIns; |
151 | |
152 | public: |
153 | explicit MachineRegisterInfo(MachineFunction *MF); |
154 | MachineRegisterInfo(const MachineRegisterInfo &) = delete; |
155 | MachineRegisterInfo &operator=(const MachineRegisterInfo &) = delete; |
156 | |
157 | const TargetRegisterInfo *getTargetRegisterInfo() const { |
158 | return MF->getSubtarget().getRegisterInfo(); |
159 | } |
160 | |
161 | void resetDelegate(Delegate *delegate) { |
162 | // Ensure another delegate does not take over unless the current |
163 | // delegate first unattaches itself. |
164 | assert(TheDelegates.count(delegate) && |
165 | "Only an existing delegate can perform reset!" ); |
166 | TheDelegates.erase(Ptr: delegate); |
167 | } |
168 | |
169 | void addDelegate(Delegate *delegate) { |
170 | assert(delegate && !TheDelegates.count(delegate) && |
171 | "Attempted to add null delegate, or to change it without " |
172 | "first resetting it!" ); |
173 | |
174 | TheDelegates.insert(Ptr: delegate); |
175 | } |
176 | |
177 | void noteNewVirtualRegister(Register Reg) { |
178 | for (auto *TheDelegate : TheDelegates) |
179 | TheDelegate->MRI_NoteNewVirtualRegister(Reg); |
180 | } |
181 | |
182 | void noteCloneVirtualRegister(Register NewReg, Register SrcReg) { |
183 | for (auto *TheDelegate : TheDelegates) |
184 | TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg); |
185 | } |
186 | |
187 | //===--------------------------------------------------------------------===// |
188 | // Function State |
189 | //===--------------------------------------------------------------------===// |
190 | |
191 | // isSSA - Returns true when the machine function is in SSA form. Early |
192 | // passes require the machine function to be in SSA form where every virtual |
193 | // register has a single defining instruction. |
194 | // |
195 | // The TwoAddressInstructionPass and PHIElimination passes take the machine |
196 | // function out of SSA form when they introduce multiple defs per virtual |
197 | // register. |
198 | bool isSSA() const { |
199 | return MF->getProperties().hasProperty( |
200 | P: MachineFunctionProperties::Property::IsSSA); |
201 | } |
202 | |
203 | // leaveSSA - Indicates that the machine function is no longer in SSA form. |
204 | void leaveSSA() { |
205 | MF->getProperties().reset(P: MachineFunctionProperties::Property::IsSSA); |
206 | } |
207 | |
208 | /// tracksLiveness - Returns true when tracking register liveness accurately. |
209 | /// (see MachineFUnctionProperties::Property description for details) |
210 | bool tracksLiveness() const { |
211 | return MF->getProperties().hasProperty( |
212 | P: MachineFunctionProperties::Property::TracksLiveness); |
213 | } |
214 | |
215 | /// invalidateLiveness - Indicates that register liveness is no longer being |
216 | /// tracked accurately. |
217 | /// |
218 | /// This should be called by late passes that invalidate the liveness |
219 | /// information. |
220 | void invalidateLiveness() { |
221 | MF->getProperties().reset( |
222 | P: MachineFunctionProperties::Property::TracksLiveness); |
223 | } |
224 | |
225 | /// Returns true if liveness for register class @p RC should be tracked at |
226 | /// the subregister level. |
227 | bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const { |
228 | return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; |
229 | } |
230 | bool shouldTrackSubRegLiveness(Register VReg) const { |
231 | assert(VReg.isVirtual() && "Must pass a VReg" ); |
232 | const TargetRegisterClass *RC = getRegClassOrNull(Reg: VReg); |
233 | return LLVM_LIKELY(RC) ? shouldTrackSubRegLiveness(RC: *RC) : false; |
234 | } |
235 | bool subRegLivenessEnabled() const { |
236 | return TracksSubRegLiveness; |
237 | } |
238 | |
239 | //===--------------------------------------------------------------------===// |
240 | // Register Info |
241 | //===--------------------------------------------------------------------===// |
242 | |
243 | /// Returns true if the updated CSR list was initialized and false otherwise. |
244 | bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; } |
245 | |
246 | /// Disables the register from the list of CSRs. |
247 | /// I.e. the register will not appear as part of the CSR mask. |
248 | /// \see UpdatedCalleeSavedRegs. |
249 | void disableCalleeSavedRegister(MCRegister Reg); |
250 | |
251 | /// Returns list of callee saved registers. |
252 | /// The function returns the updated CSR list (after taking into account |
253 | /// registers that are disabled from the CSR list). |
254 | const MCPhysReg *getCalleeSavedRegs() const; |
255 | |
256 | /// Sets the updated Callee Saved Registers list. |
257 | /// Notice that it will override ant previously disabled/saved CSRs. |
258 | void setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs); |
259 | |
260 | // Strictly for use by MachineInstr.cpp. |
261 | void addRegOperandToUseList(MachineOperand *MO); |
262 | |
263 | // Strictly for use by MachineInstr.cpp. |
264 | void removeRegOperandFromUseList(MachineOperand *MO); |
265 | |
266 | // Strictly for use by MachineInstr.cpp. |
267 | void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps); |
268 | |
269 | /// Verify the sanity of the use list for Reg. |
270 | void verifyUseList(Register Reg) const; |
271 | |
272 | /// Verify the use list of all registers. |
273 | void verifyUseLists() const; |
274 | |
275 | /// reg_begin/reg_end - Provide iteration support to walk over all definitions |
276 | /// and uses of a register within the MachineFunction that corresponds to this |
277 | /// MachineRegisterInfo object. |
278 | template<bool Uses, bool Defs, bool SkipDebug, |
279 | bool ByOperand, bool ByInstr, bool ByBundle> |
280 | class defusechain_iterator; |
281 | template<bool Uses, bool Defs, bool SkipDebug, |
282 | bool ByOperand, bool ByInstr, bool ByBundle> |
283 | class defusechain_instr_iterator; |
284 | |
285 | // Make it a friend so it can access getNextOperandForReg(). |
286 | template<bool, bool, bool, bool, bool, bool> |
287 | friend class defusechain_iterator; |
288 | template<bool, bool, bool, bool, bool, bool> |
289 | friend class defusechain_instr_iterator; |
290 | |
291 | /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified |
292 | /// register. |
293 | using reg_iterator = |
294 | defusechain_iterator<true, true, false, true, false, false>; |
295 | reg_iterator reg_begin(Register RegNo) const { |
296 | return reg_iterator(getRegUseDefListHead(RegNo)); |
297 | } |
298 | static reg_iterator reg_end() { return reg_iterator(nullptr); } |
299 | |
300 | inline iterator_range<reg_iterator> reg_operands(Register Reg) const { |
301 | return make_range(x: reg_begin(RegNo: Reg), y: reg_end()); |
302 | } |
303 | |
304 | /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses |
305 | /// of the specified register, stepping by MachineInstr. |
306 | using reg_instr_iterator = |
307 | defusechain_instr_iterator<true, true, false, false, true, false>; |
308 | reg_instr_iterator reg_instr_begin(Register RegNo) const { |
309 | return reg_instr_iterator(getRegUseDefListHead(RegNo)); |
310 | } |
311 | static reg_instr_iterator reg_instr_end() { |
312 | return reg_instr_iterator(nullptr); |
313 | } |
314 | |
315 | inline iterator_range<reg_instr_iterator> |
316 | reg_instructions(Register Reg) const { |
317 | return make_range(x: reg_instr_begin(RegNo: Reg), y: reg_instr_end()); |
318 | } |
319 | |
320 | /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses |
321 | /// of the specified register, stepping by bundle. |
322 | using reg_bundle_iterator = |
323 | defusechain_instr_iterator<true, true, false, false, false, true>; |
324 | reg_bundle_iterator reg_bundle_begin(Register RegNo) const { |
325 | return reg_bundle_iterator(getRegUseDefListHead(RegNo)); |
326 | } |
327 | static reg_bundle_iterator reg_bundle_end() { |
328 | return reg_bundle_iterator(nullptr); |
329 | } |
330 | |
331 | inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const { |
332 | return make_range(x: reg_bundle_begin(RegNo: Reg), y: reg_bundle_end()); |
333 | } |
334 | |
335 | /// reg_empty - Return true if there are no instructions using or defining the |
336 | /// specified register (it may be live-in). |
337 | bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); } |
338 | |
339 | /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses |
340 | /// of the specified register, skipping those marked as Debug. |
341 | using reg_nodbg_iterator = |
342 | defusechain_iterator<true, true, true, true, false, false>; |
343 | reg_nodbg_iterator reg_nodbg_begin(Register RegNo) const { |
344 | return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); |
345 | } |
346 | static reg_nodbg_iterator reg_nodbg_end() { |
347 | return reg_nodbg_iterator(nullptr); |
348 | } |
349 | |
350 | inline iterator_range<reg_nodbg_iterator> |
351 | reg_nodbg_operands(Register Reg) const { |
352 | return make_range(x: reg_nodbg_begin(RegNo: Reg), y: reg_nodbg_end()); |
353 | } |
354 | |
355 | /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk |
356 | /// all defs and uses of the specified register, stepping by MachineInstr, |
357 | /// skipping those marked as Debug. |
358 | using reg_instr_nodbg_iterator = |
359 | defusechain_instr_iterator<true, true, true, false, true, false>; |
360 | reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const { |
361 | return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); |
362 | } |
363 | static reg_instr_nodbg_iterator reg_instr_nodbg_end() { |
364 | return reg_instr_nodbg_iterator(nullptr); |
365 | } |
366 | |
367 | inline iterator_range<reg_instr_nodbg_iterator> |
368 | reg_nodbg_instructions(Register Reg) const { |
369 | return make_range(x: reg_instr_nodbg_begin(RegNo: Reg), y: reg_instr_nodbg_end()); |
370 | } |
371 | |
372 | /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk |
373 | /// all defs and uses of the specified register, stepping by bundle, |
374 | /// skipping those marked as Debug. |
375 | using reg_bundle_nodbg_iterator = |
376 | defusechain_instr_iterator<true, true, true, false, false, true>; |
377 | reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const { |
378 | return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); |
379 | } |
380 | static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() { |
381 | return reg_bundle_nodbg_iterator(nullptr); |
382 | } |
383 | |
384 | inline iterator_range<reg_bundle_nodbg_iterator> |
385 | reg_nodbg_bundles(Register Reg) const { |
386 | return make_range(x: reg_bundle_nodbg_begin(RegNo: Reg), y: reg_bundle_nodbg_end()); |
387 | } |
388 | |
389 | /// reg_nodbg_empty - Return true if the only instructions using or defining |
390 | /// Reg are Debug instructions. |
391 | bool reg_nodbg_empty(Register RegNo) const { |
392 | return reg_nodbg_begin(RegNo) == reg_nodbg_end(); |
393 | } |
394 | |
395 | /// def_iterator/def_begin/def_end - Walk all defs of the specified register. |
396 | using def_iterator = |
397 | defusechain_iterator<false, true, false, true, false, false>; |
398 | def_iterator def_begin(Register RegNo) const { |
399 | return def_iterator(getRegUseDefListHead(RegNo)); |
400 | } |
401 | static def_iterator def_end() { return def_iterator(nullptr); } |
402 | |
403 | inline iterator_range<def_iterator> def_operands(Register Reg) const { |
404 | return make_range(x: def_begin(RegNo: Reg), y: def_end()); |
405 | } |
406 | |
407 | /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the |
408 | /// specified register, stepping by MachineInst. |
409 | using def_instr_iterator = |
410 | defusechain_instr_iterator<false, true, false, false, true, false>; |
411 | def_instr_iterator def_instr_begin(Register RegNo) const { |
412 | return def_instr_iterator(getRegUseDefListHead(RegNo)); |
413 | } |
414 | static def_instr_iterator def_instr_end() { |
415 | return def_instr_iterator(nullptr); |
416 | } |
417 | |
418 | inline iterator_range<def_instr_iterator> |
419 | def_instructions(Register Reg) const { |
420 | return make_range(x: def_instr_begin(RegNo: Reg), y: def_instr_end()); |
421 | } |
422 | |
423 | /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the |
424 | /// specified register, stepping by bundle. |
425 | using def_bundle_iterator = |
426 | defusechain_instr_iterator<false, true, false, false, false, true>; |
427 | def_bundle_iterator def_bundle_begin(Register RegNo) const { |
428 | return def_bundle_iterator(getRegUseDefListHead(RegNo)); |
429 | } |
430 | static def_bundle_iterator def_bundle_end() { |
431 | return def_bundle_iterator(nullptr); |
432 | } |
433 | |
434 | inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const { |
435 | return make_range(x: def_bundle_begin(RegNo: Reg), y: def_bundle_end()); |
436 | } |
437 | |
438 | /// def_empty - Return true if there are no instructions defining the |
439 | /// specified register (it may be live-in). |
440 | bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); } |
441 | |
442 | StringRef getVRegName(Register Reg) const { |
443 | return VReg2Name.inBounds(n: Reg) ? StringRef(VReg2Name[Reg]) : "" ; |
444 | } |
445 | |
446 | void insertVRegByName(StringRef Name, Register Reg) { |
447 | assert((Name.empty() || !VRegNames.contains(Name)) && |
448 | "Named VRegs Must be Unique." ); |
449 | if (!Name.empty()) { |
450 | VRegNames.insert(key: Name); |
451 | VReg2Name.grow(n: Reg); |
452 | VReg2Name[Reg] = Name.str(); |
453 | } |
454 | } |
455 | |
456 | /// Return true if there is exactly one operand defining the specified |
457 | /// register. |
458 | bool hasOneDef(Register RegNo) const { |
459 | return hasSingleElement(C: def_operands(Reg: RegNo)); |
460 | } |
461 | |
462 | /// Returns the defining operand if there is exactly one operand defining the |
463 | /// specified register, otherwise nullptr. |
464 | MachineOperand *getOneDef(Register Reg) const { |
465 | def_iterator DI = def_begin(RegNo: Reg); |
466 | if (DI == def_end()) // No defs. |
467 | return nullptr; |
468 | |
469 | def_iterator OneDef = DI; |
470 | if (++DI == def_end()) |
471 | return &*OneDef; |
472 | return nullptr; // Multiple defs. |
473 | } |
474 | |
475 | /// use_iterator/use_begin/use_end - Walk all uses of the specified register. |
476 | using use_iterator = |
477 | defusechain_iterator<true, false, false, true, false, false>; |
478 | use_iterator use_begin(Register RegNo) const { |
479 | return use_iterator(getRegUseDefListHead(RegNo)); |
480 | } |
481 | static use_iterator use_end() { return use_iterator(nullptr); } |
482 | |
483 | inline iterator_range<use_iterator> use_operands(Register Reg) const { |
484 | return make_range(x: use_begin(RegNo: Reg), y: use_end()); |
485 | } |
486 | |
487 | /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the |
488 | /// specified register, stepping by MachineInstr. |
489 | using use_instr_iterator = |
490 | defusechain_instr_iterator<true, false, false, false, true, false>; |
491 | use_instr_iterator use_instr_begin(Register RegNo) const { |
492 | return use_instr_iterator(getRegUseDefListHead(RegNo)); |
493 | } |
494 | static use_instr_iterator use_instr_end() { |
495 | return use_instr_iterator(nullptr); |
496 | } |
497 | |
498 | inline iterator_range<use_instr_iterator> |
499 | use_instructions(Register Reg) const { |
500 | return make_range(x: use_instr_begin(RegNo: Reg), y: use_instr_end()); |
501 | } |
502 | |
503 | /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the |
504 | /// specified register, stepping by bundle. |
505 | using use_bundle_iterator = |
506 | defusechain_instr_iterator<true, false, false, false, false, true>; |
507 | use_bundle_iterator use_bundle_begin(Register RegNo) const { |
508 | return use_bundle_iterator(getRegUseDefListHead(RegNo)); |
509 | } |
510 | static use_bundle_iterator use_bundle_end() { |
511 | return use_bundle_iterator(nullptr); |
512 | } |
513 | |
514 | inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const { |
515 | return make_range(x: use_bundle_begin(RegNo: Reg), y: use_bundle_end()); |
516 | } |
517 | |
518 | /// use_empty - Return true if there are no instructions using the specified |
519 | /// register. |
520 | bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); } |
521 | |
522 | /// hasOneUse - Return true if there is exactly one instruction using the |
523 | /// specified register. |
524 | bool hasOneUse(Register RegNo) const { |
525 | return hasSingleElement(C: use_operands(Reg: RegNo)); |
526 | } |
527 | |
528 | /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the |
529 | /// specified register, skipping those marked as Debug. |
530 | using use_nodbg_iterator = |
531 | defusechain_iterator<true, false, true, true, false, false>; |
532 | use_nodbg_iterator use_nodbg_begin(Register RegNo) const { |
533 | return use_nodbg_iterator(getRegUseDefListHead(RegNo)); |
534 | } |
535 | static use_nodbg_iterator use_nodbg_end() { |
536 | return use_nodbg_iterator(nullptr); |
537 | } |
538 | |
539 | inline iterator_range<use_nodbg_iterator> |
540 | use_nodbg_operands(Register Reg) const { |
541 | return make_range(x: use_nodbg_begin(RegNo: Reg), y: use_nodbg_end()); |
542 | } |
543 | |
544 | /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk |
545 | /// all uses of the specified register, stepping by MachineInstr, skipping |
546 | /// those marked as Debug. |
547 | using use_instr_nodbg_iterator = |
548 | defusechain_instr_iterator<true, false, true, false, true, false>; |
549 | use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const { |
550 | return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo)); |
551 | } |
552 | static use_instr_nodbg_iterator use_instr_nodbg_end() { |
553 | return use_instr_nodbg_iterator(nullptr); |
554 | } |
555 | |
556 | inline iterator_range<use_instr_nodbg_iterator> |
557 | use_nodbg_instructions(Register Reg) const { |
558 | return make_range(x: use_instr_nodbg_begin(RegNo: Reg), y: use_instr_nodbg_end()); |
559 | } |
560 | |
561 | /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk |
562 | /// all uses of the specified register, stepping by bundle, skipping |
563 | /// those marked as Debug. |
564 | using use_bundle_nodbg_iterator = |
565 | defusechain_instr_iterator<true, false, true, false, false, true>; |
566 | use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const { |
567 | return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo)); |
568 | } |
569 | static use_bundle_nodbg_iterator use_bundle_nodbg_end() { |
570 | return use_bundle_nodbg_iterator(nullptr); |
571 | } |
572 | |
573 | inline iterator_range<use_bundle_nodbg_iterator> |
574 | use_nodbg_bundles(Register Reg) const { |
575 | return make_range(x: use_bundle_nodbg_begin(RegNo: Reg), y: use_bundle_nodbg_end()); |
576 | } |
577 | |
578 | /// use_nodbg_empty - Return true if there are no non-Debug instructions |
579 | /// using the specified register. |
580 | bool use_nodbg_empty(Register RegNo) const { |
581 | return use_nodbg_begin(RegNo) == use_nodbg_end(); |
582 | } |
583 | |
584 | /// hasOneNonDBGUse - Return true if there is exactly one non-Debug |
585 | /// use of the specified register. |
586 | bool hasOneNonDBGUse(Register RegNo) const; |
587 | |
588 | /// hasOneNonDBGUse - Return true if there is exactly one non-Debug |
589 | /// instruction using the specified register. Said instruction may have |
590 | /// multiple uses. |
591 | bool hasOneNonDBGUser(Register RegNo) const; |
592 | |
593 | |
594 | /// hasAtMostUses - Return true if the given register has at most \p MaxUsers |
595 | /// non-debug user instructions. |
596 | bool hasAtMostUserInstrs(Register Reg, unsigned MaxUsers) const; |
597 | |
598 | /// replaceRegWith - Replace all instances of FromReg with ToReg in the |
599 | /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), |
600 | /// except that it also changes any definitions of the register as well. |
601 | /// |
602 | /// Note that it is usually necessary to first constrain ToReg's register |
603 | /// class and register bank to match the FromReg constraints using one of the |
604 | /// methods: |
605 | /// |
606 | /// constrainRegClass(ToReg, getRegClass(FromReg)) |
607 | /// constrainRegAttrs(ToReg, FromReg) |
608 | /// RegisterBankInfo::constrainGenericRegister(ToReg, |
609 | /// *MRI.getRegClass(FromReg), MRI) |
610 | /// |
611 | /// These functions will return a falsy result if the virtual registers have |
612 | /// incompatible constraints. |
613 | /// |
614 | /// Note that if ToReg is a physical register the function will replace and |
615 | /// apply sub registers to ToReg in order to obtain a final/proper physical |
616 | /// register. |
617 | void replaceRegWith(Register FromReg, Register ToReg); |
618 | |
619 | /// getVRegDef - Return the machine instr that defines the specified virtual |
620 | /// register or null if none is found. This assumes that the code is in SSA |
621 | /// form, so there should only be one definition. |
622 | MachineInstr *getVRegDef(Register Reg) const; |
623 | |
624 | /// getUniqueVRegDef - Return the unique machine instr that defines the |
625 | /// specified virtual register or null if none is found. If there are |
626 | /// multiple definitions or no definition, return null. |
627 | MachineInstr *getUniqueVRegDef(Register Reg) const; |
628 | |
629 | /// clearKillFlags - Iterate over all the uses of the given register and |
630 | /// clear the kill flag from the MachineOperand. This function is used by |
631 | /// optimization passes which extend register lifetimes and need only |
632 | /// preserve conservative kill flag information. |
633 | void clearKillFlags(Register Reg) const; |
634 | |
635 | void dumpUses(Register RegNo) const; |
636 | |
637 | /// Returns true if PhysReg is unallocatable and constant throughout the |
638 | /// function. Writing to a constant register has no effect. |
639 | bool isConstantPhysReg(MCRegister PhysReg) const; |
640 | |
641 | /// Get an iterator over the pressure sets affected by the given physical or |
642 | /// virtual register. If RegUnit is physical, it must be a register unit (from |
643 | /// MCRegUnitIterator). |
644 | PSetIterator getPressureSets(Register RegUnit) const; |
645 | |
646 | //===--------------------------------------------------------------------===// |
647 | // Virtual Register Info |
648 | //===--------------------------------------------------------------------===// |
649 | |
650 | /// Return the register class of the specified virtual register. |
651 | /// This shouldn't be used directly unless \p Reg has a register class. |
652 | /// \see getRegClassOrNull when this might happen. |
653 | const TargetRegisterClass *getRegClass(Register Reg) const { |
654 | assert(isa<const TargetRegisterClass *>(VRegInfo[Reg.id()].first) && |
655 | "Register class not set, wrong accessor" ); |
656 | return cast<const TargetRegisterClass *>(Val: VRegInfo[Reg.id()].first); |
657 | } |
658 | |
659 | /// Return the register class of \p Reg, or null if Reg has not been assigned |
660 | /// a register class yet. |
661 | /// |
662 | /// \note A null register class can only happen when these two |
663 | /// conditions are met: |
664 | /// 1. Generic virtual registers are created. |
665 | /// 2. The machine function has not completely been through the |
666 | /// instruction selection process. |
667 | /// None of this condition is possible without GlobalISel for now. |
668 | /// In other words, if GlobalISel is not used or if the query happens after |
669 | /// the select pass, using getRegClass is safe. |
670 | const TargetRegisterClass *getRegClassOrNull(Register Reg) const { |
671 | const RegClassOrRegBank &Val = VRegInfo[Reg].first; |
672 | return dyn_cast_if_present<const TargetRegisterClass *>(Val); |
673 | } |
674 | |
675 | /// Return the register bank of \p Reg, or null if Reg has not been assigned |
676 | /// a register bank or has been assigned a register class. |
677 | /// \note It is possible to get the register bank from the register class via |
678 | /// RegisterBankInfo::getRegBankFromRegClass. |
679 | const RegisterBank *getRegBankOrNull(Register Reg) const { |
680 | const RegClassOrRegBank &Val = VRegInfo[Reg].first; |
681 | return dyn_cast_if_present<const RegisterBank *>(Val); |
682 | } |
683 | |
684 | /// Return the register bank or register class of \p Reg. |
685 | /// \note Before the register bank gets assigned (i.e., before the |
686 | /// RegBankSelect pass) \p Reg may not have either. |
687 | const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const { |
688 | return VRegInfo[Reg].first; |
689 | } |
690 | |
691 | /// setRegClass - Set the register class of the specified virtual register. |
692 | void setRegClass(Register Reg, const TargetRegisterClass *RC); |
693 | |
694 | /// Set the register bank to \p RegBank for \p Reg. |
695 | void setRegBank(Register Reg, const RegisterBank &RegBank); |
696 | |
697 | void setRegClassOrRegBank(Register Reg, |
698 | const RegClassOrRegBank &RCOrRB){ |
699 | VRegInfo[Reg].first = RCOrRB; |
700 | } |
701 | |
702 | /// constrainRegClass - Constrain the register class of the specified virtual |
703 | /// register to be a common subclass of RC and the current register class, |
704 | /// but only if the new class has at least MinNumRegs registers. Return the |
705 | /// new register class, or NULL if no such class exists. |
706 | /// This should only be used when the constraint is known to be trivial, like |
707 | /// GR32 -> GR32_NOSP. Beware of increasing register pressure. |
708 | /// |
709 | /// \note Assumes that the register has a register class assigned. |
710 | /// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's |
711 | /// InstructionSelect pass and constrainRegAttrs in every other pass, |
712 | /// including non-select passes of GlobalISel, instead. |
713 | const TargetRegisterClass *constrainRegClass(Register Reg, |
714 | const TargetRegisterClass *RC, |
715 | unsigned MinNumRegs = 0); |
716 | |
717 | /// Constrain the register class or the register bank of the virtual register |
718 | /// \p Reg (and low-level type) to be a common subclass or a common bank of |
719 | /// both registers provided respectively (and a common low-level type). Do |
720 | /// nothing if any of the attributes (classes, banks, or low-level types) of |
721 | /// the registers are deemed incompatible, or if the resulting register will |
722 | /// have a class smaller than before and of size less than \p MinNumRegs. |
723 | /// Return true if such register attributes exist, false otherwise. |
724 | /// |
725 | /// \note Use this method instead of constrainRegClass and |
726 | /// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG |
727 | /// ISel / FastISel and GlobalISel's InstructionSelect pass respectively. |
728 | bool constrainRegAttrs(Register Reg, Register ConstrainingReg, |
729 | unsigned MinNumRegs = 0); |
730 | |
731 | /// recomputeRegClass - Try to find a legal super-class of Reg's register |
732 | /// class that still satisfies the constraints from the instructions using |
733 | /// Reg. Returns true if Reg was upgraded. |
734 | /// |
735 | /// This method can be used after constraints have been removed from a |
736 | /// virtual register, for example after removing instructions or splitting |
737 | /// the live range. |
738 | bool recomputeRegClass(Register Reg); |
739 | |
740 | /// createVirtualRegister - Create and return a new virtual register in the |
741 | /// function with the specified register class. |
742 | Register createVirtualRegister(const TargetRegisterClass *RegClass, |
743 | StringRef Name = "" ); |
744 | |
745 | /// All attributes(register class or bank and low-level type) a virtual |
746 | /// register can have. |
747 | struct VRegAttrs { |
748 | RegClassOrRegBank RCOrRB; |
749 | LLT Ty; |
750 | }; |
751 | |
752 | /// Returns register class or bank and low level type of \p Reg. Always safe |
753 | /// to use. Special values are returned when \p Reg does not have some of the |
754 | /// attributes. |
755 | VRegAttrs getVRegAttrs(Register Reg) { |
756 | return {.RCOrRB: getRegClassOrRegBank(Reg), .Ty: getType(Reg)}; |
757 | } |
758 | |
759 | /// Create and return a new virtual register in the function with the |
760 | /// specified register attributes(register class or bank and low level type). |
761 | Register createVirtualRegister(VRegAttrs RegAttr, StringRef Name = "" ); |
762 | |
763 | /// Create and return a new virtual register in the function with the same |
764 | /// attributes as the given register. |
765 | Register cloneVirtualRegister(Register VReg, StringRef Name = "" ); |
766 | |
767 | /// Get the low-level type of \p Reg or LLT{} if Reg is not a generic |
768 | /// (target independent) virtual register. |
769 | LLT getType(Register Reg) const { |
770 | if (Reg.isVirtual() && VRegToType.inBounds(n: Reg)) |
771 | return VRegToType[Reg]; |
772 | return LLT{}; |
773 | } |
774 | |
775 | /// Set the low-level type of \p VReg to \p Ty. |
776 | void setType(Register VReg, LLT Ty); |
777 | |
778 | /// Create and return a new generic virtual register with low-level |
779 | /// type \p Ty. |
780 | Register createGenericVirtualRegister(LLT Ty, StringRef Name = "" ); |
781 | |
782 | /// Remove all types associated to virtual registers (after instruction |
783 | /// selection and constraining of all generic virtual registers). |
784 | void clearVirtRegTypes(); |
785 | |
786 | /// Creates a new virtual register that has no register class, register bank |
787 | /// or size assigned yet. This is only allowed to be used |
788 | /// temporarily while constructing machine instructions. Most operations are |
789 | /// undefined on an incomplete register until one of setRegClass(), |
790 | /// setRegBank() or setSize() has been called on it. |
791 | Register createIncompleteVirtualRegister(StringRef Name = "" ); |
792 | |
793 | /// getNumVirtRegs - Return the number of virtual registers created. |
794 | unsigned getNumVirtRegs() const { return VRegInfo.size(); } |
795 | |
796 | /// clearVirtRegs - Remove all virtual registers (after physreg assignment). |
797 | void clearVirtRegs(); |
798 | |
799 | /// setRegAllocationHint - Specify a register allocation hint for the |
800 | /// specified virtual register. This is typically used by target, and in case |
801 | /// of an earlier hint it will be overwritten. |
802 | void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) { |
803 | assert(VReg.isVirtual()); |
804 | RegAllocHints[VReg].first = Type; |
805 | RegAllocHints[VReg].second.clear(); |
806 | RegAllocHints[VReg].second.push_back(Elt: PrefReg); |
807 | } |
808 | |
809 | /// addRegAllocationHint - Add a register allocation hint to the hints |
810 | /// vector for VReg. |
811 | void addRegAllocationHint(Register VReg, Register PrefReg) { |
812 | assert(VReg.isVirtual()); |
813 | RegAllocHints[VReg].second.push_back(Elt: PrefReg); |
814 | } |
815 | |
816 | /// Specify the preferred (target independent) register allocation hint for |
817 | /// the specified virtual register. |
818 | void setSimpleHint(Register VReg, Register PrefReg) { |
819 | setRegAllocationHint(VReg, /*Type=*/Type: 0, PrefReg); |
820 | } |
821 | |
822 | void clearSimpleHint(Register VReg) { |
823 | assert (!RegAllocHints[VReg].first && |
824 | "Expected to clear a non-target hint!" ); |
825 | RegAllocHints[VReg].second.clear(); |
826 | } |
827 | |
828 | /// getRegAllocationHint - Return the register allocation hint for the |
829 | /// specified virtual register. If there are many hints, this returns the |
830 | /// one with the greatest weight. |
831 | std::pair<unsigned, Register> getRegAllocationHint(Register VReg) const { |
832 | assert(VReg.isVirtual()); |
833 | Register BestHint = (RegAllocHints[VReg.id()].second.size() ? |
834 | RegAllocHints[VReg.id()].second[0] : Register()); |
835 | return {RegAllocHints[VReg.id()].first, BestHint}; |
836 | } |
837 | |
838 | /// getSimpleHint - same as getRegAllocationHint except it will only return |
839 | /// a target independent hint. |
840 | Register getSimpleHint(Register VReg) const { |
841 | assert(VReg.isVirtual()); |
842 | std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg); |
843 | return Hint.first ? Register() : Hint.second; |
844 | } |
845 | |
846 | /// getRegAllocationHints - Return a reference to the vector of all |
847 | /// register allocation hints for VReg. |
848 | const std::pair<unsigned, SmallVector<Register, 4>> & |
849 | getRegAllocationHints(Register VReg) const { |
850 | assert(VReg.isVirtual()); |
851 | return RegAllocHints[VReg]; |
852 | } |
853 | |
854 | /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the |
855 | /// specified register as undefined which causes the DBG_VALUE to be |
856 | /// deleted during LiveDebugVariables analysis. |
857 | void markUsesInDebugValueAsUndef(Register Reg) const; |
858 | |
859 | /// updateDbgUsersToReg - Update a collection of debug instructions |
860 | /// to refer to the designated register. |
861 | void updateDbgUsersToReg(MCRegister OldReg, MCRegister NewReg, |
862 | ArrayRef<MachineInstr *> Users) const { |
863 | // If this operand is a register, check whether it overlaps with OldReg. |
864 | // If it does, replace with NewReg. |
865 | auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) { |
866 | if (Op.isReg() && |
867 | getTargetRegisterInfo()->regsOverlap(RegA: Op.getReg(), RegB: OldReg)) |
868 | Op.setReg(NewReg); |
869 | }; |
870 | |
871 | // Iterate through (possibly several) operands to DBG_VALUEs and update |
872 | // each. For DBG_PHIs, only one operand will be present. |
873 | for (MachineInstr *MI : Users) { |
874 | if (MI->isDebugValue()) { |
875 | for (auto &Op : MI->debug_operands()) |
876 | UpdateOp(Op); |
877 | assert(MI->hasDebugOperandForReg(NewReg) && |
878 | "Expected debug value to have some overlap with OldReg" ); |
879 | } else if (MI->isDebugPHI()) { |
880 | UpdateOp(MI->getOperand(i: 0)); |
881 | } else { |
882 | llvm_unreachable("Non-DBG_VALUE, Non-DBG_PHI debug instr updated" ); |
883 | } |
884 | } |
885 | } |
886 | |
887 | /// Return true if the specified register is modified in this function. |
888 | /// This checks that no defining machine operands exist for the register or |
889 | /// any of its aliases. Definitions found on functions marked noreturn are |
890 | /// ignored, to consider them pass 'true' for optional parameter |
891 | /// SkipNoReturnDef. The register is also considered modified when it is set |
892 | /// in the UsedPhysRegMask. |
893 | bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const; |
894 | |
895 | /// Return true if the specified register is modified or read in this |
896 | /// function. This checks that no machine operands exist for the register or |
897 | /// any of its aliases. If SkipRegMaskTest is false, the register is |
898 | /// considered used when it is set in the UsedPhysRegMask. |
899 | bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest = false) const; |
900 | |
901 | /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. |
902 | /// This corresponds to the bit mask attached to register mask operands. |
903 | void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { |
904 | UsedPhysRegMask.setBitsNotInMask(Mask: RegMask); |
905 | } |
906 | |
907 | const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; } |
908 | |
909 | //===--------------------------------------------------------------------===// |
910 | // Reserved Register Info |
911 | //===--------------------------------------------------------------------===// |
912 | // |
913 | // The set of reserved registers must be invariant during register |
914 | // allocation. For example, the target cannot suddenly decide it needs a |
915 | // frame pointer when the register allocator has already used the frame |
916 | // pointer register for something else. |
917 | // |
918 | // These methods can be used by target hooks like hasFP() to avoid changing |
919 | // the reserved register set during register allocation. |
920 | |
921 | /// freezeReservedRegs - Called by the register allocator to freeze the set |
922 | /// of reserved registers before allocation begins. |
923 | void freezeReservedRegs(); |
924 | |
925 | /// reserveReg -- Mark a register as reserved so checks like isAllocatable |
926 | /// will not suggest using it. This should not be used during the middle |
927 | /// of a function walk, or when liveness info is available. |
928 | void reserveReg(MCRegister PhysReg, const TargetRegisterInfo *TRI) { |
929 | assert(reservedRegsFrozen() && |
930 | "Reserved registers haven't been frozen yet. " ); |
931 | MCRegAliasIterator R(PhysReg, TRI, true); |
932 | |
933 | for (; R.isValid(); ++R) |
934 | ReservedRegs.set(*R); |
935 | } |
936 | |
937 | /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called |
938 | /// to ensure the set of reserved registers stays constant. |
939 | bool reservedRegsFrozen() const { |
940 | return !ReservedRegs.empty(); |
941 | } |
942 | |
943 | /// canReserveReg - Returns true if PhysReg can be used as a reserved |
944 | /// register. Any register can be reserved before freezeReservedRegs() is |
945 | /// called. |
946 | bool canReserveReg(MCRegister PhysReg) const { |
947 | return !reservedRegsFrozen() || ReservedRegs.test(Idx: PhysReg); |
948 | } |
949 | |
950 | /// getReservedRegs - Returns a reference to the frozen set of reserved |
951 | /// registers. This method should always be preferred to calling |
952 | /// TRI::getReservedRegs() when possible. |
953 | const BitVector &getReservedRegs() const { |
954 | assert(reservedRegsFrozen() && |
955 | "Reserved registers haven't been frozen yet. " |
956 | "Use TRI::getReservedRegs()." ); |
957 | return ReservedRegs; |
958 | } |
959 | |
960 | /// isReserved - Returns true when PhysReg is a reserved register. |
961 | /// |
962 | /// Reserved registers may belong to an allocatable register class, but the |
963 | /// target has explicitly requested that they are not used. |
964 | bool isReserved(MCRegister PhysReg) const { |
965 | return getReservedRegs().test(Idx: PhysReg.id()); |
966 | } |
967 | |
968 | /// Returns true when the given register unit is considered reserved. |
969 | /// |
970 | /// Register units are considered reserved when for at least one of their |
971 | /// root registers, the root register and all super registers are reserved. |
972 | /// This currently iterates the register hierarchy and may be slower than |
973 | /// expected. |
974 | bool isReservedRegUnit(unsigned Unit) const; |
975 | |
976 | /// isAllocatable - Returns true when PhysReg belongs to an allocatable |
977 | /// register class and it hasn't been reserved. |
978 | /// |
979 | /// Allocatable registers may show up in the allocation order of some virtual |
980 | /// register, so a register allocator needs to track its liveness and |
981 | /// availability. |
982 | bool isAllocatable(MCRegister PhysReg) const { |
983 | return getTargetRegisterInfo()->isInAllocatableClass(RegNo: PhysReg) && |
984 | !isReserved(PhysReg); |
985 | } |
986 | |
987 | //===--------------------------------------------------------------------===// |
988 | // LiveIn Management |
989 | //===--------------------------------------------------------------------===// |
990 | |
991 | /// addLiveIn - Add the specified register as a live-in. Note that it |
992 | /// is an error to add the same register to the same set more than once. |
993 | void addLiveIn(MCRegister Reg, Register vreg = Register()) { |
994 | LiveIns.push_back(x: std::make_pair(x&: Reg, y&: vreg)); |
995 | } |
996 | |
997 | // Iteration support for the live-ins set. It's kept in sorted order |
998 | // by register number. |
999 | using livein_iterator = |
1000 | std::vector<std::pair<MCRegister,Register>>::const_iterator; |
1001 | livein_iterator livein_begin() const { return LiveIns.begin(); } |
1002 | livein_iterator livein_end() const { return LiveIns.end(); } |
1003 | bool livein_empty() const { return LiveIns.empty(); } |
1004 | |
1005 | ArrayRef<std::pair<MCRegister, Register>> liveins() const { |
1006 | return LiveIns; |
1007 | } |
1008 | |
1009 | bool isLiveIn(Register Reg) const; |
1010 | |
1011 | /// getLiveInPhysReg - If VReg is a live-in virtual register, return the |
1012 | /// corresponding live-in physical register. |
1013 | MCRegister getLiveInPhysReg(Register VReg) const; |
1014 | |
1015 | /// getLiveInVirtReg - If PReg is a live-in physical register, return the |
1016 | /// corresponding live-in virtual register. |
1017 | Register getLiveInVirtReg(MCRegister PReg) const; |
1018 | |
1019 | /// EmitLiveInCopies - Emit copies to initialize livein virtual registers |
1020 | /// into the given entry block. |
1021 | void EmitLiveInCopies(MachineBasicBlock *EntryMBB, |
1022 | const TargetRegisterInfo &TRI, |
1023 | const TargetInstrInfo &TII); |
1024 | |
1025 | /// Returns a mask covering all bits that can appear in lane masks of |
1026 | /// subregisters of the virtual register @p Reg. |
1027 | LaneBitmask getMaxLaneMaskForVReg(Register Reg) const; |
1028 | |
1029 | /// defusechain_iterator - This class provides iterator support for machine |
1030 | /// operands in the function that use or define a specific register. If |
1031 | /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it |
1032 | /// returns defs. If neither are true then you are silly and it always |
1033 | /// returns end(). If SkipDebug is true it skips uses marked Debug |
1034 | /// when incrementing. |
1035 | template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand, |
1036 | bool ByInstr, bool ByBundle> |
1037 | class defusechain_iterator { |
1038 | friend class MachineRegisterInfo; |
1039 | |
1040 | public: |
1041 | using iterator_category = std::forward_iterator_tag; |
1042 | using value_type = MachineOperand; |
1043 | using difference_type = std::ptrdiff_t; |
1044 | using pointer = value_type *; |
1045 | using reference = value_type &; |
1046 | |
1047 | private: |
1048 | MachineOperand *Op = nullptr; |
1049 | |
1050 | explicit defusechain_iterator(MachineOperand *op) : Op(op) { |
1051 | // If the first node isn't one we're interested in, advance to one that |
1052 | // we are interested in. |
1053 | if (op) { |
1054 | if ((!ReturnUses && op->isUse()) || |
1055 | (!ReturnDefs && op->isDef()) || |
1056 | (SkipDebug && op->isDebug())) |
1057 | advance(); |
1058 | } |
1059 | } |
1060 | |
1061 | void advance() { |
1062 | assert(Op && "Cannot increment end iterator!" ); |
1063 | Op = getNextOperandForReg(MO: Op); |
1064 | |
1065 | // All defs come before the uses, so stop def_iterator early. |
1066 | if (!ReturnUses) { |
1067 | if (Op) { |
1068 | if (Op->isUse()) |
1069 | Op = nullptr; |
1070 | else |
1071 | assert(!Op->isDebug() && "Can't have debug defs" ); |
1072 | } |
1073 | } else { |
1074 | // If this is an operand we don't care about, skip it. |
1075 | while (Op && ((!ReturnDefs && Op->isDef()) || |
1076 | (SkipDebug && Op->isDebug()))) |
1077 | Op = getNextOperandForReg(MO: Op); |
1078 | } |
1079 | } |
1080 | |
1081 | public: |
1082 | defusechain_iterator() = default; |
1083 | |
1084 | bool operator==(const defusechain_iterator &x) const { |
1085 | return Op == x.Op; |
1086 | } |
1087 | bool operator!=(const defusechain_iterator &x) const { |
1088 | return !operator==(x); |
1089 | } |
1090 | |
1091 | /// atEnd - return true if this iterator is equal to reg_end() on the value. |
1092 | bool atEnd() const { return Op == nullptr; } |
1093 | |
1094 | // Iterator traversal: forward iteration only |
1095 | defusechain_iterator &operator++() { // Preincrement |
1096 | assert(Op && "Cannot increment end iterator!" ); |
1097 | if (ByOperand) |
1098 | advance(); |
1099 | else if (ByInstr) { |
1100 | MachineInstr *P = Op->getParent(); |
1101 | do { |
1102 | advance(); |
1103 | } while (Op && Op->getParent() == P); |
1104 | } else if (ByBundle) { |
1105 | MachineBasicBlock::instr_iterator P = |
1106 | getBundleStart(I: Op->getParent()->getIterator()); |
1107 | do { |
1108 | advance(); |
1109 | } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P); |
1110 | } |
1111 | |
1112 | return *this; |
1113 | } |
1114 | defusechain_iterator operator++(int) { // Postincrement |
1115 | defusechain_iterator tmp = *this; ++*this; return tmp; |
1116 | } |
1117 | |
1118 | /// getOperandNo - Return the operand # of this MachineOperand in its |
1119 | /// MachineInstr. |
1120 | unsigned getOperandNo() const { |
1121 | assert(Op && "Cannot dereference end iterator!" ); |
1122 | return Op - &Op->getParent()->getOperand(i: 0); |
1123 | } |
1124 | |
1125 | // Retrieve a reference to the current operand. |
1126 | MachineOperand &operator*() const { |
1127 | assert(Op && "Cannot dereference end iterator!" ); |
1128 | return *Op; |
1129 | } |
1130 | |
1131 | MachineOperand *operator->() const { |
1132 | assert(Op && "Cannot dereference end iterator!" ); |
1133 | return Op; |
1134 | } |
1135 | }; |
1136 | |
1137 | /// defusechain_iterator - This class provides iterator support for machine |
1138 | /// operands in the function that use or define a specific register. If |
1139 | /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it |
1140 | /// returns defs. If neither are true then you are silly and it always |
1141 | /// returns end(). If SkipDebug is true it skips uses marked Debug |
1142 | /// when incrementing. |
1143 | template <bool ReturnUses, bool ReturnDefs, bool SkipDebug, bool ByOperand, |
1144 | bool ByInstr, bool ByBundle> |
1145 | class defusechain_instr_iterator { |
1146 | friend class MachineRegisterInfo; |
1147 | |
1148 | public: |
1149 | using iterator_category = std::forward_iterator_tag; |
1150 | using value_type = MachineInstr; |
1151 | using difference_type = std::ptrdiff_t; |
1152 | using pointer = value_type *; |
1153 | using reference = value_type &; |
1154 | |
1155 | private: |
1156 | MachineOperand *Op = nullptr; |
1157 | |
1158 | explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) { |
1159 | // If the first node isn't one we're interested in, advance to one that |
1160 | // we are interested in. |
1161 | if (op) { |
1162 | if ((!ReturnUses && op->isUse()) || |
1163 | (!ReturnDefs && op->isDef()) || |
1164 | (SkipDebug && op->isDebug())) |
1165 | advance(); |
1166 | } |
1167 | } |
1168 | |
1169 | void advance() { |
1170 | assert(Op && "Cannot increment end iterator!" ); |
1171 | Op = getNextOperandForReg(MO: Op); |
1172 | |
1173 | // All defs come before the uses, so stop def_iterator early. |
1174 | if (!ReturnUses) { |
1175 | if (Op) { |
1176 | if (Op->isUse()) |
1177 | Op = nullptr; |
1178 | else |
1179 | assert(!Op->isDebug() && "Can't have debug defs" ); |
1180 | } |
1181 | } else { |
1182 | // If this is an operand we don't care about, skip it. |
1183 | while (Op && ((!ReturnDefs && Op->isDef()) || |
1184 | (SkipDebug && Op->isDebug()))) |
1185 | Op = getNextOperandForReg(MO: Op); |
1186 | } |
1187 | } |
1188 | |
1189 | public: |
1190 | defusechain_instr_iterator() = default; |
1191 | |
1192 | bool operator==(const defusechain_instr_iterator &x) const { |
1193 | return Op == x.Op; |
1194 | } |
1195 | bool operator!=(const defusechain_instr_iterator &x) const { |
1196 | return !operator==(x); |
1197 | } |
1198 | |
1199 | /// atEnd - return true if this iterator is equal to reg_end() on the value. |
1200 | bool atEnd() const { return Op == nullptr; } |
1201 | |
1202 | // Iterator traversal: forward iteration only |
1203 | defusechain_instr_iterator &operator++() { // Preincrement |
1204 | assert(Op && "Cannot increment end iterator!" ); |
1205 | if (ByOperand) |
1206 | advance(); |
1207 | else if (ByInstr) { |
1208 | MachineInstr *P = Op->getParent(); |
1209 | do { |
1210 | advance(); |
1211 | } while (Op && Op->getParent() == P); |
1212 | } else if (ByBundle) { |
1213 | MachineBasicBlock::instr_iterator P = |
1214 | getBundleStart(I: Op->getParent()->getIterator()); |
1215 | do { |
1216 | advance(); |
1217 | } while (Op && getBundleStart(I: Op->getParent()->getIterator()) == P); |
1218 | } |
1219 | |
1220 | return *this; |
1221 | } |
1222 | defusechain_instr_iterator operator++(int) { // Postincrement |
1223 | defusechain_instr_iterator tmp = *this; ++*this; return tmp; |
1224 | } |
1225 | |
1226 | // Retrieve a reference to the current operand. |
1227 | MachineInstr &operator*() const { |
1228 | assert(Op && "Cannot dereference end iterator!" ); |
1229 | if (ByBundle) |
1230 | return *getBundleStart(I: Op->getParent()->getIterator()); |
1231 | return *Op->getParent(); |
1232 | } |
1233 | |
1234 | MachineInstr *operator->() const { return &operator*(); } |
1235 | }; |
1236 | }; |
1237 | |
1238 | /// Iterate over the pressure sets affected by the given physical or virtual |
1239 | /// register. If Reg is physical, it must be a register unit (from |
1240 | /// MCRegUnitIterator). |
1241 | class PSetIterator { |
1242 | const int *PSet = nullptr; |
1243 | unsigned Weight = 0; |
1244 | |
1245 | public: |
1246 | PSetIterator() = default; |
1247 | |
1248 | PSetIterator(Register RegUnit, const MachineRegisterInfo *MRI) { |
1249 | const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo(); |
1250 | if (RegUnit.isVirtual()) { |
1251 | const TargetRegisterClass *RC = MRI->getRegClass(Reg: RegUnit); |
1252 | PSet = TRI->getRegClassPressureSets(RC); |
1253 | Weight = TRI->getRegClassWeight(RC).RegWeight; |
1254 | } else { |
1255 | PSet = TRI->getRegUnitPressureSets(RegUnit); |
1256 | Weight = TRI->getRegUnitWeight(RegUnit); |
1257 | } |
1258 | if (*PSet == -1) |
1259 | PSet = nullptr; |
1260 | } |
1261 | |
1262 | bool isValid() const { return PSet; } |
1263 | |
1264 | unsigned getWeight() const { return Weight; } |
1265 | |
1266 | unsigned operator*() const { return *PSet; } |
1267 | |
1268 | void operator++() { |
1269 | assert(isValid() && "Invalid PSetIterator." ); |
1270 | ++PSet; |
1271 | if (*PSet == -1) |
1272 | PSet = nullptr; |
1273 | } |
1274 | }; |
1275 | |
1276 | inline PSetIterator |
1277 | MachineRegisterInfo::getPressureSets(Register RegUnit) const { |
1278 | return PSetIterator(RegUnit, this); |
1279 | } |
1280 | |
1281 | } // end namespace llvm |
1282 | |
1283 | #endif // LLVM_CODEGEN_MACHINEREGISTERINFO_H |
1284 | |