1	//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// This file contains the declaration of the MachineInstr class, which is the
10	// basic representation for all target dependent machine instructions used by
11	// the back end.
12	//
13	//===----------------------------------------------------------------------===//
14
15	#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16	#define LLVM_CODEGEN_MACHINEINSTR_H
17
18	#include "llvm/ADT/DenseMapInfo.h"
19	#include "llvm/ADT/PointerSumType.h"
20	#include "llvm/ADT/ilist.h"
21	#include "llvm/ADT/ilist_node.h"
22	#include "llvm/ADT/iterator_range.h"
23	#include "llvm/Analysis/MemoryLocation.h"
24	#include "llvm/CodeGen/MachineMemOperand.h"
25	#include "llvm/CodeGen/MachineOperand.h"
26	#include "llvm/CodeGen/TargetOpcodes.h"
27	#include "llvm/IR/DebugLoc.h"
28	#include "llvm/IR/InlineAsm.h"
29	#include "llvm/MC/MCInstrDesc.h"
30	#include "llvm/MC/MCSymbol.h"
31	#include "llvm/Support/ArrayRecycler.h"
32	#include "llvm/Support/MathExtras.h"
33	#include "llvm/Support/TrailingObjects.h"
34	#include <algorithm>
35	#include <cassert>
36	#include <cstdint>
37	#include <utility>
38
39	namespace llvm {
40
41	class DILabel;
42	class Instruction;
43	class MDNode;
44	class AAResults;
45	template <typename T> class ArrayRef;
46	class DIExpression;
47	class DILocalVariable;
48	class MachineBasicBlock;
49	class MachineFunction;
50	class MachineRegisterInfo;
51	class ModuleSlotTracker;
52	class raw_ostream;
53	template <typename T> class SmallVectorImpl;
54	class SmallBitVector;
55	class StringRef;
56	class TargetInstrInfo;
57	class TargetRegisterClass;
58	class TargetRegisterInfo;
59
60	//===----------------------------------------------------------------------===//
61	/// Representation of each machine instruction.
62	///
63	/// This class isn't a POD type, but it must have a trivial destructor. When a
64	/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
65	/// without having their destructor called.
66	///
67	class MachineInstr
68	: public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
69	ilist_sentinel_tracking<true>> {
70	public:
71	using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
72
73	/// Flags to specify different kinds of comments to output in
74	/// assembly code. These flags carry semantic information not
75	/// otherwise easily derivable from the IR text.
76	///
77	enum CommentFlag {
78	ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
79	NoSchedComment = 0x2,
80	TAsmComments = 0x4 // Target Asm comments should start from this value.
81	};
82
83	enum MIFlag {
84	NoFlags = 0,
85	FrameSetup = 1 << 0, // Instruction is used as a part of
86	// function frame setup code.
87	FrameDestroy = 1 << 1, // Instruction is used as a part of
88	// function frame destruction code.
89	BundledPred = 1 << 2, // Instruction has bundled predecessors.
90	BundledSucc = 1 << 3, // Instruction has bundled successors.
91	FmNoNans = 1 << 4, // Instruction does not support Fast
92	// math nan values.
93	FmNoInfs = 1 << 5, // Instruction does not support Fast
94	// math infinity values.
95	FmNsz = 1 << 6, // Instruction is not required to retain
96	// signed zero values.
97	FmArcp = 1 << 7, // Instruction supports Fast math
98	// reciprocal approximations.
99	FmContract = 1 << 8, // Instruction supports Fast math
100	// contraction operations like fma.
101	FmAfn = 1 << 9, // Instruction may map to Fast math
102	// intrinsic approximation.
103	FmReassoc = 1 << 10, // Instruction supports Fast math
104	// reassociation of operand order.
105	NoUWrap = 1 << 11, // Instruction supports binary operator
106	// no unsigned wrap.
107	NoSWrap = 1 << 12, // Instruction supports binary operator
108	// no signed wrap.
109	IsExact = 1 << 13, // Instruction supports division is
110	// known to be exact.
111	NoFPExcept = 1 << 14, // Instruction does not raise
112	// floatint-point exceptions.
113	NoMerge = 1 << 15, // Passes that drop source location info
114	// (e.g. branch folding) should skip
115	// this instruction.
116	Unpredictable = 1 << 16, // Instruction with unpredictable condition.
117	NoConvergent = 1 << 17, // Call does not require convergence guarantees.
118	NonNeg = 1 << 18, // The operand is non-negative.
119	Disjoint = 1 << 19, // Each bit is zero in at least one of the inputs.
120	};
121
122	private:
123	const MCInstrDesc *MCID; // Instruction descriptor.
124	MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
125
126	// Operands are allocated by an ArrayRecycler.
127	MachineOperand *Operands = nullptr; // Pointer to the first operand.
128
129	#define LLVM_MI_NUMOPERANDS_BITS 24
130	#define LLVM_MI_FLAGS_BITS 24
131	#define LLVM_MI_ASMPRINTERFLAGS_BITS 8
132
133	/// Number of operands on instruction.
134	uint32_t NumOperands : LLVM_MI_NUMOPERANDS_BITS;
135
136	// OperandCapacity has uint8_t size, so it should be next to NumOperands
137	// to properly pack.
138	using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
139	OperandCapacity CapOperands; // Capacity of the Operands array.
140
141	/// Various bits of additional information about the machine instruction.
142	uint32_t Flags : LLVM_MI_FLAGS_BITS;
143
144	/// Various bits of information used by the AsmPrinter to emit helpful
145	/// comments. This is *not* semantic information. Do not use this for
146	/// anything other than to convey comment information to AsmPrinter.
147	uint8_t AsmPrinterFlags : LLVM_MI_ASMPRINTERFLAGS_BITS;
148
149	/// Internal implementation detail class that provides out-of-line storage for
150	/// extra info used by the machine instruction when this info cannot be stored
151	/// in-line within the instruction itself.
152	///
153	/// This has to be defined eagerly due to the implementation constraints of
154	/// `PointerSumType` where it is used.
155	class ExtraInfo final : TrailingObjects<ExtraInfo, MachineMemOperand *,
156	MCSymbol *, MDNode *, uint32_t> {
157	public:
158	static ExtraInfo *create(BumpPtrAllocator &Allocator,
159	ArrayRef<MachineMemOperand *> MMOs,
160	MCSymbol *PreInstrSymbol = nullptr,
161	MCSymbol *PostInstrSymbol = nullptr,
162	MDNode *HeapAllocMarker = nullptr,
163	MDNode *PCSections = nullptr, uint32_t CFIType = 0,
164	MDNode *MMRAs = nullptr) {
165	bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
166	bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
167	bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
168	bool HasMMRAs = MMRAs != nullptr;
169	bool HasCFIType = CFIType != 0;
170	bool HasPCSections = PCSections != nullptr;
171	auto *Result = new (Allocator.Allocate(
172	Size: totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *, uint32_t>(
173	Counts: MMOs.size(), Counts: HasPreInstrSymbol + HasPostInstrSymbol,
174	Counts: HasHeapAllocMarker + HasPCSections + HasMMRAs, Counts: HasCFIType),
175	Alignment: alignof(ExtraInfo)))
176	ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
177	HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs);
178
179	// Copy the actual data into the trailing objects.
180	std::copy(first: MMOs.begin(), last: MMOs.end(),
181	result: Result->getTrailingObjects<MachineMemOperand *>());
182
183	unsigned MDNodeIdx = 0;
184
185	if (HasPreInstrSymbol)
186	Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
187	if (HasPostInstrSymbol)
188	Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
189	PostInstrSymbol;
190	if (HasHeapAllocMarker)
191	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = HeapAllocMarker;
192	if (HasPCSections)
193	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = PCSections;
194	if (HasCFIType)
195	Result->getTrailingObjects<uint32_t>()[0] = CFIType;
196	if (HasMMRAs)
197	Result->getTrailingObjects<MDNode *>()[MDNodeIdx++] = MMRAs;
198
199	return Result;
200	}
201
202	ArrayRef<MachineMemOperand *> getMMOs() const {
203	return ArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
204	}
205
206	MCSymbol *getPreInstrSymbol() const {
207	return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
208	}
209
210	MCSymbol *getPostInstrSymbol() const {
211	return HasPostInstrSymbol
212	? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
213	: nullptr;
214	}
215
216	MDNode *getHeapAllocMarker() const {
217	return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
218	}
219
220	MDNode *getPCSections() const {
221	return HasPCSections
222	? getTrailingObjects<MDNode *>()[HasHeapAllocMarker]
223	: nullptr;
224	}
225
226	uint32_t getCFIType() const {
227	return HasCFIType ? getTrailingObjects<uint32_t>()[0] : 0;
228	}
229
230	MDNode *getMMRAMetadata() const {
231	return HasMMRAs ? getTrailingObjects<MDNode *>()[HasHeapAllocMarker +
232	HasPCSections]
233	: nullptr;
234	}
235
236	private:
237	friend TrailingObjects;
238
239	// Description of the extra info, used to interpret the actual optional
240	// data appended.
241	//
242	// Note that this is not terribly space optimized. This leaves a great deal
243	// of flexibility to fit more in here later.
244	const int NumMMOs;
245	const bool HasPreInstrSymbol;
246	const bool HasPostInstrSymbol;
247	const bool HasHeapAllocMarker;
248	const bool HasPCSections;
249	const bool HasCFIType;
250	const bool HasMMRAs;
251
252	// Implement the `TrailingObjects` internal API.
253	size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
254	return NumMMOs;
255	}
256	size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
257	return HasPreInstrSymbol + HasPostInstrSymbol;
258	}
259	size_t numTrailingObjects(OverloadToken<MDNode *>) const {
260	return HasHeapAllocMarker + HasPCSections;
261	}
262	size_t numTrailingObjects(OverloadToken<uint32_t>) const {
263	return HasCFIType;
264	}
265
266	// Just a boring constructor to allow us to initialize the sizes. Always use
267	// the `create` routine above.
268	ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
269	bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType,
270	bool HasMMRAs)
271	: NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
272	HasPostInstrSymbol(HasPostInstrSymbol),
273	HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections),
274	HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {}
275	};
276
277	/// Enumeration of the kinds of inline extra info available. It is important
278	/// that the `MachineMemOperand` inline kind has a tag value of zero to make
279	/// it accessible as an `ArrayRef`.
280	enum ExtraInfoInlineKinds {
281	EIIK_MMO = 0,
282	EIIK_PreInstrSymbol,
283	EIIK_PostInstrSymbol,
284	EIIK_OutOfLine
285	};
286
287	// We store extra information about the instruction here. The common case is
288	// expected to be nothing or a single pointer (typically a MMO or a symbol).
289	// We work to optimize this common case by storing it inline here rather than
290	// requiring a separate allocation, but we fall back to an allocation when
291	// multiple pointers are needed.
292	PointerSumType<ExtraInfoInlineKinds,
293	PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
294	PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
295	PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
296	PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
297	Info;
298
299	DebugLoc DbgLoc; // Source line information.
300
301	/// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
302	/// defined by this instruction.
303	unsigned DebugInstrNum;
304
305	// Intrusive list support
306	friend struct ilist_traits<MachineInstr>;
307	friend struct ilist_callback_traits<MachineBasicBlock>;
308	void setParent(MachineBasicBlock *P) { Parent = P; }
309
310	/// This constructor creates a copy of the given
311	/// MachineInstr in the given MachineFunction.
312	MachineInstr(MachineFunction &, const MachineInstr &);
313
314	/// This constructor create a MachineInstr and add the implicit operands.
315	/// It reserves space for number of operands specified by
316	/// MCInstrDesc. An explicit DebugLoc is supplied.
317	MachineInstr(MachineFunction &, const MCInstrDesc &TID, DebugLoc DL,
318	bool NoImp = false);
319
320	// MachineInstrs are pool-allocated and owned by MachineFunction.
321	friend class MachineFunction;
322
323	void
324	dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
325	SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
326
327	static bool opIsRegDef(const MachineOperand &Op) {
328	return Op.isReg() && Op.isDef();
329	}
330
331	static bool opIsRegUse(const MachineOperand &Op) {
332	return Op.isReg() && Op.isUse();
333	}
334
335	public:
336	MachineInstr(const MachineInstr &) = delete;
337	MachineInstr &operator=(const MachineInstr &) = delete;
338	// Use MachineFunction::DeleteMachineInstr() instead.
339	~MachineInstr() = delete;
340
341	const MachineBasicBlock* getParent() const { return Parent; }
342	MachineBasicBlock* getParent() { return Parent; }
343
344	/// Move the instruction before \p MovePos.
345	void moveBefore(MachineInstr *MovePos);
346
347	/// Return the function that contains the basic block that this instruction
348	/// belongs to.
349	///
350	/// Note: this is undefined behaviour if the instruction does not have a
351	/// parent.
352	const MachineFunction *getMF() const;
353	MachineFunction *getMF() {
354	return const_cast<MachineFunction *>(
355	static_cast<const MachineInstr *>(this)->getMF());
356	}
357
358	/// Return the asm printer flags bitvector.
359	uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
360
361	/// Clear the AsmPrinter bitvector.
362	void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
363
364	/// Return whether an AsmPrinter flag is set.
365	bool getAsmPrinterFlag(CommentFlag Flag) const {
366	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
367	"Flag is out of range for the AsmPrinterFlags field");
368	return AsmPrinterFlags & Flag;
369	}
370
371	/// Set a flag for the AsmPrinter.
372	void setAsmPrinterFlag(uint8_t Flag) {
373	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
374	"Flag is out of range for the AsmPrinterFlags field");
375	AsmPrinterFlags |= Flag;
376	}
377
378	/// Clear specific AsmPrinter flags.
379	void clearAsmPrinterFlag(CommentFlag Flag) {
380	assert(isUInt<LLVM_MI_ASMPRINTERFLAGS_BITS>(unsigned(Flag)) &&
381	"Flag is out of range for the AsmPrinterFlags field");
382	AsmPrinterFlags &= ~Flag;
383	}
384
385	/// Return the MI flags bitvector.
386	uint32_t getFlags() const {
387	return Flags;
388	}
389
390	/// Return whether an MI flag is set.
391	bool getFlag(MIFlag Flag) const {
392	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
393	"Flag is out of range for the Flags field");
394	return Flags & Flag;
395	}
396
397	/// Set a MI flag.
398	void setFlag(MIFlag Flag) {
399	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
400	"Flag is out of range for the Flags field");
401	Flags |= (uint32_t)Flag;
402	}
403
404	void setFlags(unsigned flags) {
405	assert(isUInt<LLVM_MI_FLAGS_BITS>(flags) &&
406	"flags to be set are out of range for the Flags field");
407	// Filter out the automatically maintained flags.
408	unsigned Mask = BundledPred | BundledSucc;
409	Flags = (Flags & Mask) | (flags & ~Mask);
410	}
411
412	/// clearFlag - Clear a MI flag.
413	void clearFlag(MIFlag Flag) {
414	assert(isUInt<LLVM_MI_FLAGS_BITS>(unsigned(Flag)) &&
415	"Flag to clear is out of range for the Flags field");
416	Flags &= ~((uint32_t)Flag);
417	}
418
419	/// Return true if MI is in a bundle (but not the first MI in a bundle).
420	///
421	/// A bundle looks like this before it's finalized:
422	/// ----------------
423	/// | MI |
424	/// ----------------
425	/// |
426	/// ----------------
427	/// | MI * |
428	/// ----------------
429	/// |
430	/// ----------------
431	/// | MI * |
432	/// ----------------
433	/// In this case, the first MI starts a bundle but is not inside a bundle, the
434	/// next 2 MIs are considered "inside" the bundle.
435	///
436	/// After a bundle is finalized, it looks like this:
437	/// ----------------
438	/// | Bundle |
439	/// ----------------
440	/// |
441	/// ----------------
442	/// | MI * |
443	/// ----------------
444	/// |
445	/// ----------------
446	/// | MI * |
447	/// ----------------
448	/// |
449	/// ----------------
450	/// | MI * |
451	/// ----------------
452	/// The first instruction has the special opcode "BUNDLE". It's not "inside"
453	/// a bundle, but the next three MIs are.
454	bool isInsideBundle() const {
455	return getFlag(Flag: BundledPred);
456	}
457
458	/// Return true if this instruction part of a bundle. This is true
459	/// if either itself or its following instruction is marked "InsideBundle".
460	bool isBundled() const {
461	return isBundledWithPred() || isBundledWithSucc();
462	}
463
464	/// Return true if this instruction is part of a bundle, and it is not the
465	/// first instruction in the bundle.
466	bool isBundledWithPred() const { return getFlag(Flag: BundledPred); }
467
468	/// Return true if this instruction is part of a bundle, and it is not the
469	/// last instruction in the bundle.
470	bool isBundledWithSucc() const { return getFlag(Flag: BundledSucc); }
471
472	/// Bundle this instruction with its predecessor. This can be an unbundled
473	/// instruction, or it can be the first instruction in a bundle.
474	void bundleWithPred();
475
476	/// Bundle this instruction with its successor. This can be an unbundled
477	/// instruction, or it can be the last instruction in a bundle.
478	void bundleWithSucc();
479
480	/// Break bundle above this instruction.
481	void unbundleFromPred();
482
483	/// Break bundle below this instruction.
484	void unbundleFromSucc();
485
486	/// Returns the debug location id of this MachineInstr.
487	const DebugLoc &getDebugLoc() const { return DbgLoc; }
488
489	/// Return the operand containing the offset to be used if this DBG_VALUE
490	/// instruction is indirect; will be an invalid register if this value is
491	/// not indirect, and an immediate with value 0 otherwise.
492	const MachineOperand &getDebugOffset() const {
493	assert(isNonListDebugValue() && "not a DBG_VALUE");
494	return getOperand(i: 1);
495	}
496	MachineOperand &getDebugOffset() {
497	assert(isNonListDebugValue() && "not a DBG_VALUE");
498	return getOperand(i: 1);
499	}
500
501	/// Return the operand for the debug variable referenced by
502	/// this DBG_VALUE instruction.
503	const MachineOperand &getDebugVariableOp() const;
504	MachineOperand &getDebugVariableOp();
505
506	/// Return the debug variable referenced by
507	/// this DBG_VALUE instruction.
508	const DILocalVariable *getDebugVariable() const;
509
510	/// Return the operand for the complex address expression referenced by
511	/// this DBG_VALUE instruction.
512	const MachineOperand &getDebugExpressionOp() const;
513	MachineOperand &getDebugExpressionOp();
514
515	/// Return the complex address expression referenced by
516	/// this DBG_VALUE instruction.
517	const DIExpression *getDebugExpression() const;
518
519	/// Return the debug label referenced by
520	/// this DBG_LABEL instruction.
521	const DILabel *getDebugLabel() const;
522
523	/// Fetch the instruction number of this MachineInstr. If it does not have
524	/// one already, a new and unique number will be assigned.
525	unsigned getDebugInstrNum();
526
527	/// Fetch instruction number of this MachineInstr -- but before it's inserted
528	/// into \p MF. Needed for transformations that create an instruction but
529	/// don't immediately insert them.
530	unsigned getDebugInstrNum(MachineFunction &MF);
531
532	/// Examine the instruction number of this MachineInstr. May be zero if
533	/// it hasn't been assigned a number yet.
534	unsigned peekDebugInstrNum() const { return DebugInstrNum; }
535
536	/// Set instruction number of this MachineInstr. Avoid using unless you're
537	/// deserializing this information.
538	void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
539
540	/// Drop any variable location debugging information associated with this
541	/// instruction. Use when an instruction is modified in such a way that it no
542	/// longer defines the value it used to. Variable locations using that value
543	/// will be dropped.
544	void dropDebugNumber() { DebugInstrNum = 0; }
545
546	/// Emit an error referring to the source location of this instruction.
547	/// This should only be used for inline assembly that is somehow
548	/// impossible to compile. Other errors should have been handled much
549	/// earlier.
550	///
551	/// If this method returns, the caller should try to recover from the error.
552	void emitError(StringRef Msg) const;
553
554	/// Returns the target instruction descriptor of this MachineInstr.
555	const MCInstrDesc &getDesc() const { return *MCID; }
556
557	/// Returns the opcode of this MachineInstr.
558	unsigned getOpcode() const { return MCID->Opcode; }
559
560	/// Retuns the total number of operands.
561	unsigned getNumOperands() const { return NumOperands; }
562
563	/// Returns the total number of operands which are debug locations.
564	unsigned getNumDebugOperands() const {
565	return std::distance(first: debug_operands().begin(), last: debug_operands().end());
566	}
567
568	const MachineOperand& getOperand(unsigned i) const {
569	assert(i < getNumOperands() && "getOperand() out of range!");
570	return Operands[i];
571	}
572	MachineOperand& getOperand(unsigned i) {
573	assert(i < getNumOperands() && "getOperand() out of range!");
574	return Operands[i];
575	}
576
577	MachineOperand &getDebugOperand(unsigned Index) {
578	assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
579	return *(debug_operands().begin() + Index);
580	}
581	const MachineOperand &getDebugOperand(unsigned Index) const {
582	assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!");
583	return *(debug_operands().begin() + Index);
584	}
585
586	/// Returns whether this debug value has at least one debug operand with the
587	/// register \p Reg.
588	bool hasDebugOperandForReg(Register Reg) const {
589	return any_of(Range: debug_operands(), P: [Reg](const MachineOperand &Op) {
590	return Op.isReg() && Op.getReg() == Reg;
591	});
592	}
593
594	/// Returns a range of all of the operands that correspond to a debug use of
595	/// \p Reg.
596	template <typename Operand, typename Instruction>
597	static iterator_range<
598	filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
599	getDebugOperandsForReg(Instruction *MI, Register Reg) {
600	std::function<bool(Operand & Op)> OpUsesReg(
601	[Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
602	return make_filter_range(MI->debug_operands(), OpUsesReg);
603	}
604	iterator_range<filter_iterator<const MachineOperand *,
605	std::function<bool(const MachineOperand &Op)>>>
606	getDebugOperandsForReg(Register Reg) const {
607	return MachineInstr::getDebugOperandsForReg<const MachineOperand,
608	const MachineInstr>(MI: this, Reg);
609	}
610	iterator_range<filter_iterator<MachineOperand *,
611	std::function<bool(MachineOperand &Op)>>>
612	getDebugOperandsForReg(Register Reg) {
613	return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
614	MI: this, Reg);
615	}
616
617	bool isDebugOperand(const MachineOperand *Op) const {
618	return Op >= adl_begin(range: debug_operands()) && Op <= adl_end(range: debug_operands());
619	}
620
621	unsigned getDebugOperandIndex(const MachineOperand *Op) const {
622	assert(isDebugOperand(Op) && "Expected a debug operand.");
623	return std::distance(first: adl_begin(range: debug_operands()), last: Op);
624	}
625
626	/// Returns the total number of definitions.
627	unsigned getNumDefs() const {
628	return getNumExplicitDefs() + MCID->implicit_defs().size();
629	}
630
631	/// Returns true if the instruction has implicit definition.
632	bool hasImplicitDef() const {
633	for (const MachineOperand &MO : implicit_operands())
634	if (MO.isDef() && MO.isImplicit())
635	return true;
636	return false;
637	}
638
639	/// Returns the implicit operands number.
640	unsigned getNumImplicitOperands() const {
641	return getNumOperands() - getNumExplicitOperands();
642	}
643
644	/// Return true if operand \p OpIdx is a subregister index.
645	bool isOperandSubregIdx(unsigned OpIdx) const {
646	assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
647	if (isExtractSubreg() && OpIdx == 2)
648	return true;
649	if (isInsertSubreg() && OpIdx == 3)
650	return true;
651	if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
652	return true;
653	if (isSubregToReg() && OpIdx == 3)
654	return true;
655	return false;
656	}
657
658	/// Returns the number of non-implicit operands.
659	unsigned getNumExplicitOperands() const;
660
661	/// Returns the number of non-implicit definitions.
662	unsigned getNumExplicitDefs() const;
663
664	/// iterator/begin/end - Iterate over all operands of a machine instruction.
665	using mop_iterator = MachineOperand *;
666	using const_mop_iterator = const MachineOperand *;
667
668	mop_iterator operands_begin() { return Operands; }
669	mop_iterator operands_end() { return Operands + NumOperands; }
670
671	const_mop_iterator operands_begin() const { return Operands; }
672	const_mop_iterator operands_end() const { return Operands + NumOperands; }
673
674	iterator_range<mop_iterator> operands() {
675	return make_range(x: operands_begin(), y: operands_end());
676	}
677	iterator_range<const_mop_iterator> operands() const {
678	return make_range(x: operands_begin(), y: operands_end());
679	}
680	iterator_range<mop_iterator> explicit_operands() {
681	return make_range(x: operands_begin(),
682	y: operands_begin() + getNumExplicitOperands());
683	}
684	iterator_range<const_mop_iterator> explicit_operands() const {
685	return make_range(x: operands_begin(),
686	y: operands_begin() + getNumExplicitOperands());
687	}
688	iterator_range<mop_iterator> implicit_operands() {
689	return make_range(x: explicit_operands().end(), y: operands_end());
690	}
691	iterator_range<const_mop_iterator> implicit_operands() const {
692	return make_range(x: explicit_operands().end(), y: operands_end());
693	}
694	/// Returns a range over all operands that are used to determine the variable
695	/// location for this DBG_VALUE instruction.
696	iterator_range<mop_iterator> debug_operands() {
697	assert((isDebugValueLike()) && "Must be a debug value instruction.");
698	return isNonListDebugValue()
699	? make_range(x: operands_begin(), y: operands_begin() + 1)
700	: make_range(x: operands_begin() + 2, y: operands_end());
701	}
702	/// \copydoc debug_operands()
703	iterator_range<const_mop_iterator> debug_operands() const {
704	assert((isDebugValueLike()) && "Must be a debug value instruction.");
705	return isNonListDebugValue()
706	? make_range(x: operands_begin(), y: operands_begin() + 1)
707	: make_range(x: operands_begin() + 2, y: operands_end());
708	}
709	/// Returns a range over all explicit operands that are register definitions.
710	/// Implicit definition are not included!
711	iterator_range<mop_iterator> defs() {
712	return make_range(x: operands_begin(),
713	y: operands_begin() + getNumExplicitDefs());
714	}
715	/// \copydoc defs()
716	iterator_range<const_mop_iterator> defs() const {
717	return make_range(x: operands_begin(),
718	y: operands_begin() + getNumExplicitDefs());
719	}
720	/// Returns a range that includes all operands that are register uses.
721	/// This may include unrelated operands which are not register uses.
722	iterator_range<mop_iterator> uses() {
723	return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end());
724	}
725	/// \copydoc uses()
726	iterator_range<const_mop_iterator> uses() const {
727	return make_range(x: operands_begin() + getNumExplicitDefs(), y: operands_end());
728	}
729	iterator_range<mop_iterator> explicit_uses() {
730	return make_range(x: operands_begin() + getNumExplicitDefs(),
731	y: operands_begin() + getNumExplicitOperands());
732	}
733	iterator_range<const_mop_iterator> explicit_uses() const {
734	return make_range(x: operands_begin() + getNumExplicitDefs(),
735	y: operands_begin() + getNumExplicitOperands());
736	}
737
738	using filtered_mop_iterator =
739	filter_iterator<mop_iterator, bool (*)(const MachineOperand &)>;
740	using filtered_const_mop_iterator =
741	filter_iterator<const_mop_iterator, bool (*)(const MachineOperand &)>;
742
743	/// Returns an iterator range over all operands that are (explicit or
744	/// implicit) register defs.
745	iterator_range<filtered_mop_iterator> all_defs() {
746	return make_filter_range(Range: operands(), Pred: opIsRegDef);
747	}
748	/// \copydoc all_defs()
749	iterator_range<filtered_const_mop_iterator> all_defs() const {
750	return make_filter_range(Range: operands(), Pred: opIsRegDef);
751	}
752
753	/// Returns an iterator range over all operands that are (explicit or
754	/// implicit) register uses.
755	iterator_range<filtered_mop_iterator> all_uses() {
756	return make_filter_range(Range: uses(), Pred: opIsRegUse);
757	}
758	/// \copydoc all_uses()
759	iterator_range<filtered_const_mop_iterator> all_uses() const {
760	return make_filter_range(Range: uses(), Pred: opIsRegUse);
761	}
762
763	/// Returns the number of the operand iterator \p I points to.
764	unsigned getOperandNo(const_mop_iterator I) const {
765	return I - operands_begin();
766	}
767
768	/// Access to memory operands of the instruction. If there are none, that does
769	/// not imply anything about whether the function accesses memory. Instead,
770	/// the caller must behave conservatively.
771	ArrayRef<MachineMemOperand *> memoperands() const {
772	if (!Info)
773	return {};
774
775	if (Info.is<EIIK_MMO>())
776	return ArrayRef(Info.getAddrOfZeroTagPointer(), 1);
777
778	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
779	return EI->getMMOs();
780
781	return {};
782	}
783
784	/// Access to memory operands of the instruction.
785	///
786	/// If `memoperands_begin() == memoperands_end()`, that does not imply
787	/// anything about whether the function accesses memory. Instead, the caller
788	/// must behave conservatively.
789	mmo_iterator memoperands_begin() const { return memoperands().begin(); }
790
791	/// Access to memory operands of the instruction.
792	///
793	/// If `memoperands_begin() == memoperands_end()`, that does not imply
794	/// anything about whether the function accesses memory. Instead, the caller
795	/// must behave conservatively.
796	mmo_iterator memoperands_end() const { return memoperands().end(); }
797
798	/// Return true if we don't have any memory operands which described the
799	/// memory access done by this instruction. If this is true, calling code
800	/// must be conservative.
801	bool memoperands_empty() const { return memoperands().empty(); }
802
803	/// Return true if this instruction has exactly one MachineMemOperand.
804	bool hasOneMemOperand() const { return memoperands().size() == 1; }
805
806	/// Return the number of memory operands.
807	unsigned getNumMemOperands() const { return memoperands().size(); }
808
809	/// Helper to extract a pre-instruction symbol if one has been added.
810	MCSymbol *getPreInstrSymbol() const {
811	if (!Info)
812	return nullptr;
813	if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
814	return S;
815	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
816	return EI->getPreInstrSymbol();
817
818	return nullptr;
819	}
820
821	/// Helper to extract a post-instruction symbol if one has been added.
822	MCSymbol *getPostInstrSymbol() const {
823	if (!Info)
824	return nullptr;
825	if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
826	return S;
827	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
828	return EI->getPostInstrSymbol();
829
830	return nullptr;
831	}
832
833	/// Helper to extract a heap alloc marker if one has been added.
834	MDNode *getHeapAllocMarker() const {
835	if (!Info)
836	return nullptr;
837	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
838	return EI->getHeapAllocMarker();
839
840	return nullptr;
841	}
842
843	/// Helper to extract PCSections metadata target sections.
844	MDNode *getPCSections() const {
845	if (!Info)
846	return nullptr;
847	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
848	return EI->getPCSections();
849
850	return nullptr;
851	}
852
853	/// Helper to extract mmra.op metadata.
854	MDNode *getMMRAMetadata() const {
855	if (!Info)
856	return nullptr;
857	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
858	return EI->getMMRAMetadata();
859	return nullptr;
860	}
861
862	/// Helper to extract a CFI type hash if one has been added.
863	uint32_t getCFIType() const {
864	if (!Info)
865	return 0;
866	if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
867	return EI->getCFIType();
868
869	return 0;
870	}
871
872	/// API for querying MachineInstr properties. They are the same as MCInstrDesc
873	/// queries but they are bundle aware.
874
875	enum QueryType {
876	IgnoreBundle, // Ignore bundles
877	AnyInBundle, // Return true if any instruction in bundle has property
878	AllInBundle // Return true if all instructions in bundle have property
879	};
880
881	/// Return true if the instruction (or in the case of a bundle,
882	/// the instructions inside the bundle) has the specified property.
883	/// The first argument is the property being queried.
884	/// The second argument indicates whether the query should look inside
885	/// instruction bundles.
886	bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
887	assert(MCFlag < 64 &&
888	"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
889	// Inline the fast path for unbundled or bundle-internal instructions.
890	if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
891	return getDesc().getFlags() & (1ULL << MCFlag);
892
893	// If this is the first instruction in a bundle, take the slow path.
894	return hasPropertyInBundle(Mask: 1ULL << MCFlag, Type);
895	}
896
897	/// Return true if this is an instruction that should go through the usual
898	/// legalization steps.
899	bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
900	return hasProperty(MCFlag: MCID::PreISelOpcode, Type);
901	}
902
903	/// Return true if this instruction can have a variable number of operands.
904	/// In this case, the variable operands will be after the normal
905	/// operands but before the implicit definitions and uses (if any are
906	/// present).
907	bool isVariadic(QueryType Type = IgnoreBundle) const {
908	return hasProperty(MCFlag: MCID::Variadic, Type);
909	}
910
911	/// Set if this instruction has an optional definition, e.g.
912	/// ARM instructions which can set condition code if 's' bit is set.
913	bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
914	return hasProperty(MCFlag: MCID::HasOptionalDef, Type);
915	}
916
917	/// Return true if this is a pseudo instruction that doesn't
918	/// correspond to a real machine instruction.
919	bool isPseudo(QueryType Type = IgnoreBundle) const {
920	return hasProperty(MCFlag: MCID::Pseudo, Type);
921	}
922
923	/// Return true if this instruction doesn't produce any output in the form of
924	/// executable instructions.
925	bool isMetaInstruction(QueryType Type = IgnoreBundle) const {
926	return hasProperty(MCFlag: MCID::Meta, Type);
927	}
928
929	bool isReturn(QueryType Type = AnyInBundle) const {
930	return hasProperty(MCFlag: MCID::Return, Type);
931	}
932
933	/// Return true if this is an instruction that marks the end of an EH scope,
934	/// i.e., a catchpad or a cleanuppad instruction.
935	bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
936	return hasProperty(MCFlag: MCID::EHScopeReturn, Type);
937	}
938
939	bool isCall(QueryType Type = AnyInBundle) const {
940	return hasProperty(MCFlag: MCID::Call, Type);
941	}
942
943	/// Return true if this is a call instruction that may have an associated
944	/// call site entry in the debug info.
945	bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
946	/// Return true if copying, moving, or erasing this instruction requires
947	/// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
948	/// \ref eraseCallSiteInfo).
949	bool shouldUpdateCallSiteInfo() const;
950
951	/// Returns true if the specified instruction stops control flow
952	/// from executing the instruction immediately following it. Examples include
953	/// unconditional branches and return instructions.
954	bool isBarrier(QueryType Type = AnyInBundle) const {
955	return hasProperty(MCFlag: MCID::Barrier, Type);
956	}
957
958	/// Returns true if this instruction part of the terminator for a basic block.
959	/// Typically this is things like return and branch instructions.
960	///
961	/// Various passes use this to insert code into the bottom of a basic block,
962	/// but before control flow occurs.
963	bool isTerminator(QueryType Type = AnyInBundle) const {
964	return hasProperty(MCFlag: MCID::Terminator, Type);
965	}
966
967	/// Returns true if this is a conditional, unconditional, or indirect branch.
968	/// Predicates below can be used to discriminate between
969	/// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
970	/// get more information.
971	bool isBranch(QueryType Type = AnyInBundle) const {
972	return hasProperty(MCFlag: MCID::Branch, Type);
973	}
974
975	/// Return true if this is an indirect branch, such as a
976	/// branch through a register.
977	bool isIndirectBranch(QueryType Type = AnyInBundle) const {
978	return hasProperty(MCFlag: MCID::IndirectBranch, Type);
979	}
980
981	/// Return true if this is a branch which may fall
982	/// through to the next instruction or may transfer control flow to some other
983	/// block. The TargetInstrInfo::analyzeBranch method can be used to get more
984	/// information about this branch.
985	bool isConditionalBranch(QueryType Type = AnyInBundle) const {
986	return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
987	}
988
989	/// Return true if this is a branch which always
990	/// transfers control flow to some other block. The
991	/// TargetInstrInfo::analyzeBranch method can be used to get more information
992	/// about this branch.
993	bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
994	return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
995	}
996
997	/// Return true if this instruction has a predicate operand that
998	/// controls execution. It may be set to 'always', or may be set to other
999	/// values. There are various methods in TargetInstrInfo that can be used to
1000	/// control and modify the predicate in this instruction.
1001	bool isPredicable(QueryType Type = AllInBundle) const {
1002	// If it's a bundle than all bundled instructions must be predicable for this
1003	// to return true.
1004	return hasProperty(MCFlag: MCID::Predicable, Type);
1005	}
1006
1007	/// Return true if this instruction is a comparison.
1008	bool isCompare(QueryType Type = IgnoreBundle) const {
1009	return hasProperty(MCFlag: MCID::Compare, Type);
1010	}
1011
1012	/// Return true if this instruction is a move immediate
1013	/// (including conditional moves) instruction.
1014	bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
1015	return hasProperty(MCFlag: MCID::MoveImm, Type);
1016	}
1017
1018	/// Return true if this instruction is a register move.
1019	/// (including moving values from subreg to reg)
1020	bool isMoveReg(QueryType Type = IgnoreBundle) const {
1021	return hasProperty(MCFlag: MCID::MoveReg, Type);
1022	}
1023
1024	/// Return true if this instruction is a bitcast instruction.
1025	bool isBitcast(QueryType Type = IgnoreBundle) const {
1026	return hasProperty(MCFlag: MCID::Bitcast, Type);
1027	}
1028
1029	/// Return true if this instruction is a select instruction.
1030	bool isSelect(QueryType Type = IgnoreBundle) const {
1031	return hasProperty(MCFlag: MCID::Select, Type);
1032	}
1033
1034	/// Return true if this instruction cannot be safely duplicated.
1035	/// For example, if the instruction has a unique labels attached
1036	/// to it, duplicating it would cause multiple definition errors.
1037	bool isNotDuplicable(QueryType Type = AnyInBundle) const {
1038	if (getPreInstrSymbol() || getPostInstrSymbol())
1039	return true;
1040	return hasProperty(MCFlag: MCID::NotDuplicable, Type);
1041	}
1042
1043	/// Return true if this instruction is convergent.
1044	/// Convergent instructions can not be made control-dependent on any
1045	/// additional values.
1046	bool isConvergent(QueryType Type = AnyInBundle) const {
1047	if (isInlineAsm()) {
1048	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1049	if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1050	return true;
1051	}
1052	if (getFlag(Flag: NoConvergent))
1053	return false;
1054	return hasProperty(MCFlag: MCID::Convergent, Type);
1055	}
1056
1057	/// Returns true if the specified instruction has a delay slot
1058	/// which must be filled by the code generator.
1059	bool hasDelaySlot(QueryType Type = AnyInBundle) const {
1060	return hasProperty(MCFlag: MCID::DelaySlot, Type);
1061	}
1062
1063	/// Return true for instructions that can be folded as
1064	/// memory operands in other instructions. The most common use for this
1065	/// is instructions that are simple loads from memory that don't modify
1066	/// the loaded value in any way, but it can also be used for instructions
1067	/// that can be expressed as constant-pool loads, such as V_SETALLONES
1068	/// on x86, to allow them to be folded when it is beneficial.
1069	/// This should only be set on instructions that return a value in their
1070	/// only virtual register definition.
1071	bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
1072	return hasProperty(MCFlag: MCID::FoldableAsLoad, Type);
1073	}
1074
1075	/// Return true if this instruction behaves
1076	/// the same way as the generic REG_SEQUENCE instructions.
1077	/// E.g., on ARM,
1078	/// dX VMOVDRR rY, rZ
1079	/// is equivalent to
1080	/// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
1081	///
1082	/// Note that for the optimizers to be able to take advantage of
1083	/// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
1084	/// override accordingly.
1085	bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
1086	return hasProperty(MCFlag: MCID::RegSequence, Type);
1087	}
1088
1089	/// Return true if this instruction behaves
1090	/// the same way as the generic EXTRACT_SUBREG instructions.
1091	/// E.g., on ARM,
1092	/// rX, rY VMOVRRD dZ
1093	/// is equivalent to two EXTRACT_SUBREG:
1094	/// rX = EXTRACT_SUBREG dZ, ssub_0
1095	/// rY = EXTRACT_SUBREG dZ, ssub_1
1096	///
1097	/// Note that for the optimizers to be able to take advantage of
1098	/// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
1099	/// override accordingly.
1100	bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
1101	return hasProperty(MCFlag: MCID::ExtractSubreg, Type);
1102	}
1103
1104	/// Return true if this instruction behaves
1105	/// the same way as the generic INSERT_SUBREG instructions.
1106	/// E.g., on ARM,
1107	/// dX = VSETLNi32 dY, rZ, Imm
1108	/// is equivalent to a INSERT_SUBREG:
1109	/// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
1110	///
1111	/// Note that for the optimizers to be able to take advantage of
1112	/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
1113	/// override accordingly.
1114	bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
1115	return hasProperty(MCFlag: MCID::InsertSubreg, Type);
1116	}
1117
1118	//===--------------------------------------------------------------------===//
1119	// Side Effect Analysis
1120	//===--------------------------------------------------------------------===//
1121
1122	/// Return true if this instruction could possibly read memory.
1123	/// Instructions with this flag set are not necessarily simple load
1124	/// instructions, they may load a value and modify it, for example.
1125	bool mayLoad(QueryType Type = AnyInBundle) const {
1126	if (isInlineAsm()) {
1127	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1128	if (ExtraInfo & InlineAsm::Extra_MayLoad)
1129	return true;
1130	}
1131	return hasProperty(MCFlag: MCID::MayLoad, Type);
1132	}
1133
1134	/// Return true if this instruction could possibly modify memory.
1135	/// Instructions with this flag set are not necessarily simple store
1136	/// instructions, they may store a modified value based on their operands, or
1137	/// may not actually modify anything, for example.
1138	bool mayStore(QueryType Type = AnyInBundle) const {
1139	if (isInlineAsm()) {
1140	unsigned ExtraInfo = getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
1141	if (ExtraInfo & InlineAsm::Extra_MayStore)
1142	return true;
1143	}
1144	return hasProperty(MCFlag: MCID::MayStore, Type);
1145	}
1146
1147	/// Return true if this instruction could possibly read or modify memory.
1148	bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
1149	return mayLoad(Type) || mayStore(Type);
1150	}
1151
1152	/// Return true if this instruction could possibly raise a floating-point
1153	/// exception. This is the case if the instruction is a floating-point
1154	/// instruction that can in principle raise an exception, as indicated
1155	/// by the MCID::MayRaiseFPException property, *and* at the same time,
1156	/// the instruction is used in a context where we expect floating-point
1157	/// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
1158	bool mayRaiseFPException() const {
1159	return hasProperty(MCFlag: MCID::MayRaiseFPException) &&
1160	!getFlag(Flag: MachineInstr::MIFlag::NoFPExcept);
1161	}
1162
1163	//===--------------------------------------------------------------------===//
1164	// Flags that indicate whether an instruction can be modified by a method.
1165	//===--------------------------------------------------------------------===//
1166
1167	/// Return true if this may be a 2- or 3-address
1168	/// instruction (of the form "X = op Y, Z, ..."), which produces the same
1169	/// result if Y and Z are exchanged. If this flag is set, then the
1170	/// TargetInstrInfo::commuteInstruction method may be used to hack on the
1171	/// instruction.
1172	///
1173	/// Note that this flag may be set on instructions that are only commutable
1174	/// sometimes. In these cases, the call to commuteInstruction will fail.
1175	/// Also note that some instructions require non-trivial modification to
1176	/// commute them.
1177	bool isCommutable(QueryType Type = IgnoreBundle) const {
1178	return hasProperty(MCFlag: MCID::Commutable, Type);
1179	}
1180
1181	/// Return true if this is a 2-address instruction
1182	/// which can be changed into a 3-address instruction if needed. Doing this
1183	/// transformation can be profitable in the register allocator, because it
1184	/// means that the instruction can use a 2-address form if possible, but
1185	/// degrade into a less efficient form if the source and dest register cannot
1186	/// be assigned to the same register. For example, this allows the x86
1187	/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1188	/// is the same speed as the shift but has bigger code size.
1189	///
1190	/// If this returns true, then the target must implement the
1191	/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1192	/// is allowed to fail if the transformation isn't valid for this specific
1193	/// instruction (e.g. shl reg, 4 on x86).
1194	///
1195	bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1196	return hasProperty(MCFlag: MCID::ConvertibleTo3Addr, Type);
1197	}
1198
1199	/// Return true if this instruction requires
1200	/// custom insertion support when the DAG scheduler is inserting it into a
1201	/// machine basic block. If this is true for the instruction, it basically
1202	/// means that it is a pseudo instruction used at SelectionDAG time that is
1203	/// expanded out into magic code by the target when MachineInstrs are formed.
1204	///
1205	/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1206	/// is used to insert this into the MachineBasicBlock.
1207	bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1208	return hasProperty(MCFlag: MCID::UsesCustomInserter, Type);
1209	}
1210
1211	/// Return true if this instruction requires *adjustment*
1212	/// after instruction selection by calling a target hook. For example, this
1213	/// can be used to fill in ARM 's' optional operand depending on whether
1214	/// the conditional flag register is used.
1215	bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1216	return hasProperty(MCFlag: MCID::HasPostISelHook, Type);
1217	}
1218
1219	/// Returns true if this instruction is a candidate for remat.
1220	/// This flag is deprecated, please don't use it anymore. If this
1221	/// flag is set, the isReallyTriviallyReMaterializable() method is called to
1222	/// verify the instruction is really rematerializable.
1223	bool isRematerializable(QueryType Type = AllInBundle) const {
1224	// It's only possible to re-mat a bundle if all bundled instructions are
1225	// re-materializable.
1226	return hasProperty(MCFlag: MCID::Rematerializable, Type);
1227	}
1228
1229	/// Returns true if this instruction has the same cost (or less) than a move
1230	/// instruction. This is useful during certain types of optimizations
1231	/// (e.g., remat during two-address conversion or machine licm)
1232	/// where we would like to remat or hoist the instruction, but not if it costs
1233	/// more than moving the instruction into the appropriate register. Note, we
1234	/// are not marking copies from and to the same register class with this flag.
1235	bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1236	// Only returns true for a bundle if all bundled instructions are cheap.
1237	return hasProperty(MCFlag: MCID::CheapAsAMove, Type);
1238	}
1239
1240	/// Returns true if this instruction source operands
1241	/// have special register allocation requirements that are not captured by the
1242	/// operand register classes. e.g. ARM::STRD's two source registers must be an
1243	/// even / odd pair, ARM::STM registers have to be in ascending order.
1244	/// Post-register allocation passes should not attempt to change allocations
1245	/// for sources of instructions with this flag.
1246	bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1247	return hasProperty(MCFlag: MCID::ExtraSrcRegAllocReq, Type);
1248	}
1249
1250	/// Returns true if this instruction def operands
1251	/// have special register allocation requirements that are not captured by the
1252	/// operand register classes. e.g. ARM::LDRD's two def registers must be an
1253	/// even / odd pair, ARM::LDM registers have to be in ascending order.
1254	/// Post-register allocation passes should not attempt to change allocations
1255	/// for definitions of instructions with this flag.
1256	bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1257	return hasProperty(MCFlag: MCID::ExtraDefRegAllocReq, Type);
1258	}
1259
1260	enum MICheckType {
1261	CheckDefs, // Check all operands for equality
1262	CheckKillDead, // Check all operands including kill / dead markers
1263	IgnoreDefs, // Ignore all definitions
1264	IgnoreVRegDefs // Ignore virtual register definitions
1265	};
1266
1267	/// Return true if this instruction is identical to \p Other.
1268	/// Two instructions are identical if they have the same opcode and all their
1269	/// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1270	/// Note that this means liveness related flags (dead, undef, kill) do not
1271	/// affect the notion of identical.
1272	bool isIdenticalTo(const MachineInstr &Other,
1273	MICheckType Check = CheckDefs) const;
1274
1275	/// Returns true if this instruction is a debug instruction that represents an
1276	/// identical debug value to \p Other.
1277	/// This function considers these debug instructions equivalent if they have
1278	/// identical variables, debug locations, and debug operands, and if the
1279	/// DIExpressions combined with the directness flags are equivalent.
1280	bool isEquivalentDbgInstr(const MachineInstr &Other) const;
1281
1282	/// Unlink 'this' from the containing basic block, and return it without
1283	/// deleting it.
1284	///
1285	/// This function can not be used on bundled instructions, use
1286	/// removeFromBundle() to remove individual instructions from a bundle.
1287	MachineInstr *removeFromParent();
1288
1289	/// Unlink this instruction from its basic block and return it without
1290	/// deleting it.
1291	///
1292	/// If the instruction is part of a bundle, the other instructions in the
1293	/// bundle remain bundled.
1294	MachineInstr *removeFromBundle();
1295
1296	/// Unlink 'this' from the containing basic block and delete it.
1297	///
1298	/// If this instruction is the header of a bundle, the whole bundle is erased.
1299	/// This function can not be used for instructions inside a bundle, use
1300	/// eraseFromBundle() to erase individual bundled instructions.
1301	void eraseFromParent();
1302
1303	/// Unlink 'this' from its basic block and delete it.
1304	///
1305	/// If the instruction is part of a bundle, the other instructions in the
1306	/// bundle remain bundled.
1307	void eraseFromBundle();
1308
1309	bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1310	bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1311	bool isAnnotationLabel() const {
1312	return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1313	}
1314
1315	/// Returns true if the MachineInstr represents a label.
1316	bool isLabel() const {
1317	return isEHLabel() || isGCLabel() || isAnnotationLabel();
1318	}
1319
1320	bool isCFIInstruction() const {
1321	return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1322	}
1323
1324	bool isPseudoProbe() const {
1325	return getOpcode() == TargetOpcode::PSEUDO_PROBE;
1326	}
1327
1328	// True if the instruction represents a position in the function.
1329	bool isPosition() const { return isLabel() || isCFIInstruction(); }
1330
1331	bool isNonListDebugValue() const {
1332	return getOpcode() == TargetOpcode::DBG_VALUE;
1333	}
1334	bool isDebugValueList() const {
1335	return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
1336	}
1337	bool isDebugValue() const {
1338	return isNonListDebugValue() || isDebugValueList();
1339	}
1340	bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1341	bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1342	bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
1343	bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
1344	bool isDebugInstr() const {
1345	return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
1346	}
1347	bool isDebugOrPseudoInstr() const {
1348	return isDebugInstr() || isPseudoProbe();
1349	}
1350
1351	bool isDebugOffsetImm() const {
1352	return isNonListDebugValue() && getDebugOffset().isImm();
1353	}
1354
1355	/// A DBG_VALUE is indirect iff the location operand is a register and
1356	/// the offset operand is an immediate.
1357	bool isIndirectDebugValue() const {
1358	return isDebugOffsetImm() && getDebugOperand(Index: 0).isReg();
1359	}
1360
1361	/// A DBG_VALUE is an entry value iff its debug expression contains the
1362	/// DW_OP_LLVM_entry_value operation.
1363	bool isDebugEntryValue() const;
1364
1365	/// Return true if the instruction is a debug value which describes a part of
1366	/// a variable as unavailable.
1367	bool isUndefDebugValue() const {
1368	if (!isDebugValue())
1369	return false;
1370	// If any $noreg locations are given, this DV is undef.
1371	for (const MachineOperand &Op : debug_operands())
1372	if (Op.isReg() && !Op.getReg().isValid())
1373	return true;
1374	return false;
1375	}
1376
1377	bool isJumpTableDebugInfo() const {
1378	return getOpcode() == TargetOpcode::JUMP_TABLE_DEBUG_INFO;
1379	}
1380
1381	bool isPHI() const {
1382	return getOpcode() == TargetOpcode::PHI ||
1383	getOpcode() == TargetOpcode::G_PHI;
1384	}
1385	bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1386	bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1387	bool isInlineAsm() const {
1388	return getOpcode() == TargetOpcode::INLINEASM ||
1389	getOpcode() == TargetOpcode::INLINEASM_BR;
1390	}
1391	/// Returns true if the register operand can be folded with a load or store
1392	/// into a frame index. Does so by checking the InlineAsm::Flag immediate
1393	/// operand at OpId - 1.
1394	bool mayFoldInlineAsmRegOp(unsigned OpId) const;
1395
1396	bool isStackAligningInlineAsm() const;
1397	InlineAsm::AsmDialect getInlineAsmDialect() const;
1398
1399	bool isInsertSubreg() const {
1400	return getOpcode() == TargetOpcode::INSERT_SUBREG;
1401	}
1402
1403	bool isSubregToReg() const {
1404	return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1405	}
1406
1407	bool isRegSequence() const {
1408	return getOpcode() == TargetOpcode::REG_SEQUENCE;
1409	}
1410
1411	bool isBundle() const {
1412	return getOpcode() == TargetOpcode::BUNDLE;
1413	}
1414
1415	bool isCopy() const {
1416	return getOpcode() == TargetOpcode::COPY;
1417	}
1418
1419	bool isFullCopy() const {
1420	return isCopy() && !getOperand(i: 0).getSubReg() && !getOperand(i: 1).getSubReg();
1421	}
1422
1423	bool isExtractSubreg() const {
1424	return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1425	}
1426
1427	/// Return true if the instruction behaves like a copy.
1428	/// This does not include native copy instructions.
1429	bool isCopyLike() const {
1430	return isCopy() || isSubregToReg();
1431	}
1432
1433	/// Return true is the instruction is an identity copy.
1434	bool isIdentityCopy() const {
1435	return isCopy() && getOperand(i: 0).getReg() == getOperand(i: 1).getReg() &&
1436	getOperand(i: 0).getSubReg() == getOperand(i: 1).getSubReg();
1437	}
1438
1439	/// Return true if this is a transient instruction that is either very likely
1440	/// to be eliminated during register allocation (such as copy-like
1441	/// instructions), or if this instruction doesn't have an execution-time cost.
1442	bool isTransient() const {
1443	switch (getOpcode()) {
1444	default:
1445	return isMetaInstruction();
1446	// Copy-like instructions are usually eliminated during register allocation.
1447	case TargetOpcode::PHI:
1448	case TargetOpcode::G_PHI:
1449	case TargetOpcode::COPY:
1450	case TargetOpcode::INSERT_SUBREG:
1451	case TargetOpcode::SUBREG_TO_REG:
1452	case TargetOpcode::REG_SEQUENCE:
1453	return true;
1454	}
1455	}
1456
1457	/// Return the number of instructions inside the MI bundle, excluding the
1458	/// bundle header.
1459	///
1460	/// This is the number of instructions that MachineBasicBlock::iterator
1461	/// skips, 0 for unbundled instructions.
1462	unsigned getBundleSize() const;
1463
1464	/// Return true if the MachineInstr reads the specified register.
1465	/// If TargetRegisterInfo is non-null, then it also checks if there
1466	/// is a read of a super-register.
1467	/// This does not count partial redefines of virtual registers as reads:
1468	/// %reg1024:6 = OP.
1469	bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1470	return findRegisterUseOperandIdx(Reg, TRI, isKill: false) != -1;
1471	}
1472
1473	/// Return true if the MachineInstr reads the specified virtual register.
1474	/// Take into account that a partial define is a
1475	/// read-modify-write operation.
1476	bool readsVirtualRegister(Register Reg) const {
1477	return readsWritesVirtualRegister(Reg).first;
1478	}
1479
1480	/// Return a pair of bools (reads, writes) indicating if this instruction
1481	/// reads or writes Reg. This also considers partial defines.
1482	/// If Ops is not null, all operand indices for Reg are added.
1483	std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1484	SmallVectorImpl<unsigned> *Ops = nullptr) const;
1485
1486	/// Return true if the MachineInstr kills the specified register.
1487	/// If TargetRegisterInfo is non-null, then it also checks if there is
1488	/// a kill of a super-register.
1489	bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1490	return findRegisterUseOperandIdx(Reg, TRI, isKill: true) != -1;
1491	}
1492
1493	/// Return true if the MachineInstr fully defines the specified register.
1494	/// If TargetRegisterInfo is non-null, then it also checks
1495	/// if there is a def of a super-register.
1496	/// NOTE: It's ignoring subreg indices on virtual registers.
1497	bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1498	return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: false) != -1;
1499	}
1500
1501	/// Return true if the MachineInstr modifies (fully define or partially
1502	/// define) the specified register.
1503	/// NOTE: It's ignoring subreg indices on virtual registers.
1504	bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1505	return findRegisterDefOperandIdx(Reg, TRI, isDead: false, Overlap: true) != -1;
1506	}
1507
1508	/// Returns true if the register is dead in this machine instruction.
1509	/// If TargetRegisterInfo is non-null, then it also checks
1510	/// if there is a dead def of a super-register.
1511	bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const {
1512	return findRegisterDefOperandIdx(Reg, TRI, isDead: true, Overlap: false) != -1;
1513	}
1514
1515	/// Returns true if the MachineInstr has an implicit-use operand of exactly
1516	/// the given register (not considering sub/super-registers).
1517	bool hasRegisterImplicitUseOperand(Register Reg) const;
1518
1519	/// Returns the operand index that is a use of the specific register or -1
1520	/// if it is not found. It further tightens the search criteria to a use
1521	/// that kills the register if isKill is true.
1522	int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1523	bool isKill = false) const;
1524
1525	/// Wrapper for findRegisterUseOperandIdx, it returns
1526	/// a pointer to the MachineOperand rather than an index.
1527	MachineOperand *findRegisterUseOperand(Register Reg,
1528	const TargetRegisterInfo *TRI,
1529	bool isKill = false) {
1530	int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill);
1531	return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1532	}
1533
1534	const MachineOperand *findRegisterUseOperand(Register Reg,
1535	const TargetRegisterInfo *TRI,
1536	bool isKill = false) const {
1537	return const_cast<MachineInstr *>(this)->findRegisterUseOperand(Reg, TRI,
1538	isKill);
1539	}
1540
1541	/// Returns the operand index that is a def of the specified register or
1542	/// -1 if it is not found. If isDead is true, defs that are not dead are
1543	/// skipped. If Overlap is true, then it also looks for defs that merely
1544	/// overlap the specified register. If TargetRegisterInfo is non-null,
1545	/// then it also checks if there is a def of a super-register.
1546	/// This may also return a register mask operand when Overlap is true.
1547	int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI,
1548	bool isDead = false,
1549	bool Overlap = false) const;
1550
1551	/// Wrapper for findRegisterDefOperandIdx, it returns
1552	/// a pointer to the MachineOperand rather than an index.
1553	MachineOperand *findRegisterDefOperand(Register Reg,
1554	const TargetRegisterInfo *TRI,
1555	bool isDead = false,
1556	bool Overlap = false) {
1557	int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap);
1558	return (Idx == -1) ? nullptr : &getOperand(i: Idx);
1559	}
1560
1561	const MachineOperand *findRegisterDefOperand(Register Reg,
1562	const TargetRegisterInfo *TRI,
1563	bool isDead = false,
1564	bool Overlap = false) const {
1565	return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1566	Reg, TRI, isDead, Overlap);
1567	}
1568
1569	/// Find the index of the first operand in the
1570	/// operand list that is used to represent the predicate. It returns -1 if
1571	/// none is found.
1572	int findFirstPredOperandIdx() const;
1573
1574	/// Find the index of the flag word operand that
1575	/// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1576	/// getOperand(OpIdx) does not belong to an inline asm operand group.
1577	///
1578	/// If GroupNo is not NULL, it will receive the number of the operand group
1579	/// containing OpIdx.
1580	int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1581
1582	/// Compute the static register class constraint for operand OpIdx.
1583	/// For normal instructions, this is derived from the MCInstrDesc.
1584	/// For inline assembly it is derived from the flag words.
1585	///
1586	/// Returns NULL if the static register class constraint cannot be
1587	/// determined.
1588	const TargetRegisterClass*
1589	getRegClassConstraint(unsigned OpIdx,
1590	const TargetInstrInfo *TII,
1591	const TargetRegisterInfo *TRI) const;
1592
1593	/// Applies the constraints (def/use) implied by this MI on \p Reg to
1594	/// the given \p CurRC.
1595	/// If \p ExploreBundle is set and MI is part of a bundle, all the
1596	/// instructions inside the bundle will be taken into account. In other words,
1597	/// this method accumulates all the constraints of the operand of this MI and
1598	/// the related bundle if MI is a bundle or inside a bundle.
1599	///
1600	/// Returns the register class that satisfies both \p CurRC and the
1601	/// constraints set by MI. Returns NULL if such a register class does not
1602	/// exist.
1603	///
1604	/// \pre CurRC must not be NULL.
1605	const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1606	Register Reg, const TargetRegisterClass *CurRC,
1607	const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1608	bool ExploreBundle = false) const;
1609
1610	/// Applies the constraints (def/use) implied by the \p OpIdx operand
1611	/// to the given \p CurRC.
1612	///
1613	/// Returns the register class that satisfies both \p CurRC and the
1614	/// constraints set by \p OpIdx MI. Returns NULL if such a register class
1615	/// does not exist.
1616	///
1617	/// \pre CurRC must not be NULL.
1618	/// \pre The operand at \p OpIdx must be a register.
1619	const TargetRegisterClass *
1620	getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1621	const TargetInstrInfo *TII,
1622	const TargetRegisterInfo *TRI) const;
1623
1624	/// Add a tie between the register operands at DefIdx and UseIdx.
1625	/// The tie will cause the register allocator to ensure that the two
1626	/// operands are assigned the same physical register.
1627	///
1628	/// Tied operands are managed automatically for explicit operands in the
1629	/// MCInstrDesc. This method is for exceptional cases like inline asm.
1630	void tieOperands(unsigned DefIdx, unsigned UseIdx);
1631
1632	/// Given the index of a tied register operand, find the
1633	/// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1634	/// index of the tied operand which must exist.
1635	unsigned findTiedOperandIdx(unsigned OpIdx) const;
1636
1637	/// Given the index of a register def operand,
1638	/// check if the register def is tied to a source operand, due to either
1639	/// two-address elimination or inline assembly constraints. Returns the
1640	/// first tied use operand index by reference if UseOpIdx is not null.
1641	bool isRegTiedToUseOperand(unsigned DefOpIdx,
1642	unsigned *UseOpIdx = nullptr) const {
1643	const MachineOperand &MO = getOperand(i: DefOpIdx);
1644	if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1645	return false;
1646	if (UseOpIdx)
1647	*UseOpIdx = findTiedOperandIdx(OpIdx: DefOpIdx);
1648	return true;
1649	}
1650
1651	/// Return true if the use operand of the specified index is tied to a def
1652	/// operand. It also returns the def operand index by reference if DefOpIdx
1653	/// is not null.
1654	bool isRegTiedToDefOperand(unsigned UseOpIdx,
1655	unsigned *DefOpIdx = nullptr) const {
1656	const MachineOperand &MO = getOperand(i: UseOpIdx);
1657	if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1658	return false;
1659	if (DefOpIdx)
1660	*DefOpIdx = findTiedOperandIdx(OpIdx: UseOpIdx);
1661	return true;
1662	}
1663
1664	/// Clears kill flags on all operands.
1665	void clearKillInfo();
1666
1667	/// Replace all occurrences of FromReg with ToReg:SubIdx,
1668	/// properly composing subreg indices where necessary.
1669	void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1670	const TargetRegisterInfo &RegInfo);
1671
1672	/// We have determined MI kills a register. Look for the
1673	/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1674	/// add a implicit operand if it's not found. Returns true if the operand
1675	/// exists / is added.
1676	bool addRegisterKilled(Register IncomingReg,
1677	const TargetRegisterInfo *RegInfo,
1678	bool AddIfNotFound = false);
1679
1680	/// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1681	/// all aliasing registers.
1682	void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1683
1684	/// We have determined MI defined a register without a use.
1685	/// Look for the operand that defines it and mark it as IsDead. If
1686	/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1687	/// true if the operand exists / is added.
1688	bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1689	bool AddIfNotFound = false);
1690
1691	/// Clear all dead flags on operands defining register @p Reg.
1692	void clearRegisterDeads(Register Reg);
1693
1694	/// Mark all subregister defs of register @p Reg with the undef flag.
1695	/// This function is used when we determined to have a subregister def in an
1696	/// otherwise undefined super register.
1697	void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1698
1699	/// We have determined MI defines a register. Make sure there is an operand
1700	/// defining Reg.
1701	void addRegisterDefined(Register Reg,
1702	const TargetRegisterInfo *RegInfo = nullptr);
1703
1704	/// Mark every physreg used by this instruction as
1705	/// dead except those in the UsedRegs list.
1706	///
1707	/// On instructions with register mask operands, also add implicit-def
1708	/// operands for all registers in UsedRegs.
1709	void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1710	const TargetRegisterInfo &TRI);
1711
1712	/// Return true if it is safe to move this instruction. If
1713	/// SawStore is set to true, it means that there is a store (or call) between
1714	/// the instruction's location and its intended destination.
1715	bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1716
1717	/// Returns true if this instruction's memory access aliases the memory
1718	/// access of Other.
1719	//
1720	/// Assumes any physical registers used to compute addresses
1721	/// have the same value for both instructions. Returns false if neither
1722	/// instruction writes to memory.
1723	///
1724	/// @param AA Optional alias analysis, used to compare memory operands.
1725	/// @param Other MachineInstr to check aliasing against.
1726	/// @param UseTBAA Whether to pass TBAA information to alias analysis.
1727	bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1728
1729	/// Return true if this instruction may have an ordered
1730	/// or volatile memory reference, or if the information describing the memory
1731	/// reference is not available. Return false if it is known to have no
1732	/// ordered or volatile memory references.
1733	bool hasOrderedMemoryRef() const;
1734
1735	/// Return true if this load instruction never traps and points to a memory
1736	/// location whose value doesn't change during the execution of this function.
1737	///
1738	/// Examples include loading a value from the constant pool or from the
1739	/// argument area of a function (if it does not change). If the instruction
1740	/// does multiple loads, this returns true only if all of the loads are
1741	/// dereferenceable and invariant.
1742	bool isDereferenceableInvariantLoad() const;
1743
1744	/// If the specified instruction is a PHI that always merges together the
1745	/// same virtual register, return the register, otherwise return 0.
1746	unsigned isConstantValuePHI() const;
1747
1748	/// Return true if this instruction has side effects that are not modeled
1749	/// by mayLoad / mayStore, etc.
1750	/// For all instructions, the property is encoded in MCInstrDesc::Flags
1751	/// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1752	/// INLINEASM instruction, in which case the side effect property is encoded
1753	/// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1754	///
1755	bool hasUnmodeledSideEffects() const;
1756
1757	/// Returns true if it is illegal to fold a load across this instruction.
1758	bool isLoadFoldBarrier() const;
1759
1760	/// Return true if all the defs of this instruction are dead.
1761	bool allDefsAreDead() const;
1762
1763	/// Return true if all the implicit defs of this instruction are dead.
1764	bool allImplicitDefsAreDead() const;
1765
1766	/// Return a valid size if the instruction is a spill instruction.
1767	std::optional<LocationSize> getSpillSize(const TargetInstrInfo *TII) const;
1768
1769	/// Return a valid size if the instruction is a folded spill instruction.
1770	std::optional<LocationSize>
1771	getFoldedSpillSize(const TargetInstrInfo *TII) const;
1772
1773	/// Return a valid size if the instruction is a restore instruction.
1774	std::optional<LocationSize> getRestoreSize(const TargetInstrInfo *TII) const;
1775
1776	/// Return a valid size if the instruction is a folded restore instruction.
1777	std::optional<LocationSize>
1778	getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1779
1780	/// Copy implicit register operands from specified
1781	/// instruction to this instruction.
1782	void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1783
1784	/// Debugging support
1785	/// @{
1786	/// Determine the generic type to be printed (if needed) on uses and defs.
1787	LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1788	const MachineRegisterInfo &MRI) const;
1789
1790	/// Return true when an instruction has tied register that can't be determined
1791	/// by the instruction's descriptor. This is useful for MIR printing, to
1792	/// determine whether we need to print the ties or not.
1793	bool hasComplexRegisterTies() const;
1794
1795	/// Print this MI to \p OS.
1796	/// Don't print information that can be inferred from other instructions if
1797	/// \p IsStandalone is false. It is usually true when only a fragment of the
1798	/// function is printed.
1799	/// Only print the defs and the opcode if \p SkipOpers is true.
1800	/// Otherwise, also print operands if \p SkipDebugLoc is true.
1801	/// Otherwise, also print the debug loc, with a terminating newline.
1802	/// \p TII is used to print the opcode name. If it's not present, but the
1803	/// MI is in a function, the opcode will be printed using the function's TII.
1804	void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1805	bool SkipDebugLoc = false, bool AddNewLine = true,
1806	const TargetInstrInfo *TII = nullptr) const;
1807	void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1808	bool SkipOpers = false, bool SkipDebugLoc = false,
1809	bool AddNewLine = true,
1810	const TargetInstrInfo *TII = nullptr) const;
1811	void dump() const;
1812	/// Print on dbgs() the current instruction and the instructions defining its
1813	/// operands and so on until we reach \p MaxDepth.
1814	void dumpr(const MachineRegisterInfo &MRI,
1815	unsigned MaxDepth = UINT_MAX) const;
1816	/// @}
1817
1818	//===--------------------------------------------------------------------===//
1819	// Accessors used to build up machine instructions.
1820
1821	/// Add the specified operand to the instruction. If it is an implicit
1822	/// operand, it is added to the end of the operand list. If it is an
1823	/// explicit operand it is added at the end of the explicit operand list
1824	/// (before the first implicit operand).
1825	///
1826	/// MF must be the machine function that was used to allocate this
1827	/// instruction.
1828	///
1829	/// MachineInstrBuilder provides a more convenient interface for creating
1830	/// instructions and adding operands.
1831	void addOperand(MachineFunction &MF, const MachineOperand &Op);
1832
1833	/// Add an operand without providing an MF reference. This only works for
1834	/// instructions that are inserted in a basic block.
1835	///
1836	/// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1837	/// preferred.
1838	void addOperand(const MachineOperand &Op);
1839
1840	/// Inserts Ops BEFORE It. Can untie/retie tied operands.
1841	void insert(mop_iterator InsertBefore, ArrayRef<MachineOperand> Ops);
1842
1843	/// Replace the instruction descriptor (thus opcode) of
1844	/// the current instruction with a new one.
1845	void setDesc(const MCInstrDesc &TID);
1846
1847	/// Replace current source information with new such.
1848	/// Avoid using this, the constructor argument is preferable.
1849	void setDebugLoc(DebugLoc DL) {
1850	DbgLoc = std::move(DL);
1851	assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
1852	}
1853
1854	/// Erase an operand from an instruction, leaving it with one
1855	/// fewer operand than it started with.
1856	void removeOperand(unsigned OpNo);
1857
1858	/// Clear this MachineInstr's memory reference descriptor list. This resets
1859	/// the memrefs to their most conservative state. This should be used only
1860	/// as a last resort since it greatly pessimizes our knowledge of the memory
1861	/// access performed by the instruction.
1862	void dropMemRefs(MachineFunction &MF);
1863
1864	/// Assign this MachineInstr's memory reference descriptor list.
1865	///
1866	/// Unlike other methods, this *will* allocate them into a new array
1867	/// associated with the provided `MachineFunction`.
1868	void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1869
1870	/// Add a MachineMemOperand to the machine instruction.
1871	/// This function should be used only occasionally. The setMemRefs function
1872	/// is the primary method for setting up a MachineInstr's MemRefs list.
1873	void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1874
1875	/// Clone another MachineInstr's memory reference descriptor list and replace
1876	/// ours with it.
1877	///
1878	/// Note that `*this` may be the incoming MI!
1879	///
1880	/// Prefer this API whenever possible as it can avoid allocations in common
1881	/// cases.
1882	void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1883
1884	/// Clone the merge of multiple MachineInstrs' memory reference descriptors
1885	/// list and replace ours with it.
1886	///
1887	/// Note that `*this` may be one of the incoming MIs!
1888	///
1889	/// Prefer this API whenever possible as it can avoid allocations in common
1890	/// cases.
1891	void cloneMergedMemRefs(MachineFunction &MF,
1892	ArrayRef<const MachineInstr *> MIs);
1893
1894	/// Set a symbol that will be emitted just prior to the instruction itself.
1895	///
1896	/// Setting this to a null pointer will remove any such symbol.
1897	///
1898	/// FIXME: This is not fully implemented yet.
1899	void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1900
1901	/// Set a symbol that will be emitted just after the instruction itself.
1902	///
1903	/// Setting this to a null pointer will remove any such symbol.
1904	///
1905	/// FIXME: This is not fully implemented yet.
1906	void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1907
1908	/// Clone another MachineInstr's pre- and post- instruction symbols and
1909	/// replace ours with it.
1910	void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1911
1912	/// Set a marker on instructions that denotes where we should create and emit
1913	/// heap alloc site labels. This waits until after instruction selection and
1914	/// optimizations to create the label, so it should still work if the
1915	/// instruction is removed or duplicated.
1916	void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1917
1918	// Set metadata on instructions that say which sections to emit instruction
1919	// addresses into.
1920	void setPCSections(MachineFunction &MF, MDNode *MD);
1921
1922	void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs);
1923
1924	/// Set the CFI type for the instruction.
1925	void setCFIType(MachineFunction &MF, uint32_t Type);
1926
1927	/// Return the MIFlags which represent both MachineInstrs. This
1928	/// should be used when merging two MachineInstrs into one. This routine does
1929	/// not modify the MIFlags of this MachineInstr.
1930	uint32_t mergeFlagsWith(const MachineInstr& Other) const;
1931
1932	static uint32_t copyFlagsFromInstruction(const Instruction &I);
1933
1934	/// Copy all flags to MachineInst MIFlags
1935	void copyIRFlags(const Instruction &I);
1936
1937	/// Break any tie involving OpIdx.
1938	void untieRegOperand(unsigned OpIdx) {
1939	MachineOperand &MO = getOperand(i: OpIdx);
1940	if (MO.isReg() && MO.isTied()) {
1941	getOperand(i: findTiedOperandIdx(OpIdx)).TiedTo = 0;
1942	MO.TiedTo = 0;
1943	}
1944	}
1945
1946	/// Add all implicit def and use operands to this instruction.
1947	void addImplicitDefUseOperands(MachineFunction &MF);
1948
1949	/// Scan instructions immediately following MI and collect any matching
1950	/// DBG_VALUEs.
1951	void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1952
1953	/// Find all DBG_VALUEs that point to the register def in this instruction
1954	/// and point them to \p Reg instead.
1955	void changeDebugValuesDefReg(Register Reg);
1956
1957	/// Sets all register debug operands in this debug value instruction to be
1958	/// undef.
1959	void setDebugValueUndef() {
1960	assert(isDebugValue() && "Must be a debug value instruction.");
1961	for (MachineOperand &MO : debug_operands()) {
1962	if (MO.isReg()) {
1963	MO.setReg(0);
1964	MO.setSubReg(0);
1965	}
1966	}
1967	}
1968
1969	std::tuple<Register, Register> getFirst2Regs() const {
1970	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg());
1971	}
1972
1973	std::tuple<Register, Register, Register> getFirst3Regs() const {
1974	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1975	getOperand(i: 2).getReg());
1976	}
1977
1978	std::tuple<Register, Register, Register, Register> getFirst4Regs() const {
1979	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1980	getOperand(i: 2).getReg(), getOperand(i: 3).getReg());
1981	}
1982
1983	std::tuple<Register, Register, Register, Register, Register>
1984	getFirst5Regs() const {
1985	return std::tuple(getOperand(i: 0).getReg(), getOperand(i: 1).getReg(),
1986	getOperand(i: 2).getReg(), getOperand(i: 3).getReg(),
1987	getOperand(i: 4).getReg());
1988	}
1989
1990	std::tuple<LLT, LLT> getFirst2LLTs() const;
1991	std::tuple<LLT, LLT, LLT> getFirst3LLTs() const;
1992	std::tuple<LLT, LLT, LLT, LLT> getFirst4LLTs() const;
1993	std::tuple<LLT, LLT, LLT, LLT, LLT> getFirst5LLTs() const;
1994
1995	std::tuple<Register, LLT, Register, LLT> getFirst2RegLLTs() const;
1996	std::tuple<Register, LLT, Register, LLT, Register, LLT>
1997	getFirst3RegLLTs() const;
1998	std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
1999	getFirst4RegLLTs() const;
2000	std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT,
2001	Register, LLT>
2002	getFirst5RegLLTs() const;
2003
2004	private:
2005	/// If this instruction is embedded into a MachineFunction, return the
2006	/// MachineRegisterInfo object for the current function, otherwise
2007	/// return null.
2008	MachineRegisterInfo *getRegInfo();
2009	const MachineRegisterInfo *getRegInfo() const;
2010
2011	/// Unlink all of the register operands in this instruction from their
2012	/// respective use lists. This requires that the operands already be on their
2013	/// use lists.
2014	void removeRegOperandsFromUseLists(MachineRegisterInfo&);
2015
2016	/// Add all of the register operands in this instruction from their
2017	/// respective use lists. This requires that the operands not be on their
2018	/// use lists yet.
2019	void addRegOperandsToUseLists(MachineRegisterInfo&);
2020
2021	/// Slow path for hasProperty when we're dealing with a bundle.
2022	bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
2023
2024	/// Implements the logic of getRegClassConstraintEffectForVReg for the
2025	/// this MI and the given operand index \p OpIdx.
2026	/// If the related operand does not constrained Reg, this returns CurRC.
2027	const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
2028	unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
2029	const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
2030
2031	/// Stores extra instruction information inline or allocates as ExtraInfo
2032	/// based on the number of pointers.
2033	void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
2034	MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
2035	MDNode *HeapAllocMarker, MDNode *PCSections,
2036	uint32_t CFIType, MDNode *MMRAs);
2037	};
2038
2039	/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
2040	/// instruction rather than by pointer value.
2041	/// The hashing and equality testing functions ignore definitions so this is
2042	/// useful for CSE, etc.
2043	struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
2044	static inline MachineInstr *getEmptyKey() {
2045	return nullptr;
2046	}
2047
2048	static inline MachineInstr *getTombstoneKey() {
2049	return reinterpret_cast<MachineInstr*>(-1);
2050	}
2051
2052	static unsigned getHashValue(const MachineInstr* const &MI);
2053
2054	static bool isEqual(const MachineInstr* const &LHS,
2055	const MachineInstr* const &RHS) {
2056	if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
2057	LHS == getEmptyKey() || LHS == getTombstoneKey())
2058	return LHS == RHS;
2059	return LHS->isIdenticalTo(Other: *RHS, Check: MachineInstr::IgnoreVRegDefs);
2060	}
2061	};
2062
2063	//===----------------------------------------------------------------------===//
2064	// Debugging Support
2065
2066	inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
2067	MI.print(OS);
2068	return OS;
2069	}
2070
2071	} // end namespace llvm
2072
2073	#endif // LLVM_CODEGEN_MACHINEINSTR_H
2074