1	//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// This file describes the target machine instruction set to the code generator.
10	//
11	//===----------------------------------------------------------------------===//
12
13	#ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14	#define LLVM_CODEGEN_TARGETINSTRINFO_H
15
16	#include "llvm/ADT/ArrayRef.h"
17	#include "llvm/ADT/DenseMap.h"
18	#include "llvm/ADT/DenseMapInfo.h"
19	#include "llvm/ADT/Uniformity.h"
20	#include "llvm/CodeGen/MIRFormatter.h"
21	#include "llvm/CodeGen/MachineBasicBlock.h"
22	#include "llvm/CodeGen/MachineCombinerPattern.h"
23	#include "llvm/CodeGen/MachineCycleAnalysis.h"
24	#include "llvm/CodeGen/MachineFunction.h"
25	#include "llvm/CodeGen/MachineInstr.h"
26	#include "llvm/CodeGen/MachineInstrBuilder.h"
27	#include "llvm/CodeGen/MachineOperand.h"
28	#include "llvm/CodeGen/MachineOutliner.h"
29	#include "llvm/CodeGen/RegisterClassInfo.h"
30	#include "llvm/CodeGen/VirtRegMap.h"
31	#include "llvm/MC/MCInstrInfo.h"
32	#include "llvm/Support/BranchProbability.h"
33	#include "llvm/Support/ErrorHandling.h"
34	#include <array>
35	#include <cassert>
36	#include <cstddef>
37	#include <cstdint>
38	#include <utility>
39	#include <vector>
40
41	namespace llvm {
42
43	class DFAPacketizer;
44	class InstrItineraryData;
45	class LiveIntervals;
46	class LiveVariables;
47	class MachineLoop;
48	class MachineMemOperand;
49	class MachineRegisterInfo;
50	class MCAsmInfo;
51	class MCInst;
52	struct MCSchedModel;
53	class Module;
54	class ScheduleDAG;
55	class ScheduleDAGMI;
56	class ScheduleHazardRecognizer;
57	class SDNode;
58	class SelectionDAG;
59	class SMSchedule;
60	class SwingSchedulerDAG;
61	class RegScavenger;
62	class TargetRegisterClass;
63	class TargetRegisterInfo;
64	class TargetSchedModel;
65	class TargetSubtargetInfo;
66	enum class MachineTraceStrategy;
67
68	template <class T> class SmallVectorImpl;
69
70	using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
71
72	struct DestSourcePair {
73	const MachineOperand *Destination;
74	const MachineOperand *Source;
75
76	DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
77	: Destination(&Dest), Source(&Src) {}
78	};
79
80	/// Used to describe a register and immediate addition.
81	struct RegImmPair {
82	Register Reg;
83	int64_t Imm;
84
85	RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
86	};
87
88	/// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
89	/// It holds the register values, the scale value and the displacement.
90	/// It also holds a descriptor for the expression used to calculate the address
91	/// from the operands.
92	struct ExtAddrMode {
93	enum class Formula {
94	Basic = 0, // BaseReg + ScaledReg * Scale + Displacement
95	SExtScaledReg = 1, // BaseReg + sext(ScaledReg) * Scale + Displacement
96	ZExtScaledReg = 2 // BaseReg + zext(ScaledReg) * Scale + Displacement
97	};
98
99	Register BaseReg;
100	Register ScaledReg;
101	int64_t Scale = 0;
102	int64_t Displacement = 0;
103	Formula Form = Formula::Basic;
104	ExtAddrMode() = default;
105	};
106
107	//---------------------------------------------------------------------------
108	///
109	/// TargetInstrInfo - Interface to description of machine instruction set
110	///
111	class TargetInstrInfo : public MCInstrInfo {
112	public:
113	TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
114	unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
115	: CallFrameSetupOpcode(CFSetupOpcode),
116	CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
117	ReturnOpcode(ReturnOpcode) {}
118	TargetInstrInfo(const TargetInstrInfo &) = delete;
119	TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
120	virtual ~TargetInstrInfo();
121
122	static bool isGenericOpcode(unsigned Opc) {
123	return Opc <= TargetOpcode::GENERIC_OP_END;
124	}
125
126	static bool isGenericAtomicRMWOpcode(unsigned Opc) {
127	return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
128	Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
129	}
130
131	/// Given a machine instruction descriptor, returns the register
132	/// class constraint for OpNum, or NULL.
133	virtual
134	const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
135	const TargetRegisterInfo *TRI,
136	const MachineFunction &MF) const;
137
138	/// Return true if the instruction is trivially rematerializable, meaning it
139	/// has no side effects and requires no operands that aren't always available.
140	/// This means the only allowed uses are constants and unallocatable physical
141	/// registers so that the instructions result is independent of the place
142	/// in the function.
143	bool isTriviallyReMaterializable(const MachineInstr &MI) const {
144	return (MI.getOpcode() == TargetOpcode::IMPLICIT_DEF &&
145	MI.getNumOperands() == 1) ||
146	(MI.getDesc().isRematerializable() &&
147	isReallyTriviallyReMaterializable(MI));
148	}
149
150	/// Given \p MO is a PhysReg use return if it can be ignored for the purpose
151	/// of instruction rematerialization or sinking.
152	virtual bool isIgnorableUse(const MachineOperand &MO) const {
153	return false;
154	}
155
156	virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
157	MachineCycleInfo *CI) const {
158	return true;
159	}
160
161	protected:
162	/// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
163	/// set, this hook lets the target specify whether the instruction is actually
164	/// trivially rematerializable, taking into consideration its operands. This
165	/// predicate must return false if the instruction has any side effects other
166	/// than producing a value, or if it requres any address registers that are
167	/// not always available.
168	virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
169
170	/// This method commutes the operands of the given machine instruction MI.
171	/// The operands to be commuted are specified by their indices OpIdx1 and
172	/// OpIdx2.
173	///
174	/// If a target has any instructions that are commutable but require
175	/// converting to different instructions or making non-trivial changes
176	/// to commute them, this method can be overloaded to do that.
177	/// The default implementation simply swaps the commutable operands.
178	///
179	/// If NewMI is false, MI is modified in place and returned; otherwise, a
180	/// new machine instruction is created and returned.
181	///
182	/// Do not call this method for a non-commutable instruction.
183	/// Even though the instruction is commutable, the method may still
184	/// fail to commute the operands, null pointer is returned in such cases.
185	virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
186	unsigned OpIdx1,
187	unsigned OpIdx2) const;
188
189	/// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
190	/// operand indices to (ResultIdx1, ResultIdx2).
191	/// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
192	/// predefined to some indices or be undefined (designated by the special
193	/// value 'CommuteAnyOperandIndex').
194	/// The predefined result indices cannot be re-defined.
195	/// The function returns true iff after the result pair redefinition
196	/// the fixed result pair is equal to or equivalent to the source pair of
197	/// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
198	/// the pairs (x,y) and (y,x) are equivalent.
199	static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
200	unsigned CommutableOpIdx1,
201	unsigned CommutableOpIdx2);
202
203	public:
204	/// These methods return the opcode of the frame setup/destroy instructions
205	/// if they exist (-1 otherwise). Some targets use pseudo instructions in
206	/// order to abstract away the difference between operating with a frame
207	/// pointer and operating without, through the use of these two instructions.
208	/// A FrameSetup MI in MF implies MFI::AdjustsStack.
209	///
210	unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
211	unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
212
213	/// Returns true if the argument is a frame pseudo instruction.
214	bool isFrameInstr(const MachineInstr &I) const {
215	return I.getOpcode() == getCallFrameSetupOpcode() ||
216	I.getOpcode() == getCallFrameDestroyOpcode();
217	}
218
219	/// Returns true if the argument is a frame setup pseudo instruction.
220	bool isFrameSetup(const MachineInstr &I) const {
221	return I.getOpcode() == getCallFrameSetupOpcode();
222	}
223
224	/// Returns size of the frame associated with the given frame instruction.
225	/// For frame setup instruction this is frame that is set up space set up
226	/// after the instruction. For frame destroy instruction this is the frame
227	/// freed by the caller.
228	/// Note, in some cases a call frame (or a part of it) may be prepared prior
229	/// to the frame setup instruction. It occurs in the calls that involve
230	/// inalloca arguments. This function reports only the size of the frame part
231	/// that is set up between the frame setup and destroy pseudo instructions.
232	int64_t getFrameSize(const MachineInstr &I) const {
233	assert(isFrameInstr(I) && "Not a frame instruction");
234	assert(I.getOperand(0).getImm() >= 0);
235	return I.getOperand(i: 0).getImm();
236	}
237
238	/// Returns the total frame size, which is made up of the space set up inside
239	/// the pair of frame start-stop instructions and the space that is set up
240	/// prior to the pair.
241	int64_t getFrameTotalSize(const MachineInstr &I) const {
242	if (isFrameSetup(I)) {
243	assert(I.getOperand(1).getImm() >= 0 &&
244	"Frame size must not be negative");
245	return getFrameSize(I) + I.getOperand(i: 1).getImm();
246	}
247	return getFrameSize(I);
248	}
249
250	unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
251	unsigned getReturnOpcode() const { return ReturnOpcode; }
252
253	/// Returns the actual stack pointer adjustment made by an instruction
254	/// as part of a call sequence. By default, only call frame setup/destroy
255	/// instructions adjust the stack, but targets may want to override this
256	/// to enable more fine-grained adjustment, or adjust by a different value.
257	virtual int getSPAdjust(const MachineInstr &MI) const;
258
259	/// Return true if the instruction is a "coalescable" extension instruction.
260	/// That is, it's like a copy where it's legal for the source to overlap the
261	/// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
262	/// expected the pre-extension value is available as a subreg of the result
263	/// register. This also returns the sub-register index in SubIdx.
264	virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
265	Register &DstReg, unsigned &SubIdx) const {
266	return false;
267	}
268
269	/// If the specified machine instruction is a direct
270	/// load from a stack slot, return the virtual or physical register number of
271	/// the destination along with the FrameIndex of the loaded stack slot. If
272	/// not, return 0. This predicate must return 0 if the instruction has
273	/// any side effects other than loading from the stack slot.
274	virtual Register isLoadFromStackSlot(const MachineInstr &MI,
275	int &FrameIndex) const {
276	return 0;
277	}
278
279	/// Optional extension of isLoadFromStackSlot that returns the number of
280	/// bytes loaded from the stack. This must be implemented if a backend
281	/// supports partial stack slot spills/loads to further disambiguate
282	/// what the load does.
283	virtual Register isLoadFromStackSlot(const MachineInstr &MI,
284	int &FrameIndex,
285	unsigned &MemBytes) const {
286	MemBytes = 0;
287	return isLoadFromStackSlot(MI, FrameIndex);
288	}
289
290	/// Check for post-frame ptr elimination stack locations as well.
291	/// This uses a heuristic so it isn't reliable for correctness.
292	virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
293	int &FrameIndex) const {
294	return 0;
295	}
296
297	/// If the specified machine instruction has a load from a stack slot,
298	/// return true along with the FrameIndices of the loaded stack slot and the
299	/// machine mem operands containing the reference.
300	/// If not, return false. Unlike isLoadFromStackSlot, this returns true for
301	/// any instructions that loads from the stack. This is just a hint, as some
302	/// cases may be missed.
303	virtual bool hasLoadFromStackSlot(
304	const MachineInstr &MI,
305	SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
306
307	/// If the specified machine instruction is a direct
308	/// store to a stack slot, return the virtual or physical register number of
309	/// the source reg along with the FrameIndex of the loaded stack slot. If
310	/// not, return 0. This predicate must return 0 if the instruction has
311	/// any side effects other than storing to the stack slot.
312	virtual Register isStoreToStackSlot(const MachineInstr &MI,
313	int &FrameIndex) const {
314	return 0;
315	}
316
317	/// Optional extension of isStoreToStackSlot that returns the number of
318	/// bytes stored to the stack. This must be implemented if a backend
319	/// supports partial stack slot spills/loads to further disambiguate
320	/// what the store does.
321	virtual Register isStoreToStackSlot(const MachineInstr &MI,
322	int &FrameIndex,
323	unsigned &MemBytes) const {
324	MemBytes = 0;
325	return isStoreToStackSlot(MI, FrameIndex);
326	}
327
328	/// Check for post-frame ptr elimination stack locations as well.
329	/// This uses a heuristic, so it isn't reliable for correctness.
330	virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI,
331	int &FrameIndex) const {
332	return 0;
333	}
334
335	/// If the specified machine instruction has a store to a stack slot,
336	/// return true along with the FrameIndices of the loaded stack slot and the
337	/// machine mem operands containing the reference.
338	/// If not, return false. Unlike isStoreToStackSlot,
339	/// this returns true for any instructions that stores to the
340	/// stack. This is just a hint, as some cases may be missed.
341	virtual bool hasStoreToStackSlot(
342	const MachineInstr &MI,
343	SmallVectorImpl<const MachineMemOperand *> &Accesses) const;
344
345	/// Return true if the specified machine instruction
346	/// is a copy of one stack slot to another and has no other effect.
347	/// Provide the identity of the two frame indices.
348	virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
349	int &SrcFrameIndex) const {
350	return false;
351	}
352
353	/// Compute the size in bytes and offset within a stack slot of a spilled
354	/// register or subregister.
355	///
356	/// \param [out] Size in bytes of the spilled value.
357	/// \param [out] Offset in bytes within the stack slot.
358	/// \returns true if both Size and Offset are successfully computed.
359	///
360	/// Not all subregisters have computable spill slots. For example,
361	/// subregisters registers may not be byte-sized, and a pair of discontiguous
362	/// subregisters has no single offset.
363	///
364	/// Targets with nontrivial bigendian implementations may need to override
365	/// this, particularly to support spilled vector registers.
366	virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
367	unsigned &Size, unsigned &Offset,
368	const MachineFunction &MF) const;
369
370	/// Return true if the given instruction is terminator that is unspillable,
371	/// according to isUnspillableTerminatorImpl.
372	bool isUnspillableTerminator(const MachineInstr *MI) const {
373	return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
374	}
375
376	/// Returns the size in bytes of the specified MachineInstr, or ~0U
377	/// when this function is not implemented by a target.
378	virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
379	return ~0U;
380	}
381
382	/// Return true if the instruction is as cheap as a move instruction.
383	///
384	/// Targets for different archs need to override this, and different
385	/// micro-architectures can also be finely tuned inside.
386	virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
387	return MI.isAsCheapAsAMove();
388	}
389
390	/// Return true if the instruction should be sunk by MachineSink.
391	///
392	/// MachineSink determines on its own whether the instruction is safe to sink;
393	/// this gives the target a hook to override the default behavior with regards
394	/// to which instructions should be sunk.
395	virtual bool shouldSink(const MachineInstr &MI) const { return true; }
396
397	/// Return false if the instruction should not be hoisted by MachineLICM.
398	///
399	/// MachineLICM determines on its own whether the instruction is safe to
400	/// hoist; this gives the target a hook to extend this assessment and prevent
401	/// an instruction being hoisted from a given loop for target specific
402	/// reasons.
403	virtual bool shouldHoist(const MachineInstr &MI,
404	const MachineLoop *FromLoop) const {
405	return true;
406	}
407
408	/// Re-issue the specified 'original' instruction at the
409	/// specific location targeting a new destination register.
410	/// The register in Orig->getOperand(0).getReg() will be substituted by
411	/// DestReg:SubIdx. Any existing subreg index is preserved or composed with
412	/// SubIdx.
413	virtual void reMaterialize(MachineBasicBlock &MBB,
414	MachineBasicBlock::iterator MI, Register DestReg,
415	unsigned SubIdx, const MachineInstr &Orig,
416	const TargetRegisterInfo &TRI) const;
417
418	/// Clones instruction or the whole instruction bundle \p Orig and
419	/// insert into \p MBB before \p InsertBefore. The target may update operands
420	/// that are required to be unique.
421	///
422	/// \p Orig must not return true for MachineInstr::isNotDuplicable().
423	virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
424	MachineBasicBlock::iterator InsertBefore,
425	const MachineInstr &Orig) const;
426
427	/// This method must be implemented by targets that
428	/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
429	/// may be able to convert a two-address instruction into one or more true
430	/// three-address instructions on demand. This allows the X86 target (for
431	/// example) to convert ADD and SHL instructions into LEA instructions if they
432	/// would require register copies due to two-addressness.
433	///
434	/// This method returns a null pointer if the transformation cannot be
435	/// performed, otherwise it returns the last new instruction.
436	///
437	/// If \p LIS is not nullptr, the LiveIntervals info should be updated for
438	/// replacing \p MI with new instructions, even though this function does not
439	/// remove MI.
440	virtual MachineInstr *convertToThreeAddress(MachineInstr &MI,
441	LiveVariables *LV,
442	LiveIntervals *LIS) const {
443	return nullptr;
444	}
445
446	// This constant can be used as an input value of operand index passed to
447	// the method findCommutedOpIndices() to tell the method that the
448	// corresponding operand index is not pre-defined and that the method
449	// can pick any commutable operand.
450	static const unsigned CommuteAnyOperandIndex = ~0U;
451
452	/// This method commutes the operands of the given machine instruction MI.
453	///
454	/// The operands to be commuted are specified by their indices OpIdx1 and
455	/// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
456	/// 'CommuteAnyOperandIndex', which means that the method is free to choose
457	/// any arbitrarily chosen commutable operand. If both arguments are set to
458	/// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
459	/// operands; then commutes them if such operands could be found.
460	///
461	/// If NewMI is false, MI is modified in place and returned; otherwise, a
462	/// new machine instruction is created and returned.
463	///
464	/// Do not call this method for a non-commutable instruction or
465	/// for non-commuable operands.
466	/// Even though the instruction is commutable, the method may still
467	/// fail to commute the operands, null pointer is returned in such cases.
468	MachineInstr *
469	commuteInstruction(MachineInstr &MI, bool NewMI = false,
470	unsigned OpIdx1 = CommuteAnyOperandIndex,
471	unsigned OpIdx2 = CommuteAnyOperandIndex) const;
472
473	/// Returns true iff the routine could find two commutable operands in the
474	/// given machine instruction.
475	/// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
476	/// If any of the INPUT values is set to the special value
477	/// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
478	/// operand, then returns its index in the corresponding argument.
479	/// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
480	/// looks for 2 commutable operands.
481	/// If INPUT values refer to some operands of MI, then the method simply
482	/// returns true if the corresponding operands are commutable and returns
483	/// false otherwise.
484	///
485	/// For example, calling this method this way:
486	/// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
487	/// findCommutedOpIndices(MI, Op1, Op2);
488	/// can be interpreted as a query asking to find an operand that would be
489	/// commutable with the operand#1.
490	virtual bool findCommutedOpIndices(const MachineInstr &MI,
491	unsigned &SrcOpIdx1,
492	unsigned &SrcOpIdx2) const;
493
494	/// Returns true if the target has a preference on the operands order of
495	/// the given machine instruction. And specify if \p Commute is required to
496	/// get the desired operands order.
497	virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
498	return false;
499	}
500
501	/// A pair composed of a register and a sub-register index.
502	/// Used to give some type checking when modeling Reg:SubReg.
503	struct RegSubRegPair {
504	Register Reg;
505	unsigned SubReg;
506
507	RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
508	: Reg(Reg), SubReg(SubReg) {}
509
510	bool operator==(const RegSubRegPair& P) const {
511	return Reg == P.Reg && SubReg == P.SubReg;
512	}
513	bool operator!=(const RegSubRegPair& P) const {
514	return !(*this == P);
515	}
516	};
517
518	/// A pair composed of a pair of a register and a sub-register index,
519	/// and another sub-register index.
520	/// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
521	struct RegSubRegPairAndIdx : RegSubRegPair {
522	unsigned SubIdx;
523
524	RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0,
525	unsigned SubIdx = 0)
526	: RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
527	};
528
529	/// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
530	/// and \p DefIdx.
531	/// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
532	/// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
533	/// flag are not added to this list.
534	/// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
535	/// two elements:
536	/// - %1:sub1, sub0
537	/// - %2<:0>, sub1
538	///
539	/// \returns true if it is possible to build such an input sequence
540	/// with the pair \p MI, \p DefIdx. False otherwise.
541	///
542	/// \pre MI.isRegSequence() or MI.isRegSequenceLike().
543	///
544	/// \note The generic implementation does not provide any support for
545	/// MI.isRegSequenceLike(). In other words, one has to override
546	/// getRegSequenceLikeInputs for target specific instructions.
547	bool
548	getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
549	SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
550
551	/// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
552	/// and \p DefIdx.
553	/// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
554	/// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
555	/// - %1:sub1, sub0
556	///
557	/// \returns true if it is possible to build such an input sequence
558	/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
559	/// False otherwise.
560	///
561	/// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
562	///
563	/// \note The generic implementation does not provide any support for
564	/// MI.isExtractSubregLike(). In other words, one has to override
565	/// getExtractSubregLikeInputs for target specific instructions.
566	bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
567	RegSubRegPairAndIdx &InputReg) const;
568
569	/// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
570	/// and \p DefIdx.
571	/// \p [out] BaseReg and \p [out] InsertedReg contain
572	/// the equivalent inputs of INSERT_SUBREG.
573	/// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
574	/// - BaseReg: %0:sub0
575	/// - InsertedReg: %1:sub1, sub3
576	///
577	/// \returns true if it is possible to build such an input sequence
578	/// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
579	/// False otherwise.
580	///
581	/// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
582	///
583	/// \note The generic implementation does not provide any support for
584	/// MI.isInsertSubregLike(). In other words, one has to override
585	/// getInsertSubregLikeInputs for target specific instructions.
586	bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
587	RegSubRegPair &BaseReg,
588	RegSubRegPairAndIdx &InsertedReg) const;
589
590	/// Return true if two machine instructions would produce identical values.
591	/// By default, this is only true when the two instructions
592	/// are deemed identical except for defs. If this function is called when the
593	/// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
594	/// aggressive checks.
595	virtual bool produceSameValue(const MachineInstr &MI0,
596	const MachineInstr &MI1,
597	const MachineRegisterInfo *MRI = nullptr) const;
598
599	/// \returns true if a branch from an instruction with opcode \p BranchOpc
600	/// bytes is capable of jumping to a position \p BrOffset bytes away.
601	virtual bool isBranchOffsetInRange(unsigned BranchOpc,
602	int64_t BrOffset) const {
603	llvm_unreachable("target did not implement");
604	}
605
606	/// \returns The block that branch instruction \p MI jumps to.
607	virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
608	llvm_unreachable("target did not implement");
609	}
610
611	/// Insert an unconditional indirect branch at the end of \p MBB to \p
612	/// NewDestBB. Optionally, insert the clobbered register restoring in \p
613	/// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
614	/// the offset of the position to insert the new branch.
615	virtual void insertIndirectBranch(MachineBasicBlock &MBB,
616	MachineBasicBlock &NewDestBB,
617	MachineBasicBlock &RestoreBB,
618	const DebugLoc &DL, int64_t BrOffset = 0,
619	RegScavenger *RS = nullptr) const {
620	llvm_unreachable("target did not implement");
621	}
622
623	/// Analyze the branching code at the end of MBB, returning
624	/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
625	/// implemented for a target). Upon success, this returns false and returns
626	/// with the following information in various cases:
627	///
628	/// 1. If this block ends with no branches (it just falls through to its succ)
629	/// just return false, leaving TBB/FBB null.
630	/// 2. If this block ends with only an unconditional branch, it sets TBB to be
631	/// the destination block.
632	/// 3. If this block ends with a conditional branch and it falls through to a
633	/// successor block, it sets TBB to be the branch destination block and a
634	/// list of operands that evaluate the condition. These operands can be
635	/// passed to other TargetInstrInfo methods to create new branches.
636	/// 4. If this block ends with a conditional branch followed by an
637	/// unconditional branch, it returns the 'true' destination in TBB, the
638	/// 'false' destination in FBB, and a list of operands that evaluate the
639	/// condition. These operands can be passed to other TargetInstrInfo
640	/// methods to create new branches.
641	///
642	/// Note that removeBranch and insertBranch must be implemented to support
643	/// cases where this method returns success.
644	///
645	/// If AllowModify is true, then this routine is allowed to modify the basic
646	/// block (e.g. delete instructions after the unconditional branch).
647	///
648	/// The CFG information in MBB.Predecessors and MBB.Successors must be valid
649	/// before calling this function.
650	virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
651	MachineBasicBlock *&FBB,
652	SmallVectorImpl<MachineOperand> &Cond,
653	bool AllowModify = false) const {
654	return true;
655	}
656
657	/// Represents a predicate at the MachineFunction level. The control flow a
658	/// MachineBranchPredicate represents is:
659	///
660	/// Reg = LHS `Predicate` RHS == ConditionDef
661	/// if Reg then goto TrueDest else goto FalseDest
662	///
663	struct MachineBranchPredicate {
664	enum ComparePredicate {
665	PRED_EQ, // True if two values are equal
666	PRED_NE, // True if two values are not equal
667	PRED_INVALID // Sentinel value
668	};
669
670	ComparePredicate Predicate = PRED_INVALID;
671	MachineOperand LHS = MachineOperand::CreateImm(Val: 0);
672	MachineOperand RHS = MachineOperand::CreateImm(Val: 0);
673	MachineBasicBlock *TrueDest = nullptr;
674	MachineBasicBlock *FalseDest = nullptr;
675	MachineInstr *ConditionDef = nullptr;
676
677	/// SingleUseCondition is true if ConditionDef is dead except for the
678	/// branch(es) at the end of the basic block.
679	///
680	bool SingleUseCondition = false;
681
682	explicit MachineBranchPredicate() = default;
683	};
684
685	/// Analyze the branching code at the end of MBB and parse it into the
686	/// MachineBranchPredicate structure if possible. Returns false on success
687	/// and true on failure.
688	///
689	/// If AllowModify is true, then this routine is allowed to modify the basic
690	/// block (e.g. delete instructions after the unconditional branch).
691	///
692	virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
693	MachineBranchPredicate &MBP,
694	bool AllowModify = false) const {
695	return true;
696	}
697
698	/// Remove the branching code at the end of the specific MBB.
699	/// This is only invoked in cases where analyzeBranch returns success. It
700	/// returns the number of instructions that were removed.
701	/// If \p BytesRemoved is non-null, report the change in code size from the
702	/// removed instructions.
703	virtual unsigned removeBranch(MachineBasicBlock &MBB,
704	int *BytesRemoved = nullptr) const {
705	llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
706	}
707
708	/// Insert branch code into the end of the specified MachineBasicBlock. The
709	/// operands to this method are the same as those returned by analyzeBranch.
710	/// This is only invoked in cases where analyzeBranch returns success. It
711	/// returns the number of instructions inserted. If \p BytesAdded is non-null,
712	/// report the change in code size from the added instructions.
713	///
714	/// It is also invoked by tail merging to add unconditional branches in
715	/// cases where analyzeBranch doesn't apply because there was no original
716	/// branch to analyze. At least this much must be implemented, else tail
717	/// merging needs to be disabled.
718	///
719	/// The CFG information in MBB.Predecessors and MBB.Successors must be valid
720	/// before calling this function.
721	virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
722	MachineBasicBlock *FBB,
723	ArrayRef<MachineOperand> Cond,
724	const DebugLoc &DL,
725	int *BytesAdded = nullptr) const {
726	llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
727	}
728
729	unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
730	MachineBasicBlock *DestBB,
731	const DebugLoc &DL,
732	int *BytesAdded = nullptr) const {
733	return insertBranch(MBB, TBB: DestBB, FBB: nullptr, Cond: ArrayRef<MachineOperand>(), DL,
734	BytesAdded);
735	}
736
737	/// Object returned by analyzeLoopForPipelining. Allows software pipelining
738	/// implementations to query attributes of the loop being pipelined and to
739	/// apply target-specific updates to the loop once pipelining is complete.
740	class PipelinerLoopInfo {
741	public:
742	virtual ~PipelinerLoopInfo();
743	/// Return true if the given instruction should not be pipelined and should
744	/// be ignored. An example could be a loop comparison, or induction variable
745	/// update with no users being pipelined.
746	virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
747
748	/// Return true if the proposed schedule should used. Otherwise return
749	/// false to not pipeline the loop. This function should be used to ensure
750	/// that pipelined loops meet target-specific quality heuristics.
751	virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS) {
752	return true;
753	}
754
755	/// Create a condition to determine if the trip count of the loop is greater
756	/// than TC, where TC is always one more than for the previous prologue or
757	/// 0 if this is being called for the outermost prologue.
758	///
759	/// If the trip count is statically known to be greater than TC, return
760	/// true. If the trip count is statically known to be not greater than TC,
761	/// return false. Otherwise return nullopt and fill out Cond with the test
762	/// condition.
763	///
764	/// Note: This hook is guaranteed to be called from the innermost to the
765	/// outermost prologue of the loop being software pipelined.
766	virtual std::optional<bool>
767	createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
768	SmallVectorImpl<MachineOperand> &Cond) = 0;
769
770	/// Modify the loop such that the trip count is
771	/// OriginalTC + TripCountAdjust.
772	virtual void adjustTripCount(int TripCountAdjust) = 0;
773
774	/// Called when the loop's preheader has been modified to NewPreheader.
775	virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
776
777	/// Called when the loop is being removed. Any instructions in the preheader
778	/// should be removed.
779	///
780	/// Once this function is called, no other functions on this object are
781	/// valid; the loop has been removed.
782	virtual void disposed() = 0;
783	};
784
785	/// Analyze loop L, which must be a single-basic-block loop, and if the
786	/// conditions can be understood enough produce a PipelinerLoopInfo object.
787	virtual std::unique_ptr<PipelinerLoopInfo>
788	analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
789	return nullptr;
790	}
791
792	/// Analyze the loop code, return true if it cannot be understood. Upon
793	/// success, this function returns false and returns information about the
794	/// induction variable and compare instruction used at the end.
795	virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
796	MachineInstr *&CmpInst) const {
797	return true;
798	}
799
800	/// Generate code to reduce the loop iteration by one and check if the loop
801	/// is finished. Return the value/register of the new loop count. We need
802	/// this function when peeling off one or more iterations of a loop. This
803	/// function assumes the nth iteration is peeled first.
804	virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
805	MachineBasicBlock &PreHeader,
806	MachineInstr *IndVar, MachineInstr &Cmp,
807	SmallVectorImpl<MachineOperand> &Cond,
808	SmallVectorImpl<MachineInstr *> &PrevInsts,
809	unsigned Iter, unsigned MaxIter) const {
810	llvm_unreachable("Target didn't implement ReduceLoopCount");
811	}
812
813	/// Delete the instruction OldInst and everything after it, replacing it with
814	/// an unconditional branch to NewDest. This is used by the tail merging pass.
815	virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
816	MachineBasicBlock *NewDest) const;
817
818	/// Return true if it's legal to split the given basic
819	/// block at the specified instruction (i.e. instruction would be the start
820	/// of a new basic block).
821	virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
822	MachineBasicBlock::iterator MBBI) const {
823	return true;
824	}
825
826	/// Return true if it's profitable to predicate
827	/// instructions with accumulated instruction latency of "NumCycles"
828	/// of the specified basic block, where the probability of the instructions
829	/// being executed is given by Probability, and Confidence is a measure
830	/// of our confidence that it will be properly predicted.
831	virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
832	unsigned ExtraPredCycles,
833	BranchProbability Probability) const {
834	return false;
835	}
836
837	/// Second variant of isProfitableToIfCvt. This one
838	/// checks for the case where two basic blocks from true and false path
839	/// of a if-then-else (diamond) are predicated on mutually exclusive
840	/// predicates, where the probability of the true path being taken is given
841	/// by Probability, and Confidence is a measure of our confidence that it
842	/// will be properly predicted.
843	virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
844	unsigned ExtraTCycles,
845	MachineBasicBlock &FMBB, unsigned NumFCycles,
846	unsigned ExtraFCycles,
847	BranchProbability Probability) const {
848	return false;
849	}
850
851	/// Return true if it's profitable for if-converter to duplicate instructions
852	/// of specified accumulated instruction latencies in the specified MBB to
853	/// enable if-conversion.
854	/// The probability of the instructions being executed is given by
855	/// Probability, and Confidence is a measure of our confidence that it
856	/// will be properly predicted.
857	virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
858	unsigned NumCycles,
859	BranchProbability Probability) const {
860	return false;
861	}
862
863	/// Return the increase in code size needed to predicate a contiguous run of
864	/// NumInsts instructions.
865	virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF,
866	unsigned NumInsts) const {
867	return 0;
868	}
869
870	/// Return an estimate for the code size reduction (in bytes) which will be
871	/// caused by removing the given branch instruction during if-conversion.
872	virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
873	return getInstSizeInBytes(MI);
874	}
875
876	/// Return true if it's profitable to unpredicate
877	/// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
878	/// exclusive predicates.
879	/// e.g.
880	/// subeq r0, r1, #1
881	/// addne r0, r1, #1
882	/// =>
883	/// sub r0, r1, #1
884	/// addne r0, r1, #1
885	///
886	/// This may be profitable is conditional instructions are always executed.
887	virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
888	MachineBasicBlock &FMBB) const {
889	return false;
890	}
891
892	/// Return true if it is possible to insert a select
893	/// instruction that chooses between TrueReg and FalseReg based on the
894	/// condition code in Cond.
895	///
896	/// When successful, also return the latency in cycles from TrueReg,
897	/// FalseReg, and Cond to the destination register. In most cases, a select
898	/// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
899	///
900	/// Some x86 implementations have 2-cycle cmov instructions.
901	///
902	/// @param MBB Block where select instruction would be inserted.
903	/// @param Cond Condition returned by analyzeBranch.
904	/// @param DstReg Virtual dest register that the result should write to.
905	/// @param TrueReg Virtual register to select when Cond is true.
906	/// @param FalseReg Virtual register to select when Cond is false.
907	/// @param CondCycles Latency from Cond+Branch to select output.
908	/// @param TrueCycles Latency from TrueReg to select output.
909	/// @param FalseCycles Latency from FalseReg to select output.
910	virtual bool canInsertSelect(const MachineBasicBlock &MBB,
911	ArrayRef<MachineOperand> Cond, Register DstReg,
912	Register TrueReg, Register FalseReg,
913	int &CondCycles, int &TrueCycles,
914	int &FalseCycles) const {
915	return false;
916	}
917
918	/// Insert a select instruction into MBB before I that will copy TrueReg to
919	/// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
920	///
921	/// This function can only be called after canInsertSelect() returned true.
922	/// The condition in Cond comes from analyzeBranch, and it can be assumed
923	/// that the same flags or registers required by Cond are available at the
924	/// insertion point.
925	///
926	/// @param MBB Block where select instruction should be inserted.
927	/// @param I Insertion point.
928	/// @param DL Source location for debugging.
929	/// @param DstReg Virtual register to be defined by select instruction.
930	/// @param Cond Condition as computed by analyzeBranch.
931	/// @param TrueReg Virtual register to copy when Cond is true.
932	/// @param FalseReg Virtual register to copy when Cons is false.
933	virtual void insertSelect(MachineBasicBlock &MBB,
934	MachineBasicBlock::iterator I, const DebugLoc &DL,
935	Register DstReg, ArrayRef<MachineOperand> Cond,
936	Register TrueReg, Register FalseReg) const {
937	llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
938	}
939
940	/// Analyze the given select instruction, returning true if
941	/// it cannot be understood. It is assumed that MI->isSelect() is true.
942	///
943	/// When successful, return the controlling condition and the operands that
944	/// determine the true and false result values.
945	///
946	/// Result = SELECT Cond, TrueOp, FalseOp
947	///
948	/// Some targets can optimize select instructions, for example by predicating
949	/// the instruction defining one of the operands. Such targets should set
950	/// Optimizable.
951	///
952	/// @param MI Select instruction to analyze.
953	/// @param Cond Condition controlling the select.
954	/// @param TrueOp Operand number of the value selected when Cond is true.
955	/// @param FalseOp Operand number of the value selected when Cond is false.
956	/// @param Optimizable Returned as true if MI is optimizable.
957	/// @returns False on success.
958	virtual bool analyzeSelect(const MachineInstr &MI,
959	SmallVectorImpl<MachineOperand> &Cond,
960	unsigned &TrueOp, unsigned &FalseOp,
961	bool &Optimizable) const {
962	assert(MI.getDesc().isSelect() && "MI must be a select instruction");
963	return true;
964	}
965
966	/// Given a select instruction that was understood by
967	/// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
968	/// merging it with one of its operands. Returns NULL on failure.
969	///
970	/// When successful, returns the new select instruction. The client is
971	/// responsible for deleting MI.
972	///
973	/// If both sides of the select can be optimized, PreferFalse is used to pick
974	/// a side.
975	///
976	/// @param MI Optimizable select instruction.
977	/// @param NewMIs Set that record all MIs in the basic block up to \p
978	/// MI. Has to be updated with any newly created MI or deleted ones.
979	/// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
980	/// @returns Optimized instruction or NULL.
981	virtual MachineInstr *optimizeSelect(MachineInstr &MI,
982	SmallPtrSetImpl<MachineInstr *> &NewMIs,
983	bool PreferFalse = false) const {
984	// This function must be implemented if Optimizable is ever set.
985	llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
986	}
987
988	/// Emit instructions to copy a pair of physical registers.
989	///
990	/// This function should support copies within any legal register class as
991	/// well as any cross-class copies created during instruction selection.
992	///
993	/// The source and destination registers may overlap, which may require a
994	/// careful implementation when multiple copy instructions are required for
995	/// large registers. See for example the ARM target.
996	virtual void copyPhysReg(MachineBasicBlock &MBB,
997	MachineBasicBlock::iterator MI, const DebugLoc &DL,
998	MCRegister DestReg, MCRegister SrcReg,
999	bool KillSrc) const {
1000	llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
1001	}
1002
1003	/// Allow targets to tell MachineVerifier whether a specific register
1004	/// MachineOperand can be used as part of PC-relative addressing.
1005	/// PC-relative addressing modes in many CISC architectures contain
1006	/// (non-PC) registers as offsets or scaling values, which inherently
1007	/// tags the corresponding MachineOperand with OPERAND_PCREL.
1008	///
1009	/// @param MO The MachineOperand in question. MO.isReg() should always
1010	/// be true.
1011	/// @return Whether this operand is allowed to be used PC-relatively.
1012	virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
1013	return false;
1014	}
1015
1016	/// Return an index for MachineJumpTableInfo if \p insn is an indirect jump
1017	/// using a jump table, otherwise -1.
1018	virtual int getJumpTableIndex(const MachineInstr &MI) const { return -1; }
1019
1020	protected:
1021	/// Target-dependent implementation for IsCopyInstr.
1022	/// If the specific machine instruction is a instruction that moves/copies
1023	/// value from one register to another register return destination and source
1024	/// registers as machine operands.
1025	virtual std::optional<DestSourcePair>
1026	isCopyInstrImpl(const MachineInstr &MI) const {
1027	return std::nullopt;
1028	}
1029
1030	virtual std::optional<DestSourcePair>
1031	isCopyLikeInstrImpl(const MachineInstr &MI) const {
1032	return std::nullopt;
1033	}
1034
1035	/// Return true if the given terminator MI is not expected to spill. This
1036	/// sets the live interval as not spillable and adjusts phi node lowering to
1037	/// not introduce copies after the terminator. Use with care, these are
1038	/// currently used for hardware loop intrinsics in very controlled situations,
1039	/// created prior to registry allocation in loops that only have single phi
1040	/// users for the terminators value. They may run out of registers if not used
1041	/// carefully.
1042	virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
1043	return false;
1044	}
1045
1046	public:
1047	/// If the specific machine instruction is a instruction that moves/copies
1048	/// value from one register to another register return destination and source
1049	/// registers as machine operands.
1050	/// For COPY-instruction the method naturally returns destination and source
1051	/// registers as machine operands, for all other instructions the method calls
1052	/// target-dependent implementation.
1053	std::optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
1054	if (MI.isCopy()) {
1055	return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
1056	}
1057	return isCopyInstrImpl(MI);
1058	}
1059
1060	// Similar to `isCopyInstr`, but adds non-copy semantics on MIR, but
1061	// ultimately generates a copy instruction.
1062	std::optional<DestSourcePair> isCopyLikeInstr(const MachineInstr &MI) const {
1063	if (auto IsCopyInstr = isCopyInstr(MI))
1064	return IsCopyInstr;
1065	return isCopyLikeInstrImpl(MI);
1066	}
1067
1068	bool isFullCopyInstr(const MachineInstr &MI) const {
1069	auto DestSrc = isCopyInstr(MI);
1070	if (!DestSrc)
1071	return false;
1072
1073	const MachineOperand *DestRegOp = DestSrc->Destination;
1074	const MachineOperand *SrcRegOp = DestSrc->Source;
1075	return !DestRegOp->getSubReg() && !SrcRegOp->getSubReg();
1076	}
1077
1078	/// If the specific machine instruction is an instruction that adds an
1079	/// immediate value and a register, and stores the result in the given
1080	/// register \c Reg, return a pair of the source register and the offset
1081	/// which has been added.
1082	virtual std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
1083	Register Reg) const {
1084	return std::nullopt;
1085	}
1086
1087	/// Returns true if MI is an instruction that defines Reg to have a constant
1088	/// value and the value is recorded in ImmVal. The ImmVal is a result that
1089	/// should be interpreted as modulo size of Reg.
1090	virtual bool getConstValDefinedInReg(const MachineInstr &MI,
1091	const Register Reg,
1092	int64_t &ImmVal) const {
1093	return false;
1094	}
1095
1096	/// Store the specified register of the given register class to the specified
1097	/// stack frame index. The store instruction is to be added to the given
1098	/// machine basic block before the specified machine instruction. If isKill
1099	/// is true, the register operand is the last use and must be marked kill. If
1100	/// \p SrcReg is being directly spilled as part of assigning a virtual
1101	/// register, \p VReg is the register being assigned. This additional register
1102	/// argument is needed for certain targets when invoked from RegAllocFast to
1103	/// map the spilled physical register to its virtual register. A null register
1104	/// can be passed elsewhere.
1105	virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
1106	MachineBasicBlock::iterator MI,
1107	Register SrcReg, bool isKill, int FrameIndex,
1108	const TargetRegisterClass *RC,
1109	const TargetRegisterInfo *TRI,
1110	Register VReg) const {
1111	llvm_unreachable("Target didn't implement "
1112	"TargetInstrInfo::storeRegToStackSlot!");
1113	}
1114
1115	/// Load the specified register of the given register class from the specified
1116	/// stack frame index. The load instruction is to be added to the given
1117	/// machine basic block before the specified machine instruction. If \p
1118	/// DestReg is being directly reloaded as part of assigning a virtual
1119	/// register, \p VReg is the register being assigned. This additional register
1120	/// argument is needed for certain targets when invoked from RegAllocFast to
1121	/// map the loaded physical register to its virtual register. A null register
1122	/// can be passed elsewhere.
1123	virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
1124	MachineBasicBlock::iterator MI,
1125	Register DestReg, int FrameIndex,
1126	const TargetRegisterClass *RC,
1127	const TargetRegisterInfo *TRI,
1128	Register VReg) const {
1129	llvm_unreachable("Target didn't implement "
1130	"TargetInstrInfo::loadRegFromStackSlot!");
1131	}
1132
1133	/// This function is called for all pseudo instructions
1134	/// that remain after register allocation. Many pseudo instructions are
1135	/// created to help register allocation. This is the place to convert them
1136	/// into real instructions. The target can edit MI in place, or it can insert
1137	/// new instructions and erase MI. The function should return true if
1138	/// anything was changed.
1139	virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1140
1141	/// Check whether the target can fold a load that feeds a subreg operand
1142	/// (or a subreg operand that feeds a store).
1143	/// For example, X86 may want to return true if it can fold
1144	/// movl (%esp), %eax
1145	/// subb, %al, ...
1146	/// Into:
1147	/// subb (%esp), ...
1148	///
1149	/// Ideally, we'd like the target implementation of foldMemoryOperand() to
1150	/// reject subregs - but since this behavior used to be enforced in the
1151	/// target-independent code, moving this responsibility to the targets
1152	/// has the potential of causing nasty silent breakage in out-of-tree targets.
1153	virtual bool isSubregFoldable() const { return false; }
1154
1155	/// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1156	/// operands which can't be folded into stack references. Operands outside
1157	/// of the range are most likely foldable but it is not guaranteed.
1158	/// These instructions are unique in that stack references for some operands
1159	/// have the same execution cost (e.g. none) as the unfolded register forms.
1160	/// The ranged return is guaranteed to include all operands which can't be
1161	/// folded at zero cost.
1162	virtual std::pair<unsigned, unsigned>
1163	getPatchpointUnfoldableRange(const MachineInstr &MI) const;
1164
1165	/// Attempt to fold a load or store of the specified stack
1166	/// slot into the specified machine instruction for the specified operand(s).
1167	/// If this is possible, a new instruction is returned with the specified
1168	/// operand folded, otherwise NULL is returned.
1169	/// The new instruction is inserted before MI, and the client is responsible
1170	/// for removing the old instruction.
1171	/// If VRM is passed, the assigned physregs can be inspected by target to
1172	/// decide on using an opcode (note that those assignments can still change).
1173	MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
1174	int FI,
1175	LiveIntervals *LIS = nullptr,
1176	VirtRegMap *VRM = nullptr) const;
1177
1178	/// Same as the previous version except it allows folding of any load and
1179	/// store from / to any address, not just from a specific stack slot.
1180	MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
1181	MachineInstr &LoadMI,
1182	LiveIntervals *LIS = nullptr) const;
1183
1184	/// This function defines the logic to lower COPY instruction to
1185	/// target specific instruction(s).
1186	void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const;
1187
1188	/// Return true when there is potentially a faster code sequence
1189	/// for an instruction chain ending in \p Root. All potential patterns are
1190	/// returned in the \p Pattern vector. Pattern should be sorted in priority
1191	/// order since the pattern evaluator stops checking as soon as it finds a
1192	/// faster sequence.
1193	/// \param Root - Instruction that could be combined with one of its operands
1194	/// \param Patterns - Vector of possible combination patterns
1195	virtual bool getMachineCombinerPatterns(MachineInstr &Root,
1196	SmallVectorImpl<unsigned> &Patterns,
1197	bool DoRegPressureReduce) const;
1198
1199	/// Return true if target supports reassociation of instructions in machine
1200	/// combiner pass to reduce register pressure for a given BB.
1201	virtual bool
1202	shouldReduceRegisterPressure(const MachineBasicBlock *MBB,
1203	const RegisterClassInfo *RegClassInfo) const {
1204	return false;
1205	}
1206
1207	/// Fix up the placeholder we may add in genAlternativeCodeSequence().
1208	virtual void
1209	finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern,
1210	SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1211
1212	/// Return true when a code sequence can improve throughput. It
1213	/// should be called only for instructions in loops.
1214	/// \param Pattern - combiner pattern
1215	virtual bool isThroughputPattern(unsigned Pattern) const;
1216
1217	/// Return the objective of a combiner pattern.
1218	/// \param Pattern - combiner pattern
1219	virtual CombinerObjective getCombinerObjective(unsigned Pattern) const;
1220
1221	/// Return true if the input \P Inst is part of a chain of dependent ops
1222	/// that are suitable for reassociation, otherwise return false.
1223	/// If the instruction's operands must be commuted to have a previous
1224	/// instruction of the same type define the first source operand, \P Commuted
1225	/// will be set to true.
1226	bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1227
1228	/// Return true when \P Inst is both associative and commutative. If \P Invert
1229	/// is true, then the inverse of \P Inst operation must be tested.
1230	virtual bool isAssociativeAndCommutative(const MachineInstr &Inst,
1231	bool Invert = false) const {
1232	return false;
1233	}
1234
1235	/// Return the inverse operation opcode if it exists for \P Opcode (e.g. add
1236	/// for sub and vice versa).
1237	virtual std::optional<unsigned> getInverseOpcode(unsigned Opcode) const {
1238	return std::nullopt;
1239	}
1240
1241	/// Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
1242	bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
1243
1244	/// Return true when \P Inst has reassociable operands in the same \P MBB.
1245	virtual bool hasReassociableOperands(const MachineInstr &Inst,
1246	const MachineBasicBlock *MBB) const;
1247
1248	/// Return true when \P Inst has reassociable sibling.
1249	virtual bool hasReassociableSibling(const MachineInstr &Inst,
1250	bool &Commuted) const;
1251
1252	/// When getMachineCombinerPatterns() finds patterns, this function generates
1253	/// the instructions that could replace the original code sequence. The client
1254	/// has to decide whether the actual replacement is beneficial or not.
1255	/// \param Root - Instruction that could be combined with one of its operands
1256	/// \param Pattern - Combination pattern for Root
1257	/// \param InsInstrs - Vector of new instructions that implement P
1258	/// \param DelInstrs - Old instructions, including Root, that could be
1259	/// replaced by InsInstr
1260	/// \param InstIdxForVirtReg - map of virtual register to instruction in
1261	/// InsInstr that defines it
1262	virtual void genAlternativeCodeSequence(
1263	MachineInstr &Root, unsigned Pattern,
1264	SmallVectorImpl<MachineInstr *> &InsInstrs,
1265	SmallVectorImpl<MachineInstr *> &DelInstrs,
1266	DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1267
1268	/// When calculate the latency of the root instruction, accumulate the
1269	/// latency of the sequence to the root latency.
1270	/// \param Root - Instruction that could be combined with one of its operands
1271	virtual bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const {
1272	return true;
1273	}
1274
1275	/// The returned array encodes the operand index for each parameter because
1276	/// the operands may be commuted; the operand indices for associative
1277	/// operations might also be target-specific. Each element specifies the index
1278	/// of {Prev, A, B, X, Y}.
1279	virtual void
1280	getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern,
1281	std::array<unsigned, 5> &OperandIndices) const;
1282
1283	/// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1284	/// reduce critical path length.
1285	void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
1286	SmallVectorImpl<MachineInstr *> &InsInstrs,
1287	SmallVectorImpl<MachineInstr *> &DelInstrs,
1288	ArrayRef<unsigned> OperandIndices,
1289	DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1290
1291	/// Reassociation of some instructions requires inverse operations (e.g.
1292	/// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes
1293	/// (new root opcode, new prev opcode) that must be used to reassociate \P
1294	/// Root and \P Prev accoring to \P Pattern.
1295	std::pair<unsigned, unsigned>
1296	getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root,
1297	const MachineInstr &Prev) const;
1298
1299	/// The limit on resource length extension we accept in MachineCombiner Pass.
1300	virtual int getExtendResourceLenLimit() const { return 0; }
1301
1302	/// This is an architecture-specific helper function of reassociateOps.
1303	/// Set special operand attributes for new instructions after reassociation.
1304	virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1305	MachineInstr &NewMI1,
1306	MachineInstr &NewMI2) const {}
1307
1308	/// Return true when a target supports MachineCombiner.
1309	virtual bool useMachineCombiner() const { return false; }
1310
1311	/// Return a strategy that MachineCombiner must use when creating traces.
1312	virtual MachineTraceStrategy getMachineCombinerTraceStrategy() const;
1313
1314	/// Return true if the given SDNode can be copied during scheduling
1315	/// even if it has glue.
1316	virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1317
1318	protected:
1319	/// Target-dependent implementation for foldMemoryOperand.
1320	/// Target-independent code in foldMemoryOperand will
1321	/// take care of adding a MachineMemOperand to the newly created instruction.
1322	/// The instruction and any auxiliary instructions necessary will be inserted
1323	/// at InsertPt.
1324	virtual MachineInstr *
1325	foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
1326	ArrayRef<unsigned> Ops,
1327	MachineBasicBlock::iterator InsertPt, int FrameIndex,
1328	LiveIntervals *LIS = nullptr,
1329	VirtRegMap *VRM = nullptr) const {
1330	return nullptr;
1331	}
1332
1333	/// Target-dependent implementation for foldMemoryOperand.
1334	/// Target-independent code in foldMemoryOperand will
1335	/// take care of adding a MachineMemOperand to the newly created instruction.
1336	/// The instruction and any auxiliary instructions necessary will be inserted
1337	/// at InsertPt.
1338	virtual MachineInstr *foldMemoryOperandImpl(
1339	MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1340	MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1341	LiveIntervals *LIS = nullptr) const {
1342	return nullptr;
1343	}
1344
1345	/// Target-dependent implementation of getRegSequenceInputs.
1346	///
1347	/// \returns true if it is possible to build the equivalent
1348	/// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1349	///
1350	/// \pre MI.isRegSequenceLike().
1351	///
1352	/// \see TargetInstrInfo::getRegSequenceInputs.
1353	virtual bool getRegSequenceLikeInputs(
1354	const MachineInstr &MI, unsigned DefIdx,
1355	SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1356	return false;
1357	}
1358
1359	/// Target-dependent implementation of getExtractSubregInputs.
1360	///
1361	/// \returns true if it is possible to build the equivalent
1362	/// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1363	///
1364	/// \pre MI.isExtractSubregLike().
1365	///
1366	/// \see TargetInstrInfo::getExtractSubregInputs.
1367	virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1368	unsigned DefIdx,
1369	RegSubRegPairAndIdx &InputReg) const {
1370	return false;
1371	}
1372
1373	/// Target-dependent implementation of getInsertSubregInputs.
1374	///
1375	/// \returns true if it is possible to build the equivalent
1376	/// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1377	///
1378	/// \pre MI.isInsertSubregLike().
1379	///
1380	/// \see TargetInstrInfo::getInsertSubregInputs.
1381	virtual bool
1382	getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1383	RegSubRegPair &BaseReg,
1384	RegSubRegPairAndIdx &InsertedReg) const {
1385	return false;
1386	}
1387
1388	public:
1389	/// unfoldMemoryOperand - Separate a single instruction which folded a load or
1390	/// a store or a load and a store into two or more instruction. If this is
1391	/// possible, returns true as well as the new instructions by reference.
1392	virtual bool
1393	unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1394	bool UnfoldLoad, bool UnfoldStore,
1395	SmallVectorImpl<MachineInstr *> &NewMIs) const {
1396	return false;
1397	}
1398
1399	virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1400	SmallVectorImpl<SDNode *> &NewNodes) const {
1401	return false;
1402	}
1403
1404	/// Returns the opcode of the would be new
1405	/// instruction after load / store are unfolded from an instruction of the
1406	/// specified opcode. It returns zero if the specified unfolding is not
1407	/// possible. If LoadRegIndex is non-null, it is filled in with the operand
1408	/// index of the operand which will hold the register holding the loaded
1409	/// value.
1410	virtual unsigned
1411	getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1412	unsigned *LoadRegIndex = nullptr) const {
1413	return 0;
1414	}
1415
1416	/// This is used by the pre-regalloc scheduler to determine if two loads are
1417	/// loading from the same base address. It should only return true if the base
1418	/// pointers are the same and the only differences between the two addresses
1419	/// are the offset. It also returns the offsets by reference.
1420	virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1421	int64_t &Offset1,
1422	int64_t &Offset2) const {
1423	return false;
1424	}
1425
1426	/// This is a used by the pre-regalloc scheduler to determine (in conjunction
1427	/// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1428	/// On some targets if two loads are loading from
1429	/// addresses in the same cache line, it's better if they are scheduled
1430	/// together. This function takes two integers that represent the load offsets
1431	/// from the common base address. It returns true if it decides it's desirable
1432	/// to schedule the two loads together. "NumLoads" is the number of loads that
1433	/// have already been scheduled after Load1.
1434	virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1435	int64_t Offset1, int64_t Offset2,
1436	unsigned NumLoads) const {
1437	return false;
1438	}
1439
1440	/// Get the base operand and byte offset of an instruction that reads/writes
1441	/// memory. This is a convenience function for callers that are only prepared
1442	/// to handle a single base operand.
1443	/// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1444	/// abstraction that supports negative offsets.
1445	bool getMemOperandWithOffset(const MachineInstr &MI,
1446	const MachineOperand *&BaseOp, int64_t &Offset,
1447	bool &OffsetIsScalable,
1448	const TargetRegisterInfo *TRI) const;
1449
1450	/// Get zero or more base operands and the byte offset of an instruction that
1451	/// reads/writes memory. Note that there may be zero base operands if the
1452	/// instruction accesses a constant address.
1453	/// It returns false if MI does not read/write memory.
1454	/// It returns false if base operands and offset could not be determined.
1455	/// It is not guaranteed to always recognize base operands and offsets in all
1456	/// cases.
1457	/// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1458	/// abstraction that supports negative offsets.
1459	virtual bool getMemOperandsWithOffsetWidth(
1460	const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
1461	int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
1462	const TargetRegisterInfo *TRI) const {
1463	return false;
1464	}
1465
1466	/// Return true if the instruction contains a base register and offset. If
1467	/// true, the function also sets the operand position in the instruction
1468	/// for the base register and offset.
1469	virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1470	unsigned &BasePos,
1471	unsigned &OffsetPos) const {
1472	return false;
1473	}
1474
1475	/// Target dependent implementation to get the values constituting the address
1476	/// MachineInstr that is accessing memory. These values are returned as a
1477	/// struct ExtAddrMode which contains all relevant information to make up the
1478	/// address.
1479	virtual std::optional<ExtAddrMode>
1480	getAddrModeFromMemoryOp(const MachineInstr &MemI,
1481	const TargetRegisterInfo *TRI) const {
1482	return std::nullopt;
1483	}
1484
1485	/// Check if it's possible and beneficial to fold the addressing computation
1486	/// `AddrI` into the addressing mode of the load/store instruction `MemI`. The
1487	/// memory instruction is a user of the virtual register `Reg`, which in turn
1488	/// is the ultimate destination of zero or more COPY instructions from the
1489	/// output register of `AddrI`.
1490	/// Return the adddressing mode after folding in `AM`.
1491	virtual bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
1492	const MachineInstr &AddrI,
1493	ExtAddrMode &AM) const {
1494	return false;
1495	}
1496
1497	/// Emit a load/store instruction with the same value register as `MemI`, but
1498	/// using the address from `AM`. The addressing mode must have been obtained
1499	/// from `canFoldIntoAddr` for the same memory instruction.
1500	virtual MachineInstr *emitLdStWithAddr(MachineInstr &MemI,
1501	const ExtAddrMode &AM) const {
1502	llvm_unreachable("target did not implement emitLdStWithAddr()");
1503	}
1504
1505	/// Returns true if MI's Def is NullValueReg, and the MI
1506	/// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1507	/// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1508	/// function can return true even if becomes zero. Specifically cases such as
1509	/// NullValueReg = shl NullValueReg, 63.
1510	virtual bool preservesZeroValueInReg(const MachineInstr *MI,
1511	const Register NullValueReg,
1512	const TargetRegisterInfo *TRI) const {
1513	return false;
1514	}
1515
1516	/// If the instruction is an increment of a constant value, return the amount.
1517	virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1518	return false;
1519	}
1520
1521	/// Returns true if the two given memory operations should be scheduled
1522	/// adjacent. Note that you have to add:
1523	/// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1524	/// or
1525	/// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1526	/// to TargetPassConfig::createMachineScheduler() to have an effect.
1527	///
1528	/// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1529	/// \p Offset1 and \p Offset2 are the byte offsets for the memory
1530	/// operations.
1531	/// \p OffsetIsScalable1 and \p OffsetIsScalable2 indicate if the offset is
1532	/// scaled by a runtime quantity.
1533	/// \p ClusterSize is the number of operations in the resulting load/store
1534	/// cluster if this hook returns true.
1535	/// \p NumBytes is the number of bytes that will be loaded from all the
1536	/// clustered loads if this hook returns true.
1537	virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
1538	int64_t Offset1, bool OffsetIsScalable1,
1539	ArrayRef<const MachineOperand *> BaseOps2,
1540	int64_t Offset2, bool OffsetIsScalable2,
1541	unsigned ClusterSize,
1542	unsigned NumBytes) const {
1543	llvm_unreachable("target did not implement shouldClusterMemOps()");
1544	}
1545
1546	/// Reverses the branch condition of the specified condition list,
1547	/// returning false on success and true if it cannot be reversed.
1548	virtual bool
1549	reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1550	return true;
1551	}
1552
1553	/// Insert a noop into the instruction stream at the specified point.
1554	virtual void insertNoop(MachineBasicBlock &MBB,
1555	MachineBasicBlock::iterator MI) const;
1556
1557	/// Insert noops into the instruction stream at the specified point.
1558	virtual void insertNoops(MachineBasicBlock &MBB,
1559	MachineBasicBlock::iterator MI,
1560	unsigned Quantity) const;
1561
1562	/// Return the noop instruction to use for a noop.
1563	virtual MCInst getNop() const;
1564
1565	/// Return true for post-incremented instructions.
1566	virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1567
1568	/// Returns true if the instruction is already predicated.
1569	virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1570
1571	/// Assumes the instruction is already predicated and returns true if the
1572	/// instruction can be predicated again.
1573	virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const {
1574	assert(isPredicated(MI) && "Instruction is not predicated");
1575	return false;
1576	}
1577
1578	// Returns a MIRPrinter comment for this machine operand.
1579	virtual std::string
1580	createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
1581	unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1582
1583	/// Returns true if the instruction is a
1584	/// terminator instruction that has not been predicated.
1585	bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1586
1587	/// Returns true if MI is an unconditional tail call.
1588	virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1589	return false;
1590	}
1591
1592	/// Returns true if the tail call can be made conditional on BranchCond.
1593	virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1594	const MachineInstr &TailCall) const {
1595	return false;
1596	}
1597
1598	/// Replace the conditional branch in MBB with a conditional tail call.
1599	virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1600	SmallVectorImpl<MachineOperand> &Cond,
1601	const MachineInstr &TailCall) const {
1602	llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1603	}
1604
1605	/// Convert the instruction into a predicated instruction.
1606	/// It returns true if the operation was successful.
1607	virtual bool PredicateInstruction(MachineInstr &MI,
1608	ArrayRef<MachineOperand> Pred) const;
1609
1610	/// Returns true if the first specified predicate
1611	/// subsumes the second, e.g. GE subsumes GT.
1612	virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1613	ArrayRef<MachineOperand> Pred2) const {
1614	return false;
1615	}
1616
1617	/// If the specified instruction defines any predicate
1618	/// or condition code register(s) used for predication, returns true as well
1619	/// as the definition predicate(s) by reference.
1620	/// SkipDead should be set to false at any point that dead
1621	/// predicate instructions should be considered as being defined.
1622	/// A dead predicate instruction is one that is guaranteed to be removed
1623	/// after a call to PredicateInstruction.
1624	virtual bool ClobbersPredicate(MachineInstr &MI,
1625	std::vector<MachineOperand> &Pred,
1626	bool SkipDead) const {
1627	return false;
1628	}
1629
1630	/// Return true if the specified instruction can be predicated.
1631	/// By default, this returns true for every instruction with a
1632	/// PredicateOperand.
1633	virtual bool isPredicable(const MachineInstr &MI) const {
1634	return MI.getDesc().isPredicable();
1635	}
1636
1637	/// Return true if it's safe to move a machine
1638	/// instruction that defines the specified register class.
1639	virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1640	return true;
1641	}
1642
1643	/// Test if the given instruction should be considered a scheduling boundary.
1644	/// This primarily includes labels and terminators.
1645	virtual bool isSchedulingBoundary(const MachineInstr &MI,
1646	const MachineBasicBlock *MBB,
1647	const MachineFunction &MF) const;
1648
1649	/// Measure the specified inline asm to determine an approximation of its
1650	/// length.
1651	virtual unsigned getInlineAsmLength(
1652	const char *Str, const MCAsmInfo &MAI,
1653	const TargetSubtargetInfo *STI = nullptr) const;
1654
1655	/// Allocate and return a hazard recognizer to use for this target when
1656	/// scheduling the machine instructions before register allocation.
1657	virtual ScheduleHazardRecognizer *
1658	CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1659	const ScheduleDAG *DAG) const;
1660
1661	/// Allocate and return a hazard recognizer to use for this target when
1662	/// scheduling the machine instructions before register allocation.
1663	virtual ScheduleHazardRecognizer *
1664	CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1665	const ScheduleDAGMI *DAG) const;
1666
1667	/// Allocate and return a hazard recognizer to use for this target when
1668	/// scheduling the machine instructions after register allocation.
1669	virtual ScheduleHazardRecognizer *
1670	CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1671	const ScheduleDAG *DAG) const;
1672
1673	/// Allocate and return a hazard recognizer to use for by non-scheduling
1674	/// passes.
1675	virtual ScheduleHazardRecognizer *
1676	CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1677	return nullptr;
1678	}
1679
1680	/// Provide a global flag for disabling the PreRA hazard recognizer that
1681	/// targets may choose to honor.
1682	bool usePreRAHazardRecognizer() const;
1683
1684	/// For a comparison instruction, return the source registers
1685	/// in SrcReg and SrcReg2 if having two register operands, and the value it
1686	/// compares against in CmpValue. Return true if the comparison instruction
1687	/// can be analyzed.
1688	virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1689	Register &SrcReg2, int64_t &Mask,
1690	int64_t &Value) const {
1691	return false;
1692	}
1693
1694	/// See if the comparison instruction can be converted
1695	/// into something more efficient. E.g., on ARM most instructions can set the
1696	/// flags register, obviating the need for a separate CMP.
1697	virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1698	Register SrcReg2, int64_t Mask,
1699	int64_t Value,
1700	const MachineRegisterInfo *MRI) const {
1701	return false;
1702	}
1703	virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1704
1705	/// Try to remove the load by folding it to a register operand at the use.
1706	/// We fold the load instructions if and only if the
1707	/// def and use are in the same BB. We only look at one load and see
1708	/// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1709	/// defined by the load we are trying to fold. DefMI returns the machine
1710	/// instruction that defines FoldAsLoadDefReg, and the function returns
1711	/// the machine instruction generated due to folding.
1712	virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1713	const MachineRegisterInfo *MRI,
1714	Register &FoldAsLoadDefReg,
1715	MachineInstr *&DefMI) const {
1716	return nullptr;
1717	}
1718
1719	/// 'Reg' is known to be defined by a move immediate instruction,
1720	/// try to fold the immediate into the use instruction.
1721	/// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1722	/// then the caller may assume that DefMI has been erased from its parent
1723	/// block. The caller may assume that it will not be erased by this
1724	/// function otherwise.
1725	virtual bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1726	Register Reg, MachineRegisterInfo *MRI) const {
1727	return false;
1728	}
1729
1730	/// Return the number of u-operations the given machine
1731	/// instruction will be decoded to on the target cpu. The itinerary's
1732	/// IssueWidth is the number of microops that can be dispatched each
1733	/// cycle. An instruction with zero microops takes no dispatch resources.
1734	virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1735	const MachineInstr &MI) const;
1736
1737	/// Return true for pseudo instructions that don't consume any
1738	/// machine resources in their current form. These are common cases that the
1739	/// scheduler should consider free, rather than conservatively handling them
1740	/// as instructions with no itinerary.
1741	bool isZeroCost(unsigned Opcode) const {
1742	return Opcode <= TargetOpcode::COPY;
1743	}
1744
1745	virtual std::optional<unsigned>
1746	getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1747	unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1748
1749	/// Compute and return the use operand latency of a given pair of def and use.
1750	/// In most cases, the static scheduling itinerary was enough to determine the
1751	/// operand latency. But it may not be possible for instructions with variable
1752	/// number of defs / uses.
1753	///
1754	/// This is a raw interface to the itinerary that may be directly overridden
1755	/// by a target. Use computeOperandLatency to get the best estimate of
1756	/// latency.
1757	virtual std::optional<unsigned>
1758	getOperandLatency(const InstrItineraryData *ItinData,
1759	const MachineInstr &DefMI, unsigned DefIdx,
1760	const MachineInstr &UseMI, unsigned UseIdx) const;
1761
1762	/// Compute the instruction latency of a given instruction.
1763	/// If the instruction has higher cost when predicated, it's returned via
1764	/// PredCost.
1765	virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1766	const MachineInstr &MI,
1767	unsigned *PredCost = nullptr) const;
1768
1769	virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1770
1771	virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1772	SDNode *Node) const;
1773
1774	/// Return the default expected latency for a def based on its opcode.
1775	unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1776	const MachineInstr &DefMI) const;
1777
1778	/// Return true if this opcode has high latency to its result.
1779	virtual bool isHighLatencyDef(int opc) const { return false; }
1780
1781	/// Compute operand latency between a def of 'Reg'
1782	/// and a use in the current loop. Return true if the target considered
1783	/// it 'high'. This is used by optimization passes such as machine LICM to
1784	/// determine whether it makes sense to hoist an instruction out even in a
1785	/// high register pressure situation.
1786	virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1787	const MachineRegisterInfo *MRI,
1788	const MachineInstr &DefMI, unsigned DefIdx,
1789	const MachineInstr &UseMI,
1790	unsigned UseIdx) const {
1791	return false;
1792	}
1793
1794	/// Compute operand latency of a def of 'Reg'. Return true
1795	/// if the target considered it 'low'.
1796	virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1797	const MachineInstr &DefMI,
1798	unsigned DefIdx) const;
1799
1800	/// Perform target-specific instruction verification.
1801	virtual bool verifyInstruction(const MachineInstr &MI,
1802	StringRef &ErrInfo) const {
1803	return true;
1804	}
1805
1806	/// Return the current execution domain and bit mask of
1807	/// possible domains for instruction.
1808	///
1809	/// Some micro-architectures have multiple execution domains, and multiple
1810	/// opcodes that perform the same operation in different domains. For
1811	/// example, the x86 architecture provides the por, orps, and orpd
1812	/// instructions that all do the same thing. There is a latency penalty if a
1813	/// register is written in one domain and read in another.
1814	///
1815	/// This function returns a pair (domain, mask) containing the execution
1816	/// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1817	/// function can be used to change the opcode to one of the domains in the
1818	/// bit mask. Instructions whose execution domain can't be changed should
1819	/// return a 0 mask.
1820	///
1821	/// The execution domain numbers don't have any special meaning except domain
1822	/// 0 is used for instructions that are not associated with any interesting
1823	/// execution domain.
1824	///
1825	virtual std::pair<uint16_t, uint16_t>
1826	getExecutionDomain(const MachineInstr &MI) const {
1827	return std::make_pair(x: 0, y: 0);
1828	}
1829
1830	/// Change the opcode of MI to execute in Domain.
1831	///
1832	/// The bit (1 << Domain) must be set in the mask returned from
1833	/// getExecutionDomain(MI).
1834	virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1835
1836	/// Returns the preferred minimum clearance
1837	/// before an instruction with an unwanted partial register update.
1838	///
1839	/// Some instructions only write part of a register, and implicitly need to
1840	/// read the other parts of the register. This may cause unwanted stalls
1841	/// preventing otherwise unrelated instructions from executing in parallel in
1842	/// an out-of-order CPU.
1843	///
1844	/// For example, the x86 instruction cvtsi2ss writes its result to bits
1845	/// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1846	/// the instruction needs to wait for the old value of the register to become
1847	/// available:
1848	///
1849	/// addps %xmm1, %xmm0
1850	/// movaps %xmm0, (%rax)
1851	/// cvtsi2ss %rbx, %xmm0
1852	///
1853	/// In the code above, the cvtsi2ss instruction needs to wait for the addps
1854	/// instruction before it can issue, even though the high bits of %xmm0
1855	/// probably aren't needed.
1856	///
1857	/// This hook returns the preferred clearance before MI, measured in
1858	/// instructions. Other defs of MI's operand OpNum are avoided in the last N
1859	/// instructions before MI. It should only return a positive value for
1860	/// unwanted dependencies. If the old bits of the defined register have
1861	/// useful values, or if MI is determined to otherwise read the dependency,
1862	/// the hook should return 0.
1863	///
1864	/// The unwanted dependency may be handled by:
1865	///
1866	/// 1. Allocating the same register for an MI def and use. That makes the
1867	/// unwanted dependency identical to a required dependency.
1868	///
1869	/// 2. Allocating a register for the def that has no defs in the previous N
1870	/// instructions.
1871	///
1872	/// 3. Calling breakPartialRegDependency() with the same arguments. This
1873	/// allows the target to insert a dependency breaking instruction.
1874	///
1875	virtual unsigned
1876	getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1877	const TargetRegisterInfo *TRI) const {
1878	// The default implementation returns 0 for no partial register dependency.
1879	return 0;
1880	}
1881
1882	/// Return the minimum clearance before an instruction that reads an
1883	/// unused register.
1884	///
1885	/// For example, AVX instructions may copy part of a register operand into
1886	/// the unused high bits of the destination register.
1887	///
1888	/// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1889	///
1890	/// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1891	/// false dependence on any previous write to %xmm0.
1892	///
1893	/// This hook works similarly to getPartialRegUpdateClearance, except that it
1894	/// does not take an operand index. Instead sets \p OpNum to the index of the
1895	/// unused register.
1896	virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1897	const TargetRegisterInfo *TRI) const {
1898	// The default implementation returns 0 for no undef register dependency.
1899	return 0;
1900	}
1901
1902	/// Insert a dependency-breaking instruction
1903	/// before MI to eliminate an unwanted dependency on OpNum.
1904	///
1905	/// If it wasn't possible to avoid a def in the last N instructions before MI
1906	/// (see getPartialRegUpdateClearance), this hook will be called to break the
1907	/// unwanted dependency.
1908	///
1909	/// On x86, an xorps instruction can be used as a dependency breaker:
1910	///
1911	/// addps %xmm1, %xmm0
1912	/// movaps %xmm0, (%rax)
1913	/// xorps %xmm0, %xmm0
1914	/// cvtsi2ss %rbx, %xmm0
1915	///
1916	/// An <imp-kill> operand should be added to MI if an instruction was
1917	/// inserted. This ties the instructions together in the post-ra scheduler.
1918	///
1919	virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1920	const TargetRegisterInfo *TRI) const {}
1921
1922	/// Create machine specific model for scheduling.
1923	virtual DFAPacketizer *
1924	CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1925	return nullptr;
1926	}
1927
1928	/// Sometimes, it is possible for the target
1929	/// to tell, even without aliasing information, that two MIs access different
1930	/// memory addresses. This function returns true if two MIs access different
1931	/// memory addresses and false otherwise.
1932	///
1933	/// Assumes any physical registers used to compute addresses have the same
1934	/// value for both instructions. (This is the most useful assumption for
1935	/// post-RA scheduling.)
1936	///
1937	/// See also MachineInstr::mayAlias, which is implemented on top of this
1938	/// function.
1939	virtual bool
1940	areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
1941	const MachineInstr &MIb) const {
1942	assert(MIa.mayLoadOrStore() &&
1943	"MIa must load from or modify a memory location");
1944	assert(MIb.mayLoadOrStore() &&
1945	"MIb must load from or modify a memory location");
1946	return false;
1947	}
1948
1949	/// Return the value to use for the MachineCSE's LookAheadLimit,
1950	/// which is a heuristic used for CSE'ing phys reg defs.
1951	virtual unsigned getMachineCSELookAheadLimit() const {
1952	// The default lookahead is small to prevent unprofitable quadratic
1953	// behavior.
1954	return 5;
1955	}
1956
1957	/// Return the maximal number of alias checks on memory operands. For
1958	/// instructions with more than one memory operands, the alias check on a
1959	/// single MachineInstr pair has quadratic overhead and results in
1960	/// unacceptable performance in the worst case. The limit here is to clamp
1961	/// that maximal checks performed. Usually, that's the product of memory
1962	/// operand numbers from that pair of MachineInstr to be checked. For
1963	/// instance, with two MachineInstrs with 4 and 5 memory operands
1964	/// correspondingly, a total of 20 checks are required. With this limit set to
1965	/// 16, their alias check is skipped. We choose to limit the product instead
1966	/// of the individual instruction as targets may have special MachineInstrs
1967	/// with a considerably high number of memory operands, such as `ldm` in ARM.
1968	/// Setting this limit per MachineInstr would result in either too high
1969	/// overhead or too rigid restriction.
1970	virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1971
1972	/// Return an array that contains the ids of the target indices (used for the
1973	/// TargetIndex machine operand) and their names.
1974	///
1975	/// MIR Serialization is able to serialize only the target indices that are
1976	/// defined by this method.
1977	virtual ArrayRef<std::pair<int, const char *>>
1978	getSerializableTargetIndices() const {
1979	return std::nullopt;
1980	}
1981
1982	/// Decompose the machine operand's target flags into two values - the direct
1983	/// target flag value and any of bit flags that are applied.
1984	virtual std::pair<unsigned, unsigned>
1985	decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1986	return std::make_pair(x: 0u, y: 0u);
1987	}
1988
1989	/// Return an array that contains the direct target flag values and their
1990	/// names.
1991	///
1992	/// MIR Serialization is able to serialize only the target flags that are
1993	/// defined by this method.
1994	virtual ArrayRef<std::pair<unsigned, const char *>>
1995	getSerializableDirectMachineOperandTargetFlags() const {
1996	return std::nullopt;
1997	}
1998
1999	/// Return an array that contains the bitmask target flag values and their
2000	/// names.
2001	///
2002	/// MIR Serialization is able to serialize only the target flags that are
2003	/// defined by this method.
2004	virtual ArrayRef<std::pair<unsigned, const char *>>
2005	getSerializableBitmaskMachineOperandTargetFlags() const {
2006	return std::nullopt;
2007	}
2008
2009	/// Return an array that contains the MMO target flag values and their
2010	/// names.
2011	///
2012	/// MIR Serialization is able to serialize only the MMO target flags that are
2013	/// defined by this method.
2014	virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
2015	getSerializableMachineMemOperandTargetFlags() const {
2016	return std::nullopt;
2017	}
2018
2019	/// Determines whether \p Inst is a tail call instruction. Override this
2020	/// method on targets that do not properly set MCID::Return and MCID::Call on
2021	/// tail call instructions."
2022	virtual bool isTailCall(const MachineInstr &Inst) const {
2023	return Inst.isReturn() && Inst.isCall();
2024	}
2025
2026	/// True if the instruction is bound to the top of its basic block and no
2027	/// other instructions shall be inserted before it. This can be implemented
2028	/// to prevent register allocator to insert spills for \p Reg before such
2029	/// instructions.
2030	virtual bool isBasicBlockPrologue(const MachineInstr &MI,
2031	Register Reg = Register()) const {
2032	return false;
2033	}
2034
2035	/// Allows targets to use appropriate copy instruction while spilitting live
2036	/// range of a register in register allocation.
2037	virtual unsigned getLiveRangeSplitOpcode(Register Reg,
2038	const MachineFunction &MF) const {
2039	return TargetOpcode::COPY;
2040	}
2041
2042	/// During PHI eleimination lets target to make necessary checks and
2043	/// insert the copy to the PHI destination register in a target specific
2044	/// manner.
2045	virtual MachineInstr *createPHIDestinationCopy(
2046	MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt,
2047	const DebugLoc &DL, Register Src, Register Dst) const {
2048	return BuildMI(BB&: MBB, I: InsPt, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: Dst)
2049	.addReg(RegNo: Src);
2050	}
2051
2052	/// During PHI eleimination lets target to make necessary checks and
2053	/// insert the copy to the PHI destination register in a target specific
2054	/// manner.
2055	virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB,
2056	MachineBasicBlock::iterator InsPt,
2057	const DebugLoc &DL, Register Src,
2058	unsigned SrcSubReg,
2059	Register Dst) const {
2060	return BuildMI(BB&: MBB, I: InsPt, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: Dst)
2061	.addReg(RegNo: Src, flags: 0, SubReg: SrcSubReg);
2062	}
2063
2064	/// Returns a \p outliner::OutlinedFunction struct containing target-specific
2065	/// information for a set of outlining candidates. Returns std::nullopt if the
2066	/// candidates are not suitable for outlining.
2067	virtual std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
2068	std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
2069	llvm_unreachable(
2070	"Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
2071	}
2072
2073	/// Optional target hook to create the LLVM IR attributes for the outlined
2074	/// function. If overridden, the overriding function must call the default
2075	/// implementation.
2076	virtual void mergeOutliningCandidateAttributes(
2077	Function &F, std::vector<outliner::Candidate> &Candidates) const;
2078
2079	protected:
2080	/// Target-dependent implementation for getOutliningTypeImpl.
2081	virtual outliner::InstrType
2082	getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
2083	llvm_unreachable(
2084	"Target didn't implement TargetInstrInfo::getOutliningTypeImpl!");
2085	}
2086
2087	public:
2088	/// Returns how or if \p MIT should be outlined. \p Flags is the
2089	/// target-specific information returned by isMBBSafeToOutlineFrom.
2090	outliner::InstrType
2091	getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const;
2092
2093	/// Optional target hook that returns true if \p MBB is safe to outline from,
2094	/// and returns any target-specific information in \p Flags.
2095	virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
2096	unsigned &Flags) const;
2097
2098	/// Optional target hook which partitions \p MBB into outlinable ranges for
2099	/// instruction mapping purposes. Each range is defined by two iterators:
2100	/// [start, end).
2101	///
2102	/// Ranges are expected to be ordered top-down. That is, ranges closer to the
2103	/// top of the block should come before ranges closer to the end of the block.
2104	///
2105	/// Ranges cannot overlap.
2106	///
2107	/// If an entire block is mappable, then its range is [MBB.begin(), MBB.end())
2108	///
2109	/// All instructions not present in an outlinable range are considered
2110	/// illegal.
2111	virtual SmallVector<
2112	std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
2113	getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const {
2114	return {std::make_pair(x: MBB.begin(), y: MBB.end())};
2115	}
2116
2117	/// Insert a custom frame for outlined functions.
2118	virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
2119	const outliner::OutlinedFunction &OF) const {
2120	llvm_unreachable(
2121	"Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
2122	}
2123
2124	/// Insert a call to an outlined function into the program.
2125	/// Returns an iterator to the spot where we inserted the call. This must be
2126	/// implemented by the target.
2127	virtual MachineBasicBlock::iterator
2128	insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
2129	MachineBasicBlock::iterator &It, MachineFunction &MF,
2130	outliner::Candidate &C) const {
2131	llvm_unreachable(
2132	"Target didn't implement TargetInstrInfo::insertOutlinedCall!");
2133	}
2134
2135	/// Insert an architecture-specific instruction to clear a register. If you
2136	/// need to avoid sideeffects (e.g. avoid XOR on x86, which sets EFLAGS), set
2137	/// \p AllowSideEffects to \p false.
2138	virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
2139	MachineBasicBlock::iterator Iter,
2140	DebugLoc &DL,
2141	bool AllowSideEffects = true) const {
2142	#if 0
2143	// FIXME: This should exist once all platforms that use stack protectors
2144	// implements it.
2145	llvm_unreachable(
2146	"Target didn't implement TargetInstrInfo::buildClearRegister!");
2147	#endif
2148	}
2149
2150	/// Return true if the function can safely be outlined from.
2151	/// A function \p MF is considered safe for outlining if an outlined function
2152	/// produced from instructions in F will produce a program which produces the
2153	/// same output for any set of given inputs.
2154	virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
2155	bool OutlineFromLinkOnceODRs) const {
2156	llvm_unreachable("Target didn't implement "
2157	"TargetInstrInfo::isFunctionSafeToOutlineFrom!");
2158	}
2159
2160	/// Return true if the function should be outlined from by default.
2161	virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const {
2162	return false;
2163	}
2164
2165	/// Return true if the function is a viable candidate for machine function
2166	/// splitting. The criteria for if a function can be split may vary by target.
2167	virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const;
2168
2169	/// Return true if the MachineBasicBlock can safely be split to the cold
2170	/// section. On AArch64, certain instructions may cause a block to be unsafe
2171	/// to split to the cold section.
2172	virtual bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const {
2173	return true;
2174	}
2175
2176	/// Produce the expression describing the \p MI loading a value into
2177	/// the physical register \p Reg. This hook should only be used with
2178	/// \p MIs belonging to VReg-less functions.
2179	virtual std::optional<ParamLoadedValue>
2180	describeLoadedValue(const MachineInstr &MI, Register Reg) const;
2181
2182	/// Given the generic extension instruction \p ExtMI, returns true if this
2183	/// extension is a likely candidate for being folded into an another
2184	/// instruction.
2185	virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI,
2186	MachineRegisterInfo &MRI) const {
2187	return false;
2188	}
2189
2190	/// Return MIR formatter to format/parse MIR operands. Target can override
2191	/// this virtual function and return target specific MIR formatter.
2192	virtual const MIRFormatter *getMIRFormatter() const {
2193	if (!Formatter.get())
2194	Formatter = std::make_unique<MIRFormatter>();
2195	return Formatter.get();
2196	}
2197
2198	/// Returns the target-specific default value for tail duplication.
2199	/// This value will be used if the tail-dup-placement-threshold argument is
2200	/// not provided.
2201	virtual unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
2202	return OptLevel >= CodeGenOptLevel::Aggressive ? 4 : 2;
2203	}
2204
2205	/// Returns the callee operand from the given \p MI.
2206	virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
2207	return MI.getOperand(i: 0);
2208	}
2209
2210	/// Return the uniformity behavior of the given instruction.
2211	virtual InstructionUniformity
2212	getInstructionUniformity(const MachineInstr &MI) const {
2213	return InstructionUniformity::Default;
2214	}
2215
2216	/// Returns true if the given \p MI defines a TargetIndex operand that can be
2217	/// tracked by their offset, can have values, and can have debug info
2218	/// associated with it. If so, sets \p Index and \p Offset of the target index
2219	/// operand.
2220	virtual bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index,
2221	int64_t &Offset) const {
2222	return false;
2223	}
2224
2225	// Get the call frame size just before MI.
2226	unsigned getCallFrameSizeAt(MachineInstr &MI) const;
2227
2228	/// Fills in the necessary MachineOperands to refer to a frame index.
2229	/// The best way to understand this is to print `asm(""::"m"(x));` after
2230	/// finalize-isel. Example:
2231	/// INLINEASM ... 262190 /* mem:m */, %stack.0.x.addr, 1, $noreg, 0, $noreg
2232	/// we would add placeholders for: ^ ^ ^ ^
2233	virtual void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
2234	int FI) const {
2235	llvm_unreachable("unknown number of operands necessary");
2236	}
2237
2238	/// Gets the opcode for the Pseudo Instruction used to initialize
2239	/// the undef value. If no Instruction is available, this will
2240	/// fail compilation.
2241	virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
2242	(void)RegClassID;
2243
2244	llvm_unreachable("Unexpected register class.");
2245	}
2246
2247	private:
2248	mutable std::unique_ptr<MIRFormatter> Formatter;
2249	unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2250	unsigned CatchRetOpcode;
2251	unsigned ReturnOpcode;
2252	};
2253
2254	/// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2255	template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
2256	using RegInfo = DenseMapInfo<unsigned>;
2257
2258	static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
2259	return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2260	RegInfo::getEmptyKey());
2261	}
2262
2263	static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
2264	return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2265	RegInfo::getTombstoneKey());
2266	}
2267
2268	/// Reuse getHashValue implementation from
2269	/// std::pair<unsigned, unsigned>.
2270	static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2271	std::pair<unsigned, unsigned> PairVal = std::make_pair(x: Val.Reg, y: Val.SubReg);
2272	return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2273	}
2274
2275	static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
2276	const TargetInstrInfo::RegSubRegPair &RHS) {
2277	return RegInfo::isEqual(LHS: LHS.Reg, RHS: RHS.Reg) &&
2278	RegInfo::isEqual(LHS: LHS.SubReg, RHS: RHS.SubReg);
2279	}
2280	};
2281
2282	} // end namespace llvm
2283
2284	#endif // LLVM_CODEGEN_TARGETINSTRINFO_H
2285