1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created. It allows use of code like this:
11//
12// MIMetadata MIMD(MI); // Propagates DebugLoc and other metadata
13// M = BuildMI(MBB, MI, MIMD, TII.get(X86::ADD8rr), Dst)
14// .addReg(argVal1)
15// .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35
36namespace llvm {
37
38class MCInstrDesc;
39class MDNode;
40
41namespace RegState {
42
43enum {
44 /// Register definition.
45 Define = 0x2,
46 /// Not emitted register (e.g. carry, or temporary result).
47 Implicit = 0x4,
48 /// The last use of a register.
49 Kill = 0x8,
50 /// Unused definition.
51 Dead = 0x10,
52 /// Value of the register doesn't matter.
53 Undef = 0x20,
54 /// Register definition happens before uses.
55 EarlyClobber = 0x40,
56 /// Register 'use' is for debugging purpose.
57 Debug = 0x80,
58 /// Register reads a value that is defined inside the same instruction or
59 /// bundle.
60 InternalRead = 0x100,
61 /// Register that may be renamed.
62 Renamable = 0x200,
63 DefineNoRead = Define | Undef,
64 ImplicitDefine = Implicit | Define,
65 ImplicitKill = Implicit | Kill
66};
67
68} // end namespace RegState
69
70class MachineInstrBuilder {
71 MachineFunction *MF = nullptr;
72 MachineInstr *MI = nullptr;
73
74public:
75 MachineInstrBuilder() = default;
76
77 /// Create a MachineInstrBuilder for manipulating an existing instruction.
78 /// F must be the machine function that was used to allocate I.
79 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
80 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
81 : MF(&F), MI(&*I) {}
82
83 /// Allow automatic conversion to the machine instruction we are working on.
84 operator MachineInstr*() const { return MI; }
85 MachineInstr *operator->() const { return MI; }
86 operator MachineBasicBlock::iterator() const { return MI; }
87
88 /// If conversion operators fail, use this method to get the MachineInstr
89 /// explicitly.
90 MachineInstr *getInstr() const { return MI; }
91
92 /// Get the register for the operand index.
93 /// The operand at the index should be a register (asserted by
94 /// MachineOperand).
95 Register getReg(unsigned Idx) const { return MI->getOperand(i: Idx).getReg(); }
96
97 /// Add a new virtual register operand.
98 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
99 unsigned SubReg = 0) const {
100 assert((flags & 0x1) == 0 &&
101 "Passing in 'true' to addReg is forbidden! Use enums instead.");
102 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateReg(Reg: RegNo,
103 isDef: flags & RegState::Define,
104 isImp: flags & RegState::Implicit,
105 isKill: flags & RegState::Kill,
106 isDead: flags & RegState::Dead,
107 isUndef: flags & RegState::Undef,
108 isEarlyClobber: flags & RegState::EarlyClobber,
109 SubReg,
110 isDebug: flags & RegState::Debug,
111 isInternalRead: flags & RegState::InternalRead,
112 isRenamable: flags & RegState::Renamable));
113 return *this;
114 }
115
116 /// Add a virtual register definition operand.
117 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
118 unsigned SubReg = 0) const {
119 return addReg(RegNo, flags: Flags | RegState::Define, SubReg);
120 }
121
122 /// Add a virtual register use operand. It is an error for Flags to contain
123 /// `RegState::Define` when calling this function.
124 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
125 unsigned SubReg = 0) const {
126 assert(!(Flags & RegState::Define) &&
127 "Misleading addUse defines register, use addReg instead.");
128 return addReg(RegNo, flags: Flags, SubReg);
129 }
130
131 /// Add a new immediate operand.
132 const MachineInstrBuilder &addImm(int64_t Val) const {
133 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateImm(Val));
134 return *this;
135 }
136
137 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
138 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCImm(CI: Val));
139 return *this;
140 }
141
142 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
143 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFPImm(CFP: Val));
144 return *this;
145 }
146
147 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
148 unsigned TargetFlags = 0) const {
149 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMBB(MBB, TargetFlags));
150 return *this;
151 }
152
153 const MachineInstrBuilder &addFrameIndex(int Idx) const {
154 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateFI(Idx));
155 return *this;
156 }
157
158 const MachineInstrBuilder &
159 addConstantPoolIndex(unsigned Idx, int Offset = 0,
160 unsigned TargetFlags = 0) const {
161 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
162 return *this;
163 }
164
165 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
166 unsigned TargetFlags = 0) const {
167 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateTargetIndex(Idx, Offset,
168 TargetFlags));
169 return *this;
170 }
171
172 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
173 unsigned TargetFlags = 0) const {
174 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateJTI(Idx, TargetFlags));
175 return *this;
176 }
177
178 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
179 int64_t Offset = 0,
180 unsigned TargetFlags = 0) const {
181 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateGA(GV, Offset, TargetFlags));
182 return *this;
183 }
184
185 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
186 unsigned TargetFlags = 0) const {
187 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateES(SymName: FnName, TargetFlags));
188 return *this;
189 }
190
191 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
192 int64_t Offset = 0,
193 unsigned TargetFlags = 0) const {
194 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateBA(BA, Offset, TargetFlags));
195 return *this;
196 }
197
198 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
199 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateRegMask(Mask));
200 return *this;
201 }
202
203 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
204 MI->addMemOperand(MF&: *MF, MO: MMO);
205 return *this;
206 }
207
208 const MachineInstrBuilder &
209 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
210 MI->setMemRefs(MF&: *MF, MemRefs: MMOs);
211 return *this;
212 }
213
214 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
215 MI->cloneMemRefs(MF&: *MF, MI: OtherMI);
216 return *this;
217 }
218
219 const MachineInstrBuilder &
220 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
221 MI->cloneMergedMemRefs(MF&: *MF, MIs: OtherMIs);
222 return *this;
223 }
224
225 const MachineInstrBuilder &add(const MachineOperand &MO) const {
226 MI->addOperand(MF&: *MF, Op: MO);
227 return *this;
228 }
229
230 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
231 for (const MachineOperand &MO : MOs) {
232 MI->addOperand(MF&: *MF, Op: MO);
233 }
234 return *this;
235 }
236
237 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
238 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMetadata(Meta: MD));
239 assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
240 : true) &&
241 "first MDNode argument of a DBG_VALUE not a variable");
242 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
243 : true) &&
244 "first MDNode argument of a DBG_LABEL not a label");
245 return *this;
246 }
247
248 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
249 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateCFIIndex(CFIIndex));
250 return *this;
251 }
252
253 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
254 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateIntrinsicID(ID));
255 return *this;
256 }
257
258 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
259 MI->addOperand(MF&: *MF, Op: MachineOperand::CreatePredicate(Pred));
260 return *this;
261 }
262
263 const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const {
264 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateShuffleMask(Mask: Val));
265 return *this;
266 }
267
268 const MachineInstrBuilder &addSym(MCSymbol *Sym,
269 unsigned char TargetFlags = 0) const {
270 MI->addOperand(MF&: *MF, Op: MachineOperand::CreateMCSymbol(Sym, TargetFlags));
271 return *this;
272 }
273
274 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
275 MI->setFlags(Flags);
276 return *this;
277 }
278
279 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
280 MI->setFlag(Flag);
281 return *this;
282 }
283
284 const MachineInstrBuilder &setOperandDead(unsigned OpIdx) const {
285 MI->getOperand(i: OpIdx).setIsDead();
286 return *this;
287 }
288
289 // Add a displacement from an existing MachineOperand with an added offset.
290 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
291 unsigned char TargetFlags = 0) const {
292 // If caller specifies new TargetFlags then use it, otherwise the
293 // default behavior is to copy the target flags from the existing
294 // MachineOperand. This means if the caller wants to clear the
295 // target flags it needs to do so explicitly.
296 if (0 == TargetFlags)
297 TargetFlags = Disp.getTargetFlags();
298
299 switch (Disp.getType()) {
300 default:
301 llvm_unreachable("Unhandled operand type in addDisp()");
302 case MachineOperand::MO_Immediate:
303 return addImm(Val: Disp.getImm() + off);
304 case MachineOperand::MO_ConstantPoolIndex:
305 return addConstantPoolIndex(Idx: Disp.getIndex(), Offset: Disp.getOffset() + off,
306 TargetFlags);
307 case MachineOperand::MO_GlobalAddress:
308 return addGlobalAddress(GV: Disp.getGlobal(), Offset: Disp.getOffset() + off,
309 TargetFlags);
310 case MachineOperand::MO_BlockAddress:
311 return addBlockAddress(BA: Disp.getBlockAddress(), Offset: Disp.getOffset() + off,
312 TargetFlags);
313 case MachineOperand::MO_JumpTableIndex:
314 assert(off == 0 && "cannot create offset into jump tables");
315 return addJumpTableIndex(Idx: Disp.getIndex(), TargetFlags);
316 }
317 }
318
319 const MachineInstrBuilder &setPCSections(MDNode *MD) const {
320 if (MD)
321 MI->setPCSections(MF&: *MF, MD);
322 return *this;
323 }
324
325 const MachineInstrBuilder &setMMRAMetadata(MDNode *MMRA) const {
326 if (MMRA)
327 MI->setMMRAMetadata(MF&: *MF, MMRAs: MMRA);
328 return *this;
329 }
330
331 /// Copy all the implicit operands from OtherMI onto this one.
332 const MachineInstrBuilder &
333 copyImplicitOps(const MachineInstr &OtherMI) const {
334 MI->copyImplicitOps(MF&: *MF, MI: OtherMI);
335 return *this;
336 }
337
338 bool constrainAllUses(const TargetInstrInfo &TII,
339 const TargetRegisterInfo &TRI,
340 const RegisterBankInfo &RBI) const {
341 return constrainSelectedInstRegOperands(I&: *MI, TII, TRI, RBI);
342 }
343};
344
345/// Set of metadata that should be preserved when using BuildMI(). This provides
346/// a more convenient way of preserving DebugLoc, PCSections and MMRA.
347class MIMetadata {
348public:
349 MIMetadata() = default;
350 MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr, MDNode *MMRA = nullptr)
351 : DL(std::move(DL)), PCSections(PCSections), MMRA(MMRA) {}
352 MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr,
353 MDNode *MMRA = nullptr)
354 : DL(DI), PCSections(PCSections), MMRA(MMRA) {}
355 explicit MIMetadata(const Instruction &From)
356 : DL(From.getDebugLoc()),
357 PCSections(From.getMetadata(KindID: LLVMContext::MD_pcsections)) {}
358 explicit MIMetadata(const MachineInstr &From)
359 : DL(From.getDebugLoc()), PCSections(From.getPCSections()) {}
360
361 const DebugLoc &getDL() const { return DL; }
362 MDNode *getPCSections() const { return PCSections; }
363 MDNode *getMMRAMetadata() const { return MMRA; }
364
365private:
366 DebugLoc DL;
367 MDNode *PCSections = nullptr;
368 MDNode *MMRA = nullptr;
369};
370
371/// Builder interface. Specify how to create the initial instruction itself.
372inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
373 const MCInstrDesc &MCID) {
374 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
375 .setPCSections(MIMD.getPCSections())
376 .setMMRAMetadata(MIMD.getMMRAMetadata());
377}
378
379/// This version of the builder sets up the first operand as a
380/// destination virtual register.
381inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD,
382 const MCInstrDesc &MCID, Register DestReg) {
383 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL: MIMD.getDL()))
384 .setPCSections(MIMD.getPCSections())
385 .setMMRAMetadata(MIMD.getMMRAMetadata())
386 .addReg(RegNo: DestReg, flags: RegState::Define);
387}
388
389/// This version of the builder inserts the newly-built instruction before
390/// the given position in the given MachineBasicBlock, and sets up the first
391/// operand as a destination virtual register.
392inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
393 MachineBasicBlock::iterator I,
394 const MIMetadata &MIMD,
395 const MCInstrDesc &MCID, Register DestReg) {
396 MachineFunction &MF = *BB.getParent();
397 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
398 BB.insert(I, MI);
399 return MachineInstrBuilder(MF, MI)
400 .setPCSections(MIMD.getPCSections())
401 .setMMRAMetadata(MIMD.getMMRAMetadata())
402 .addReg(RegNo: DestReg, flags: RegState::Define);
403}
404
405/// This version of the builder inserts the newly-built instruction before
406/// the given position in the given MachineBasicBlock, and sets up the first
407/// operand as a destination virtual register.
408///
409/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
410/// added to the same bundle.
411inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
412 MachineBasicBlock::instr_iterator I,
413 const MIMetadata &MIMD,
414 const MCInstrDesc &MCID, Register DestReg) {
415 MachineFunction &MF = *BB.getParent();
416 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
417 BB.insert(I, M: MI);
418 return MachineInstrBuilder(MF, MI)
419 .setPCSections(MIMD.getPCSections())
420 .setMMRAMetadata(MIMD.getMMRAMetadata())
421 .addReg(RegNo: DestReg, flags: RegState::Define);
422}
423
424inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
425 const MIMetadata &MIMD,
426 const MCInstrDesc &MCID, Register DestReg) {
427 // Calling the overload for instr_iterator is always correct. However, the
428 // definition is not available in headers, so inline the check.
429 if (I.isInsideBundle())
430 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID,
431 DestReg);
432 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID, DestReg);
433}
434
435inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
436 const MIMetadata &MIMD,
437 const MCInstrDesc &MCID, Register DestReg) {
438 return BuildMI(BB, I&: *I, MIMD, MCID, DestReg);
439}
440
441/// This version of the builder inserts the newly-built instruction before the
442/// given position in the given MachineBasicBlock, and does NOT take a
443/// destination register.
444inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
445 MachineBasicBlock::iterator I,
446 const MIMetadata &MIMD,
447 const MCInstrDesc &MCID) {
448 MachineFunction &MF = *BB.getParent();
449 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
450 BB.insert(I, MI);
451 return MachineInstrBuilder(MF, MI)
452 .setPCSections(MIMD.getPCSections())
453 .setMMRAMetadata(MIMD.getMMRAMetadata());
454}
455
456inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
457 MachineBasicBlock::instr_iterator I,
458 const MIMetadata &MIMD,
459 const MCInstrDesc &MCID) {
460 MachineFunction &MF = *BB.getParent();
461 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL: MIMD.getDL());
462 BB.insert(I, M: MI);
463 return MachineInstrBuilder(MF, MI)
464 .setPCSections(MIMD.getPCSections())
465 .setMMRAMetadata(MIMD.getMMRAMetadata());
466}
467
468inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
469 const MIMetadata &MIMD,
470 const MCInstrDesc &MCID) {
471 // Calling the overload for instr_iterator is always correct. However, the
472 // definition is not available in headers, so inline the check.
473 if (I.isInsideBundle())
474 return BuildMI(BB, I: MachineBasicBlock::instr_iterator(I), MIMD, MCID);
475 return BuildMI(BB, I: MachineBasicBlock::iterator(I), MIMD, MCID);
476}
477
478inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
479 const MIMetadata &MIMD,
480 const MCInstrDesc &MCID) {
481 return BuildMI(BB, I&: *I, MIMD, MCID);
482}
483
484/// This version of the builder inserts the newly-built instruction at the end
485/// of the given MachineBasicBlock, and does NOT take a destination register.
486inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
487 const MIMetadata &MIMD,
488 const MCInstrDesc &MCID) {
489 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID);
490}
491
492/// This version of the builder inserts the newly-built instruction at the
493/// end of the given MachineBasicBlock, and sets up the first operand as a
494/// destination virtual register.
495inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
496 const MIMetadata &MIMD,
497 const MCInstrDesc &MCID, Register DestReg) {
498 return BuildMI(BB&: *BB, I: BB->end(), MIMD, MCID, DestReg);
499}
500
501/// This version of the builder builds a DBG_VALUE intrinsic
502/// for either a value in a register or a register-indirect
503/// address. The convention is that a DBG_VALUE is indirect iff the
504/// second operand is an immediate.
505MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
506 const MCInstrDesc &MCID, bool IsIndirect,
507 Register Reg, const MDNode *Variable,
508 const MDNode *Expr);
509
510/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
511/// for a MachineOperand.
512MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
513 const MCInstrDesc &MCID, bool IsIndirect,
514 ArrayRef<MachineOperand> MOs,
515 const MDNode *Variable, const MDNode *Expr);
516
517/// This version of the builder builds a DBG_VALUE intrinsic
518/// for either a value in a register or a register-indirect
519/// address and inserts it at position I.
520MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
521 MachineBasicBlock::iterator I, const DebugLoc &DL,
522 const MCInstrDesc &MCID, bool IsIndirect,
523 Register Reg, const MDNode *Variable,
524 const MDNode *Expr);
525
526/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
527/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
528MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
529 MachineBasicBlock::iterator I, const DebugLoc &DL,
530 const MCInstrDesc &MCID, bool IsIndirect,
531 ArrayRef<MachineOperand> MOs,
532 const MDNode *Variable, const MDNode *Expr);
533
534/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
535MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
536 MachineBasicBlock::iterator I,
537 const MachineInstr &Orig, int FrameIndex,
538 Register SpillReg);
539MachineInstr *
540buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I,
541 const MachineInstr &Orig, int FrameIndex,
542 SmallVectorImpl<const MachineOperand *> &SpilledOperands);
543
544/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
545/// modifying an instruction in place while iterating over a basic block.
546void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);
547
548inline unsigned getDefRegState(bool B) {
549 return B ? RegState::Define : 0;
550}
551inline unsigned getImplRegState(bool B) {
552 return B ? RegState::Implicit : 0;
553}
554inline unsigned getKillRegState(bool B) {
555 return B ? RegState::Kill : 0;
556}
557inline unsigned getDeadRegState(bool B) {
558 return B ? RegState::Dead : 0;
559}
560inline unsigned getUndefRegState(bool B) {
561 return B ? RegState::Undef : 0;
562}
563inline unsigned getInternalReadRegState(bool B) {
564 return B ? RegState::InternalRead : 0;
565}
566inline unsigned getDebugRegState(bool B) {
567 return B ? RegState::Debug : 0;
568}
569inline unsigned getRenamableRegState(bool B) {
570 return B ? RegState::Renamable : 0;
571}
572
573/// Get all register state flags from machine operand \p RegOp.
574inline unsigned getRegState(const MachineOperand &RegOp) {
575 assert(RegOp.isReg() && "Not a register operand");
576 return getDefRegState(B: RegOp.isDef()) | getImplRegState(B: RegOp.isImplicit()) |
577 getKillRegState(B: RegOp.isKill()) | getDeadRegState(B: RegOp.isDead()) |
578 getUndefRegState(B: RegOp.isUndef()) |
579 getInternalReadRegState(B: RegOp.isInternalRead()) |
580 getDebugRegState(B: RegOp.isDebug()) |
581 getRenamableRegState(B: RegOp.getReg().isPhysical() &&
582 RegOp.isRenamable());
583}
584
585/// Helper class for constructing bundles of MachineInstrs.
586///
587/// MIBundleBuilder can create a bundle from scratch by inserting new
588/// MachineInstrs one at a time, or it can create a bundle from a sequence of
589/// existing MachineInstrs in a basic block.
590class MIBundleBuilder {
591 MachineBasicBlock &MBB;
592 MachineBasicBlock::instr_iterator Begin;
593 MachineBasicBlock::instr_iterator End;
594
595public:
596 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
597 /// BB above the bundle or instruction at Pos.
598 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
599 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
600
601 /// Create a bundle from the sequence of instructions between B and E.
602 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
603 MachineBasicBlock::iterator E)
604 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
605 assert(B != E && "No instructions to bundle");
606 ++B;
607 while (B != E) {
608 MachineInstr &MI = *B;
609 ++B;
610 MI.bundleWithPred();
611 }
612 }
613
614 /// Create an MIBundleBuilder representing an existing instruction or bundle
615 /// that has MI as its head.
616 explicit MIBundleBuilder(MachineInstr *MI)
617 : MBB(*MI->getParent()), Begin(MI),
618 End(getBundleEnd(I: MI->getIterator())) {}
619
620 /// Return a reference to the basic block containing this bundle.
621 MachineBasicBlock &getMBB() const { return MBB; }
622
623 /// Return true if no instructions have been inserted in this bundle yet.
624 /// Empty bundles aren't representable in a MachineBasicBlock.
625 bool empty() const { return Begin == End; }
626
627 /// Return an iterator to the first bundled instruction.
628 MachineBasicBlock::instr_iterator begin() const { return Begin; }
629
630 /// Return an iterator beyond the last bundled instruction.
631 MachineBasicBlock::instr_iterator end() const { return End; }
632
633 /// Insert MI into this bundle before I which must point to an instruction in
634 /// the bundle, or end().
635 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
636 MachineInstr *MI) {
637 MBB.insert(I, M: MI);
638 if (I == Begin) {
639 if (!empty())
640 MI->bundleWithSucc();
641 Begin = MI->getIterator();
642 return *this;
643 }
644 if (I == End) {
645 MI->bundleWithPred();
646 return *this;
647 }
648 // MI was inserted in the middle of the bundle, so its neighbors' flags are
649 // already fine. Update MI's bundle flags manually.
650 MI->setFlag(MachineInstr::BundledPred);
651 MI->setFlag(MachineInstr::BundledSucc);
652 return *this;
653 }
654
655 /// Insert MI into MBB by prepending it to the instructions in the bundle.
656 /// MI will become the first instruction in the bundle.
657 MIBundleBuilder &prepend(MachineInstr *MI) {
658 return insert(I: begin(), MI);
659 }
660
661 /// Insert MI into MBB by appending it to the instructions in the bundle.
662 /// MI will become the last instruction in the bundle.
663 MIBundleBuilder &append(MachineInstr *MI) {
664 return insert(I: end(), MI);
665 }
666};
667
668} // end namespace llvm
669
670#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H
671

source code of llvm/include/llvm/CodeGen/MachineInstrBuilder.h