1 | /* IA-32 common hooks. |
2 | Copyright (C) 1988-2024 Free Software Foundation, Inc. |
3 | |
4 | This file is part of GCC. |
5 | |
6 | GCC is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. |
10 | |
11 | GCC is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | GNU General Public License for more details. |
15 | |
16 | You should have received a copy of the GNU General Public License |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ |
19 | |
20 | #include "config.h" |
21 | #include "system.h" |
22 | #include "coretypes.h" |
23 | #include "diagnostic-core.h" |
24 | #include "tm.h" |
25 | #include "memmodel.h" |
26 | #include "tm_p.h" |
27 | #include "common/common-target.h" |
28 | #include "common/common-target-def.h" |
29 | #include "opts.h" |
30 | #include "flags.h" |
31 | |
32 | /* Define a set of ISAs which are available when a given ISA is |
33 | enabled. MMX and SSE ISAs are handled separately. */ |
34 | |
35 | #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX |
36 | #define OPTION_MASK_ISA_3DNOW_SET \ |
37 | (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET) |
38 | #define OPTION_MASK_ISA_3DNOW_A_SET \ |
39 | (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET) |
40 | |
41 | #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE |
42 | #define OPTION_MASK_ISA_SSE2_SET \ |
43 | (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET) |
44 | #define OPTION_MASK_ISA_SSE3_SET \ |
45 | (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET) |
46 | #define OPTION_MASK_ISA_SSSE3_SET \ |
47 | (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET) |
48 | #define OPTION_MASK_ISA_SSE4_1_SET \ |
49 | (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET) |
50 | #define OPTION_MASK_ISA_SSE4_2_SET \ |
51 | (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET) |
52 | #define OPTION_MASK_ISA_AVX_SET \ |
53 | (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \ |
54 | | OPTION_MASK_ISA_XSAVE_SET) |
55 | #define OPTION_MASK_ISA_FMA_SET \ |
56 | (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET) |
57 | #define OPTION_MASK_ISA_AVX2_SET \ |
58 | (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET) |
59 | #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR |
60 | #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE |
61 | #define OPTION_MASK_ISA_XSAVEOPT_SET \ |
62 | (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET) |
63 | #define OPTION_MASK_ISA_AVX512F_SET \ |
64 | (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET) |
65 | #define OPTION_MASK_ISA_AVX512CD_SET \ |
66 | (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET) |
67 | #define OPTION_MASK_ISA_AVX512PF_SET \ |
68 | (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET) |
69 | #define OPTION_MASK_ISA_AVX512ER_SET \ |
70 | (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET) |
71 | #define OPTION_MASK_ISA_AVX512DQ_SET \ |
72 | (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET) |
73 | #define OPTION_MASK_ISA_AVX512BW_SET \ |
74 | (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET) |
75 | #define OPTION_MASK_ISA_AVX512VL_SET \ |
76 | (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET) |
77 | #define OPTION_MASK_ISA_AVX512IFMA_SET \ |
78 | (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET) |
79 | #define OPTION_MASK_ISA2_AVXIFMA_SET OPTION_MASK_ISA2_AVXIFMA |
80 | #define OPTION_MASK_ISA_AVX512VBMI_SET \ |
81 | (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET) |
82 | #define OPTION_MASK_ISA2_AVX5124FMAPS_SET OPTION_MASK_ISA2_AVX5124FMAPS |
83 | #define OPTION_MASK_ISA2_AVX5124VNNIW_SET OPTION_MASK_ISA2_AVX5124VNNIW |
84 | #define OPTION_MASK_ISA_AVX512VBMI2_SET \ |
85 | (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512BW_SET) |
86 | #define OPTION_MASK_ISA_AVX512FP16_SET OPTION_MASK_ISA_AVX512BW_SET |
87 | #define OPTION_MASK_ISA2_AVX512FP16_SET OPTION_MASK_ISA2_AVX512FP16 |
88 | #define OPTION_MASK_ISA_AVX512VNNI_SET \ |
89 | (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET) |
90 | #define OPTION_MASK_ISA2_AVXVNNI_SET OPTION_MASK_ISA2_AVXVNNI |
91 | #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \ |
92 | (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET) |
93 | #define OPTION_MASK_ISA_AVX512BITALG_SET \ |
94 | (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512BW_SET) |
95 | #define OPTION_MASK_ISA2_AVX512BF16_SET OPTION_MASK_ISA2_AVX512BF16 |
96 | #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM |
97 | #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW |
98 | #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED |
99 | #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX |
100 | #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1 |
101 | #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT |
102 | #define OPTION_MASK_ISA_XSAVES_SET \ |
103 | (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET) |
104 | #define OPTION_MASK_ISA_XSAVEC_SET \ |
105 | (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET) |
106 | #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB |
107 | #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET OPTION_MASK_ISA2_AVX512VP2INTERSECT |
108 | #define OPTION_MASK_ISA2_AMX_TILE_SET OPTION_MASK_ISA2_AMX_TILE |
109 | #define OPTION_MASK_ISA2_AMX_INT8_SET \ |
110 | (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_INT8) |
111 | #define OPTION_MASK_ISA2_AMX_BF16_SET \ |
112 | (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_BF16) |
113 | #define OPTION_MASK_ISA2_AVXVNNIINT8_SET OPTION_MASK_ISA2_AVXVNNIINT8 |
114 | #define OPTION_MASK_ISA2_AVXNECONVERT_SET OPTION_MASK_ISA2_AVXNECONVERT |
115 | #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD |
116 | #define OPTION_MASK_ISA2_AMX_FP16_SET \ |
117 | (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_FP16) |
118 | #define OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI |
119 | #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT |
120 | #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \ |
121 | (OPTION_MASK_ISA2_AMX_TILE_SET | OPTION_MASK_ISA2_AMX_COMPLEX) |
122 | #define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16 |
123 | #define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3 |
124 | #define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512 |
125 | #define OPTION_MASK_ISA2_SM4_SET OPTION_MASK_ISA2_SM4 |
126 | #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F |
127 | #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512 |
128 | #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR |
129 | #define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256 |
130 | #define OPTION_MASK_ISA2_AVX10_1_512_SET \ |
131 | (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512) |
132 | |
133 | /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same |
134 | as -msse4.2. */ |
135 | #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET |
136 | |
137 | #define OPTION_MASK_ISA_SSE4A_SET \ |
138 | (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET) |
139 | #define OPTION_MASK_ISA_FMA4_SET \ |
140 | (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \ |
141 | | OPTION_MASK_ISA_AVX_SET) |
142 | #define OPTION_MASK_ISA_XOP_SET \ |
143 | (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET) |
144 | #define OPTION_MASK_ISA_LWP_SET \ |
145 | OPTION_MASK_ISA_LWP |
146 | |
147 | /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */ |
148 | #define OPTION_MASK_ISA_AES_SET \ |
149 | (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET) |
150 | #define OPTION_MASK_ISA_SHA_SET \ |
151 | (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET) |
152 | #define OPTION_MASK_ISA_PCLMUL_SET \ |
153 | (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET) |
154 | |
155 | #define OPTION_MASK_ISA_ABM_SET \ |
156 | (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT_SET) |
157 | |
158 | #define OPTION_MASK_ISA2_PCONFIG_SET OPTION_MASK_ISA2_PCONFIG |
159 | #define OPTION_MASK_ISA2_WBNOINVD_SET OPTION_MASK_ISA2_WBNOINVD |
160 | #define OPTION_MASK_ISA2_SGX_SET OPTION_MASK_ISA2_SGX |
161 | #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI |
162 | #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2 |
163 | #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT |
164 | #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM |
165 | #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT |
166 | #define OPTION_MASK_ISA2_CX16_SET OPTION_MASK_ISA2_CX16 |
167 | #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF |
168 | #define OPTION_MASK_ISA2_MOVBE_SET OPTION_MASK_ISA2_MOVBE |
169 | #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32 |
170 | |
171 | #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE |
172 | #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND |
173 | #define OPTION_MASK_ISA2_PTWRITE_SET OPTION_MASK_ISA2_PTWRITE |
174 | #define OPTION_MASK_ISA_F16C_SET \ |
175 | (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET) |
176 | #define OPTION_MASK_ISA2_MWAITX_SET OPTION_MASK_ISA2_MWAITX |
177 | #define OPTION_MASK_ISA2_MWAIT_SET OPTION_MASK_ISA2_MWAIT |
178 | #define OPTION_MASK_ISA2_CLZERO_SET OPTION_MASK_ISA2_CLZERO |
179 | #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU |
180 | #define OPTION_MASK_ISA2_RDPID_SET OPTION_MASK_ISA2_RDPID |
181 | #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI |
182 | #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK |
183 | #define OPTION_MASK_ISA2_VAES_SET OPTION_MASK_ISA2_VAES |
184 | #define OPTION_MASK_ISA_VPCLMULQDQ_SET \ |
185 | (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_PCLMUL_SET \ |
186 | | OPTION_MASK_ISA_AVX_SET) |
187 | #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI |
188 | #define OPTION_MASK_ISA2_MOVDIR64B_SET OPTION_MASK_ISA2_MOVDIR64B |
189 | #define OPTION_MASK_ISA2_WAITPKG_SET OPTION_MASK_ISA2_WAITPKG |
190 | #define OPTION_MASK_ISA2_CLDEMOTE_SET OPTION_MASK_ISA2_CLDEMOTE |
191 | #define OPTION_MASK_ISA2_ENQCMD_SET OPTION_MASK_ISA2_ENQCMD |
192 | #define OPTION_MASK_ISA2_SERIALIZE_SET OPTION_MASK_ISA2_SERIALIZE |
193 | #define OPTION_MASK_ISA2_TSXLDTRK_SET OPTION_MASK_ISA2_TSXLDTRK |
194 | #define OPTION_MASK_ISA2_UINTR_SET OPTION_MASK_ISA2_UINTR |
195 | #define OPTION_MASK_ISA2_HRESET_SET OPTION_MASK_ISA2_HRESET |
196 | #define OPTION_MASK_ISA2_KL_SET OPTION_MASK_ISA2_KL |
197 | #define OPTION_MASK_ISA2_WIDEKL_SET \ |
198 | (OPTION_MASK_ISA2_WIDEKL | OPTION_MASK_ISA2_KL_SET) |
199 | |
200 | /* Define a set of ISAs which aren't available when a given ISA is |
201 | disabled. MMX and SSE ISAs are handled separately. */ |
202 | |
203 | #define OPTION_MASK_ISA_MMX_UNSET \ |
204 | (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET) |
205 | #define OPTION_MASK_ISA_3DNOW_UNSET \ |
206 | (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET) |
207 | #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A |
208 | |
209 | #define OPTION_MASK_ISA_SSE_UNSET \ |
210 | (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET) |
211 | #define OPTION_MASK_ISA_SSE2_UNSET \ |
212 | (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET) |
213 | #define OPTION_MASK_ISA_SSE3_UNSET \ |
214 | (OPTION_MASK_ISA_SSE3 \ |
215 | | OPTION_MASK_ISA_SSSE3_UNSET \ |
216 | | OPTION_MASK_ISA_SSE4A_UNSET ) |
217 | #define OPTION_MASK_ISA_SSSE3_UNSET \ |
218 | (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET) |
219 | #define OPTION_MASK_ISA_SSE4_1_UNSET \ |
220 | (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET) |
221 | #define OPTION_MASK_ISA_SSE4_2_UNSET \ |
222 | (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET ) |
223 | #define OPTION_MASK_ISA_AVX_UNSET \ |
224 | (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \ |
225 | | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \ |
226 | | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_VPCLMULQDQ_UNSET) |
227 | #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA |
228 | #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR |
229 | #define OPTION_MASK_ISA_XSAVE_UNSET \ |
230 | (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \ |
231 | | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET \ |
232 | | OPTION_MASK_ISA_AVX_UNSET) |
233 | #define OPTION_MASK_ISA2_XSAVE_UNSET \ |
234 | (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_AMX_TILE_UNSET) |
235 | #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT |
236 | #define OPTION_MASK_ISA_AVX2_UNSET \ |
237 | (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET) |
238 | #define OPTION_MASK_ISA2_AVX2_UNSET \ |
239 | (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ |
240 | | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ |
241 | | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ |
242 | | OPTION_MASK_ISA2_AVX10_1_256_UNSET) |
243 | #define OPTION_MASK_ISA_AVX512F_UNSET \ |
244 | (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ |
245 | | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ |
246 | | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \ |
247 | | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \ |
248 | | OPTION_MASK_ISA_AVX512VNNI_UNSET \ |
249 | | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET) |
250 | #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD |
251 | #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF |
252 | #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER |
253 | #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ |
254 | #define OPTION_MASK_ISA_AVX512BW_UNSET \ |
255 | (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET \ |
256 | | OPTION_MASK_ISA_AVX512VBMI2_UNSET | OPTION_MASK_ISA_AVX512BITALG_UNSET) |
257 | #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL |
258 | #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA |
259 | #define OPTION_MASK_ISA2_AVXIFMA_UNSET OPTION_MASK_ISA2_AVXIFMA |
260 | #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI |
261 | #define OPTION_MASK_ISA2_AVX5124FMAPS_UNSET OPTION_MASK_ISA2_AVX5124FMAPS |
262 | #define OPTION_MASK_ISA2_AVX5124VNNIW_UNSET OPTION_MASK_ISA2_AVX5124VNNIW |
263 | #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2 |
264 | #define OPTION_MASK_ISA_AVX512FP16_UNSET OPTION_MASK_ISA_AVX512BW_UNSET |
265 | #define OPTION_MASK_ISA2_AVX512FP16_UNSET OPTION_MASK_ISA2_AVX512FP16 |
266 | #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI |
267 | #define OPTION_MASK_ISA2_AVXVNNI_UNSET OPTION_MASK_ISA2_AVXVNNI |
268 | #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ |
269 | #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG |
270 | #define OPTION_MASK_ISA2_AVX512BF16_UNSET OPTION_MASK_ISA2_AVX512BF16 |
271 | #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM |
272 | #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW |
273 | #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED |
274 | #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX |
275 | #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1 |
276 | #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT |
277 | #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC |
278 | #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES |
279 | #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB |
280 | #define OPTION_MASK_ISA2_MWAITX_UNSET OPTION_MASK_ISA2_MWAITX |
281 | #define OPTION_MASK_ISA2_MWAIT_UNSET OPTION_MASK_ISA2_MWAIT |
282 | #define OPTION_MASK_ISA2_CLZERO_UNSET OPTION_MASK_ISA2_CLZERO |
283 | #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU |
284 | #define OPTION_MASK_ISA2_RDPID_UNSET OPTION_MASK_ISA2_RDPID |
285 | #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI |
286 | #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK |
287 | #define OPTION_MASK_ISA2_VAES_UNSET OPTION_MASK_ISA2_VAES |
288 | #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ |
289 | #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI |
290 | #define OPTION_MASK_ISA2_MOVDIR64B_UNSET OPTION_MASK_ISA2_MOVDIR64B |
291 | #define OPTION_MASK_ISA2_WAITPKG_UNSET OPTION_MASK_ISA2_WAITPKG |
292 | #define OPTION_MASK_ISA2_CLDEMOTE_UNSET OPTION_MASK_ISA2_CLDEMOTE |
293 | #define OPTION_MASK_ISA2_ENQCMD_UNSET OPTION_MASK_ISA2_ENQCMD |
294 | #define OPTION_MASK_ISA2_SERIALIZE_UNSET OPTION_MASK_ISA2_SERIALIZE |
295 | #define OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET OPTION_MASK_ISA2_AVX512VP2INTERSECT |
296 | #define OPTION_MASK_ISA2_TSXLDTRK_UNSET OPTION_MASK_ISA2_TSXLDTRK |
297 | #define OPTION_MASK_ISA2_AMX_TILE_UNSET \ |
298 | (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_INT8_UNSET \ |
299 | | OPTION_MASK_ISA2_AMX_BF16_UNSET | OPTION_MASK_ISA2_AMX_FP16_UNSET \ |
300 | | OPTION_MASK_ISA2_AMX_COMPLEX_UNSET) |
301 | #define OPTION_MASK_ISA2_AMX_INT8_UNSET OPTION_MASK_ISA2_AMX_INT8 |
302 | #define OPTION_MASK_ISA2_AMX_BF16_UNSET OPTION_MASK_ISA2_AMX_BF16 |
303 | #define OPTION_MASK_ISA2_UINTR_UNSET OPTION_MASK_ISA2_UINTR |
304 | #define OPTION_MASK_ISA2_HRESET_UNSET OPTION_MASK_ISA2_HRESET |
305 | #define OPTION_MASK_ISA2_KL_UNSET \ |
306 | (OPTION_MASK_ISA2_KL | OPTION_MASK_ISA2_WIDEKL_UNSET) |
307 | #define OPTION_MASK_ISA2_WIDEKL_UNSET OPTION_MASK_ISA2_WIDEKL |
308 | #define OPTION_MASK_ISA2_AVXVNNIINT8_UNSET OPTION_MASK_ISA2_AVXVNNIINT8 |
309 | #define OPTION_MASK_ISA2_AVXNECONVERT_UNSET OPTION_MASK_ISA2_AVXNECONVERT |
310 | #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD |
311 | #define OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16 |
312 | #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI |
313 | #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT |
314 | #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX |
315 | #define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16 |
316 | #define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3 |
317 | #define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512 |
318 | #define OPTION_MASK_ISA2_SM4_UNSET OPTION_MASK_ISA2_SM4 |
319 | #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F |
320 | #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 |
321 | #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR |
322 | #define OPTION_MASK_ISA2_AVX10_1_256_UNSET \ |
323 | (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET) |
324 | #define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512 |
325 | |
326 | /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same |
327 | as -mno-sse4.1. */ |
328 | #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET |
329 | |
330 | #define OPTION_MASK_ISA_SSE4A_UNSET \ |
331 | (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET) |
332 | |
333 | #define OPTION_MASK_ISA_FMA4_UNSET \ |
334 | (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET) |
335 | #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP |
336 | #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP |
337 | |
338 | #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES |
339 | #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA |
340 | #define OPTION_MASK_ISA_PCLMUL_UNSET \ |
341 | (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_VPCLMULQDQ_UNSET) |
342 | #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM |
343 | #define OPTION_MASK_ISA2_PCONFIG_UNSET OPTION_MASK_ISA2_PCONFIG |
344 | #define OPTION_MASK_ISA2_WBNOINVD_UNSET OPTION_MASK_ISA2_WBNOINVD |
345 | #define OPTION_MASK_ISA2_SGX_UNSET OPTION_MASK_ISA2_SGX |
346 | #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI |
347 | #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2 |
348 | #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT |
349 | #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM |
350 | #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT |
351 | #define OPTION_MASK_ISA2_CX16_UNSET OPTION_MASK_ISA2_CX16 |
352 | #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF |
353 | #define OPTION_MASK_ISA2_MOVBE_UNSET OPTION_MASK_ISA2_MOVBE |
354 | #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32 |
355 | |
356 | #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE |
357 | #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND |
358 | #define OPTION_MASK_ISA2_PTWRITE_UNSET OPTION_MASK_ISA2_PTWRITE |
359 | #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C |
360 | |
361 | #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \ |
362 | (OPTION_MASK_ISA_MMX_UNSET \ |
363 | | OPTION_MASK_ISA_SSE_UNSET) |
364 | |
365 | #define OPTION_MASK_ISA2_AVX512F_UNSET \ |
366 | (OPTION_MASK_ISA2_AVX512BW_UNSET \ |
367 | | OPTION_MASK_ISA2_AVX5124FMAPS_UNSET \ |
368 | | OPTION_MASK_ISA2_AVX5124VNNIW_UNSET \ |
369 | | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET) |
370 | #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \ |
371 | OPTION_MASK_ISA2_SSE_UNSET |
372 | #define OPTION_MASK_ISA2_AVX_UNSET \ |
373 | (OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \ |
374 | | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET \ |
375 | | OPTION_MASK_ISA2_SM4_UNSET) |
376 | #define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET |
377 | #define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET |
378 | #define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET |
379 | #define OPTION_MASK_ISA2_SSSE3_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET |
380 | #define OPTION_MASK_ISA2_SSE3_UNSET OPTION_MASK_ISA2_SSSE3_UNSET |
381 | #define OPTION_MASK_ISA2_SSE2_UNSET \ |
382 | (OPTION_MASK_ISA2_SSE3_UNSET | OPTION_MASK_ISA2_KL_UNSET) |
383 | #define OPTION_MASK_ISA2_SSE_UNSET OPTION_MASK_ISA2_SSE2_UNSET |
384 | |
385 | #define OPTION_MASK_ISA2_AVX512BW_UNSET \ |
386 | (OPTION_MASK_ISA2_AVX512BF16_UNSET \ |
387 | | OPTION_MASK_ISA2_AVX512FP16_UNSET) |
388 | |
389 | /* Set 1 << value as value of -malign-FLAG option. */ |
390 | |
391 | static void |
392 | set_malign_value (const char **flag, unsigned value) |
393 | { |
394 | char *r = XNEWVEC (char, 6); |
395 | sprintf (s: r, format: "%d" , 1 << value); |
396 | *flag = r; |
397 | } |
398 | |
399 | /* Implement TARGET_HANDLE_OPTION. */ |
400 | |
401 | bool |
402 | ix86_handle_option (struct gcc_options *opts, |
403 | struct gcc_options *opts_set ATTRIBUTE_UNUSED, |
404 | const struct cl_decoded_option *decoded, |
405 | location_t loc) |
406 | { |
407 | size_t code = decoded->opt_index; |
408 | int value = decoded->value; |
409 | |
410 | switch (code) |
411 | { |
412 | case OPT_mgeneral_regs_only: |
413 | if (value) |
414 | { |
415 | HOST_WIDE_INT general_regs_only_flags = 0; |
416 | HOST_WIDE_INT general_regs_only_flags2 = 0; |
417 | |
418 | /* NB: Enable the GPR only instructions which are enabled |
419 | implicitly by SSE ISAs unless they have been disabled |
420 | explicitly. */ |
421 | if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)) |
422 | { |
423 | if (!TARGET_EXPLICIT_CRC32_P (opts)) |
424 | general_regs_only_flags |= OPTION_MASK_ISA_CRC32; |
425 | if (!TARGET_EXPLICIT_POPCNT_P (opts)) |
426 | general_regs_only_flags |= OPTION_MASK_ISA_POPCNT; |
427 | } |
428 | if (TARGET_SSE3_P (opts->x_ix86_isa_flags)) |
429 | { |
430 | if (!TARGET_EXPLICIT_MWAIT_P (opts)) |
431 | general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT; |
432 | } |
433 | |
434 | /* Disable MMX, SSE and x87 instructions if only |
435 | general registers are allowed. */ |
436 | opts->x_ix86_isa_flags |
437 | &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET; |
438 | opts->x_ix86_isa_flags2 |
439 | &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET; |
440 | opts->x_ix86_isa_flags |= general_regs_only_flags; |
441 | opts->x_ix86_isa_flags2 |= general_regs_only_flags2; |
442 | opts->x_ix86_isa_flags_explicit |
443 | |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET |
444 | | general_regs_only_flags); |
445 | opts->x_ix86_isa_flags2_explicit |
446 | |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET |
447 | | general_regs_only_flags2); |
448 | |
449 | opts->x_target_flags &= ~MASK_80387; |
450 | } |
451 | else |
452 | gcc_unreachable (); |
453 | return true; |
454 | |
455 | case OPT_mmmx: |
456 | if (value) |
457 | { |
458 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET; |
459 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET; |
460 | } |
461 | else |
462 | { |
463 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET; |
464 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET; |
465 | } |
466 | return true; |
467 | |
468 | case OPT_m3dnow: |
469 | if (value) |
470 | { |
471 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET; |
472 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET; |
473 | } |
474 | else |
475 | { |
476 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET; |
477 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET; |
478 | } |
479 | return true; |
480 | |
481 | case OPT_m3dnowa: |
482 | if (value) |
483 | { |
484 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET; |
485 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET; |
486 | } |
487 | else |
488 | { |
489 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET; |
490 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET; |
491 | } |
492 | return true; |
493 | |
494 | case OPT_msse: |
495 | if (value) |
496 | { |
497 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET; |
498 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET; |
499 | } |
500 | else |
501 | { |
502 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET; |
503 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET; |
504 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE_UNSET; |
505 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE_UNSET; |
506 | } |
507 | return true; |
508 | |
509 | case OPT_msse2: |
510 | if (value) |
511 | { |
512 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; |
513 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; |
514 | } |
515 | else |
516 | { |
517 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET; |
518 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET; |
519 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE2_UNSET; |
520 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE2_UNSET; |
521 | } |
522 | return true; |
523 | |
524 | case OPT_msse3: |
525 | if (value) |
526 | { |
527 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET; |
528 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET; |
529 | } |
530 | else |
531 | { |
532 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET; |
533 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET; |
534 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE3_UNSET; |
535 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE3_UNSET; |
536 | } |
537 | return true; |
538 | |
539 | case OPT_mssse3: |
540 | if (value) |
541 | { |
542 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET; |
543 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET; |
544 | } |
545 | else |
546 | { |
547 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET; |
548 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET; |
549 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSSE3_UNSET; |
550 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSSE3_UNSET; |
551 | } |
552 | return true; |
553 | |
554 | case OPT_msse4_1: |
555 | if (value) |
556 | { |
557 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET; |
558 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET; |
559 | } |
560 | else |
561 | { |
562 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET; |
563 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET; |
564 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_1_UNSET; |
565 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_1_UNSET; |
566 | } |
567 | return true; |
568 | |
569 | case OPT_msse4_2: |
570 | if (value) |
571 | { |
572 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET; |
573 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET; |
574 | } |
575 | else |
576 | { |
577 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET; |
578 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET; |
579 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_2_UNSET; |
580 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_2_UNSET; |
581 | } |
582 | return true; |
583 | |
584 | case OPT_mavx: |
585 | if (value) |
586 | { |
587 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; |
588 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; |
589 | } |
590 | else |
591 | { |
592 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET; |
593 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET; |
594 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX_UNSET; |
595 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX_UNSET; |
596 | } |
597 | return true; |
598 | |
599 | case OPT_mavx2: |
600 | if (value) |
601 | { |
602 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
603 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
604 | } |
605 | else |
606 | { |
607 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET; |
608 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET; |
609 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX2_UNSET; |
610 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX2_UNSET; |
611 | } |
612 | return true; |
613 | |
614 | case OPT_mavx512f: |
615 | if (value) |
616 | { |
617 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; |
618 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; |
619 | } |
620 | else |
621 | { |
622 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET; |
623 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; |
624 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; |
625 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; |
626 | opts->x_ix86_no_avx512_explicit = 1; |
627 | } |
628 | return true; |
629 | |
630 | case OPT_mavx512cd: |
631 | if (value) |
632 | { |
633 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET; |
634 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET; |
635 | } |
636 | else |
637 | { |
638 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; |
639 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; |
640 | opts->x_ix86_no_avx512_explicit = 1; |
641 | } |
642 | return true; |
643 | |
644 | case OPT_mavx512pf: |
645 | if (value) |
646 | { |
647 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET; |
648 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET; |
649 | } |
650 | else |
651 | { |
652 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET; |
653 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET; |
654 | } |
655 | return true; |
656 | |
657 | case OPT_mavx512er: |
658 | if (value) |
659 | { |
660 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET; |
661 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET; |
662 | } |
663 | else |
664 | { |
665 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET; |
666 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET; |
667 | } |
668 | return true; |
669 | |
670 | case OPT_mrdpid: |
671 | if (value) |
672 | { |
673 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RDPID_SET; |
674 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_SET; |
675 | } |
676 | else |
677 | { |
678 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RDPID_UNSET; |
679 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RDPID_UNSET; |
680 | } |
681 | return true; |
682 | |
683 | case OPT_mgfni: |
684 | if (value) |
685 | { |
686 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET; |
687 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET; |
688 | } |
689 | else |
690 | { |
691 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET; |
692 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET; |
693 | } |
694 | return true; |
695 | |
696 | case OPT_mshstk: |
697 | if (value) |
698 | { |
699 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET; |
700 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET; |
701 | } |
702 | else |
703 | { |
704 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET; |
705 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET; |
706 | } |
707 | return true; |
708 | |
709 | case OPT_mvaes: |
710 | if (value) |
711 | { |
712 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_VAES_SET; |
713 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_SET; |
714 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; |
715 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; |
716 | } |
717 | else |
718 | { |
719 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_VAES_UNSET; |
720 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_VAES_UNSET; |
721 | } |
722 | return true; |
723 | |
724 | case OPT_mvpclmulqdq: |
725 | if (value) |
726 | { |
727 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET; |
728 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET; |
729 | } |
730 | else |
731 | { |
732 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET; |
733 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET; |
734 | } |
735 | return true; |
736 | |
737 | case OPT_mmovdiri: |
738 | if (value) |
739 | { |
740 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET; |
741 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET; |
742 | } |
743 | else |
744 | { |
745 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET; |
746 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET; |
747 | } |
748 | return true; |
749 | |
750 | case OPT_mmovdir64b: |
751 | if (value) |
752 | { |
753 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVDIR64B_SET; |
754 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_SET; |
755 | } |
756 | else |
757 | { |
758 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVDIR64B_UNSET; |
759 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVDIR64B_UNSET; |
760 | } |
761 | return true; |
762 | |
763 | case OPT_mcldemote: |
764 | if (value) |
765 | { |
766 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLDEMOTE_SET; |
767 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_SET; |
768 | } |
769 | else |
770 | { |
771 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLDEMOTE_UNSET; |
772 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLDEMOTE_UNSET; |
773 | } |
774 | return true; |
775 | |
776 | case OPT_mwaitpkg: |
777 | if (value) |
778 | { |
779 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WAITPKG_SET; |
780 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_SET; |
781 | } |
782 | else |
783 | { |
784 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WAITPKG_UNSET; |
785 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WAITPKG_UNSET; |
786 | } |
787 | return true; |
788 | |
789 | case OPT_menqcmd: |
790 | if (value) |
791 | { |
792 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_ENQCMD_SET; |
793 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_SET; |
794 | } |
795 | else |
796 | { |
797 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_ENQCMD_UNSET; |
798 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_ENQCMD_UNSET; |
799 | } |
800 | return true; |
801 | |
802 | case OPT_mkl: |
803 | if (value) |
804 | { |
805 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_KL_SET; |
806 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_SET; |
807 | |
808 | /* The Keylocker instructions need XMM registers from SSE2. */ |
809 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; |
810 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; |
811 | } |
812 | else |
813 | { |
814 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_KL_UNSET; |
815 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_KL_UNSET; |
816 | } |
817 | return true; |
818 | |
819 | case OPT_mwidekl: |
820 | if (value) |
821 | { |
822 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WIDEKL_SET; |
823 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_SET; |
824 | |
825 | /* The Widekl instructions need XMM registers from SSE2. */ |
826 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET; |
827 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET; |
828 | } |
829 | else |
830 | { |
831 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WIDEKL_UNSET; |
832 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WIDEKL_UNSET; |
833 | } |
834 | return true; |
835 | |
836 | case OPT_mserialize: |
837 | if (value) |
838 | { |
839 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SERIALIZE_SET; |
840 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_SET; |
841 | } |
842 | else |
843 | { |
844 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SERIALIZE_UNSET; |
845 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SERIALIZE_UNSET; |
846 | } |
847 | return true; |
848 | |
849 | case OPT_muintr: |
850 | if (value) |
851 | { |
852 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_UINTR_SET; |
853 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_SET; |
854 | } |
855 | else |
856 | { |
857 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_UINTR_UNSET; |
858 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_UINTR_UNSET; |
859 | } |
860 | return true; |
861 | |
862 | case OPT_mhreset: |
863 | if (value) |
864 | { |
865 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_HRESET_SET; |
866 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_SET; |
867 | } |
868 | else |
869 | { |
870 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_HRESET_UNSET; |
871 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_HRESET_UNSET; |
872 | } |
873 | return true; |
874 | |
875 | case OPT_mavx5124fmaps: |
876 | if (value) |
877 | { |
878 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; |
879 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_SET; |
880 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; |
881 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; |
882 | } |
883 | else |
884 | { |
885 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; |
886 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124FMAPS_UNSET; |
887 | } |
888 | return true; |
889 | |
890 | case OPT_mavx5124vnniw: |
891 | if (value) |
892 | { |
893 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; |
894 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_SET; |
895 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET; |
896 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET; |
897 | } |
898 | else |
899 | { |
900 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; |
901 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX5124VNNIW_UNSET; |
902 | } |
903 | return true; |
904 | |
905 | case OPT_mavx512vbmi2: |
906 | if (value) |
907 | { |
908 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET; |
909 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET; |
910 | } |
911 | else |
912 | { |
913 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; |
914 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; |
915 | opts->x_ix86_no_avx512_explicit = 1; |
916 | } |
917 | return true; |
918 | |
919 | case OPT_mavx512fp16: |
920 | if (value) |
921 | { |
922 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512FP16_SET; |
923 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_SET; |
924 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512FP16_SET; |
925 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512FP16_SET; |
926 | } |
927 | else |
928 | { |
929 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET; |
930 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET; |
931 | opts->x_ix86_no_avx512_explicit = 1; |
932 | } |
933 | return true; |
934 | |
935 | case OPT_mavx512vnni: |
936 | if (value) |
937 | { |
938 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET; |
939 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET; |
940 | } |
941 | else |
942 | { |
943 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; |
944 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; |
945 | opts->x_ix86_no_avx512_explicit = 1; |
946 | } |
947 | return true; |
948 | |
949 | case OPT_mavx512vpopcntdq: |
950 | if (value) |
951 | { |
952 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; |
953 | opts->x_ix86_isa_flags_explicit |
954 | |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET; |
955 | } |
956 | else |
957 | { |
958 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; |
959 | opts->x_ix86_isa_flags_explicit |
960 | |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; |
961 | opts->x_ix86_no_avx512_explicit = 1; |
962 | } |
963 | return true; |
964 | |
965 | case OPT_mavx512bitalg: |
966 | if (value) |
967 | { |
968 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET; |
969 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET; |
970 | } |
971 | else |
972 | { |
973 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; |
974 | opts->x_ix86_isa_flags_explicit |
975 | |= OPTION_MASK_ISA_AVX512BITALG_UNSET; |
976 | opts->x_ix86_no_avx512_explicit = 1; |
977 | } |
978 | return true; |
979 | |
980 | case OPT_mavx512bf16: |
981 | if (value) |
982 | { |
983 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512BF16_SET; |
984 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_SET; |
985 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; |
986 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; |
987 | } |
988 | else |
989 | { |
990 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; |
991 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; |
992 | opts->x_ix86_no_avx512_explicit = 1; |
993 | } |
994 | return true; |
995 | |
996 | case OPT_mavxvnni: |
997 | if (value) |
998 | { |
999 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNI_SET; |
1000 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_SET; |
1001 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1002 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1003 | } |
1004 | else |
1005 | { |
1006 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXVNNI_UNSET; |
1007 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXVNNI_UNSET; |
1008 | } |
1009 | return true; |
1010 | |
1011 | case OPT_msgx: |
1012 | if (value) |
1013 | { |
1014 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SGX_SET; |
1015 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_SET; |
1016 | } |
1017 | else |
1018 | { |
1019 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SGX_UNSET; |
1020 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SGX_UNSET; |
1021 | } |
1022 | return true; |
1023 | |
1024 | case OPT_mpconfig: |
1025 | if (value) |
1026 | { |
1027 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PCONFIG_SET; |
1028 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_SET; |
1029 | } |
1030 | else |
1031 | { |
1032 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PCONFIG_UNSET; |
1033 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PCONFIG_UNSET; |
1034 | } |
1035 | return true; |
1036 | |
1037 | case OPT_mwbnoinvd: |
1038 | if (value) |
1039 | { |
1040 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_WBNOINVD_SET; |
1041 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_SET; |
1042 | } |
1043 | else |
1044 | { |
1045 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_WBNOINVD_UNSET; |
1046 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_WBNOINVD_UNSET; |
1047 | } |
1048 | return true; |
1049 | |
1050 | case OPT_mavx512dq: |
1051 | if (value) |
1052 | { |
1053 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; |
1054 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; |
1055 | } |
1056 | else |
1057 | { |
1058 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; |
1059 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; |
1060 | opts->x_ix86_no_avx512_explicit = 1; |
1061 | } |
1062 | return true; |
1063 | |
1064 | case OPT_mavx512bw: |
1065 | if (value) |
1066 | { |
1067 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET; |
1068 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET; |
1069 | } |
1070 | else |
1071 | { |
1072 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET; |
1073 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; |
1074 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET; |
1075 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET; |
1076 | opts->x_ix86_no_avx512_explicit = 1; |
1077 | } |
1078 | return true; |
1079 | |
1080 | case OPT_mavx512vl: |
1081 | if (value) |
1082 | { |
1083 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET; |
1084 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET; |
1085 | } |
1086 | else |
1087 | { |
1088 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; |
1089 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; |
1090 | opts->x_ix86_no_avx512_explicit = 1; |
1091 | } |
1092 | return true; |
1093 | |
1094 | case OPT_mavx512ifma: |
1095 | if (value) |
1096 | { |
1097 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET; |
1098 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET; |
1099 | } |
1100 | else |
1101 | { |
1102 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; |
1103 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; |
1104 | opts->x_ix86_no_avx512_explicit = 1; |
1105 | } |
1106 | return true; |
1107 | |
1108 | case OPT_mavx512vbmi: |
1109 | if (value) |
1110 | { |
1111 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET; |
1112 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET; |
1113 | } |
1114 | else |
1115 | { |
1116 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; |
1117 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; |
1118 | opts->x_ix86_no_avx512_explicit = 1; |
1119 | } |
1120 | return true; |
1121 | |
1122 | case OPT_mavx512vp2intersect: |
1123 | if (value) |
1124 | { |
1125 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; |
1126 | opts->x_ix86_isa_flags2_explicit |= |
1127 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_SET; |
1128 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET; |
1129 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET; |
1130 | } |
1131 | else |
1132 | { |
1133 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; |
1134 | opts->x_ix86_isa_flags2_explicit |= |
1135 | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET; |
1136 | } |
1137 | return true; |
1138 | |
1139 | case OPT_mtsxldtrk: |
1140 | if (value) |
1141 | { |
1142 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_TSXLDTRK_SET; |
1143 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_SET; |
1144 | } |
1145 | else |
1146 | { |
1147 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_TSXLDTRK_UNSET; |
1148 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_TSXLDTRK_UNSET; |
1149 | } |
1150 | return true; |
1151 | |
1152 | case OPT_mamx_tile: |
1153 | if (value) |
1154 | { |
1155 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_TILE_SET; |
1156 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_SET; |
1157 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; |
1158 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; |
1159 | } |
1160 | else |
1161 | { |
1162 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_TILE_UNSET; |
1163 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_TILE_UNSET; |
1164 | } |
1165 | return true; |
1166 | |
1167 | case OPT_mamx_int8: |
1168 | if (value) |
1169 | { |
1170 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_INT8_SET; |
1171 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_SET; |
1172 | } |
1173 | else |
1174 | { |
1175 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_INT8_UNSET; |
1176 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_INT8_UNSET; |
1177 | } |
1178 | return true; |
1179 | |
1180 | case OPT_mamx_bf16: |
1181 | if (value) |
1182 | { |
1183 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_BF16_SET; |
1184 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_SET; |
1185 | } |
1186 | else |
1187 | { |
1188 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_BF16_UNSET; |
1189 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_BF16_UNSET; |
1190 | } |
1191 | return true; |
1192 | |
1193 | case OPT_mavxifma: |
1194 | if (value) |
1195 | { |
1196 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXIFMA_SET; |
1197 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_SET; |
1198 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1199 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1200 | } |
1201 | else |
1202 | { |
1203 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXIFMA_UNSET; |
1204 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXIFMA_UNSET; |
1205 | } |
1206 | return true; |
1207 | |
1208 | case OPT_mavxvnniint8: |
1209 | if (value) |
1210 | { |
1211 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT8_SET; |
1212 | opts->x_ix86_isa_flags2_explicit |= |
1213 | OPTION_MASK_ISA2_AVXVNNIINT8_SET; |
1214 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1215 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1216 | } |
1217 | else |
1218 | { |
1219 | opts->x_ix86_isa_flags2 &= |
1220 | ~OPTION_MASK_ISA2_AVXVNNIINT8_UNSET; |
1221 | opts->x_ix86_isa_flags2_explicit |= |
1222 | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET; |
1223 | } |
1224 | return true; |
1225 | |
1226 | case OPT_mavxneconvert: |
1227 | if (value) |
1228 | { |
1229 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXNECONVERT_SET; |
1230 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVXNECONVERT_SET; |
1231 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1232 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1233 | } |
1234 | else |
1235 | { |
1236 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVXNECONVERT_UNSET; |
1237 | opts->x_ix86_isa_flags2_explicit |
1238 | |= OPTION_MASK_ISA2_AVXNECONVERT_UNSET; |
1239 | } |
1240 | return true; |
1241 | |
1242 | case OPT_mcmpccxadd: |
1243 | if (value) |
1244 | { |
1245 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CMPCCXADD_SET; |
1246 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_SET; |
1247 | } |
1248 | else |
1249 | { |
1250 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CMPCCXADD_UNSET; |
1251 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CMPCCXADD_UNSET; |
1252 | } |
1253 | return true; |
1254 | |
1255 | case OPT_mamx_fp16: |
1256 | if (value) |
1257 | { |
1258 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_FP16_SET; |
1259 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_SET; |
1260 | } |
1261 | else |
1262 | { |
1263 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_FP16_UNSET; |
1264 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_FP16_UNSET; |
1265 | } |
1266 | return true; |
1267 | |
1268 | case OPT_mprefetchi: |
1269 | if (value) |
1270 | { |
1271 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PREFETCHI_SET; |
1272 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_SET; |
1273 | } |
1274 | else |
1275 | { |
1276 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PREFETCHI_UNSET; |
1277 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PREFETCHI_UNSET; |
1278 | } |
1279 | return true; |
1280 | |
1281 | case OPT_mraoint: |
1282 | if (value) |
1283 | { |
1284 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET; |
1285 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET; |
1286 | } |
1287 | else |
1288 | { |
1289 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET; |
1290 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET; |
1291 | } |
1292 | return true; |
1293 | |
1294 | case OPT_mamx_complex: |
1295 | if (value) |
1296 | { |
1297 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_COMPLEX_SET; |
1298 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_SET; |
1299 | } |
1300 | else |
1301 | { |
1302 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AMX_COMPLEX_UNSET; |
1303 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_COMPLEX_UNSET; |
1304 | } |
1305 | return true; |
1306 | |
1307 | case OPT_mavxvnniint16: |
1308 | if (value) |
1309 | { |
1310 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET; |
1311 | opts->x_ix86_isa_flags2_explicit |= |
1312 | OPTION_MASK_ISA2_AVXVNNIINT16_SET; |
1313 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1314 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1315 | } |
1316 | else |
1317 | { |
1318 | opts->x_ix86_isa_flags2 &= |
1319 | ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET; |
1320 | opts->x_ix86_isa_flags2_explicit |= |
1321 | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET; |
1322 | } |
1323 | return true; |
1324 | |
1325 | case OPT_msm3: |
1326 | if (value) |
1327 | { |
1328 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM3_SET; |
1329 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_SET; |
1330 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; |
1331 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; |
1332 | } |
1333 | else |
1334 | { |
1335 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM3_UNSET; |
1336 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM3_UNSET; |
1337 | } |
1338 | return true; |
1339 | |
1340 | case OPT_msha512: |
1341 | if (value) |
1342 | { |
1343 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET; |
1344 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET; |
1345 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; |
1346 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; |
1347 | } |
1348 | else |
1349 | { |
1350 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET; |
1351 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET; |
1352 | } |
1353 | return true; |
1354 | |
1355 | case OPT_msm4: |
1356 | if (value) |
1357 | { |
1358 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SM4_SET; |
1359 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_SET; |
1360 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET; |
1361 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET; |
1362 | } |
1363 | else |
1364 | { |
1365 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SM4_UNSET; |
1366 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SM4_UNSET; |
1367 | } |
1368 | return true; |
1369 | |
1370 | case OPT_mapxf: |
1371 | if (value) |
1372 | { |
1373 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_APX_F_SET; |
1374 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_SET; |
1375 | opts->x_ix86_apx_features = apx_all; |
1376 | } |
1377 | else |
1378 | { |
1379 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_APX_F_UNSET; |
1380 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_APX_F_UNSET; |
1381 | opts->x_ix86_apx_features = apx_none; |
1382 | } |
1383 | return true; |
1384 | |
1385 | case OPT_mevex512: |
1386 | if (value) |
1387 | { |
1388 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512_SET; |
1389 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_SET; |
1390 | } |
1391 | else |
1392 | { |
1393 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET; |
1394 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET; |
1395 | opts->x_ix86_no_avx512_explicit = 1; |
1396 | } |
1397 | return true; |
1398 | |
1399 | case OPT_musermsr: |
1400 | if (value) |
1401 | { |
1402 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_USER_MSR_SET; |
1403 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_SET; |
1404 | } |
1405 | else |
1406 | { |
1407 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_USER_MSR_UNSET; |
1408 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_USER_MSR_UNSET; |
1409 | } |
1410 | return true; |
1411 | |
1412 | case OPT_mavx10_1_256: |
1413 | if (value) |
1414 | { |
1415 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET; |
1416 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET; |
1417 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1418 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1419 | } |
1420 | else |
1421 | { |
1422 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET; |
1423 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET; |
1424 | opts->x_ix86_no_avx10_1_explicit = 1; |
1425 | } |
1426 | return true; |
1427 | |
1428 | case OPT_mavx10_1_512: |
1429 | if (value) |
1430 | { |
1431 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET; |
1432 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET; |
1433 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; |
1434 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; |
1435 | } |
1436 | else |
1437 | { |
1438 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET; |
1439 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET; |
1440 | opts->x_ix86_no_avx10_1_explicit = 1; |
1441 | } |
1442 | return true; |
1443 | |
1444 | case OPT_mfma: |
1445 | if (value) |
1446 | { |
1447 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET; |
1448 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET; |
1449 | } |
1450 | else |
1451 | { |
1452 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET; |
1453 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET; |
1454 | } |
1455 | return true; |
1456 | |
1457 | case OPT_mrtm: |
1458 | if (value) |
1459 | { |
1460 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET; |
1461 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET; |
1462 | } |
1463 | else |
1464 | { |
1465 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET; |
1466 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET; |
1467 | } |
1468 | return true; |
1469 | |
1470 | case OPT_msse4: |
1471 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET; |
1472 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET; |
1473 | return true; |
1474 | |
1475 | case OPT_mno_sse4: |
1476 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET; |
1477 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET; |
1478 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SSE4_UNSET; |
1479 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SSE4_UNSET; |
1480 | return true; |
1481 | |
1482 | case OPT_msse4a: |
1483 | if (value) |
1484 | { |
1485 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET; |
1486 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET; |
1487 | } |
1488 | else |
1489 | { |
1490 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET; |
1491 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET; |
1492 | } |
1493 | return true; |
1494 | |
1495 | case OPT_mfma4: |
1496 | if (value) |
1497 | { |
1498 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET; |
1499 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET; |
1500 | } |
1501 | else |
1502 | { |
1503 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET; |
1504 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET; |
1505 | } |
1506 | return true; |
1507 | |
1508 | case OPT_mxop: |
1509 | if (value) |
1510 | { |
1511 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET; |
1512 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET; |
1513 | } |
1514 | else |
1515 | { |
1516 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET; |
1517 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET; |
1518 | } |
1519 | return true; |
1520 | |
1521 | case OPT_mlwp: |
1522 | if (value) |
1523 | { |
1524 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET; |
1525 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET; |
1526 | } |
1527 | else |
1528 | { |
1529 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET; |
1530 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET; |
1531 | } |
1532 | return true; |
1533 | |
1534 | case OPT_mabm: |
1535 | if (value) |
1536 | { |
1537 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET; |
1538 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET; |
1539 | } |
1540 | else |
1541 | { |
1542 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET; |
1543 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET; |
1544 | } |
1545 | return true; |
1546 | |
1547 | case OPT_mbmi: |
1548 | if (value) |
1549 | { |
1550 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET; |
1551 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET; |
1552 | } |
1553 | else |
1554 | { |
1555 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET; |
1556 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET; |
1557 | } |
1558 | return true; |
1559 | |
1560 | case OPT_mbmi2: |
1561 | if (value) |
1562 | { |
1563 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET; |
1564 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET; |
1565 | } |
1566 | else |
1567 | { |
1568 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET; |
1569 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET; |
1570 | } |
1571 | return true; |
1572 | |
1573 | case OPT_mlzcnt: |
1574 | if (value) |
1575 | { |
1576 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET; |
1577 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET; |
1578 | } |
1579 | else |
1580 | { |
1581 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET; |
1582 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET; |
1583 | } |
1584 | return true; |
1585 | |
1586 | case OPT_mtbm: |
1587 | if (value) |
1588 | { |
1589 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET; |
1590 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET; |
1591 | } |
1592 | else |
1593 | { |
1594 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET; |
1595 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET; |
1596 | } |
1597 | return true; |
1598 | |
1599 | case OPT_mpopcnt: |
1600 | if (value) |
1601 | { |
1602 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET; |
1603 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET; |
1604 | } |
1605 | else |
1606 | { |
1607 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET; |
1608 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET; |
1609 | } |
1610 | return true; |
1611 | |
1612 | case OPT_msahf: |
1613 | if (value) |
1614 | { |
1615 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET; |
1616 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET; |
1617 | } |
1618 | else |
1619 | { |
1620 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET; |
1621 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET; |
1622 | } |
1623 | return true; |
1624 | |
1625 | case OPT_mcx16: |
1626 | if (value) |
1627 | { |
1628 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CX16_SET; |
1629 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_SET; |
1630 | } |
1631 | else |
1632 | { |
1633 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CX16_UNSET; |
1634 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CX16_UNSET; |
1635 | } |
1636 | return true; |
1637 | |
1638 | case OPT_mmovbe: |
1639 | if (value) |
1640 | { |
1641 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MOVBE_SET; |
1642 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_SET; |
1643 | } |
1644 | else |
1645 | { |
1646 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MOVBE_UNSET; |
1647 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MOVBE_UNSET; |
1648 | } |
1649 | return true; |
1650 | |
1651 | case OPT_mcrc32: |
1652 | if (value) |
1653 | { |
1654 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET; |
1655 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET; |
1656 | } |
1657 | else |
1658 | { |
1659 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET; |
1660 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET; |
1661 | } |
1662 | return true; |
1663 | |
1664 | case OPT_maes: |
1665 | if (value) |
1666 | { |
1667 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET; |
1668 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET; |
1669 | } |
1670 | else |
1671 | { |
1672 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET; |
1673 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET; |
1674 | } |
1675 | return true; |
1676 | |
1677 | case OPT_msha: |
1678 | if (value) |
1679 | { |
1680 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET; |
1681 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET; |
1682 | } |
1683 | else |
1684 | { |
1685 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET; |
1686 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET; |
1687 | } |
1688 | return true; |
1689 | |
1690 | case OPT_mpclmul: |
1691 | if (value) |
1692 | { |
1693 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET; |
1694 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET; |
1695 | } |
1696 | else |
1697 | { |
1698 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET; |
1699 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET; |
1700 | } |
1701 | return true; |
1702 | |
1703 | case OPT_mfsgsbase: |
1704 | if (value) |
1705 | { |
1706 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET; |
1707 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET; |
1708 | } |
1709 | else |
1710 | { |
1711 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET; |
1712 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET; |
1713 | } |
1714 | return true; |
1715 | |
1716 | case OPT_mrdrnd: |
1717 | if (value) |
1718 | { |
1719 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET; |
1720 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET; |
1721 | } |
1722 | else |
1723 | { |
1724 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET; |
1725 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET; |
1726 | } |
1727 | return true; |
1728 | |
1729 | case OPT_mptwrite: |
1730 | if (value) |
1731 | { |
1732 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_PTWRITE_SET; |
1733 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_SET; |
1734 | } |
1735 | else |
1736 | { |
1737 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_PTWRITE_UNSET; |
1738 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_PTWRITE_UNSET; |
1739 | } |
1740 | return true; |
1741 | |
1742 | case OPT_mf16c: |
1743 | if (value) |
1744 | { |
1745 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET; |
1746 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET; |
1747 | } |
1748 | else |
1749 | { |
1750 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET; |
1751 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET; |
1752 | } |
1753 | return true; |
1754 | |
1755 | case OPT_mfxsr: |
1756 | if (value) |
1757 | { |
1758 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET; |
1759 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET; |
1760 | } |
1761 | else |
1762 | { |
1763 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET; |
1764 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET; |
1765 | } |
1766 | return true; |
1767 | |
1768 | case OPT_mxsave: |
1769 | if (value) |
1770 | { |
1771 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET; |
1772 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET; |
1773 | } |
1774 | else |
1775 | { |
1776 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET; |
1777 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET; |
1778 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_XSAVE_UNSET; |
1779 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_XSAVE_UNSET; |
1780 | } |
1781 | return true; |
1782 | |
1783 | case OPT_mxsaveopt: |
1784 | if (value) |
1785 | { |
1786 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET; |
1787 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET; |
1788 | } |
1789 | else |
1790 | { |
1791 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET; |
1792 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET; |
1793 | } |
1794 | return true; |
1795 | |
1796 | case OPT_mxsavec: |
1797 | if (value) |
1798 | { |
1799 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET; |
1800 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET; |
1801 | } |
1802 | else |
1803 | { |
1804 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET; |
1805 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET; |
1806 | } |
1807 | return true; |
1808 | |
1809 | case OPT_mxsaves: |
1810 | if (value) |
1811 | { |
1812 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET; |
1813 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET; |
1814 | } |
1815 | else |
1816 | { |
1817 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET; |
1818 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET; |
1819 | } |
1820 | return true; |
1821 | |
1822 | case OPT_mrdseed: |
1823 | if (value) |
1824 | { |
1825 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET; |
1826 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET; |
1827 | } |
1828 | else |
1829 | { |
1830 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET; |
1831 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET; |
1832 | } |
1833 | return true; |
1834 | |
1835 | case OPT_mprfchw: |
1836 | if (value) |
1837 | { |
1838 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET; |
1839 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET; |
1840 | } |
1841 | else |
1842 | { |
1843 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET; |
1844 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET; |
1845 | } |
1846 | return true; |
1847 | |
1848 | case OPT_madx: |
1849 | if (value) |
1850 | { |
1851 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET; |
1852 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET; |
1853 | } |
1854 | else |
1855 | { |
1856 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET; |
1857 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET; |
1858 | } |
1859 | return true; |
1860 | |
1861 | case OPT_mprefetchwt1: |
1862 | if (value) |
1863 | { |
1864 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET; |
1865 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET; |
1866 | } |
1867 | else |
1868 | { |
1869 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET; |
1870 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET; |
1871 | } |
1872 | return true; |
1873 | |
1874 | case OPT_mclflushopt: |
1875 | if (value) |
1876 | { |
1877 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET; |
1878 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET; |
1879 | } |
1880 | else |
1881 | { |
1882 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET; |
1883 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET; |
1884 | } |
1885 | return true; |
1886 | |
1887 | case OPT_mclwb: |
1888 | if (value) |
1889 | { |
1890 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET; |
1891 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET; |
1892 | } |
1893 | else |
1894 | { |
1895 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET; |
1896 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET; |
1897 | } |
1898 | return true; |
1899 | |
1900 | case OPT_mmwaitx: |
1901 | if (value) |
1902 | { |
1903 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAITX_SET; |
1904 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_SET; |
1905 | } |
1906 | else |
1907 | { |
1908 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAITX_UNSET; |
1909 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAITX_UNSET; |
1910 | } |
1911 | return true; |
1912 | |
1913 | case OPT_mmwait: |
1914 | if (value) |
1915 | { |
1916 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_MWAIT_SET; |
1917 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_SET; |
1918 | } |
1919 | else |
1920 | { |
1921 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_MWAIT_UNSET; |
1922 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_MWAIT_UNSET; |
1923 | } |
1924 | return true; |
1925 | |
1926 | case OPT_mclzero: |
1927 | if (value) |
1928 | { |
1929 | opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_CLZERO_SET; |
1930 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_SET; |
1931 | } |
1932 | else |
1933 | { |
1934 | opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_CLZERO_UNSET; |
1935 | opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_CLZERO_UNSET; |
1936 | } |
1937 | return true; |
1938 | |
1939 | case OPT_mpku: |
1940 | if (value) |
1941 | { |
1942 | opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET; |
1943 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET; |
1944 | } |
1945 | else |
1946 | { |
1947 | opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET; |
1948 | opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET; |
1949 | } |
1950 | return true; |
1951 | |
1952 | |
1953 | case OPT_malign_loops_: |
1954 | warning_at (loc, 0, "%<-malign-loops%> is obsolete, " |
1955 | "use %<-falign-loops%>" ); |
1956 | if (value > MAX_CODE_ALIGN) |
1957 | error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d" , |
1958 | value, MAX_CODE_ALIGN); |
1959 | else |
1960 | set_malign_value (flag: &opts->x_str_align_loops, value); |
1961 | return true; |
1962 | |
1963 | case OPT_malign_jumps_: |
1964 | warning_at (loc, 0, "%<-malign-jumps%> is obsolete, " |
1965 | "use %<-falign-jumps%>" ); |
1966 | if (value > MAX_CODE_ALIGN) |
1967 | error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d" , |
1968 | value, MAX_CODE_ALIGN); |
1969 | else |
1970 | set_malign_value (flag: &opts->x_str_align_jumps, value); |
1971 | return true; |
1972 | |
1973 | case OPT_malign_functions_: |
1974 | warning_at (loc, 0, |
1975 | "%<-malign-functions%> is obsolete, " |
1976 | "use %<-falign-functions%>" ); |
1977 | if (value > MAX_CODE_ALIGN) |
1978 | error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d" , |
1979 | value, MAX_CODE_ALIGN); |
1980 | else |
1981 | set_malign_value (flag: &opts->x_str_align_functions, value); |
1982 | return true; |
1983 | |
1984 | case OPT_mbranch_cost_: |
1985 | if (value > 5) |
1986 | { |
1987 | error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5" , value); |
1988 | opts->x_ix86_branch_cost = 5; |
1989 | } |
1990 | return true; |
1991 | |
1992 | default: |
1993 | return true; |
1994 | } |
1995 | } |
1996 | |
1997 | static const struct default_options ix86_option_optimization_table[] = |
1998 | { |
1999 | /* Enable redundant extension instructions removal at -O2 and higher. */ |
2000 | { .levels: OPT_LEVELS_2_PLUS, .opt_index: OPT_free, NULL, .value: 1 }, |
2001 | /* Enable function splitting at -O2 and higher. */ |
2002 | { .levels: OPT_LEVELS_2_PLUS, .opt_index: OPT_freorder_blocks_and_partition, NULL, .value: 1 }, |
2003 | /* The STC algorithm produces the smallest code at -Os, for x86. */ |
2004 | { .levels: OPT_LEVELS_2_PLUS, .opt_index: OPT_freorder_blocks_algorithm_, NULL, |
2005 | .value: REORDER_BLOCKS_ALGORITHM_STC }, |
2006 | |
2007 | /* Turn on -funroll-loops with -munroll-only-small-loops to enable small |
2008 | loop unrolling at -O2. */ |
2009 | { .levels: OPT_LEVELS_2_PLUS_SPEED_ONLY, .opt_index: OPT_funroll_loops, NULL, .value: 1 }, |
2010 | { .levels: OPT_LEVELS_2_PLUS_SPEED_ONLY, .opt_index: OPT_munroll_only_small_loops, NULL, .value: 1 }, |
2011 | /* Turns off -frename-registers and -fweb which are enabled by |
2012 | funroll-loops. */ |
2013 | { .levels: OPT_LEVELS_ALL, .opt_index: OPT_frename_registers, NULL, .value: 0 }, |
2014 | { .levels: OPT_LEVELS_ALL, .opt_index: OPT_fweb, NULL, .value: 0 }, |
2015 | /* Turn off -fschedule-insns by default. It tends to make the |
2016 | problem with not enough registers even worse. */ |
2017 | { .levels: OPT_LEVELS_ALL, .opt_index: OPT_fschedule_insns, NULL, .value: 0 }, |
2018 | |
2019 | #ifdef SUBTARGET_OPTIMIZATION_OPTIONS |
2020 | SUBTARGET_OPTIMIZATION_OPTIONS, |
2021 | #endif |
2022 | { .levels: OPT_LEVELS_NONE, .opt_index: 0, NULL, .value: 0 } |
2023 | }; |
2024 | |
2025 | /* Implement TARGET_OPTION_INIT_STRUCT. */ |
2026 | |
2027 | static void |
2028 | ix86_option_init_struct (struct gcc_options *opts) |
2029 | { |
2030 | if (TARGET_MACHO) |
2031 | /* The Darwin libraries never set errno, so we might as well |
2032 | avoid calling them when that's the only reason we would. */ |
2033 | opts->x_flag_errno_math = 0; |
2034 | |
2035 | opts->x_flag_pcc_struct_return = 2; |
2036 | opts->x_flag_asynchronous_unwind_tables = 2; |
2037 | } |
2038 | |
2039 | /* On the x86 -fsplit-stack and -fstack-protector both use the same |
2040 | field in the TCB, so they cannot be used together. */ |
2041 | |
2042 | static bool |
2043 | ix86_supports_split_stack (bool report, |
2044 | struct gcc_options *opts ATTRIBUTE_UNUSED) |
2045 | { |
2046 | #if defined(TARGET_THREAD_SPLIT_STACK_OFFSET) && defined(OPTION_GLIBC_P) |
2047 | if (!OPTION_GLIBC_P (opts)) |
2048 | #endif |
2049 | { |
2050 | if (report) |
2051 | error ("%<-fsplit-stack%> currently only supported on GNU/Linux" ); |
2052 | return false; |
2053 | } |
2054 | |
2055 | bool ret = true; |
2056 | |
2057 | #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET |
2058 | if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) |
2059 | { |
2060 | if (report) |
2061 | error ("%<-fsplit-stack%> requires " |
2062 | "assembler support for CFI directives" ); |
2063 | ret = false; |
2064 | } |
2065 | #endif |
2066 | |
2067 | return ret; |
2068 | } |
2069 | |
2070 | /* Implement TARGET_EXCEPT_UNWIND_INFO. */ |
2071 | |
2072 | static enum unwind_info_type |
2073 | i386_except_unwind_info (struct gcc_options *opts) |
2074 | { |
2075 | /* Honor the --enable-sjlj-exceptions configure switch. */ |
2076 | #ifdef CONFIG_SJLJ_EXCEPTIONS |
2077 | if (CONFIG_SJLJ_EXCEPTIONS) |
2078 | return UI_SJLJ; |
2079 | #endif |
2080 | |
2081 | /* On windows 64, prefer SEH exceptions over anything else. */ |
2082 | if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables) |
2083 | return UI_SEH; |
2084 | |
2085 | if (DWARF2_UNWIND_INFO) |
2086 | return UI_DWARF2; |
2087 | |
2088 | return UI_SJLJ; |
2089 | } |
2090 | |
2091 | #undef TARGET_EXCEPT_UNWIND_INFO |
2092 | #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info |
2093 | |
2094 | #undef TARGET_DEFAULT_TARGET_FLAGS |
2095 | #define TARGET_DEFAULT_TARGET_FLAGS \ |
2096 | (TARGET_DEFAULT \ |
2097 | | TARGET_SUBTARGET_DEFAULT \ |
2098 | | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) |
2099 | |
2100 | #undef TARGET_HANDLE_OPTION |
2101 | #define TARGET_HANDLE_OPTION ix86_handle_option |
2102 | |
2103 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
2104 | #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table |
2105 | #undef TARGET_OPTION_INIT_STRUCT |
2106 | #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct |
2107 | |
2108 | #undef TARGET_SUPPORTS_SPLIT_STACK |
2109 | #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack |
2110 | |
2111 | /* This table must be in sync with enum processor_type in i386.h. */ |
2112 | const char *const processor_names[] = |
2113 | { |
2114 | "generic" , |
2115 | "i386" , |
2116 | "i486" , |
2117 | "pentium" , |
2118 | "lakemont" , |
2119 | "pentiumpro" , |
2120 | "pentium4" , |
2121 | "nocona" , |
2122 | "core2" , |
2123 | "nehalem" , |
2124 | "sandybridge" , |
2125 | "haswell" , |
2126 | "bonnell" , |
2127 | "silvermont" , |
2128 | "goldmont" , |
2129 | "goldmont-plus" , |
2130 | "tremont" , |
2131 | "sierraforest" , |
2132 | "grandridge" , |
2133 | "clearwaterforest" , |
2134 | "knl" , |
2135 | "knm" , |
2136 | "skylake" , |
2137 | "skylake-avx512" , |
2138 | "cannonlake" , |
2139 | "icelake-client" , |
2140 | "icelake-server" , |
2141 | "cascadelake" , |
2142 | "tigerlake" , |
2143 | "cooperlake" , |
2144 | "sapphirerapids" , |
2145 | "alderlake" , |
2146 | "rocketlake" , |
2147 | "graniterapids" , |
2148 | "graniterapids-d" , |
2149 | "arrowlake" , |
2150 | "arrowlake-s" , |
2151 | "pantherlake" , |
2152 | "intel" , |
2153 | "lujiazui" , |
2154 | "yongfeng" , |
2155 | "geode" , |
2156 | "k6" , |
2157 | "athlon" , |
2158 | "k8" , |
2159 | "amdfam10" , |
2160 | "bdver1" , |
2161 | "bdver2" , |
2162 | "bdver3" , |
2163 | "bdver4" , |
2164 | "btver1" , |
2165 | "btver2" , |
2166 | "znver1" , |
2167 | "znver2" , |
2168 | "znver3" , |
2169 | "znver4" , |
2170 | "znver5" |
2171 | }; |
2172 | |
2173 | /* Guarantee that the array is aligned with enum processor_type. */ |
2174 | STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max); |
2175 | |
2176 | const pta processor_alias_table[] = |
2177 | { |
2178 | {.name: "i386" , .processor: PROCESSOR_I386, .schedule: CPU_NONE, .flags: 0, .model: 0, .priority: P_NONE}, |
2179 | {.name: "i486" , .processor: PROCESSOR_I486, .schedule: CPU_NONE, .flags: 0, .model: 0, .priority: P_NONE}, |
2180 | {.name: "i586" , .processor: PROCESSOR_PENTIUM, .schedule: CPU_PENTIUM, .flags: 0, .model: 0, .priority: P_NONE}, |
2181 | {.name: "pentium" , .processor: PROCESSOR_PENTIUM, .schedule: CPU_PENTIUM, .flags: 0, .model: 0, .priority: P_NONE}, |
2182 | {.name: "lakemont" , .processor: PROCESSOR_LAKEMONT, .schedule: CPU_PENTIUM, .flags: PTA_NO_80387, |
2183 | .model: 0, .priority: P_NONE}, |
2184 | {.name: "pentium-mmx" , .processor: PROCESSOR_PENTIUM, .schedule: CPU_PENTIUM, .flags: PTA_MMX, .model: 0, .priority: P_NONE}, |
2185 | {.name: "winchip-c6" , .processor: PROCESSOR_I486, .schedule: CPU_NONE, .flags: PTA_MMX, .model: 0, .priority: P_NONE}, |
2186 | {.name: "winchip2" , .processor: PROCESSOR_I486, .schedule: CPU_NONE, .flags: PTA_MMX | PTA_3DNOW, |
2187 | .model: 0, .priority: P_NONE}, |
2188 | {.name: "c3" , .processor: PROCESSOR_I486, .schedule: CPU_NONE, .flags: PTA_MMX | PTA_3DNOW, .model: 0, .priority: P_NONE}, |
2189 | {.name: "samuel-2" , .processor: PROCESSOR_I486, .schedule: CPU_NONE, .flags: PTA_MMX | PTA_3DNOW, |
2190 | .model: 0, .priority: P_NONE}, |
2191 | {.name: "c3-2" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2192 | .flags: PTA_MMX | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2193 | {.name: "nehemiah" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2194 | .flags: PTA_MMX | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2195 | {.name: "c7" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2196 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2197 | {.name: "esther" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2198 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2199 | {.name: "i686" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, .flags: 0, .model: 0, .priority: P_NONE}, |
2200 | {.name: "pentiumpro" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, .flags: 0, .model: 0, .priority: P_NONE}, |
2201 | {.name: "pentium2" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, .flags: PTA_MMX | PTA_FXSR, |
2202 | .model: 0, .priority: P_NONE}, |
2203 | {.name: "pentium3" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2204 | .flags: PTA_MMX | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2205 | {.name: "pentium3m" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2206 | .flags: PTA_MMX | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2207 | {.name: "pentium-m" , .processor: PROCESSOR_PENTIUMPRO, .schedule: CPU_PENTIUMPRO, |
2208 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2209 | {.name: "pentium4" , .processor: PROCESSOR_PENTIUM4, .schedule: CPU_NONE, |
2210 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2211 | {.name: "pentium4m" , .processor: PROCESSOR_PENTIUM4, .schedule: CPU_NONE, |
2212 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2213 | {.name: "prescott" , .processor: PROCESSOR_NOCONA, .schedule: CPU_NONE, |
2214 | .flags: PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2215 | {.name: "nocona" , .processor: PROCESSOR_NOCONA, .schedule: CPU_NONE, |
2216 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2217 | | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2218 | {.name: "core2" , .processor: PROCESSOR_CORE2, .schedule: CPU_CORE2, .flags: PTA_CORE2, |
2219 | M_CPU_TYPE (INTEL_CORE2), .priority: P_PROC_SSSE3}, |
2220 | {.name: "nehalem" , .processor: PROCESSOR_NEHALEM, .schedule: CPU_NEHALEM, .flags: PTA_NEHALEM, |
2221 | M_CPU_SUBTYPE (INTEL_COREI7_NEHALEM), .priority: P_PROC_DYNAMIC}, |
2222 | {.name: "corei7" , .processor: PROCESSOR_NEHALEM, .schedule: CPU_NEHALEM, .flags: PTA_NEHALEM, |
2223 | M_CPU_TYPE (INTEL_COREI7), .priority: P_PROC_DYNAMIC}, |
2224 | {.name: "westmere" , .processor: PROCESSOR_NEHALEM, .schedule: CPU_NEHALEM, .flags: PTA_WESTMERE, |
2225 | M_CPU_SUBTYPE (INTEL_COREI7_WESTMERE), .priority: P_PROC_DYNAMIC}, |
2226 | {.name: "sandybridge" , .processor: PROCESSOR_SANDYBRIDGE, .schedule: CPU_NEHALEM, |
2227 | .flags: PTA_SANDYBRIDGE, |
2228 | M_CPU_SUBTYPE (INTEL_COREI7_SANDYBRIDGE), .priority: P_PROC_DYNAMIC}, |
2229 | {.name: "corei7-avx" , .processor: PROCESSOR_SANDYBRIDGE, .schedule: CPU_NEHALEM, |
2230 | .flags: PTA_SANDYBRIDGE, .model: 0, .priority: P_PROC_DYNAMIC}, |
2231 | {.name: "ivybridge" , .processor: PROCESSOR_SANDYBRIDGE, .schedule: CPU_NEHALEM, |
2232 | .flags: PTA_IVYBRIDGE, |
2233 | M_CPU_SUBTYPE (INTEL_COREI7_IVYBRIDGE), .priority: P_PROC_DYNAMIC}, |
2234 | {.name: "core-avx-i" , .processor: PROCESSOR_SANDYBRIDGE, .schedule: CPU_NEHALEM, |
2235 | .flags: PTA_IVYBRIDGE, .model: 0, .priority: P_PROC_DYNAMIC}, |
2236 | {.name: "haswell" , .processor: PROCESSOR_HASWELL, .schedule: CPU_HASWELL, .flags: PTA_HASWELL, |
2237 | M_CPU_SUBTYPE (INTEL_COREI7_HASWELL), .priority: P_PROC_DYNAMIC}, |
2238 | {.name: "core-avx2" , .processor: PROCESSOR_HASWELL, .schedule: CPU_HASWELL, .flags: PTA_HASWELL, |
2239 | .model: 0, .priority: P_PROC_DYNAMIC}, |
2240 | {.name: "broadwell" , .processor: PROCESSOR_HASWELL, .schedule: CPU_HASWELL, .flags: PTA_BROADWELL, |
2241 | M_CPU_SUBTYPE (INTEL_COREI7_BROADWELL), .priority: P_PROC_DYNAMIC}, |
2242 | {.name: "skylake" , .processor: PROCESSOR_SKYLAKE, .schedule: CPU_HASWELL, .flags: PTA_SKYLAKE, |
2243 | M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE), .priority: P_PROC_AVX2}, |
2244 | {.name: "skylake-avx512" , .processor: PROCESSOR_SKYLAKE_AVX512, .schedule: CPU_HASWELL, |
2245 | .flags: PTA_SKYLAKE_AVX512, |
2246 | M_CPU_SUBTYPE (INTEL_COREI7_SKYLAKE_AVX512), .priority: P_PROC_AVX512F}, |
2247 | {.name: "cannonlake" , .processor: PROCESSOR_CANNONLAKE, .schedule: CPU_HASWELL, .flags: PTA_CANNONLAKE, |
2248 | M_CPU_SUBTYPE (INTEL_COREI7_CANNONLAKE), .priority: P_PROC_AVX512F}, |
2249 | {.name: "icelake-client" , .processor: PROCESSOR_ICELAKE_CLIENT, .schedule: CPU_HASWELL, |
2250 | .flags: PTA_ICELAKE_CLIENT, |
2251 | M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_CLIENT), .priority: P_PROC_AVX512F}, |
2252 | {.name: "rocketlake" , .processor: PROCESSOR_ROCKETLAKE, .schedule: CPU_HASWELL, |
2253 | .flags: PTA_ROCKETLAKE, |
2254 | M_CPU_SUBTYPE (INTEL_COREI7_ROCKETLAKE), .priority: P_PROC_AVX512F}, |
2255 | {.name: "icelake-server" , .processor: PROCESSOR_ICELAKE_SERVER, .schedule: CPU_HASWELL, |
2256 | .flags: PTA_ICELAKE_SERVER, |
2257 | M_CPU_SUBTYPE (INTEL_COREI7_ICELAKE_SERVER), .priority: P_PROC_AVX512F}, |
2258 | {.name: "cascadelake" , .processor: PROCESSOR_CASCADELAKE, .schedule: CPU_HASWELL, |
2259 | .flags: PTA_CASCADELAKE, |
2260 | M_CPU_SUBTYPE (INTEL_COREI7_CASCADELAKE), .priority: P_PROC_AVX512F}, |
2261 | {.name: "tigerlake" , .processor: PROCESSOR_TIGERLAKE, .schedule: CPU_HASWELL, .flags: PTA_TIGERLAKE, |
2262 | M_CPU_SUBTYPE (INTEL_COREI7_TIGERLAKE), .priority: P_PROC_AVX512F}, |
2263 | {.name: "cooperlake" , .processor: PROCESSOR_COOPERLAKE, .schedule: CPU_HASWELL, .flags: PTA_COOPERLAKE, |
2264 | M_CPU_SUBTYPE (INTEL_COREI7_COOPERLAKE), .priority: P_PROC_AVX512F}, |
2265 | {.name: "sapphirerapids" , .processor: PROCESSOR_SAPPHIRERAPIDS, .schedule: CPU_HASWELL, .flags: PTA_SAPPHIRERAPIDS, |
2266 | M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), .priority: P_PROC_AVX512F}, |
2267 | {.name: "emeraldrapids" , .processor: PROCESSOR_SAPPHIRERAPIDS, .schedule: CPU_HASWELL, .flags: PTA_SAPPHIRERAPIDS, |
2268 | M_CPU_SUBTYPE (INTEL_COREI7_SAPPHIRERAPIDS), .priority: P_PROC_AVX512F}, |
2269 | {.name: "alderlake" , .processor: PROCESSOR_ALDERLAKE, .schedule: CPU_HASWELL, .flags: PTA_ALDERLAKE, |
2270 | M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), .priority: P_PROC_AVX2}, |
2271 | {.name: "raptorlake" , .processor: PROCESSOR_ALDERLAKE, .schedule: CPU_HASWELL, .flags: PTA_ALDERLAKE, |
2272 | M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), .priority: P_PROC_AVX2}, |
2273 | {.name: "meteorlake" , .processor: PROCESSOR_ALDERLAKE, .schedule: CPU_HASWELL, .flags: PTA_ALDERLAKE, |
2274 | M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), .priority: P_PROC_AVX2}, |
2275 | {.name: "graniterapids" , .processor: PROCESSOR_GRANITERAPIDS, .schedule: CPU_HASWELL, .flags: PTA_GRANITERAPIDS, |
2276 | M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), .priority: P_PROC_AVX512F}, |
2277 | {.name: "graniterapids-d" , .processor: PROCESSOR_GRANITERAPIDS_D, .schedule: CPU_HASWELL, |
2278 | .flags: PTA_GRANITERAPIDS_D, M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS_D), |
2279 | .priority: P_PROC_AVX512F}, |
2280 | {.name: "arrowlake" , .processor: PROCESSOR_ARROWLAKE, .schedule: CPU_HASWELL, .flags: PTA_ARROWLAKE, |
2281 | M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE), .priority: P_PROC_AVX2}, |
2282 | {.name: "arrowlake-s" , .processor: PROCESSOR_ARROWLAKE_S, .schedule: CPU_HASWELL, .flags: PTA_ARROWLAKE_S, |
2283 | M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), .priority: P_PROC_AVX2}, |
2284 | {.name: "lunarlake" , .processor: PROCESSOR_ARROWLAKE_S, .schedule: CPU_HASWELL, .flags: PTA_ARROWLAKE_S, |
2285 | M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), .priority: P_PROC_AVX2}, |
2286 | {.name: "pantherlake" , .processor: PROCESSOR_PANTHERLAKE, .schedule: CPU_HASWELL, .flags: PTA_PANTHERLAKE, |
2287 | M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), .priority: P_PROC_AVX2}, |
2288 | {.name: "bonnell" , .processor: PROCESSOR_BONNELL, .schedule: CPU_ATOM, .flags: PTA_BONNELL, |
2289 | M_CPU_TYPE (INTEL_BONNELL), .priority: P_PROC_SSSE3}, |
2290 | {.name: "atom" , .processor: PROCESSOR_BONNELL, .schedule: CPU_ATOM, .flags: PTA_BONNELL, |
2291 | M_CPU_TYPE (INTEL_BONNELL), .priority: P_PROC_SSSE3}, |
2292 | {.name: "silvermont" , .processor: PROCESSOR_SILVERMONT, .schedule: CPU_SLM, .flags: PTA_SILVERMONT, |
2293 | M_CPU_TYPE (INTEL_SILVERMONT), .priority: P_PROC_SSE4_2}, |
2294 | {.name: "slm" , .processor: PROCESSOR_SILVERMONT, .schedule: CPU_SLM, .flags: PTA_SILVERMONT, |
2295 | M_CPU_TYPE (INTEL_SILVERMONT), .priority: P_PROC_SSE4_2}, |
2296 | {.name: "goldmont" , .processor: PROCESSOR_GOLDMONT, .schedule: CPU_GLM, .flags: PTA_GOLDMONT, |
2297 | M_CPU_TYPE (INTEL_GOLDMONT), .priority: P_PROC_SSE4_2}, |
2298 | {.name: "goldmont-plus" , .processor: PROCESSOR_GOLDMONT_PLUS, .schedule: CPU_GLM, .flags: PTA_GOLDMONT_PLUS, |
2299 | M_CPU_TYPE (INTEL_GOLDMONT_PLUS), .priority: P_PROC_SSE4_2}, |
2300 | {.name: "tremont" , .processor: PROCESSOR_TREMONT, .schedule: CPU_HASWELL, .flags: PTA_TREMONT, |
2301 | M_CPU_TYPE (INTEL_TREMONT), .priority: P_PROC_SSE4_2}, |
2302 | {.name: "gracemont" , .processor: PROCESSOR_ALDERLAKE, .schedule: CPU_HASWELL, .flags: PTA_ALDERLAKE, |
2303 | M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), .priority: P_PROC_AVX2}, |
2304 | {.name: "sierraforest" , .processor: PROCESSOR_SIERRAFOREST, .schedule: CPU_HASWELL, .flags: PTA_SIERRAFOREST, |
2305 | M_CPU_TYPE (INTEL_SIERRAFOREST), .priority: P_PROC_AVX2}, |
2306 | {.name: "grandridge" , .processor: PROCESSOR_GRANDRIDGE, .schedule: CPU_HASWELL, .flags: PTA_GRANDRIDGE, |
2307 | M_CPU_TYPE (INTEL_GRANDRIDGE), .priority: P_PROC_AVX2}, |
2308 | {.name: "clearwaterforest" , .processor: PROCESSOR_CLEARWATERFOREST, .schedule: CPU_HASWELL, |
2309 | .flags: PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), .priority: P_PROC_AVX2}, |
2310 | {.name: "knl" , .processor: PROCESSOR_KNL, .schedule: CPU_SLM, .flags: PTA_KNL, |
2311 | M_CPU_TYPE (INTEL_KNL), .priority: P_PROC_AVX512F}, |
2312 | {.name: "knm" , .processor: PROCESSOR_KNM, .schedule: CPU_SLM, .flags: PTA_KNM, |
2313 | M_CPU_TYPE (INTEL_KNM), .priority: P_PROC_AVX512F}, |
2314 | {.name: "intel" , .processor: PROCESSOR_INTEL, .schedule: CPU_SLM, .flags: PTA_NEHALEM, |
2315 | M_VENDOR (VENDOR_INTEL), .priority: P_NONE}, |
2316 | {.name: "geode" , .processor: PROCESSOR_GEODE, .schedule: CPU_GEODE, |
2317 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, .model: 0, .priority: P_NONE}, |
2318 | {.name: "k6" , .processor: PROCESSOR_K6, .schedule: CPU_K6, .flags: PTA_MMX, .model: 0, .priority: P_NONE}, |
2319 | {.name: "k6-2" , .processor: PROCESSOR_K6, .schedule: CPU_K6, .flags: PTA_MMX | PTA_3DNOW, .model: 0, .priority: P_NONE}, |
2320 | {.name: "k6-3" , .processor: PROCESSOR_K6, .schedule: CPU_K6, .flags: PTA_MMX | PTA_3DNOW, .model: 0, .priority: P_NONE}, |
2321 | {.name: "athlon" , .processor: PROCESSOR_ATHLON, .schedule: CPU_ATHLON, |
2322 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, .model: 0, .priority: P_NONE}, |
2323 | {.name: "athlon-tbird" , .processor: PROCESSOR_ATHLON, .schedule: CPU_ATHLON, |
2324 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, .model: 0, .priority: P_NONE}, |
2325 | {.name: "athlon-4" , .processor: PROCESSOR_ATHLON, .schedule: CPU_ATHLON, |
2326 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2327 | {.name: "athlon-xp" , .processor: PROCESSOR_ATHLON, .schedule: CPU_ATHLON, |
2328 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2329 | {.name: "athlon-mp" , .processor: PROCESSOR_ATHLON, .schedule: CPU_ATHLON, |
2330 | .flags: PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2331 | {.name: "x86-64" , .processor: PROCESSOR_K8, .schedule: CPU_K8, .flags: PTA_X86_64_BASELINE, .model: 0, .priority: P_NONE}, |
2332 | {.name: "x86-64-v2" , .processor: PROCESSOR_K8, .schedule: CPU_GENERIC, .flags: PTA_X86_64_V2 | PTA_NO_TUNE, |
2333 | .model: 0, .priority: P_NONE}, |
2334 | {.name: "x86-64-v3" , .processor: PROCESSOR_K8, .schedule: CPU_GENERIC, .flags: PTA_X86_64_V3 | PTA_NO_TUNE, |
2335 | .model: 0, .priority: P_NONE}, |
2336 | {.name: "x86-64-v4" , .processor: PROCESSOR_K8, .schedule: CPU_GENERIC, .flags: PTA_X86_64_V4 | PTA_NO_TUNE, |
2337 | .model: 0, .priority: P_NONE}, |
2338 | {.name: "eden-x2" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2339 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, |
2340 | .model: 0, .priority: P_NONE}, |
2341 | {.name: "nano" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2342 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2343 | | PTA_SSSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2344 | {.name: "nano-1000" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2345 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2346 | | PTA_SSSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2347 | {.name: "nano-2000" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2348 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2349 | | PTA_SSSE3 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2350 | {.name: "nano-3000" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2351 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2352 | | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2353 | {.name: "nano-x2" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2354 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2355 | | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2356 | {.name: "eden-x4" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2357 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2358 | | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2359 | {.name: "nano-x4" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2360 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2361 | | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2362 | {.name: "lujiazui" , .processor: PROCESSOR_LUJIAZUI, .schedule: CPU_LUJIAZUI, |
2363 | .flags: PTA_LUJIAZUI, |
2364 | M_CPU_SUBTYPE (ZHAOXIN_FAM7H_LUJIAZUI), .priority: P_NONE}, |
2365 | {.name: "yongfeng" , .processor: PROCESSOR_YONGFENG, .schedule: CPU_YONGFENG, |
2366 | .flags: PTA_YONGFENG, |
2367 | M_CPU_SUBTYPE (ZHAOXIN_FAM7H_YONGFENG), .priority: P_NONE}, |
2368 | {.name: "k8" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2369 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2370 | | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2371 | {.name: "k8-sse3" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2372 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2373 | | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2374 | {.name: "opteron" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2375 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2376 | | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2377 | {.name: "opteron-sse3" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2378 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2379 | | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2380 | {.name: "athlon64" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2381 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2382 | | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2383 | {.name: "athlon64-sse3" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2384 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2385 | | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2386 | {.name: "athlon-fx" , .processor: PROCESSOR_K8, .schedule: CPU_K8, |
2387 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE |
2388 | | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, .model: 0, .priority: P_NONE}, |
2389 | {.name: "amdfam10" , .processor: PROCESSOR_AMDFAM10, .schedule: CPU_AMDFAM10, |
2390 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 |
2391 | | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR, |
2392 | .model: 0, .priority: P_PROC_DYNAMIC}, |
2393 | {.name: "barcelona" , .processor: PROCESSOR_AMDFAM10, .schedule: CPU_AMDFAM10, |
2394 | .flags: PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2 |
2395 | | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR, |
2396 | M_CPU_SUBTYPE (AMDFAM10H_BARCELONA), .priority: P_PROC_DYNAMIC}, |
2397 | {.name: "bdver1" , .processor: PROCESSOR_BDVER1, .schedule: CPU_BDVER1, |
2398 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2399 | | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 |
2400 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4 |
2401 | | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE, |
2402 | M_CPU_TYPE (AMDFAM15H_BDVER1), .priority: P_PROC_XOP}, |
2403 | {.name: "bdver2" , .processor: PROCESSOR_BDVER2, .schedule: CPU_BDVER2, |
2404 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2405 | | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 |
2406 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4 |
2407 | | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C |
2408 | | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE, |
2409 | M_CPU_TYPE (AMDFAM15H_BDVER2), .priority: P_PROC_FMA}, |
2410 | {.name: "bdver3" , .processor: PROCESSOR_BDVER3, .schedule: CPU_BDVER3, |
2411 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2412 | | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 |
2413 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4 |
2414 | | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C |
2415 | | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE |
2416 | | PTA_XSAVEOPT | PTA_FSGSBASE, |
2417 | M_CPU_SUBTYPE (AMDFAM15H_BDVER3), .priority: P_PROC_FMA}, |
2418 | {.name: "bdver4" , .processor: PROCESSOR_BDVER4, .schedule: CPU_BDVER4, |
2419 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2420 | | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 |
2421 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 |
2422 | | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 |
2423 | | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR |
2424 | | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND |
2425 | | PTA_MOVBE | PTA_MWAITX, |
2426 | M_CPU_SUBTYPE (AMDFAM15H_BDVER4), .priority: P_PROC_AVX2}, |
2427 | {.name: "znver1" , .processor: PROCESSOR_ZNVER1, .schedule: CPU_ZNVER1, |
2428 | .flags: PTA_ZNVER1, |
2429 | M_CPU_SUBTYPE (AMDFAM17H_ZNVER1), .priority: P_PROC_AVX2}, |
2430 | {.name: "znver2" , .processor: PROCESSOR_ZNVER2, .schedule: CPU_ZNVER2, |
2431 | .flags: PTA_ZNVER2, |
2432 | M_CPU_SUBTYPE (AMDFAM17H_ZNVER2), .priority: P_PROC_AVX2}, |
2433 | {.name: "znver3" , .processor: PROCESSOR_ZNVER3, .schedule: CPU_ZNVER3, |
2434 | .flags: PTA_ZNVER3, |
2435 | M_CPU_SUBTYPE (AMDFAM19H_ZNVER3), .priority: P_PROC_AVX2}, |
2436 | {.name: "znver4" , .processor: PROCESSOR_ZNVER4, .schedule: CPU_ZNVER4, |
2437 | .flags: PTA_ZNVER4, |
2438 | M_CPU_SUBTYPE (AMDFAM19H_ZNVER4), .priority: P_PROC_AVX512F}, |
2439 | {.name: "znver5" , .processor: PROCESSOR_ZNVER5, .schedule: CPU_ZNVER5, |
2440 | .flags: PTA_ZNVER5, |
2441 | M_CPU_SUBTYPE (AMDFAM1AH_ZNVER5), .priority: P_PROC_AVX512F}, |
2442 | {.name: "btver1" , .processor: PROCESSOR_BTVER1, .schedule: CPU_GENERIC, |
2443 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2444 | | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_PRFCHW |
2445 | | PTA_FXSR | PTA_XSAVE, |
2446 | M_CPU_SUBTYPE (AMDFAM15H_BDVER1), .priority: P_PROC_SSE4_A}, |
2447 | {.name: "btver2" , .processor: PROCESSOR_BTVER2, .schedule: CPU_BTVER2, |
2448 | .flags: PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 |
2449 | | PTA_SSSE3 | PTA_SSE4A | PTA_ABM | PTA_CX16 | PTA_SSE4_1 |
2450 | | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX |
2451 | | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW |
2452 | | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT, |
2453 | M_CPU_TYPE (AMD_BTVER2), .priority: P_PROC_BMI}, |
2454 | |
2455 | {.name: "generic" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, |
2456 | .flags: PTA_64BIT |
2457 | | PTA_HLE /* flags are only used for -march switch. */, |
2458 | .model: 0, .priority: P_NONE}, |
2459 | |
2460 | {.name: "amd" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2461 | M_VENDOR (VENDOR_AMD), .priority: P_NONE}, |
2462 | {.name: "amdfam10h" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2463 | M_CPU_TYPE (AMDFAM10H), .priority: P_NONE}, |
2464 | {.name: "amdfam15h" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2465 | M_CPU_TYPE (AMDFAM15H), .priority: P_NONE}, |
2466 | {.name: "amdfam17h" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2467 | M_CPU_TYPE (AMDFAM17H), .priority: P_NONE}, |
2468 | {.name: "amdfam19h" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2469 | M_CPU_TYPE (AMDFAM19H), .priority: P_NONE}, |
2470 | {.name: "shanghai" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2471 | M_CPU_TYPE (AMDFAM10H_SHANGHAI), .priority: P_NONE}, |
2472 | {.name: "istanbul" , .processor: PROCESSOR_GENERIC, .schedule: CPU_GENERIC, .flags: 0, |
2473 | M_CPU_TYPE (AMDFAM10H_ISTANBUL), .priority: P_NONE}, |
2474 | }; |
2475 | |
2476 | /* NB: processor_alias_table stops at the "generic" entry. */ |
2477 | unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7; |
2478 | unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table); |
2479 | |
2480 | /* Provide valid option values for -march and -mtune options. */ |
2481 | |
2482 | vec<const char *> |
2483 | ix86_get_valid_option_values (int option_code, |
2484 | const char *prefix ATTRIBUTE_UNUSED) |
2485 | { |
2486 | vec<const char *> v; |
2487 | v.create (nelems: 0); |
2488 | opt_code opt = (opt_code) option_code; |
2489 | |
2490 | switch (opt) |
2491 | { |
2492 | case OPT_march_: |
2493 | for (unsigned i = 0; i < pta_size; i++) |
2494 | { |
2495 | const char *name = processor_alias_table[i].name; |
2496 | gcc_checking_assert (name != NULL); |
2497 | v.safe_push (obj: name); |
2498 | } |
2499 | #ifdef HAVE_LOCAL_CPU_DETECT |
2500 | /* Add also "native" as possible value. */ |
2501 | v.safe_push (obj: "native" ); |
2502 | #endif |
2503 | |
2504 | break; |
2505 | case OPT_mtune_: |
2506 | for (unsigned i = 0; i < PROCESSOR_max; i++) |
2507 | { |
2508 | const char *name = processor_names[i]; |
2509 | gcc_checking_assert (name != NULL); |
2510 | v.safe_push (obj: name); |
2511 | } |
2512 | break; |
2513 | default: |
2514 | break; |
2515 | } |
2516 | |
2517 | return v; |
2518 | } |
2519 | |
2520 | #undef TARGET_GET_VALID_OPTION_VALUES |
2521 | #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values |
2522 | |
2523 | struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; |
2524 | |