| 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
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| 2 | /* |
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| 3 | * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk> |
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| 4 | */ |
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| 5 | #include <linux/io.h> |
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| 6 | #include <asm/smp_scu.h> |
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| 7 | #include <asm/smp.h> |
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| 8 | #include "addr-map.h" |
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| 9 | |
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| 10 | #define SW_BRANCH_VIRT_ADDR CIU_REG(0x24) |
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| 11 | |
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| 12 | static int mmp3_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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| 13 | { |
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| 14 | /* |
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| 15 | * Apparently, the boot ROM on the second core spins on this |
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| 16 | * register becoming non-zero and then jumps to the address written |
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| 17 | * there. No IPIs involved. |
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| 18 | */ |
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| 19 | __raw_writel(__pa_symbol(secondary_startup), SW_BRANCH_VIRT_ADDR); |
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| 20 | return 0; |
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| 21 | } |
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| 22 | |
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| 23 | static void mmp3_smp_prepare_cpus(unsigned int max_cpus) |
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| 24 | { |
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| 25 | scu_enable(SCU_VIRT_BASE); |
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| 26 | } |
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| 27 | |
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| 28 | static const struct smp_operations mmp3_smp_ops __initconst = { |
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| 29 | .smp_prepare_cpus = mmp3_smp_prepare_cpus, |
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| 30 | .smp_boot_secondary = mmp3_boot_secondary, |
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| 31 | }; |
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| 32 | CPU_METHOD_OF_DECLARE(mmp3_smp, "marvell,mmp3-smp" , &mmp3_smp_ops); |
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| 33 | |
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