1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | |
3 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
4 | #define __ASM_ARCH_BRIDGE_REGS_H |
5 | |
6 | #include "mv78xx0.h" |
7 | |
8 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
9 | #define L2_WRITETHROUGH 0x00020000 |
10 | |
11 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
12 | #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) |
13 | #define SOFT_RESET_OUT_EN 0x00000004 |
14 | |
15 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
16 | #define SOFT_RESET 0x00000001 |
17 | |
18 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
19 | |
20 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
21 | #define IRQ_CAUSE_ERR_OFF 0x0000 |
22 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
23 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
24 | #define IRQ_MASK_ERR_OFF 0x000c |
25 | #define IRQ_MASK_LOW_OFF 0x0010 |
26 | #define IRQ_MASK_HIGH_OFF 0x0014 |
27 | |
28 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
29 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
30 | |
31 | #endif |
32 | |