1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * linux/arch/arm/mach-omap1/clock.h |
4 | * |
5 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
6 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
7 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
8 | */ |
9 | |
10 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
11 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
12 | |
13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> |
16 | |
17 | struct module; |
18 | struct omap1_clk; |
19 | |
20 | struct omap_clk { |
21 | u16 cpu; |
22 | struct clk_lookup lk; |
23 | }; |
24 | |
25 | #define CLK(dev, con, ck, cp) \ |
26 | { \ |
27 | .cpu = cp, \ |
28 | .lk = { \ |
29 | .dev_id = dev, \ |
30 | .con_id = con, \ |
31 | .clk_hw = ck, \ |
32 | }, \ |
33 | } |
34 | |
35 | /* Platform flags for the clkdev-OMAP integration code */ |
36 | #define CK_310 (1 << 0) |
37 | #define CK_7XX (1 << 1) /* 7xx, 850 */ |
38 | #define CK_1510 (1 << 2) |
39 | #define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ |
40 | #define CK_1710 (1 << 4) /* 1710 extra for rate selection */ |
41 | |
42 | /** |
43 | * struct clkops - some clock function pointers |
44 | * @enable: fn ptr that enables the current clock in hardware |
45 | * @disable: fn ptr that enables the current clock in hardware |
46 | * @allow_idle: fn ptr that enables autoidle for the current clock in hardware |
47 | */ |
48 | struct clkops { |
49 | int (*enable)(struct omap1_clk *clk); |
50 | void (*disable)(struct omap1_clk *clk); |
51 | }; |
52 | |
53 | /* |
54 | * struct clk.flags possibilities |
55 | * |
56 | * XXX document the rest of the clock flags here |
57 | */ |
58 | #define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
59 | #define CLOCK_IDLE_CONTROL (1 << 1) |
60 | #define CLOCK_NO_IDLE_PARENT (1 << 2) |
61 | |
62 | /** |
63 | * struct omap1_clk - OMAP1 struct clk |
64 | * @hw: struct clk_hw for common clock framework integration |
65 | * @ops: struct clkops * for this clock |
66 | * @rate: current clock rate |
67 | * @enable_reg: register to write to enable the clock (see @enable_bit) |
68 | * @recalc: fn ptr that returns the clock's current rate |
69 | * @set_rate: fn ptr that can change the clock's current rate |
70 | * @round_rate: fn ptr that can round the clock's current rate |
71 | * @init: fn ptr to do clock-specific initialization |
72 | * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
73 | * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div |
74 | * @flags: see "struct clk.flags possibilities" above |
75 | * @rate_offset: bitshift for rate selection bitfield (OMAP1 only) |
76 | */ |
77 | struct omap1_clk { |
78 | struct clk_hw hw; |
79 | const struct clkops *ops; |
80 | unsigned long rate; |
81 | void __iomem *enable_reg; |
82 | unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate); |
83 | int (*set_rate)(struct omap1_clk *clk, unsigned long rate, |
84 | unsigned long p_rate); |
85 | long (*round_rate)(struct omap1_clk *clk, unsigned long rate, |
86 | unsigned long *p_rate); |
87 | int (*init)(struct omap1_clk *clk); |
88 | u8 enable_bit; |
89 | u8 fixed_div; |
90 | u8 flags; |
91 | u8 rate_offset; |
92 | }; |
93 | #define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw) |
94 | |
95 | void propagate_rate(struct omap1_clk *clk); |
96 | unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate); |
97 | unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate); |
98 | |
99 | extern struct omap1_clk dummy_ck; |
100 | |
101 | int omap1_clk_init(void); |
102 | void omap1_clk_late_init(void); |
103 | unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate); |
104 | long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); |
105 | int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); |
106 | unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate); |
107 | unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate); |
108 | int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate, |
109 | unsigned long p_rate); |
110 | long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); |
111 | int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); |
112 | unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate); |
113 | int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); |
114 | long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); |
115 | int omap1_init_ext_clk(struct omap1_clk *clk); |
116 | int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); |
117 | long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate); |
118 | int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate); |
119 | long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, |
120 | unsigned long *p_rate); |
121 | |
122 | struct uart_clk { |
123 | struct omap1_clk clk; |
124 | unsigned long sysc_addr; |
125 | }; |
126 | |
127 | /* Provide a method for preventing idling some ARM IDLECT clocks */ |
128 | struct arm_idlect1_clk { |
129 | struct omap1_clk clk; |
130 | unsigned long no_idle_count; |
131 | __u8 idlect_shift; |
132 | }; |
133 | |
134 | /* ARM_CKCTL bit shifts */ |
135 | #define CKCTL_PERDIV_OFFSET 0 |
136 | #define CKCTL_LCDDIV_OFFSET 2 |
137 | #define CKCTL_ARMDIV_OFFSET 4 |
138 | #define CKCTL_DSPDIV_OFFSET 6 |
139 | #define CKCTL_TCDIV_OFFSET 8 |
140 | #define CKCTL_DSPMMUDIV_OFFSET 10 |
141 | /*#define ARM_TIMXO 12*/ |
142 | #define EN_DSPCK 13 |
143 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ |
144 | /* DSP_CKCTL bit shifts */ |
145 | #define CKCTL_DSPPERDIV_OFFSET 0 |
146 | |
147 | /* ARM_IDLECT2 bit shifts */ |
148 | #define EN_WDTCK 0 |
149 | #define EN_XORPCK 1 |
150 | #define EN_PERCK 2 |
151 | #define EN_LCDCK 3 |
152 | #define EN_LBCK 4 /* Not on 1610/1710 */ |
153 | /*#define EN_HSABCK 5*/ |
154 | #define EN_APICK 6 |
155 | #define EN_TIMCK 7 |
156 | #define DMACK_REQ 8 |
157 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ |
158 | /*#define EN_LBFREECK 10*/ |
159 | #define EN_CKOUT_ARM 11 |
160 | |
161 | /* ARM_IDLECT3 bit shifts */ |
162 | #define EN_OCPI_CK 0 |
163 | #define EN_TC1_CK 2 |
164 | #define EN_TC2_CK 4 |
165 | |
166 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ |
167 | #define EN_DSPTIMCK 5 |
168 | |
169 | /* Various register defines for clock controls scattered around OMAP chip */ |
170 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
171 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
172 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ |
173 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ |
174 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ |
175 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 |
176 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 |
177 | #define SOFT_REQ_REG 0xfffe0834 |
178 | #define SOFT_REQ_REG2 0xfffe0880 |
179 | |
180 | extern __u32 arm_idlect1_mask; |
181 | extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; |
182 | |
183 | extern const struct clkops clkops_dspck; |
184 | extern const struct clkops clkops_uart_16xx; |
185 | extern const struct clkops clkops_generic; |
186 | |
187 | /* used for passing SoC type to omap1_{select,round_to}_table_rate() */ |
188 | extern u32 cpu_mask; |
189 | |
190 | extern const struct clk_ops omap1_clk_null_ops; |
191 | extern const struct clk_ops omap1_clk_gate_ops; |
192 | extern const struct clk_ops omap1_clk_rate_ops; |
193 | extern const struct clk_ops omap1_clk_full_ops; |
194 | |
195 | #endif |
196 | |