| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * DRA7xx PRM instance offset macros |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Generated by code originally written by: |
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| 8 | * Paul Walmsley (paul@pwsan.com) |
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| 9 | * Rajendra Nayak (rnayak@ti.com) |
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| 10 | * Benoit Cousson (b-cousson@ti.com) |
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| 11 | * |
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| 12 | * This file is automatically generated from the OMAP hardware databases. |
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| 13 | * We respectfully ask that any modifications to this file be coordinated |
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| 14 | * with the public linux-omap@vger.kernel.org mailing list and the |
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| 15 | * authors above to ensure that the autogeneration scripts are kept |
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| 16 | * up-to-date with the file contents. |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H |
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| 20 | #define __ARCH_ARM_MACH_OMAP2_PRM7XX_H |
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| 21 | |
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| 22 | #include "prcm-common.h" |
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| 23 | #include "prm44xx_54xx.h" |
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| 24 | #include "prm.h" |
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| 25 | |
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| 26 | #define DRA7XX_PRM_BASE 0x4ae06000 |
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| 27 | |
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| 28 | #define DRA7XX_PRM_REGADDR(inst, reg) \ |
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| 29 | OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) |
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| 30 | |
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| 31 | |
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| 32 | /* PRM instances */ |
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| 33 | #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 |
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| 34 | #define DRA7XX_PRM_CKGEN_INST 0x0100 |
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| 35 | #define DRA7XX_PRM_MPU_INST 0x0300 |
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| 36 | #define DRA7XX_PRM_DSP1_INST 0x0400 |
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| 37 | #define DRA7XX_PRM_IPU_INST 0x0500 |
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| 38 | #define DRA7XX_PRM_COREAON_INST 0x0628 |
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| 39 | #define DRA7XX_PRM_CORE_INST 0x0700 |
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| 40 | #define DRA7XX_PRM_IVA_INST 0x0f00 |
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| 41 | #define DRA7XX_PRM_CAM_INST 0x1000 |
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| 42 | #define DRA7XX_PRM_DSS_INST 0x1100 |
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| 43 | #define DRA7XX_PRM_GPU_INST 0x1200 |
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| 44 | #define DRA7XX_PRM_L3INIT_INST 0x1300 |
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| 45 | #define DRA7XX_PRM_L4PER_INST 0x1400 |
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| 46 | #define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 |
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| 47 | #define DRA7XX_PRM_WKUPAON_INST 0x1724 |
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| 48 | #define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 |
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| 49 | #define DRA7XX_PRM_EMU_INST 0x1900 |
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| 50 | #define DRA7XX_PRM_EMU_CM_INST 0x1a00 |
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| 51 | #define DRA7XX_PRM_DSP2_INST 0x1b00 |
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| 52 | #define DRA7XX_PRM_EVE1_INST 0x1b40 |
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| 53 | #define DRA7XX_PRM_EVE2_INST 0x1b80 |
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| 54 | #define DRA7XX_PRM_EVE3_INST 0x1bc0 |
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| 55 | #define DRA7XX_PRM_EVE4_INST 0x1c00 |
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| 56 | #define DRA7XX_PRM_RTC_INST 0x1c60 |
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| 57 | #define DRA7XX_PRM_VPE_INST 0x1c80 |
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| 58 | #define DRA7XX_PRM_DEVICE_INST 0x1d00 |
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| 59 | |
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| 60 | /* PRM clockdomain register offsets (from instance start) */ |
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| 61 | #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 |
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| 62 | #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 |
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| 63 | |
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| 64 | /* PRM.CKGEN_PRM register offsets */ |
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| 65 | #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) |
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| 66 | |
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| 67 | #endif |
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| 68 | |
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