1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * linux/arch/arm/mm/nommu.c |
4 | * |
5 | * ARM uCLinux supporting functions. |
6 | */ |
7 | #include <linux/module.h> |
8 | #include <linux/mm.h> |
9 | #include <linux/pagemap.h> |
10 | #include <linux/io.h> |
11 | #include <linux/memblock.h> |
12 | #include <linux/kernel.h> |
13 | |
14 | #include <asm/cacheflush.h> |
15 | #include <asm/cp15.h> |
16 | #include <asm/sections.h> |
17 | #include <asm/page.h> |
18 | #include <asm/setup.h> |
19 | #include <asm/traps.h> |
20 | #include <asm/mach/arch.h> |
21 | #include <asm/cputype.h> |
22 | #include <asm/mpu.h> |
23 | #include <asm/procinfo.h> |
24 | #include <asm/idmap.h> |
25 | |
26 | #include "mm.h" |
27 | |
28 | unsigned long vectors_base; |
29 | |
30 | /* |
31 | * empty_zero_page is a special page that is used for |
32 | * zero-initialized data and COW. |
33 | */ |
34 | struct page *empty_zero_page; |
35 | EXPORT_SYMBOL(empty_zero_page); |
36 | |
37 | #ifdef CONFIG_ARM_MPU |
38 | struct mpu_rgn_info mpu_rgn_info; |
39 | #endif |
40 | |
41 | #ifdef CONFIG_CPU_CP15 |
42 | #ifdef CONFIG_CPU_HIGH_VECTOR |
43 | unsigned long setup_vectors_base(void) |
44 | { |
45 | unsigned long reg = get_cr(); |
46 | |
47 | set_cr(reg | CR_V); |
48 | return 0xffff0000; |
49 | } |
50 | #else /* CONFIG_CPU_HIGH_VECTOR */ |
51 | /* Write exception base address to VBAR */ |
52 | static inline void set_vbar(unsigned long val) |
53 | { |
54 | asm("mcr p15, 0, %0, c12, c0, 0" : : "r" (val) : "cc" ); |
55 | } |
56 | |
57 | /* |
58 | * Security extensions, bits[7:4], permitted values, |
59 | * 0b0000 - not implemented, 0b0001/0b0010 - implemented |
60 | */ |
61 | static inline bool security_extensions_enabled(void) |
62 | { |
63 | /* Check CPUID Identification Scheme before ID_PFR1 read */ |
64 | if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) |
65 | return cpuid_feature_extract(CPUID_EXT_PFR1, 4) || |
66 | cpuid_feature_extract(CPUID_EXT_PFR1, 20); |
67 | return 0; |
68 | } |
69 | |
70 | unsigned long setup_vectors_base(void) |
71 | { |
72 | unsigned long base = 0, reg = get_cr(); |
73 | |
74 | set_cr(reg & ~CR_V); |
75 | if (security_extensions_enabled()) { |
76 | if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) |
77 | base = CONFIG_DRAM_BASE; |
78 | set_vbar(base); |
79 | } else if (IS_ENABLED(CONFIG_REMAP_VECTORS_TO_RAM)) { |
80 | if (CONFIG_DRAM_BASE != 0) |
81 | pr_err("Security extensions not enabled, vectors cannot be remapped to RAM, vectors base will be 0x00000000\n" ); |
82 | } |
83 | |
84 | return base; |
85 | } |
86 | #endif /* CONFIG_CPU_HIGH_VECTOR */ |
87 | #endif /* CONFIG_CPU_CP15 */ |
88 | |
89 | void __init arm_mm_memblock_reserve(void) |
90 | { |
91 | #ifndef CONFIG_CPU_V7M |
92 | vectors_base = IS_ENABLED(CONFIG_CPU_CP15) ? setup_vectors_base() : 0; |
93 | /* |
94 | * Register the exception vector page. |
95 | * some architectures which the DRAM is the exception vector to trap, |
96 | * alloc_page breaks with error, although it is not NULL, but "0." |
97 | */ |
98 | memblock_reserve(base: vectors_base, size: 2 * PAGE_SIZE); |
99 | #else /* ifndef CONFIG_CPU_V7M */ |
100 | /* |
101 | * There is no dedicated vector page on V7-M. So nothing needs to be |
102 | * reserved here. |
103 | */ |
104 | #endif |
105 | /* |
106 | * In any case, always ensure address 0 is never used as many things |
107 | * get very confused if 0 is returned as a legitimate address. |
108 | */ |
109 | memblock_reserve(base: 0, size: 1); |
110 | } |
111 | |
112 | static void __init adjust_lowmem_bounds_mpu(void) |
113 | { |
114 | unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; |
115 | |
116 | switch (pmsa) { |
117 | case MMFR0_PMSAv7: |
118 | pmsav7_adjust_lowmem_bounds(); |
119 | break; |
120 | case MMFR0_PMSAv8: |
121 | pmsav8_adjust_lowmem_bounds(); |
122 | break; |
123 | default: |
124 | break; |
125 | } |
126 | } |
127 | |
128 | static void __init mpu_setup(void) |
129 | { |
130 | unsigned long pmsa = read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA; |
131 | |
132 | switch (pmsa) { |
133 | case MMFR0_PMSAv7: |
134 | pmsav7_setup(); |
135 | break; |
136 | case MMFR0_PMSAv8: |
137 | pmsav8_setup(); |
138 | break; |
139 | default: |
140 | break; |
141 | } |
142 | } |
143 | |
144 | void __init adjust_lowmem_bounds(void) |
145 | { |
146 | phys_addr_t end; |
147 | adjust_lowmem_bounds_mpu(); |
148 | end = memblock_end_of_DRAM(); |
149 | high_memory = __va(end - 1) + 1; |
150 | memblock_set_current_limit(limit: end); |
151 | } |
152 | |
153 | /* |
154 | * paging_init() sets up the page tables, initialises the zone memory |
155 | * maps, and sets up the zero page, bad page and bad page tables. |
156 | */ |
157 | void __init paging_init(const struct machine_desc *mdesc) |
158 | { |
159 | void *zero_page; |
160 | |
161 | early_trap_init((void *)vectors_base); |
162 | mpu_setup(); |
163 | |
164 | /* allocate the zero page. */ |
165 | zero_page = (void *)memblock_alloc(PAGE_SIZE, PAGE_SIZE); |
166 | if (!zero_page) |
167 | panic(fmt: "%s: Failed to allocate %lu bytes align=0x%lx\n" , |
168 | __func__, PAGE_SIZE, PAGE_SIZE); |
169 | |
170 | bootmem_init(); |
171 | |
172 | empty_zero_page = virt_to_page(zero_page); |
173 | flush_dcache_page(page: empty_zero_page); |
174 | } |
175 | |
176 | /* |
177 | * We don't need to do anything here for nommu machines. |
178 | */ |
179 | void setup_mm_for_reboot(void) |
180 | { |
181 | } |
182 | |
183 | void flush_dcache_folio(struct folio *folio) |
184 | { |
185 | __cpuc_flush_dcache_area(folio_address(folio), folio_size(folio)); |
186 | } |
187 | EXPORT_SYMBOL(flush_dcache_folio); |
188 | |
189 | void flush_dcache_page(struct page *page) |
190 | { |
191 | __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE); |
192 | } |
193 | EXPORT_SYMBOL(flush_dcache_page); |
194 | |
195 | void copy_to_user_page(struct vm_area_struct *vma, struct page *page, |
196 | unsigned long uaddr, void *dst, const void *src, |
197 | unsigned long len) |
198 | { |
199 | memcpy(dst, src, len); |
200 | if (vma->vm_flags & VM_EXEC) |
201 | __cpuc_coherent_user_range(uaddr, uaddr + len); |
202 | } |
203 | |
204 | void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, |
205 | size_t size, unsigned int mtype) |
206 | { |
207 | if (pfn >= (0x100000000ULL >> PAGE_SHIFT)) |
208 | return NULL; |
209 | return (void __iomem *) (offset + (pfn << PAGE_SHIFT)); |
210 | } |
211 | EXPORT_SYMBOL(__arm_ioremap_pfn); |
212 | |
213 | void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, |
214 | unsigned int mtype, void *caller) |
215 | { |
216 | return (void __iomem *)phys_addr; |
217 | } |
218 | |
219 | void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); |
220 | |
221 | void __iomem *ioremap(resource_size_t res_cookie, size_t size) |
222 | { |
223 | return __arm_ioremap_caller(phys_addr: res_cookie, size, mtype: MT_DEVICE, |
224 | caller: __builtin_return_address(0)); |
225 | } |
226 | EXPORT_SYMBOL(ioremap); |
227 | |
228 | void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size) |
229 | { |
230 | return __arm_ioremap_caller(phys_addr: res_cookie, size, mtype: MT_DEVICE_CACHED, |
231 | caller: __builtin_return_address(0)); |
232 | } |
233 | EXPORT_SYMBOL(ioremap_cache); |
234 | |
235 | void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) |
236 | { |
237 | return __arm_ioremap_caller(phys_addr: res_cookie, size, mtype: MT_DEVICE_WC, |
238 | caller: __builtin_return_address(0)); |
239 | } |
240 | EXPORT_SYMBOL(ioremap_wc); |
241 | |
242 | #ifdef CONFIG_PCI |
243 | |
244 | #include <asm/mach/map.h> |
245 | |
246 | void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size) |
247 | { |
248 | return arch_ioremap_caller(res_cookie, size, MT_UNCACHED, |
249 | __builtin_return_address(0)); |
250 | } |
251 | EXPORT_SYMBOL_GPL(pci_remap_cfgspace); |
252 | #endif |
253 | |
254 | void *arch_memremap_wb(phys_addr_t phys_addr, size_t size) |
255 | { |
256 | return (void *)phys_addr; |
257 | } |
258 | |
259 | void iounmap(volatile void __iomem *io_addr) |
260 | { |
261 | } |
262 | EXPORT_SYMBOL(iounmap); |
263 | |