| 1 | /* |
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| 2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> |
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| 3 | * Copyright (C) 2007-2009 PetaLogix |
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| 4 | * Copyright (C) 2006 Atmark Techno, Inc. |
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| 5 | * |
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| 6 | * MMU code derived from arch/ppc/kernel/head_4xx.S: |
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| 7 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> |
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| 8 | * Initial PowerPC version. |
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| 9 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
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| 10 | * Rewritten for PReP |
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| 11 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
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| 12 | * Low-level exception handers, MMU support, and rewrite. |
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| 13 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
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| 14 | * PowerPC 8xx modifications. |
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| 15 | * Copyright (c) 1998-1999 TiVo, Inc. |
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| 16 | * PowerPC 403GCX modifications. |
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| 17 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
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| 18 | * PowerPC 403GCX/405GP modifications. |
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| 19 | * Copyright 2000 MontaVista Software Inc. |
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| 20 | * PPC405 modifications |
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| 21 | * PowerPC 403GCX/405GP modifications. |
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| 22 | * Author: MontaVista Software, Inc. |
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| 23 | * frank_rowand@mvista.com or source@mvista.com |
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| 24 | * debbie_chu@mvista.com |
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| 25 | * |
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| 26 | * This file is subject to the terms and conditions of the GNU General Public |
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| 27 | * License. See the file "COPYING" in the main directory of this archive |
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| 28 | * for more details. |
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| 29 | */ |
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| 30 | |
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| 31 | #include <linux/init.h> |
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| 32 | #include <linux/linkage.h> |
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| 33 | #include <asm/thread_info.h> |
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| 34 | #include <asm/page.h> |
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| 35 | #include <linux/of_fdt.h> /* for OF_DT_HEADER */ |
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| 36 | |
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| 37 | #include <asm/setup.h> /* COMMAND_LINE_SIZE */ |
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| 38 | #include <asm/mmu.h> |
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| 39 | #include <asm/processor.h> |
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| 40 | |
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| 41 | .section .data |
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| 42 | .global empty_zero_page |
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| 43 | .align 12 |
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| 44 | empty_zero_page: |
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| 45 | .space PAGE_SIZE |
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| 46 | .global swapper_pg_dir |
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| 47 | swapper_pg_dir: |
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| 48 | .space PAGE_SIZE |
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| 49 | |
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| 50 | .section .rodata |
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| 51 | .align 4 |
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| 52 | endian_check: |
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| 53 | .word 1 |
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| 54 | |
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| 55 | __HEAD |
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| 56 | ENTRY(_start) |
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| 57 | #if CONFIG_KERNEL_BASE_ADDR == 0 |
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| 58 | brai TOPHYS(real_start) |
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| 59 | .org 0x100 |
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| 60 | real_start: |
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| 61 | #endif |
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| 62 | |
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| 63 | mts rmsr, r0 |
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| 64 | /* Disable stack protection from bootloader */ |
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| 65 | mts rslr, r0 |
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| 66 | addi r8, r0, 0xFFFFFFFF |
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| 67 | mts rshr, r8 |
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| 68 | /* |
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| 69 | * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' |
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| 70 | * if the msrclr instruction is not enabled. We use this to detect |
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| 71 | * if the opcode is available, by issuing msrclr and then testing the result. |
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| 72 | * r8 == 0 - msr instructions are implemented |
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| 73 | * r8 != 0 - msr instructions are not implemented |
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| 74 | */ |
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| 75 | mfs r1, rmsr |
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| 76 | msrclr r8, 0 /* clear nothing - just read msr for test */ |
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| 77 | cmpu r8, r8, r1 /* r1 must contain msr reg content */ |
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| 78 | |
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| 79 | /* r7 may point to an FDT, or there may be one linked in. |
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| 80 | if it's in r7, we've got to save it away ASAP. |
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| 81 | We ensure r7 points to a valid FDT, just in case the bootloader |
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| 82 | is broken or non-existent */ |
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| 83 | beqi r7, no_fdt_arg /* NULL pointer? don't copy */ |
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| 84 | /* Does r7 point to a valid FDT? Load HEADER magic number */ |
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| 85 | /* Run time Big/Little endian platform */ |
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| 86 | /* Save 1 as word and load byte - 0 - BIG, 1 - LITTLE */ |
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| 87 | lbui r11, r0, TOPHYS(endian_check) |
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| 88 | beqid r11, big_endian /* DO NOT break delay stop dependency */ |
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| 89 | lw r11, r0, r7 /* Big endian load in delay slot */ |
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| 90 | lwr r11, r0, r7 /* Little endian load */ |
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| 91 | big_endian: |
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| 92 | rsubi r11, r11, OF_DT_HEADER /* Check FDT header */ |
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| 93 | beqi r11, _prepare_copy_fdt |
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| 94 | or r7, r0, r0 /* clear R7 when not valid DTB */ |
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| 95 | bnei r11, no_fdt_arg /* No - get out of here */ |
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| 96 | _prepare_copy_fdt: |
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| 97 | or r11, r0, r0 /* incremment */ |
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| 98 | ori r4, r0, TOPHYS(_fdt_start) |
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| 99 | ori r3, r0, (0x10000 - 4) |
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| 100 | _copy_fdt: |
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| 101 | lw r12, r7, r11 /* r12 = r7 + r11 */ |
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| 102 | sw r12, r4, r11 /* addr[r4 + r11] = r12 */ |
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| 103 | addik r11, r11, 4 /* increment counting */ |
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| 104 | bgtid r3, _copy_fdt /* loop for all entries */ |
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| 105 | addik r3, r3, -4 /* descrement loop */ |
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| 106 | no_fdt_arg: |
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| 107 | |
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| 108 | #ifndef CONFIG_CMDLINE_BOOL |
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| 109 | /* |
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| 110 | * handling command line |
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| 111 | * copy command line directly to cmd_line placed in data section. |
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| 112 | */ |
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| 113 | beqid r5, skip /* Skip if NULL pointer */ |
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| 114 | or r11, r0, r0 /* incremment */ |
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| 115 | ori r4, r0, cmd_line /* load address of command line */ |
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| 116 | tophys(r4,r4) /* convert to phys address */ |
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| 117 | ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ |
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| 118 | _copy_command_line: |
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| 119 | /* r2=r5+r11 - r5 contain pointer to command line */ |
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| 120 | lbu r2, r5, r11 |
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| 121 | beqid r2, skip /* Skip if no data */ |
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| 122 | sb r2, r4, r11 /* addr[r4+r11]= r2 */ |
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| 123 | addik r11, r11, 1 /* increment counting */ |
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| 124 | bgtid r3, _copy_command_line /* loop for all entries */ |
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| 125 | addik r3, r3, -1 /* decrement loop */ |
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| 126 | addik r5, r4, 0 /* add new space for command line */ |
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| 127 | tovirt(r5,r5) |
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| 128 | skip: |
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| 129 | #endif /* CONFIG_CMDLINE_BOOL */ |
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| 130 | |
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| 131 | #ifdef NOT_COMPILE |
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| 132 | /* save bram context */ |
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| 133 | or r11, r0, r0 /* incremment */ |
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| 134 | ori r4, r0, TOPHYS(_bram_load_start) /* save bram context */ |
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| 135 | ori r3, r0, (LMB_SIZE - 4) |
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| 136 | _copy_bram: |
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| 137 | lw r7, r0, r11 /* r7 = r0 + r11 */ |
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| 138 | sw r7, r4, r11 /* addr[r4 + r11] = r7 */ |
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| 139 | addik r11, r11, 4 /* increment counting */ |
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| 140 | bgtid r3, _copy_bram /* loop for all entries */ |
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| 141 | addik r3, r3, -4 /* descrement loop */ |
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| 142 | #endif |
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| 143 | /* We have to turn on the MMU right away. */ |
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| 144 | |
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| 145 | /* |
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| 146 | * Set up the initial MMU state so we can do the first level of |
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| 147 | * kernel initialization. This maps the first 16 MBytes of memory 1:1 |
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| 148 | * virtual to physical. |
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| 149 | */ |
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| 150 | nop |
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| 151 | addik r3, r0, MICROBLAZE_TLB_SIZE -1 /* Invalidate all TLB entries */ |
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| 152 | _invalidate: |
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| 153 | mts rtlbx, r3 |
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| 154 | mts rtlbhi, r0 /* flush: ensure V is clear */ |
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| 155 | mts rtlblo, r0 |
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| 156 | bgtid r3, _invalidate /* loop for all entries */ |
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| 157 | addik r3, r3, -1 |
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| 158 | /* sync */ |
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| 159 | |
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| 160 | /* Setup the kernel PID */ |
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| 161 | mts rpid,r0 /* Load the kernel PID */ |
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| 162 | nop |
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| 163 | bri 4 |
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| 164 | |
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| 165 | /* |
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| 166 | * We should still be executing code at physical address area |
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| 167 | * RAM_BASEADDR at this point. However, kernel code is at |
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| 168 | * a virtual address. So, set up a TLB mapping to cover this once |
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| 169 | * translation is enabled. |
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| 170 | */ |
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| 171 | |
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| 172 | addik r3,r0, CONFIG_KERNEL_START /* Load the kernel virtual address */ |
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| 173 | tophys(r4,r3) /* Load the kernel physical address */ |
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| 174 | |
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| 175 | /* start to do TLB calculation */ |
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| 176 | addik r12, r0, _end |
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| 177 | rsub r12, r3, r12 |
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| 178 | addik r12, r12, CONFIG_LOWMEM_SIZE >> PTE_SHIFT /* that's the pad */ |
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| 179 | |
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| 180 | or r9, r0, r0 /* TLB0 = 0 */ |
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| 181 | or r10, r0, r0 /* TLB1 = 0 */ |
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| 182 | |
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| 183 | addik r11, r12, -0x1000000 |
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| 184 | bgei r11, GT16 /* size is greater than 16MB */ |
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| 185 | addik r11, r12, -0x0800000 |
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| 186 | bgei r11, GT8 /* size is greater than 8MB */ |
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| 187 | addik r11, r12, -0x0400000 |
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| 188 | bgei r11, GT4 /* size is greater than 4MB */ |
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| 189 | /* size is less than 4MB */ |
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| 190 | addik r11, r12, -0x0200000 |
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| 191 | bgei r11, GT2 /* size is greater than 2MB */ |
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| 192 | addik r9, r0, 0x0100000 /* TLB0 must be 1MB */ |
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| 193 | addik r11, r12, -0x0100000 |
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| 194 | bgei r11, GT1 /* size is greater than 1MB */ |
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| 195 | /* TLB1 is 0 which is setup above */ |
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| 196 | bri tlb_end |
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| 197 | GT4: /* r11 contains the rest - will be either 1 or 4 */ |
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| 198 | ori r9, r0, 0x400000 /* TLB0 is 4MB */ |
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| 199 | bri TLB1 |
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| 200 | GT16: /* TLB0 is 16MB */ |
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| 201 | addik r9, r0, 0x1000000 /* means TLB0 is 16MB */ |
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| 202 | TLB1: |
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| 203 | /* must be used r2 because of subtract if failed */ |
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| 204 | addik r2, r11, -0x0400000 |
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| 205 | bgei r2, GT20 /* size is greater than 16MB */ |
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| 206 | /* size is >16MB and <20MB */ |
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| 207 | addik r11, r11, -0x0100000 |
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| 208 | bgei r11, GT17 /* size is greater than 17MB */ |
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| 209 | /* kernel is >16MB and < 17MB */ |
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| 210 | GT1: |
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| 211 | addik r10, r0, 0x0100000 /* means TLB1 is 1MB */ |
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| 212 | bri tlb_end |
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| 213 | GT2: /* TLB0 is 0 and TLB1 will be 4MB */ |
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| 214 | GT17: /* TLB1 is 4MB - kernel size <20MB */ |
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| 215 | addik r10, r0, 0x0400000 /* means TLB1 is 4MB */ |
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| 216 | bri tlb_end |
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| 217 | GT8: /* TLB0 is still zero that's why I can use only TLB1 */ |
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| 218 | GT20: /* TLB1 is 16MB - kernel size >20MB */ |
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| 219 | addik r10, r0, 0x1000000 /* means TLB1 is 16MB */ |
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| 220 | tlb_end: |
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| 221 | |
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| 222 | /* |
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| 223 | * Configure and load two entries into TLB slots 0 and 1. |
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| 224 | * In case we are pinning TLBs, these are reserved in by the |
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| 225 | * other TLB functions. If not reserving, then it doesn't |
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| 226 | * matter where they are loaded. |
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| 227 | */ |
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| 228 | andi r4,r4,0xfffffc00 /* Mask off the real page number */ |
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| 229 | ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */ |
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| 230 | |
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| 231 | /* |
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| 232 | * TLB0 is always used - check if is not zero (r9 stores TLB0 value) |
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| 233 | * if is use TLB1 value and clear it (r10 stores TLB1 value) |
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| 234 | */ |
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| 235 | bnei r9, tlb0_not_zero |
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| 236 | add r9, r10, r0 |
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| 237 | add r10, r0, r0 |
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| 238 | tlb0_not_zero: |
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| 239 | |
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| 240 | /* look at the code below */ |
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| 241 | ori r30, r0, 0x200 |
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| 242 | andi r29, r9, 0x100000 |
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| 243 | bneid r29, 1f |
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| 244 | addik r30, r30, 0x80 |
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| 245 | andi r29, r9, 0x400000 |
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| 246 | bneid r29, 1f |
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| 247 | addik r30, r30, 0x80 |
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| 248 | andi r29, r9, 0x1000000 |
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| 249 | bneid r29, 1f |
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| 250 | addik r30, r30, 0x80 |
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| 251 | 1: |
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| 252 | andi r3,r3,0xfffffc00 /* Mask off the effective page number */ |
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| 253 | ori r3,r3,(TLB_VALID) |
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| 254 | or r3, r3, r30 |
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| 255 | |
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| 256 | /* Load tlb_skip size value which is index to first unused TLB entry */ |
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| 257 | lwi r11, r0, TOPHYS(tlb_skip) |
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| 258 | mts rtlbx,r11 /* TLB slow 0 */ |
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| 259 | |
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| 260 | mts rtlblo,r4 /* Load the data portion of the entry */ |
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| 261 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
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| 262 | |
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| 263 | /* Increase tlb_skip size */ |
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| 264 | addik r11, r11, 1 |
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| 265 | swi r11, r0, TOPHYS(tlb_skip) |
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| 266 | |
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| 267 | /* TLB1 can be zeroes that's why we not setup it */ |
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| 268 | beqi r10, jump_over2 |
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| 269 | |
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| 270 | /* look at the code below */ |
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| 271 | ori r30, r0, 0x200 |
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| 272 | andi r29, r10, 0x100000 |
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| 273 | bneid r29, 1f |
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| 274 | addik r30, r30, 0x80 |
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| 275 | andi r29, r10, 0x400000 |
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| 276 | bneid r29, 1f |
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| 277 | addik r30, r30, 0x80 |
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| 278 | andi r29, r10, 0x1000000 |
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| 279 | bneid r29, 1f |
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| 280 | addik r30, r30, 0x80 |
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| 281 | 1: |
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| 282 | addk r4, r4, r9 /* previous addr + TLB0 size */ |
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| 283 | addk r3, r3, r9 |
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| 284 | |
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| 285 | andi r3,r3,0xfffffc00 /* Mask off the effective page number */ |
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| 286 | ori r3,r3,(TLB_VALID) |
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| 287 | or r3, r3, r30 |
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| 288 | |
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| 289 | lwi r11, r0, TOPHYS(tlb_skip) |
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| 290 | mts rtlbx, r11 /* r11 is used from TLB0 */ |
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| 291 | |
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| 292 | mts rtlblo,r4 /* Load the data portion of the entry */ |
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| 293 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
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| 294 | |
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| 295 | /* Increase tlb_skip size */ |
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| 296 | addik r11, r11, 1 |
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| 297 | swi r11, r0, TOPHYS(tlb_skip) |
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| 298 | |
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| 299 | jump_over2: |
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| 300 | /* |
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| 301 | * Load a TLB entry for LMB, since we need access to |
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| 302 | * the exception vectors, using a 4k real==virtual mapping. |
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| 303 | */ |
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| 304 | /* Use temporary TLB_ID for LMB - clear this temporary mapping later */ |
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| 305 | ori r11, r0, MICROBLAZE_LMB_TLB_ID |
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| 306 | mts rtlbx,r11 |
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| 307 | |
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| 308 | ori r4,r0,(TLB_WR | TLB_EX) |
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| 309 | ori r3,r0,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K)) |
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| 310 | |
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| 311 | mts rtlblo,r4 /* Load the data portion of the entry */ |
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| 312 | mts rtlbhi,r3 /* Load the tag portion of the entry */ |
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| 313 | |
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| 314 | /* |
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| 315 | * We now have the lower 16 Meg of RAM mapped into TLB entries, and the |
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| 316 | * caches ready to work. |
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| 317 | */ |
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| 318 | turn_on_mmu: |
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| 319 | ori r15,r0,start_here |
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| 320 | ori r4,r0,MSR_KERNEL_VMS |
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| 321 | mts rmsr,r4 |
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| 322 | nop |
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| 323 | rted r15,0 /* enables MMU */ |
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| 324 | nop |
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| 325 | |
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| 326 | start_here: |
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| 327 | |
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| 328 | /* Initialize small data anchors */ |
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| 329 | addik r13, r0, _KERNEL_SDA_BASE_ |
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| 330 | addik r2, r0, _KERNEL_SDA2_BASE_ |
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| 331 | |
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| 332 | /* Initialize stack pointer */ |
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| 333 | addik r1, r0, init_thread_union + THREAD_SIZE - 4 |
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| 334 | |
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| 335 | /* Initialize r31 with current task address */ |
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| 336 | addik r31, r0, init_task |
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| 337 | |
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| 338 | addik r11, r0, machine_early_init |
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| 339 | brald r15, r11 |
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| 340 | nop |
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| 341 | |
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| 342 | /* |
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| 343 | * Initialize the MMU. |
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| 344 | */ |
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| 345 | bralid r15, mmu_init |
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| 346 | nop |
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| 347 | |
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| 348 | /* Go back to running unmapped so we can load up new values |
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| 349 | * and change to using our exception vectors. |
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| 350 | * On the MicroBlaze, all we invalidate the used TLB entries to clear |
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| 351 | * the old 16M byte TLB mappings. |
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| 352 | */ |
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| 353 | ori r15,r0,TOPHYS(kernel_load_context) |
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| 354 | ori r4,r0,MSR_KERNEL |
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| 355 | mts rmsr,r4 |
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| 356 | nop |
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| 357 | bri 4 |
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| 358 | rted r15,0 |
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| 359 | nop |
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| 360 | |
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| 361 | /* Load up the kernel context */ |
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| 362 | kernel_load_context: |
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| 363 | ori r5, r0, MICROBLAZE_LMB_TLB_ID |
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| 364 | mts rtlbx,r5 |
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| 365 | nop |
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| 366 | mts rtlbhi,r0 |
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| 367 | nop |
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| 368 | addi r15, r0, machine_halt |
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| 369 | ori r17, r0, start_kernel |
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| 370 | ori r4, r0, MSR_KERNEL_VMS |
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| 371 | mts rmsr, r4 |
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| 372 | nop |
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| 373 | rted r17, 0 /* enable MMU and jump to start_kernel */ |
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| 374 | nop |
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| 375 | |
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