1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * DBAu1000/1500/1100 PBAu1100/1500 board support |
4 | * |
5 | * Copyright 2000, 2008 MontaVista Software Inc. |
6 | * Author: MontaVista Software, Inc. <source@mvista.com> |
7 | */ |
8 | |
9 | #include <linux/clk.h> |
10 | #include <linux/dma-mapping.h> |
11 | #include <linux/gpio.h> |
12 | #include <linux/gpio/machine.h> |
13 | #include <linux/init.h> |
14 | #include <linux/interrupt.h> |
15 | #include <linux/leds.h> |
16 | #include <linux/mmc/host.h> |
17 | #include <linux/platform_device.h> |
18 | #include <linux/pm.h> |
19 | #include <linux/spi/spi.h> |
20 | #include <linux/spi/spi_gpio.h> |
21 | #include <linux/spi/ads7846.h> |
22 | #include <asm/mach-au1x00/au1000.h> |
23 | #include <asm/mach-au1x00/gpio-au1000.h> |
24 | #include <asm/mach-au1x00/au1000_dma.h> |
25 | #include <asm/mach-au1x00/au1100_mmc.h> |
26 | #include <asm/mach-db1x00/bcsr.h> |
27 | #include <asm/reboot.h> |
28 | #include <prom.h> |
29 | #include "platform.h" |
30 | |
31 | #define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT) |
32 | |
33 | const char *get_system_type(void); |
34 | |
35 | int __init db1000_board_setup(void) |
36 | { |
37 | /* initialize board register space */ |
38 | bcsr_init(DB1000_BCSR_PHYS_ADDR, |
39 | DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS); |
40 | |
41 | switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) { |
42 | case BCSR_WHOAMI_DB1000: |
43 | case BCSR_WHOAMI_DB1500: |
44 | case BCSR_WHOAMI_DB1100: |
45 | case BCSR_WHOAMI_PB1500: |
46 | case BCSR_WHOAMI_PB1500R2: |
47 | case BCSR_WHOAMI_PB1100: |
48 | pr_info("AMD Alchemy %s Board\n" , get_system_type()); |
49 | return 0; |
50 | } |
51 | return -ENODEV; |
52 | } |
53 | |
54 | static int db1500_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin) |
55 | { |
56 | if ((slot < 12) || (slot > 13) || pin == 0) |
57 | return -1; |
58 | if (slot == 12) |
59 | return (pin == 1) ? AU1500_PCI_INTA : 0xff; |
60 | if (slot == 13) { |
61 | switch (pin) { |
62 | case 1: return AU1500_PCI_INTA; |
63 | case 2: return AU1500_PCI_INTB; |
64 | case 3: return AU1500_PCI_INTC; |
65 | case 4: return AU1500_PCI_INTD; |
66 | } |
67 | } |
68 | return -1; |
69 | } |
70 | |
71 | static u64 au1xxx_all_dmamask = DMA_BIT_MASK(32); |
72 | |
73 | static struct resource alchemy_pci_host_res[] = { |
74 | [0] = { |
75 | .start = AU1500_PCI_PHYS_ADDR, |
76 | .end = AU1500_PCI_PHYS_ADDR + 0xfff, |
77 | .flags = IORESOURCE_MEM, |
78 | }, |
79 | }; |
80 | |
81 | static struct alchemy_pci_platdata db1500_pci_pd = { |
82 | .board_map_irq = db1500_map_pci_irq, |
83 | }; |
84 | |
85 | static struct platform_device db1500_pci_host_dev = { |
86 | .dev.platform_data = &db1500_pci_pd, |
87 | .name = "alchemy-pci" , |
88 | .id = 0, |
89 | .num_resources = ARRAY_SIZE(alchemy_pci_host_res), |
90 | .resource = alchemy_pci_host_res, |
91 | }; |
92 | |
93 | int __init db1500_pci_setup(void) |
94 | { |
95 | return platform_device_register(&db1500_pci_host_dev); |
96 | } |
97 | |
98 | static struct resource au1100_lcd_resources[] = { |
99 | [0] = { |
100 | .start = AU1100_LCD_PHYS_ADDR, |
101 | .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1, |
102 | .flags = IORESOURCE_MEM, |
103 | }, |
104 | [1] = { |
105 | .start = AU1100_LCD_INT, |
106 | .end = AU1100_LCD_INT, |
107 | .flags = IORESOURCE_IRQ, |
108 | } |
109 | }; |
110 | |
111 | static struct platform_device au1100_lcd_device = { |
112 | .name = "au1100-lcd" , |
113 | .id = 0, |
114 | .dev = { |
115 | .dma_mask = &au1xxx_all_dmamask, |
116 | .coherent_dma_mask = DMA_BIT_MASK(32), |
117 | }, |
118 | .num_resources = ARRAY_SIZE(au1100_lcd_resources), |
119 | .resource = au1100_lcd_resources, |
120 | }; |
121 | |
122 | static struct resource alchemy_ac97c_res[] = { |
123 | [0] = { |
124 | .start = AU1000_AC97_PHYS_ADDR, |
125 | .end = AU1000_AC97_PHYS_ADDR + 0xfff, |
126 | .flags = IORESOURCE_MEM, |
127 | }, |
128 | [1] = { |
129 | .start = DMA_ID_AC97C_TX, |
130 | .end = DMA_ID_AC97C_TX, |
131 | .flags = IORESOURCE_DMA, |
132 | }, |
133 | [2] = { |
134 | .start = DMA_ID_AC97C_RX, |
135 | .end = DMA_ID_AC97C_RX, |
136 | .flags = IORESOURCE_DMA, |
137 | }, |
138 | }; |
139 | |
140 | static struct platform_device alchemy_ac97c_dev = { |
141 | .name = "alchemy-ac97c" , |
142 | .id = -1, |
143 | .resource = alchemy_ac97c_res, |
144 | .num_resources = ARRAY_SIZE(alchemy_ac97c_res), |
145 | }; |
146 | |
147 | static struct platform_device alchemy_ac97c_dma_dev = { |
148 | .name = "alchemy-pcm-dma" , |
149 | .id = 0, |
150 | }; |
151 | |
152 | static struct platform_device db1x00_codec_dev = { |
153 | .name = "ac97-codec" , |
154 | .id = -1, |
155 | }; |
156 | |
157 | static struct platform_device db1x00_audio_dev = { |
158 | .name = "db1000-audio" , |
159 | .dev = { |
160 | .dma_mask = &au1xxx_all_dmamask, |
161 | .coherent_dma_mask = DMA_BIT_MASK(32), |
162 | }, |
163 | }; |
164 | |
165 | /******************************************************************************/ |
166 | |
167 | #ifdef CONFIG_MMC_AU1X |
168 | static irqreturn_t db1100_mmc_cd(int irq, void *ptr) |
169 | { |
170 | mmc_detect_change(ptr, msecs_to_jiffies(500)); |
171 | return IRQ_HANDLED; |
172 | } |
173 | |
174 | static int db1100_mmc_cd_setup(void *mmc_host, int en) |
175 | { |
176 | int ret = 0, irq; |
177 | |
178 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) |
179 | irq = AU1100_GPIO19_INT; |
180 | else |
181 | irq = AU1100_GPIO14_INT; /* PB1100 SD0 CD# */ |
182 | |
183 | if (en) { |
184 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); |
185 | ret = request_irq(irq, db1100_mmc_cd, 0, |
186 | "sd0_cd" , mmc_host); |
187 | } else |
188 | free_irq(irq, mmc_host); |
189 | return ret; |
190 | } |
191 | |
192 | static int db1100_mmc1_cd_setup(void *mmc_host, int en) |
193 | { |
194 | int ret = 0, irq; |
195 | |
196 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) |
197 | irq = AU1100_GPIO20_INT; |
198 | else |
199 | irq = AU1100_GPIO15_INT; /* PB1100 SD1 CD# */ |
200 | |
201 | if (en) { |
202 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_BOTH); |
203 | ret = request_irq(irq, db1100_mmc_cd, 0, |
204 | "sd1_cd" , mmc_host); |
205 | } else |
206 | free_irq(irq, mmc_host); |
207 | return ret; |
208 | } |
209 | |
210 | static int db1100_mmc_card_readonly(void *mmc_host) |
211 | { |
212 | /* testing suggests that this bit is inverted */ |
213 | return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 0 : 1; |
214 | } |
215 | |
216 | static int db1100_mmc_card_inserted(void *mmc_host) |
217 | { |
218 | return !alchemy_gpio_get_value(19); |
219 | } |
220 | |
221 | static void db1100_mmc_set_power(void *mmc_host, int state) |
222 | { |
223 | int bit; |
224 | |
225 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) |
226 | bit = BCSR_BOARD_SD0PWR; |
227 | else |
228 | bit = BCSR_BOARD_PB1100_SD0PWR; |
229 | |
230 | if (state) { |
231 | bcsr_mod(BCSR_BOARD, 0, bit); |
232 | msleep(400); /* stabilization time */ |
233 | } else |
234 | bcsr_mod(BCSR_BOARD, bit, 0); |
235 | } |
236 | |
237 | static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b) |
238 | { |
239 | if (b != LED_OFF) |
240 | bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); |
241 | else |
242 | bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); |
243 | } |
244 | |
245 | static struct led_classdev db1100_mmc_led = { |
246 | .brightness_set = db1100_mmcled_set, |
247 | }; |
248 | |
249 | static int db1100_mmc1_card_readonly(void *mmc_host) |
250 | { |
251 | return (bcsr_read(BCSR_BOARD) & BCSR_BOARD_SD1WP) ? 1 : 0; |
252 | } |
253 | |
254 | static int db1100_mmc1_card_inserted(void *mmc_host) |
255 | { |
256 | return !alchemy_gpio_get_value(20); |
257 | } |
258 | |
259 | static void db1100_mmc1_set_power(void *mmc_host, int state) |
260 | { |
261 | int bit; |
262 | |
263 | if (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) == BCSR_WHOAMI_DB1100) |
264 | bit = BCSR_BOARD_SD1PWR; |
265 | else |
266 | bit = BCSR_BOARD_PB1100_SD1PWR; |
267 | |
268 | if (state) { |
269 | bcsr_mod(BCSR_BOARD, 0, bit); |
270 | msleep(400); /* stabilization time */ |
271 | } else |
272 | bcsr_mod(BCSR_BOARD, bit, 0); |
273 | } |
274 | |
275 | static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b) |
276 | { |
277 | if (b != LED_OFF) |
278 | bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED1, 0); |
279 | else |
280 | bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED1); |
281 | } |
282 | |
283 | static struct led_classdev db1100_mmc1_led = { |
284 | .brightness_set = db1100_mmc1led_set, |
285 | }; |
286 | |
287 | static struct au1xmmc_platform_data db1100_mmc_platdata[2] = { |
288 | [0] = { |
289 | .cd_setup = db1100_mmc_cd_setup, |
290 | .set_power = db1100_mmc_set_power, |
291 | .card_inserted = db1100_mmc_card_inserted, |
292 | .card_readonly = db1100_mmc_card_readonly, |
293 | .led = &db1100_mmc_led, |
294 | }, |
295 | [1] = { |
296 | .cd_setup = db1100_mmc1_cd_setup, |
297 | .set_power = db1100_mmc1_set_power, |
298 | .card_inserted = db1100_mmc1_card_inserted, |
299 | .card_readonly = db1100_mmc1_card_readonly, |
300 | .led = &db1100_mmc1_led, |
301 | }, |
302 | }; |
303 | |
304 | static struct resource au1100_mmc0_resources[] = { |
305 | [0] = { |
306 | .start = AU1100_SD0_PHYS_ADDR, |
307 | .end = AU1100_SD0_PHYS_ADDR + 0xfff, |
308 | .flags = IORESOURCE_MEM, |
309 | }, |
310 | [1] = { |
311 | .start = AU1100_SD_INT, |
312 | .end = AU1100_SD_INT, |
313 | .flags = IORESOURCE_IRQ, |
314 | }, |
315 | [2] = { |
316 | .start = DMA_ID_SD0_TX, |
317 | .end = DMA_ID_SD0_TX, |
318 | .flags = IORESOURCE_DMA, |
319 | }, |
320 | [3] = { |
321 | .start = DMA_ID_SD0_RX, |
322 | .end = DMA_ID_SD0_RX, |
323 | .flags = IORESOURCE_DMA, |
324 | } |
325 | }; |
326 | |
327 | static struct platform_device db1100_mmc0_dev = { |
328 | .name = "au1xxx-mmc" , |
329 | .id = 0, |
330 | .dev = { |
331 | .dma_mask = &au1xxx_all_dmamask, |
332 | .coherent_dma_mask = DMA_BIT_MASK(32), |
333 | .platform_data = &db1100_mmc_platdata[0], |
334 | }, |
335 | .num_resources = ARRAY_SIZE(au1100_mmc0_resources), |
336 | .resource = au1100_mmc0_resources, |
337 | }; |
338 | |
339 | static struct resource au1100_mmc1_res[] = { |
340 | [0] = { |
341 | .start = AU1100_SD1_PHYS_ADDR, |
342 | .end = AU1100_SD1_PHYS_ADDR + 0xfff, |
343 | .flags = IORESOURCE_MEM, |
344 | }, |
345 | [1] = { |
346 | .start = AU1100_SD_INT, |
347 | .end = AU1100_SD_INT, |
348 | .flags = IORESOURCE_IRQ, |
349 | }, |
350 | [2] = { |
351 | .start = DMA_ID_SD1_TX, |
352 | .end = DMA_ID_SD1_TX, |
353 | .flags = IORESOURCE_DMA, |
354 | }, |
355 | [3] = { |
356 | .start = DMA_ID_SD1_RX, |
357 | .end = DMA_ID_SD1_RX, |
358 | .flags = IORESOURCE_DMA, |
359 | } |
360 | }; |
361 | |
362 | static struct platform_device db1100_mmc1_dev = { |
363 | .name = "au1xxx-mmc" , |
364 | .id = 1, |
365 | .dev = { |
366 | .dma_mask = &au1xxx_all_dmamask, |
367 | .coherent_dma_mask = DMA_BIT_MASK(32), |
368 | .platform_data = &db1100_mmc_platdata[1], |
369 | }, |
370 | .num_resources = ARRAY_SIZE(au1100_mmc1_res), |
371 | .resource = au1100_mmc1_res, |
372 | }; |
373 | #endif /* CONFIG_MMC_AU1X */ |
374 | |
375 | /******************************************************************************/ |
376 | |
377 | static struct ads7846_platform_data db1100_touch_pd = { |
378 | .model = 7846, |
379 | .vref_mv = 3300, |
380 | }; |
381 | |
382 | static struct spi_gpio_platform_data db1100_spictl_pd = { |
383 | .num_chipselect = 1, |
384 | }; |
385 | |
386 | static struct gpiod_lookup_table db1100_touch_gpio_table = { |
387 | .dev_id = "spi0.0" , |
388 | .table = { |
389 | GPIO_LOOKUP("alchemy-gpio2" , 21, |
390 | "pendown" , GPIO_ACTIVE_LOW), |
391 | { } |
392 | }, |
393 | }; |
394 | |
395 | static struct spi_board_info db1100_spi_info[] __initdata = { |
396 | [0] = { |
397 | .modalias = "ads7846" , |
398 | .max_speed_hz = 3250000, |
399 | .bus_num = 0, |
400 | .chip_select = 0, |
401 | .mode = 0, |
402 | .irq = AU1100_GPIO21_INT, |
403 | .platform_data = &db1100_touch_pd, |
404 | }, |
405 | }; |
406 | |
407 | static struct platform_device db1100_spi_dev = { |
408 | .name = "spi_gpio" , |
409 | .id = 0, |
410 | .dev = { |
411 | .platform_data = &db1100_spictl_pd, |
412 | .dma_mask = &au1xxx_all_dmamask, |
413 | .coherent_dma_mask = DMA_BIT_MASK(32), |
414 | }, |
415 | }; |
416 | |
417 | /* |
418 | * Alchemy GPIO 2 has its base at 200 so the GPIO lines |
419 | * 207 thru 210 are GPIOs at offset 7 thru 10 at this chip. |
420 | */ |
421 | static struct gpiod_lookup_table db1100_spi_gpiod_table = { |
422 | .dev_id = "spi_gpio" , |
423 | .table = { |
424 | GPIO_LOOKUP("alchemy-gpio2" , 9, |
425 | "sck" , GPIO_ACTIVE_HIGH), |
426 | GPIO_LOOKUP("alchemy-gpio2" , 8, |
427 | "mosi" , GPIO_ACTIVE_HIGH), |
428 | GPIO_LOOKUP("alchemy-gpio2" , 7, |
429 | "miso" , GPIO_ACTIVE_HIGH), |
430 | GPIO_LOOKUP("alchemy-gpio2" , 10, |
431 | "cs" , GPIO_ACTIVE_HIGH), |
432 | { }, |
433 | }, |
434 | }; |
435 | |
436 | static struct platform_device *db1x00_devs[] = { |
437 | &db1x00_codec_dev, |
438 | &alchemy_ac97c_dma_dev, |
439 | &alchemy_ac97c_dev, |
440 | &db1x00_audio_dev, |
441 | }; |
442 | |
443 | static struct platform_device *db1100_devs[] = { |
444 | &au1100_lcd_device, |
445 | #ifdef CONFIG_MMC_AU1X |
446 | &db1100_mmc0_dev, |
447 | &db1100_mmc1_dev, |
448 | #endif |
449 | }; |
450 | |
451 | int __init db1000_dev_setup(void) |
452 | { |
453 | int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)); |
454 | int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; |
455 | unsigned long pfc; |
456 | struct clk *c, *p; |
457 | |
458 | if (board == BCSR_WHOAMI_DB1500) { |
459 | c0 = AU1500_GPIO2_INT; |
460 | c1 = AU1500_GPIO5_INT; |
461 | d0 = 0; /* GPIO number, NOT irq! */ |
462 | d1 = 3; /* GPIO number, NOT irq! */ |
463 | s0 = AU1500_GPIO1_INT; |
464 | s1 = AU1500_GPIO4_INT; |
465 | } else if (board == BCSR_WHOAMI_DB1100) { |
466 | c0 = AU1100_GPIO2_INT; |
467 | c1 = AU1100_GPIO5_INT; |
468 | d0 = 0; /* GPIO number, NOT irq! */ |
469 | d1 = 3; /* GPIO number, NOT irq! */ |
470 | s0 = AU1100_GPIO1_INT; |
471 | s1 = AU1100_GPIO4_INT; |
472 | |
473 | gpio_request(gpio: 19, label: "sd0_cd" ); |
474 | gpio_request(gpio: 20, label: "sd1_cd" ); |
475 | gpio_direction_input(gpio: 19); /* sd0 cd# */ |
476 | gpio_direction_input(gpio: 20); /* sd1 cd# */ |
477 | |
478 | /* spi_gpio on SSI0 pins */ |
479 | pfc = alchemy_rdsys(AU1000_SYS_PINFUNC); |
480 | pfc |= (1 << 0); /* SSI0 pins as GPIOs */ |
481 | alchemy_wrsys(pfc, AU1000_SYS_PINFUNC); |
482 | |
483 | gpiod_add_lookup_table(table: &db1100_touch_gpio_table); |
484 | spi_register_board_info(db1100_spi_info, |
485 | ARRAY_SIZE(db1100_spi_info)); |
486 | |
487 | /* link LCD clock to AUXPLL */ |
488 | p = clk_get(NULL, id: "auxpll_clk" ); |
489 | c = clk_get(NULL, id: "lcd_intclk" ); |
490 | if (!IS_ERR(ptr: c) && !IS_ERR(ptr: p)) { |
491 | clk_set_parent(clk: c, parent: p); |
492 | clk_set_rate(clk: c, rate: clk_get_rate(clk: p)); |
493 | } |
494 | if (!IS_ERR(ptr: c)) |
495 | clk_put(clk: c); |
496 | if (!IS_ERR(ptr: p)) |
497 | clk_put(clk: p); |
498 | |
499 | platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); |
500 | gpiod_add_lookup_table(table: &db1100_spi_gpiod_table); |
501 | platform_device_register(&db1100_spi_dev); |
502 | } else if (board == BCSR_WHOAMI_DB1000) { |
503 | c0 = AU1000_GPIO2_INT; |
504 | c1 = AU1000_GPIO5_INT; |
505 | d0 = 0; /* GPIO number, NOT irq! */ |
506 | d1 = 3; /* GPIO number, NOT irq! */ |
507 | s0 = AU1000_GPIO1_INT; |
508 | s1 = AU1000_GPIO4_INT; |
509 | } else if ((board == BCSR_WHOAMI_PB1500) || |
510 | (board == BCSR_WHOAMI_PB1500R2)) { |
511 | c0 = AU1500_GPIO203_INT; |
512 | d0 = 1; /* GPIO number, NOT irq! */ |
513 | s0 = AU1500_GPIO202_INT; |
514 | twosocks = 0; |
515 | flashsize = 64; |
516 | /* RTC and daughtercard irqs */ |
517 | irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW); |
518 | irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW); |
519 | /* EPSON S1D13806 0x1b000000 |
520 | * SRAM 1MB/2MB 0x1a000000 |
521 | * DS1693 RTC 0x0c000000 |
522 | */ |
523 | } else if (board == BCSR_WHOAMI_PB1100) { |
524 | c0 = AU1100_GPIO11_INT; |
525 | d0 = 9; /* GPIO number, NOT irq! */ |
526 | s0 = AU1100_GPIO10_INT; |
527 | twosocks = 0; |
528 | flashsize = 64; |
529 | /* pendown, rtc, daughtercard irqs */ |
530 | irq_set_irq_type(AU1100_GPIO8_INT, IRQ_TYPE_LEVEL_LOW); |
531 | irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW); |
532 | irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW); |
533 | /* EPSON S1D13806 0x1b000000 |
534 | * SRAM 1MB/2MB 0x1a000000 |
535 | * DiskOnChip 0x0d000000 |
536 | * DS1693 RTC 0x0c000000 |
537 | */ |
538 | platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs)); |
539 | } else |
540 | return 0; /* unknown board, no further dev setup to do */ |
541 | |
542 | irq_set_irq_type(c0, IRQ_TYPE_LEVEL_LOW); |
543 | irq_set_irq_type(s0, IRQ_TYPE_LEVEL_LOW); |
544 | |
545 | db1x_register_pcmcia_socket( |
546 | AU1000_PCMCIA_ATTR_PHYS_ADDR, |
547 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1, |
548 | AU1000_PCMCIA_MEM_PHYS_ADDR, |
549 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1, |
550 | AU1000_PCMCIA_IO_PHYS_ADDR, |
551 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1, |
552 | c0, d0, /*s0*/0, 0, 0); |
553 | |
554 | if (twosocks) { |
555 | irq_set_irq_type(c1, IRQ_TYPE_LEVEL_LOW); |
556 | irq_set_irq_type(s1, IRQ_TYPE_LEVEL_LOW); |
557 | |
558 | db1x_register_pcmcia_socket( |
559 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000, |
560 | AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1, |
561 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000, |
562 | AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1, |
563 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000, |
564 | AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1, |
565 | c1, d1, /*s1*/0, 0, 1); |
566 | } |
567 | |
568 | platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); |
569 | db1x_register_norflash(flashsize << 20, 4 /* 32bit */, F_SWAPPED); |
570 | return 0; |
571 | } |
572 | |