1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Processor capabilities determination functions. |
4 | * |
5 | * Copyright (C) xxxx the Anonymous |
6 | * Copyright (C) 1994 - 2006 Ralf Baechle |
7 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
8 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
9 | */ |
10 | #include <linux/init.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/ptrace.h> |
13 | #include <linux/smp.h> |
14 | #include <linux/stddef.h> |
15 | #include <linux/export.h> |
16 | |
17 | #include <asm/bugs.h> |
18 | #include <asm/cpu.h> |
19 | #include <asm/cpu-features.h> |
20 | #include <asm/cpu-type.h> |
21 | #include <asm/fpu.h> |
22 | #include <asm/mipsregs.h> |
23 | #include <asm/mipsmtregs.h> |
24 | #include <asm/msa.h> |
25 | #include <asm/watch.h> |
26 | #include <asm/elf.h> |
27 | #include <asm/pgtable-bits.h> |
28 | #include <asm/spram.h> |
29 | #include <asm/traps.h> |
30 | #include <linux/uaccess.h> |
31 | |
32 | #include "fpu-probe.h" |
33 | |
34 | #include <asm/mach-loongson64/cpucfg-emul.h> |
35 | |
36 | /* Hardware capabilities */ |
37 | unsigned int elf_hwcap __read_mostly; |
38 | EXPORT_SYMBOL_GPL(elf_hwcap); |
39 | |
40 | static inline unsigned long cpu_get_msa_id(void) |
41 | { |
42 | unsigned long status, msa_id; |
43 | |
44 | status = read_c0_status(); |
45 | __enable_fpu(FPU_64BIT); |
46 | enable_msa(); |
47 | msa_id = read_msa_ir(); |
48 | disable_msa(); |
49 | write_c0_status(status); |
50 | return msa_id; |
51 | } |
52 | |
53 | static int mips_dsp_disabled; |
54 | |
55 | static int __init dsp_disable(char *s) |
56 | { |
57 | cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
58 | mips_dsp_disabled = 1; |
59 | |
60 | return 1; |
61 | } |
62 | |
63 | __setup("nodsp" , dsp_disable); |
64 | |
65 | static int mips_htw_disabled; |
66 | |
67 | static int __init htw_disable(char *s) |
68 | { |
69 | mips_htw_disabled = 1; |
70 | cpu_data[0].options &= ~MIPS_CPU_HTW; |
71 | write_c0_pwctl(read_c0_pwctl() & |
72 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); |
73 | |
74 | return 1; |
75 | } |
76 | |
77 | __setup("nohtw" , htw_disable); |
78 | |
79 | static int mips_ftlb_disabled; |
80 | static int mips_has_ftlb_configured; |
81 | |
82 | enum ftlb_flags { |
83 | FTLB_EN = 1 << 0, |
84 | FTLB_SET_PROB = 1 << 1, |
85 | }; |
86 | |
87 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags); |
88 | |
89 | static int __init ftlb_disable(char *s) |
90 | { |
91 | unsigned int config4, mmuextdef; |
92 | |
93 | /* |
94 | * If the core hasn't done any FTLB configuration, there is nothing |
95 | * for us to do here. |
96 | */ |
97 | if (!mips_has_ftlb_configured) |
98 | return 1; |
99 | |
100 | /* Disable it in the boot cpu */ |
101 | if (set_ftlb_enable(&cpu_data[0], 0)) { |
102 | pr_warn("Can't turn FTLB off\n" ); |
103 | return 1; |
104 | } |
105 | |
106 | config4 = read_c0_config4(); |
107 | |
108 | /* Check that FTLB has been disabled */ |
109 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
110 | /* MMUSIZEEXT == VTLB ON, FTLB OFF */ |
111 | if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) { |
112 | /* This should never happen */ |
113 | pr_warn("FTLB could not be disabled!\n" ); |
114 | return 1; |
115 | } |
116 | |
117 | mips_ftlb_disabled = 1; |
118 | mips_has_ftlb_configured = 0; |
119 | |
120 | /* |
121 | * noftlb is mainly used for debug purposes so print |
122 | * an informative message instead of using pr_debug() |
123 | */ |
124 | pr_info("FTLB has been disabled\n" ); |
125 | |
126 | /* |
127 | * Some of these bits are duplicated in the decode_config4. |
128 | * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case |
129 | * once FTLB has been disabled so undo what decode_config4 did. |
130 | */ |
131 | cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways * |
132 | cpu_data[0].tlbsizeftlbsets; |
133 | cpu_data[0].tlbsizeftlbsets = 0; |
134 | cpu_data[0].tlbsizeftlbways = 0; |
135 | |
136 | return 1; |
137 | } |
138 | |
139 | __setup("noftlb" , ftlb_disable); |
140 | |
141 | /* |
142 | * Check if the CPU has per tc perf counters |
143 | */ |
144 | static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) |
145 | { |
146 | if (read_c0_config7() & MTI_CONF7_PTC) |
147 | c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; |
148 | } |
149 | |
150 | static inline void check_errata(void) |
151 | { |
152 | struct cpuinfo_mips *c = ¤t_cpu_data; |
153 | |
154 | switch (current_cpu_type()) { |
155 | case CPU_34K: |
156 | /* |
157 | * Erratum "RPS May Cause Incorrect Instruction Execution" |
158 | * This code only handles VPE0, any SMP/RTOS code |
159 | * making use of VPE1 will be responsible for that VPE. |
160 | */ |
161 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) |
162 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); |
163 | break; |
164 | default: |
165 | break; |
166 | } |
167 | } |
168 | |
169 | void __init check_bugs32(void) |
170 | { |
171 | check_errata(); |
172 | } |
173 | |
174 | /* |
175 | * Probe whether cpu has config register by trying to play with |
176 | * alternate cache bit and see whether it matters. |
177 | * It's used by cpu_probe to distinguish between R3000A and R3081. |
178 | */ |
179 | static inline int cpu_has_confreg(void) |
180 | { |
181 | #ifdef CONFIG_CPU_R3000 |
182 | unsigned long size1, size2; |
183 | unsigned long cfg = read_c0_conf(); |
184 | |
185 | size1 = r3k_cache_size(ST0_ISC); |
186 | write_c0_conf(cfg ^ R30XX_CONF_AC); |
187 | size2 = r3k_cache_size(ST0_ISC); |
188 | write_c0_conf(cfg); |
189 | return size1 != size2; |
190 | #else |
191 | return 0; |
192 | #endif |
193 | } |
194 | |
195 | static inline void set_elf_platform(int cpu, const char *plat) |
196 | { |
197 | if (cpu == 0) |
198 | __elf_platform = plat; |
199 | } |
200 | |
201 | static inline void set_elf_base_platform(const char *plat) |
202 | { |
203 | if (__elf_base_platform == NULL) { |
204 | __elf_base_platform = plat; |
205 | } |
206 | } |
207 | |
208 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
209 | { |
210 | #ifdef __NEED_VMBITS_PROBE |
211 | write_c0_entryhi(0x3fffffffffffe000ULL); |
212 | back_to_back_c0_hazard(); |
213 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
214 | #endif |
215 | } |
216 | |
217 | static void set_isa(struct cpuinfo_mips *c, unsigned int isa) |
218 | { |
219 | switch (isa) { |
220 | case MIPS_CPU_ISA_M64R5: |
221 | c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5; |
222 | set_elf_base_platform("mips64r5" ); |
223 | fallthrough; |
224 | case MIPS_CPU_ISA_M64R2: |
225 | c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2; |
226 | set_elf_base_platform("mips64r2" ); |
227 | fallthrough; |
228 | case MIPS_CPU_ISA_M64R1: |
229 | c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1; |
230 | set_elf_base_platform("mips64" ); |
231 | fallthrough; |
232 | case MIPS_CPU_ISA_V: |
233 | c->isa_level |= MIPS_CPU_ISA_V; |
234 | set_elf_base_platform("mips5" ); |
235 | fallthrough; |
236 | case MIPS_CPU_ISA_IV: |
237 | c->isa_level |= MIPS_CPU_ISA_IV; |
238 | set_elf_base_platform("mips4" ); |
239 | fallthrough; |
240 | case MIPS_CPU_ISA_III: |
241 | c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III; |
242 | set_elf_base_platform("mips3" ); |
243 | break; |
244 | |
245 | /* R6 incompatible with everything else */ |
246 | case MIPS_CPU_ISA_M64R6: |
247 | c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6; |
248 | set_elf_base_platform("mips64r6" ); |
249 | fallthrough; |
250 | case MIPS_CPU_ISA_M32R6: |
251 | c->isa_level |= MIPS_CPU_ISA_M32R6; |
252 | set_elf_base_platform("mips32r6" ); |
253 | /* Break here so we don't add incompatible ISAs */ |
254 | break; |
255 | case MIPS_CPU_ISA_M32R5: |
256 | c->isa_level |= MIPS_CPU_ISA_M32R5; |
257 | set_elf_base_platform("mips32r5" ); |
258 | fallthrough; |
259 | case MIPS_CPU_ISA_M32R2: |
260 | c->isa_level |= MIPS_CPU_ISA_M32R2; |
261 | set_elf_base_platform("mips32r2" ); |
262 | fallthrough; |
263 | case MIPS_CPU_ISA_M32R1: |
264 | c->isa_level |= MIPS_CPU_ISA_M32R1; |
265 | set_elf_base_platform("mips32" ); |
266 | fallthrough; |
267 | case MIPS_CPU_ISA_II: |
268 | c->isa_level |= MIPS_CPU_ISA_II; |
269 | set_elf_base_platform("mips2" ); |
270 | break; |
271 | } |
272 | } |
273 | |
274 | static char unknown_isa[] = KERN_ERR \ |
275 | "Unsupported ISA type, c0.config0: %d." ; |
276 | |
277 | static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c) |
278 | { |
279 | |
280 | unsigned int probability = c->tlbsize / c->tlbsizevtlb; |
281 | |
282 | /* |
283 | * 0 = All TLBWR instructions go to FTLB |
284 | * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the |
285 | * FTLB and 1 goes to the VTLB. |
286 | * 2 = 7:1: As above with 7:1 ratio. |
287 | * 3 = 3:1: As above with 3:1 ratio. |
288 | * |
289 | * Use the linear midpoint as the probability threshold. |
290 | */ |
291 | if (probability >= 12) |
292 | return 1; |
293 | else if (probability >= 6) |
294 | return 2; |
295 | else |
296 | /* |
297 | * So FTLB is less than 4 times bigger than VTLB. |
298 | * A 3:1 ratio can still be useful though. |
299 | */ |
300 | return 3; |
301 | } |
302 | |
303 | static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags) |
304 | { |
305 | unsigned int config; |
306 | |
307 | /* It's implementation dependent how the FTLB can be enabled */ |
308 | switch (c->cputype) { |
309 | case CPU_PROAPTIV: |
310 | case CPU_P5600: |
311 | case CPU_P6600: |
312 | /* proAptiv & related cores use Config6 to enable the FTLB */ |
313 | config = read_c0_config6(); |
314 | |
315 | if (flags & FTLB_EN) |
316 | config |= MTI_CONF6_FTLBEN; |
317 | else |
318 | config &= ~MTI_CONF6_FTLBEN; |
319 | |
320 | if (flags & FTLB_SET_PROB) { |
321 | config &= ~(3 << MTI_CONF6_FTLBP_SHIFT); |
322 | config |= calculate_ftlb_probability(c) |
323 | << MTI_CONF6_FTLBP_SHIFT; |
324 | } |
325 | |
326 | write_c0_config6(config); |
327 | back_to_back_c0_hazard(); |
328 | break; |
329 | case CPU_I6400: |
330 | case CPU_I6500: |
331 | /* There's no way to disable the FTLB */ |
332 | if (!(flags & FTLB_EN)) |
333 | return 1; |
334 | return 0; |
335 | case CPU_LOONGSON64: |
336 | /* Flush ITLB, DTLB, VTLB and FTLB */ |
337 | write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB | |
338 | LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB); |
339 | /* Loongson-3 cores use Config6 to enable the FTLB */ |
340 | config = read_c0_config6(); |
341 | if (flags & FTLB_EN) |
342 | /* Enable FTLB */ |
343 | write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS); |
344 | else |
345 | /* Disable FTLB */ |
346 | write_c0_config6(config | LOONGSON_CONF6_FTLBDIS); |
347 | break; |
348 | default: |
349 | return 1; |
350 | } |
351 | |
352 | return 0; |
353 | } |
354 | |
355 | static int mm_config(struct cpuinfo_mips *c) |
356 | { |
357 | unsigned int config0, update, mm; |
358 | |
359 | config0 = read_c0_config(); |
360 | mm = config0 & MIPS_CONF_MM; |
361 | |
362 | /* |
363 | * It's implementation dependent what type of write-merge is supported |
364 | * and whether it can be enabled/disabled. If it is settable lets make |
365 | * the merging allowed by default. Some platforms might have |
366 | * write-through caching unsupported. In this case just ignore the |
367 | * CP0.Config.MM bit field value. |
368 | */ |
369 | switch (c->cputype) { |
370 | case CPU_24K: |
371 | case CPU_34K: |
372 | case CPU_74K: |
373 | case CPU_P5600: |
374 | case CPU_P6600: |
375 | c->options |= MIPS_CPU_MM_FULL; |
376 | update = MIPS_CONF_MM_FULL; |
377 | break; |
378 | case CPU_1004K: |
379 | case CPU_1074K: |
380 | case CPU_INTERAPTIV: |
381 | case CPU_PROAPTIV: |
382 | mm = 0; |
383 | fallthrough; |
384 | default: |
385 | update = 0; |
386 | break; |
387 | } |
388 | |
389 | if (update) { |
390 | config0 = (config0 & ~MIPS_CONF_MM) | update; |
391 | write_c0_config(config0); |
392 | } else if (mm == MIPS_CONF_MM_SYSAD) { |
393 | c->options |= MIPS_CPU_MM_SYSAD; |
394 | } else if (mm == MIPS_CONF_MM_FULL) { |
395 | c->options |= MIPS_CPU_MM_FULL; |
396 | } |
397 | |
398 | return 0; |
399 | } |
400 | |
401 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
402 | { |
403 | unsigned int config0; |
404 | int isa, mt; |
405 | |
406 | config0 = read_c0_config(); |
407 | |
408 | /* |
409 | * Look for Standard TLB or Dual VTLB and FTLB |
410 | */ |
411 | mt = config0 & MIPS_CONF_MT; |
412 | if (mt == MIPS_CONF_MT_TLB) |
413 | c->options |= MIPS_CPU_TLB; |
414 | else if (mt == MIPS_CONF_MT_FTLB) |
415 | c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB; |
416 | |
417 | isa = (config0 & MIPS_CONF_AT) >> 13; |
418 | switch (isa) { |
419 | case 0: |
420 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
421 | case 0: |
422 | set_isa(c, MIPS_CPU_ISA_M32R1); |
423 | break; |
424 | case 1: |
425 | set_isa(c, MIPS_CPU_ISA_M32R2); |
426 | break; |
427 | case 2: |
428 | set_isa(c, MIPS_CPU_ISA_M32R6); |
429 | break; |
430 | default: |
431 | goto unknown; |
432 | } |
433 | break; |
434 | case 2: |
435 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
436 | case 0: |
437 | set_isa(c, MIPS_CPU_ISA_M64R1); |
438 | break; |
439 | case 1: |
440 | set_isa(c, MIPS_CPU_ISA_M64R2); |
441 | break; |
442 | case 2: |
443 | set_isa(c, MIPS_CPU_ISA_M64R6); |
444 | break; |
445 | default: |
446 | goto unknown; |
447 | } |
448 | break; |
449 | default: |
450 | goto unknown; |
451 | } |
452 | |
453 | return config0 & MIPS_CONF_M; |
454 | |
455 | unknown: |
456 | panic(fmt: unknown_isa, config0); |
457 | } |
458 | |
459 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) |
460 | { |
461 | unsigned int config1; |
462 | |
463 | config1 = read_c0_config1(); |
464 | |
465 | if (config1 & MIPS_CONF1_MD) |
466 | c->ases |= MIPS_ASE_MDMX; |
467 | if (config1 & MIPS_CONF1_PC) |
468 | c->options |= MIPS_CPU_PERF; |
469 | if (config1 & MIPS_CONF1_WR) |
470 | c->options |= MIPS_CPU_WATCH; |
471 | if (config1 & MIPS_CONF1_CA) |
472 | c->ases |= MIPS_ASE_MIPS16; |
473 | if (config1 & MIPS_CONF1_EP) |
474 | c->options |= MIPS_CPU_EJTAG; |
475 | if (config1 & MIPS_CONF1_FP) { |
476 | c->options |= MIPS_CPU_FPU; |
477 | c->options |= MIPS_CPU_32FPR; |
478 | } |
479 | if (cpu_has_tlb) { |
480 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
481 | c->tlbsizevtlb = c->tlbsize; |
482 | c->tlbsizeftlbsets = 0; |
483 | } |
484 | |
485 | return config1 & MIPS_CONF_M; |
486 | } |
487 | |
488 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) |
489 | { |
490 | unsigned int config2; |
491 | |
492 | config2 = read_c0_config2(); |
493 | |
494 | if (config2 & MIPS_CONF2_SL) |
495 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
496 | |
497 | return config2 & MIPS_CONF_M; |
498 | } |
499 | |
500 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) |
501 | { |
502 | unsigned int config3; |
503 | |
504 | config3 = read_c0_config3(); |
505 | |
506 | if (config3 & MIPS_CONF3_SM) { |
507 | c->ases |= MIPS_ASE_SMARTMIPS; |
508 | c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC; |
509 | } |
510 | if (config3 & MIPS_CONF3_RXI) |
511 | c->options |= MIPS_CPU_RIXI; |
512 | if (config3 & MIPS_CONF3_CTXTC) |
513 | c->options |= MIPS_CPU_CTXTC; |
514 | if (config3 & MIPS_CONF3_DSP) |
515 | c->ases |= MIPS_ASE_DSP; |
516 | if (config3 & MIPS_CONF3_DSP2P) { |
517 | c->ases |= MIPS_ASE_DSP2P; |
518 | if (cpu_has_mips_r6) |
519 | c->ases |= MIPS_ASE_DSP3; |
520 | } |
521 | if (config3 & MIPS_CONF3_VINT) |
522 | c->options |= MIPS_CPU_VINT; |
523 | if (config3 & MIPS_CONF3_VEIC) |
524 | c->options |= MIPS_CPU_VEIC; |
525 | if (config3 & MIPS_CONF3_LPA) |
526 | c->options |= MIPS_CPU_LPA; |
527 | if (config3 & MIPS_CONF3_MT) |
528 | c->ases |= MIPS_ASE_MIPSMT; |
529 | if (config3 & MIPS_CONF3_ULRI) |
530 | c->options |= MIPS_CPU_ULRI; |
531 | if (config3 & MIPS_CONF3_ISA) |
532 | c->options |= MIPS_CPU_MICROMIPS; |
533 | if (config3 & MIPS_CONF3_VZ) |
534 | c->ases |= MIPS_ASE_VZ; |
535 | if (config3 & MIPS_CONF3_SC) |
536 | c->options |= MIPS_CPU_SEGMENTS; |
537 | if (config3 & MIPS_CONF3_BI) |
538 | c->options |= MIPS_CPU_BADINSTR; |
539 | if (config3 & MIPS_CONF3_BP) |
540 | c->options |= MIPS_CPU_BADINSTRP; |
541 | if (config3 & MIPS_CONF3_MSA) |
542 | c->ases |= MIPS_ASE_MSA; |
543 | if (config3 & MIPS_CONF3_PW) { |
544 | c->htw_seq = 0; |
545 | c->options |= MIPS_CPU_HTW; |
546 | } |
547 | if (config3 & MIPS_CONF3_CDMM) |
548 | c->options |= MIPS_CPU_CDMM; |
549 | if (config3 & MIPS_CONF3_SP) |
550 | c->options |= MIPS_CPU_SP; |
551 | |
552 | return config3 & MIPS_CONF_M; |
553 | } |
554 | |
555 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) |
556 | { |
557 | unsigned int config4; |
558 | unsigned int newcf4; |
559 | unsigned int mmuextdef; |
560 | unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; |
561 | unsigned long asid_mask; |
562 | |
563 | config4 = read_c0_config4(); |
564 | |
565 | if (cpu_has_tlb) { |
566 | if (((config4 & MIPS_CONF4_IE) >> 29) == 2) |
567 | c->options |= MIPS_CPU_TLBINV; |
568 | |
569 | /* |
570 | * R6 has dropped the MMUExtDef field from config4. |
571 | * On R6 the fields always describe the FTLB, and only if it is |
572 | * present according to Config.MT. |
573 | */ |
574 | if (!cpu_has_mips_r6) |
575 | mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; |
576 | else if (cpu_has_ftlb) |
577 | mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT; |
578 | else |
579 | mmuextdef = 0; |
580 | |
581 | switch (mmuextdef) { |
582 | case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: |
583 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; |
584 | c->tlbsizevtlb = c->tlbsize; |
585 | break; |
586 | case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: |
587 | c->tlbsizevtlb += |
588 | ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> |
589 | MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; |
590 | c->tlbsize = c->tlbsizevtlb; |
591 | ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; |
592 | fallthrough; |
593 | case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: |
594 | if (mips_ftlb_disabled) |
595 | break; |
596 | newcf4 = (config4 & ~ftlb_page) | |
597 | (page_size_ftlb(mmuextdef) << |
598 | MIPS_CONF4_FTLBPAGESIZE_SHIFT); |
599 | write_c0_config4(newcf4); |
600 | back_to_back_c0_hazard(); |
601 | config4 = read_c0_config4(); |
602 | if (config4 != newcf4) { |
603 | pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n" , |
604 | PAGE_SIZE, config4); |
605 | /* Switch FTLB off */ |
606 | set_ftlb_enable(c, flags: 0); |
607 | mips_ftlb_disabled = 1; |
608 | break; |
609 | } |
610 | c->tlbsizeftlbsets = 1 << |
611 | ((config4 & MIPS_CONF4_FTLBSETS) >> |
612 | MIPS_CONF4_FTLBSETS_SHIFT); |
613 | c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> |
614 | MIPS_CONF4_FTLBWAYS_SHIFT) + 2; |
615 | c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; |
616 | mips_has_ftlb_configured = 1; |
617 | break; |
618 | } |
619 | } |
620 | |
621 | c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) |
622 | >> MIPS_CONF4_KSCREXIST_SHIFT; |
623 | |
624 | asid_mask = MIPS_ENTRYHI_ASID; |
625 | if (config4 & MIPS_CONF4_AE) |
626 | asid_mask |= MIPS_ENTRYHI_ASIDX; |
627 | set_cpu_asid_mask(c, asid_mask); |
628 | |
629 | /* |
630 | * Warn if the computed ASID mask doesn't match the mask the kernel |
631 | * is built for. This may indicate either a serious problem or an |
632 | * easy optimisation opportunity, but either way should be addressed. |
633 | */ |
634 | WARN_ON(asid_mask != cpu_asid_mask(c)); |
635 | |
636 | return config4 & MIPS_CONF_M; |
637 | } |
638 | |
639 | static inline unsigned int decode_config5(struct cpuinfo_mips *c) |
640 | { |
641 | unsigned int config5, max_mmid_width; |
642 | unsigned long asid_mask; |
643 | |
644 | config5 = read_c0_config5(); |
645 | config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE); |
646 | |
647 | if (cpu_has_mips_r6) { |
648 | if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid) |
649 | config5 |= MIPS_CONF5_MI; |
650 | else |
651 | config5 &= ~MIPS_CONF5_MI; |
652 | } |
653 | |
654 | write_c0_config5(config5); |
655 | |
656 | if (config5 & MIPS_CONF5_EVA) |
657 | c->options |= MIPS_CPU_EVA; |
658 | if (config5 & MIPS_CONF5_MRP) |
659 | c->options |= MIPS_CPU_MAAR; |
660 | if (config5 & MIPS_CONF5_LLB) |
661 | c->options |= MIPS_CPU_RW_LLB; |
662 | if (config5 & MIPS_CONF5_MVH) |
663 | c->options |= MIPS_CPU_MVH; |
664 | if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP)) |
665 | c->options |= MIPS_CPU_VP; |
666 | if (config5 & MIPS_CONF5_CA2) |
667 | c->ases |= MIPS_ASE_MIPS16E2; |
668 | |
669 | if (config5 & MIPS_CONF5_CRCP) |
670 | elf_hwcap |= HWCAP_MIPS_CRC32; |
671 | |
672 | if (cpu_has_mips_r6) { |
673 | /* Ensure the write to config5 above takes effect */ |
674 | back_to_back_c0_hazard(); |
675 | |
676 | /* Check whether we successfully enabled MMID support */ |
677 | config5 = read_c0_config5(); |
678 | if (config5 & MIPS_CONF5_MI) |
679 | c->options |= MIPS_CPU_MMID; |
680 | |
681 | /* |
682 | * Warn if we've hardcoded cpu_has_mmid to a value unsuitable |
683 | * for the CPU we're running on, or if CPUs in an SMP system |
684 | * have inconsistent MMID support. |
685 | */ |
686 | WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI)); |
687 | |
688 | if (cpu_has_mmid) { |
689 | write_c0_memorymapid(~0ul); |
690 | back_to_back_c0_hazard(); |
691 | asid_mask = read_c0_memorymapid(); |
692 | |
693 | /* |
694 | * We maintain a bitmap to track MMID allocation, and |
695 | * need a sensible upper bound on the size of that |
696 | * bitmap. The initial CPU with MMID support (I6500) |
697 | * supports 16 bit MMIDs, which gives us an 8KiB |
698 | * bitmap. The architecture recommends that hardware |
699 | * support 32 bit MMIDs, which would give us a 512MiB |
700 | * bitmap - that's too big in most cases. |
701 | * |
702 | * Cap MMID width at 16 bits for now & we can revisit |
703 | * this if & when hardware supports anything wider. |
704 | */ |
705 | max_mmid_width = 16; |
706 | if (asid_mask > GENMASK(max_mmid_width - 1, 0)) { |
707 | pr_info("Capping MMID width at %d bits" , |
708 | max_mmid_width); |
709 | asid_mask = GENMASK(max_mmid_width - 1, 0); |
710 | } |
711 | |
712 | set_cpu_asid_mask(c, asid_mask); |
713 | } |
714 | } |
715 | |
716 | return config5 & MIPS_CONF_M; |
717 | } |
718 | |
719 | static void decode_configs(struct cpuinfo_mips *c) |
720 | { |
721 | int ok; |
722 | |
723 | /* MIPS32 or MIPS64 compliant CPU. */ |
724 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
725 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; |
726 | |
727 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
728 | |
729 | /* Enable FTLB if present and not disabled */ |
730 | set_ftlb_enable(c, flags: mips_ftlb_disabled ? 0 : FTLB_EN); |
731 | |
732 | ok = decode_config0(c); /* Read Config registers. */ |
733 | BUG_ON(!ok); /* Arch spec violation! */ |
734 | if (ok) |
735 | ok = decode_config1(c); |
736 | if (ok) |
737 | ok = decode_config2(c); |
738 | if (ok) |
739 | ok = decode_config3(c); |
740 | if (ok) |
741 | ok = decode_config4(c); |
742 | if (ok) |
743 | ok = decode_config5(c); |
744 | |
745 | /* Probe the EBase.WG bit */ |
746 | if (cpu_has_mips_r2_r6) { |
747 | u64 ebase; |
748 | unsigned int status; |
749 | |
750 | /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */ |
751 | ebase = cpu_has_mips64r6 ? read_c0_ebase_64() |
752 | : (s32)read_c0_ebase(); |
753 | if (ebase & MIPS_EBASE_WG) { |
754 | /* WG bit already set, we can avoid the clumsy probe */ |
755 | c->options |= MIPS_CPU_EBASE_WG; |
756 | } else { |
757 | /* Its UNDEFINED to change EBase while BEV=0 */ |
758 | status = read_c0_status(); |
759 | write_c0_status(status | ST0_BEV); |
760 | irq_enable_hazard(); |
761 | /* |
762 | * On pre-r6 cores, this may well clobber the upper bits |
763 | * of EBase. This is hard to avoid without potentially |
764 | * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit. |
765 | */ |
766 | if (cpu_has_mips64r6) |
767 | write_c0_ebase_64(ebase | MIPS_EBASE_WG); |
768 | else |
769 | write_c0_ebase(ebase | MIPS_EBASE_WG); |
770 | back_to_back_c0_hazard(); |
771 | /* Restore BEV */ |
772 | write_c0_status(status); |
773 | if (read_c0_ebase() & MIPS_EBASE_WG) { |
774 | c->options |= MIPS_CPU_EBASE_WG; |
775 | write_c0_ebase(ebase); |
776 | } |
777 | } |
778 | } |
779 | |
780 | /* configure the FTLB write probability */ |
781 | set_ftlb_enable(c, flags: (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB); |
782 | |
783 | mips_probe_watch_registers(c); |
784 | |
785 | #ifndef CONFIG_MIPS_CPS |
786 | if (cpu_has_mips_r2_r6) { |
787 | unsigned int core; |
788 | |
789 | core = get_ebase_cpunum(); |
790 | if (cpu_has_mipsmt) |
791 | core >>= fls(x: core_nvpes()) - 1; |
792 | cpu_set_core(c, core); |
793 | } |
794 | #endif |
795 | } |
796 | |
797 | /* |
798 | * Probe for certain guest capabilities by writing config bits and reading back. |
799 | * Finally write back the original value. |
800 | */ |
801 | #define probe_gc0_config(name, maxconf, bits) \ |
802 | do { \ |
803 | unsigned int tmp; \ |
804 | tmp = read_gc0_##name(); \ |
805 | write_gc0_##name(tmp | (bits)); \ |
806 | back_to_back_c0_hazard(); \ |
807 | maxconf = read_gc0_##name(); \ |
808 | write_gc0_##name(tmp); \ |
809 | } while (0) |
810 | |
811 | /* |
812 | * Probe for dynamic guest capabilities by changing certain config bits and |
813 | * reading back to see if they change. Finally write back the original value. |
814 | */ |
815 | #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \ |
816 | do { \ |
817 | maxconf = read_gc0_##name(); \ |
818 | write_gc0_##name(maxconf ^ (bits)); \ |
819 | back_to_back_c0_hazard(); \ |
820 | dynconf = maxconf ^ read_gc0_##name(); \ |
821 | write_gc0_##name(maxconf); \ |
822 | maxconf |= dynconf; \ |
823 | } while (0) |
824 | |
825 | static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c) |
826 | { |
827 | unsigned int config0; |
828 | |
829 | probe_gc0_config(config, config0, MIPS_CONF_M); |
830 | |
831 | if (config0 & MIPS_CONF_M) |
832 | c->guest.conf |= BIT(1); |
833 | return config0 & MIPS_CONF_M; |
834 | } |
835 | |
836 | static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c) |
837 | { |
838 | unsigned int config1, config1_dyn; |
839 | |
840 | probe_gc0_config_dyn(config1, config1, config1_dyn, |
841 | MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR | |
842 | MIPS_CONF1_FP); |
843 | |
844 | if (config1 & MIPS_CONF1_FP) |
845 | c->guest.options |= MIPS_CPU_FPU; |
846 | if (config1_dyn & MIPS_CONF1_FP) |
847 | c->guest.options_dyn |= MIPS_CPU_FPU; |
848 | |
849 | if (config1 & MIPS_CONF1_WR) |
850 | c->guest.options |= MIPS_CPU_WATCH; |
851 | if (config1_dyn & MIPS_CONF1_WR) |
852 | c->guest.options_dyn |= MIPS_CPU_WATCH; |
853 | |
854 | if (config1 & MIPS_CONF1_PC) |
855 | c->guest.options |= MIPS_CPU_PERF; |
856 | if (config1_dyn & MIPS_CONF1_PC) |
857 | c->guest.options_dyn |= MIPS_CPU_PERF; |
858 | |
859 | if (config1 & MIPS_CONF_M) |
860 | c->guest.conf |= BIT(2); |
861 | return config1 & MIPS_CONF_M; |
862 | } |
863 | |
864 | static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c) |
865 | { |
866 | unsigned int config2; |
867 | |
868 | probe_gc0_config(config2, config2, MIPS_CONF_M); |
869 | |
870 | if (config2 & MIPS_CONF_M) |
871 | c->guest.conf |= BIT(3); |
872 | return config2 & MIPS_CONF_M; |
873 | } |
874 | |
875 | static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c) |
876 | { |
877 | unsigned int config3, config3_dyn; |
878 | |
879 | probe_gc0_config_dyn(config3, config3, config3_dyn, |
880 | MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI | |
881 | MIPS_CONF3_CTXTC); |
882 | |
883 | if (config3 & MIPS_CONF3_CTXTC) |
884 | c->guest.options |= MIPS_CPU_CTXTC; |
885 | if (config3_dyn & MIPS_CONF3_CTXTC) |
886 | c->guest.options_dyn |= MIPS_CPU_CTXTC; |
887 | |
888 | if (config3 & MIPS_CONF3_PW) |
889 | c->guest.options |= MIPS_CPU_HTW; |
890 | |
891 | if (config3 & MIPS_CONF3_ULRI) |
892 | c->guest.options |= MIPS_CPU_ULRI; |
893 | |
894 | if (config3 & MIPS_CONF3_SC) |
895 | c->guest.options |= MIPS_CPU_SEGMENTS; |
896 | |
897 | if (config3 & MIPS_CONF3_BI) |
898 | c->guest.options |= MIPS_CPU_BADINSTR; |
899 | if (config3 & MIPS_CONF3_BP) |
900 | c->guest.options |= MIPS_CPU_BADINSTRP; |
901 | |
902 | if (config3 & MIPS_CONF3_MSA) |
903 | c->guest.ases |= MIPS_ASE_MSA; |
904 | if (config3_dyn & MIPS_CONF3_MSA) |
905 | c->guest.ases_dyn |= MIPS_ASE_MSA; |
906 | |
907 | if (config3 & MIPS_CONF_M) |
908 | c->guest.conf |= BIT(4); |
909 | return config3 & MIPS_CONF_M; |
910 | } |
911 | |
912 | static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c) |
913 | { |
914 | unsigned int config4; |
915 | |
916 | probe_gc0_config(config4, config4, |
917 | MIPS_CONF_M | MIPS_CONF4_KSCREXIST); |
918 | |
919 | c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST) |
920 | >> MIPS_CONF4_KSCREXIST_SHIFT; |
921 | |
922 | if (config4 & MIPS_CONF_M) |
923 | c->guest.conf |= BIT(5); |
924 | return config4 & MIPS_CONF_M; |
925 | } |
926 | |
927 | static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c) |
928 | { |
929 | unsigned int config5, config5_dyn; |
930 | |
931 | probe_gc0_config_dyn(config5, config5, config5_dyn, |
932 | MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP); |
933 | |
934 | if (config5 & MIPS_CONF5_MRP) |
935 | c->guest.options |= MIPS_CPU_MAAR; |
936 | if (config5_dyn & MIPS_CONF5_MRP) |
937 | c->guest.options_dyn |= MIPS_CPU_MAAR; |
938 | |
939 | if (config5 & MIPS_CONF5_LLB) |
940 | c->guest.options |= MIPS_CPU_RW_LLB; |
941 | |
942 | if (config5 & MIPS_CONF5_MVH) |
943 | c->guest.options |= MIPS_CPU_MVH; |
944 | |
945 | if (config5 & MIPS_CONF_M) |
946 | c->guest.conf |= BIT(6); |
947 | return config5 & MIPS_CONF_M; |
948 | } |
949 | |
950 | static inline void decode_guest_configs(struct cpuinfo_mips *c) |
951 | { |
952 | unsigned int ok; |
953 | |
954 | ok = decode_guest_config0(c); |
955 | if (ok) |
956 | ok = decode_guest_config1(c); |
957 | if (ok) |
958 | ok = decode_guest_config2(c); |
959 | if (ok) |
960 | ok = decode_guest_config3(c); |
961 | if (ok) |
962 | ok = decode_guest_config4(c); |
963 | if (ok) |
964 | decode_guest_config5(c); |
965 | } |
966 | |
967 | static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c) |
968 | { |
969 | unsigned int guestctl0, temp; |
970 | |
971 | guestctl0 = read_c0_guestctl0(); |
972 | |
973 | if (guestctl0 & MIPS_GCTL0_G0E) |
974 | c->options |= MIPS_CPU_GUESTCTL0EXT; |
975 | if (guestctl0 & MIPS_GCTL0_G1) |
976 | c->options |= MIPS_CPU_GUESTCTL1; |
977 | if (guestctl0 & MIPS_GCTL0_G2) |
978 | c->options |= MIPS_CPU_GUESTCTL2; |
979 | if (!(guestctl0 & MIPS_GCTL0_RAD)) { |
980 | c->options |= MIPS_CPU_GUESTID; |
981 | |
982 | /* |
983 | * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0 |
984 | * first, otherwise all data accesses will be fully virtualised |
985 | * as if they were performed by guest mode. |
986 | */ |
987 | write_c0_guestctl1(0); |
988 | tlbw_use_hazard(); |
989 | |
990 | write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG); |
991 | back_to_back_c0_hazard(); |
992 | temp = read_c0_guestctl0(); |
993 | |
994 | if (temp & MIPS_GCTL0_DRG) { |
995 | write_c0_guestctl0(guestctl0); |
996 | c->options |= MIPS_CPU_DRG; |
997 | } |
998 | } |
999 | } |
1000 | |
1001 | static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c) |
1002 | { |
1003 | if (cpu_has_guestid) { |
1004 | /* determine the number of bits of GuestID available */ |
1005 | write_c0_guestctl1(MIPS_GCTL1_ID); |
1006 | back_to_back_c0_hazard(); |
1007 | c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID) |
1008 | >> MIPS_GCTL1_ID_SHIFT; |
1009 | write_c0_guestctl1(0); |
1010 | } |
1011 | } |
1012 | |
1013 | static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c) |
1014 | { |
1015 | /* determine the number of bits of GTOffset available */ |
1016 | write_c0_gtoffset(0xffffffff); |
1017 | back_to_back_c0_hazard(); |
1018 | c->gtoffset_mask = read_c0_gtoffset(); |
1019 | write_c0_gtoffset(0); |
1020 | } |
1021 | |
1022 | static inline void cpu_probe_vz(struct cpuinfo_mips *c) |
1023 | { |
1024 | cpu_probe_guestctl0(c); |
1025 | if (cpu_has_guestctl1) |
1026 | cpu_probe_guestctl1(c); |
1027 | |
1028 | cpu_probe_gtoffset(c); |
1029 | |
1030 | decode_guest_configs(c); |
1031 | } |
1032 | |
1033 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
1034 | | MIPS_CPU_COUNTER) |
1035 | |
1036 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
1037 | { |
1038 | switch (c->processor_id & PRID_IMP_MASK) { |
1039 | case PRID_IMP_R2000: |
1040 | c->cputype = CPU_R2000; |
1041 | __cpu_name[cpu] = "R2000" ; |
1042 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1043 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
1044 | MIPS_CPU_NOFPUEX; |
1045 | if (__cpu_has_fpu()) |
1046 | c->options |= MIPS_CPU_FPU; |
1047 | c->tlbsize = 64; |
1048 | break; |
1049 | case PRID_IMP_R3000: |
1050 | if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) { |
1051 | if (cpu_has_confreg()) { |
1052 | c->cputype = CPU_R3081E; |
1053 | __cpu_name[cpu] = "R3081" ; |
1054 | } else { |
1055 | c->cputype = CPU_R3000A; |
1056 | __cpu_name[cpu] = "R3000A" ; |
1057 | } |
1058 | } else { |
1059 | c->cputype = CPU_R3000; |
1060 | __cpu_name[cpu] = "R3000" ; |
1061 | } |
1062 | c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS; |
1063 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
1064 | MIPS_CPU_NOFPUEX; |
1065 | if (__cpu_has_fpu()) |
1066 | c->options |= MIPS_CPU_FPU; |
1067 | c->tlbsize = 64; |
1068 | break; |
1069 | case PRID_IMP_R4000: |
1070 | if (read_c0_config() & CONF_SC) { |
1071 | if ((c->processor_id & PRID_REV_MASK) >= |
1072 | PRID_REV_R4400) { |
1073 | c->cputype = CPU_R4400PC; |
1074 | __cpu_name[cpu] = "R4400PC" ; |
1075 | } else { |
1076 | c->cputype = CPU_R4000PC; |
1077 | __cpu_name[cpu] = "R4000PC" ; |
1078 | } |
1079 | } else { |
1080 | int cca = read_c0_config() & CONF_CM_CMASK; |
1081 | int mc; |
1082 | |
1083 | /* |
1084 | * SC and MC versions can't be reliably told apart, |
1085 | * but only the latter support coherent caching |
1086 | * modes so assume the firmware has set the KSEG0 |
1087 | * coherency attribute reasonably (if uncached, we |
1088 | * assume SC). |
1089 | */ |
1090 | switch (cca) { |
1091 | case CONF_CM_CACHABLE_CE: |
1092 | case CONF_CM_CACHABLE_COW: |
1093 | case CONF_CM_CACHABLE_CUW: |
1094 | mc = 1; |
1095 | break; |
1096 | default: |
1097 | mc = 0; |
1098 | break; |
1099 | } |
1100 | if ((c->processor_id & PRID_REV_MASK) >= |
1101 | PRID_REV_R4400) { |
1102 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
1103 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC" ; |
1104 | } else { |
1105 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
1106 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC" ; |
1107 | } |
1108 | } |
1109 | |
1110 | set_isa(c, MIPS_CPU_ISA_III); |
1111 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1112 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1113 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
1114 | MIPS_CPU_LLSC; |
1115 | c->tlbsize = 48; |
1116 | break; |
1117 | case PRID_IMP_R4300: |
1118 | c->cputype = CPU_R4300; |
1119 | __cpu_name[cpu] = "R4300" ; |
1120 | set_isa(c, MIPS_CPU_ISA_III); |
1121 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1122 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1123 | MIPS_CPU_LLSC; |
1124 | c->tlbsize = 32; |
1125 | break; |
1126 | case PRID_IMP_R4600: |
1127 | c->cputype = CPU_R4600; |
1128 | __cpu_name[cpu] = "R4600" ; |
1129 | set_isa(c, MIPS_CPU_ISA_III); |
1130 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1131 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1132 | MIPS_CPU_LLSC; |
1133 | c->tlbsize = 48; |
1134 | break; |
1135 | #if 0 |
1136 | case PRID_IMP_R4650: |
1137 | /* |
1138 | * This processor doesn't have an MMU, so it's not |
1139 | * "real easy" to run Linux on it. It is left purely |
1140 | * for documentation. Commented out because it shares |
1141 | * its c0_prid id number with the TX3900. |
1142 | */ |
1143 | c->cputype = CPU_R4650; |
1144 | __cpu_name[cpu] = "R4650" ; |
1145 | set_isa(c, MIPS_CPU_ISA_III); |
1146 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1147 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
1148 | c->tlbsize = 48; |
1149 | break; |
1150 | #endif |
1151 | case PRID_IMP_R4700: |
1152 | c->cputype = CPU_R4700; |
1153 | __cpu_name[cpu] = "R4700" ; |
1154 | set_isa(c, MIPS_CPU_ISA_III); |
1155 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1156 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1157 | MIPS_CPU_LLSC; |
1158 | c->tlbsize = 48; |
1159 | break; |
1160 | case PRID_IMP_TX49: |
1161 | c->cputype = CPU_TX49XX; |
1162 | __cpu_name[cpu] = "R49XX" ; |
1163 | set_isa(c, MIPS_CPU_ISA_III); |
1164 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1165 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
1166 | if (!(c->processor_id & 0x08)) |
1167 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; |
1168 | c->tlbsize = 48; |
1169 | break; |
1170 | case PRID_IMP_R5000: |
1171 | c->cputype = CPU_R5000; |
1172 | __cpu_name[cpu] = "R5000" ; |
1173 | set_isa(c, MIPS_CPU_ISA_IV); |
1174 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1175 | MIPS_CPU_LLSC; |
1176 | c->tlbsize = 48; |
1177 | break; |
1178 | case PRID_IMP_R5500: |
1179 | c->cputype = CPU_R5500; |
1180 | __cpu_name[cpu] = "R5500" ; |
1181 | set_isa(c, MIPS_CPU_ISA_IV); |
1182 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1183 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
1184 | c->tlbsize = 48; |
1185 | break; |
1186 | case PRID_IMP_NEVADA: |
1187 | c->cputype = CPU_NEVADA; |
1188 | __cpu_name[cpu] = "Nevada" ; |
1189 | set_isa(c, MIPS_CPU_ISA_IV); |
1190 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1191 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
1192 | c->tlbsize = 48; |
1193 | break; |
1194 | case PRID_IMP_RM7000: |
1195 | c->cputype = CPU_RM7000; |
1196 | __cpu_name[cpu] = "RM7000" ; |
1197 | set_isa(c, MIPS_CPU_ISA_IV); |
1198 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1199 | MIPS_CPU_LLSC; |
1200 | /* |
1201 | * Undocumented RM7000: Bit 29 in the info register of |
1202 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
1203 | * entries. |
1204 | * |
1205 | * 29 1 => 64 entry JTLB |
1206 | * 0 => 48 entry JTLB |
1207 | */ |
1208 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
1209 | break; |
1210 | case PRID_IMP_R10000: |
1211 | c->cputype = CPU_R10000; |
1212 | __cpu_name[cpu] = "R10000" ; |
1213 | set_isa(c, MIPS_CPU_ISA_IV); |
1214 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1215 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1216 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
1217 | MIPS_CPU_LLSC; |
1218 | c->tlbsize = 64; |
1219 | break; |
1220 | case PRID_IMP_R12000: |
1221 | c->cputype = CPU_R12000; |
1222 | __cpu_name[cpu] = "R12000" ; |
1223 | set_isa(c, MIPS_CPU_ISA_IV); |
1224 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1225 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1226 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
1227 | MIPS_CPU_LLSC; |
1228 | c->tlbsize = 64; |
1229 | write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); |
1230 | break; |
1231 | case PRID_IMP_R14000: |
1232 | if (((c->processor_id >> 4) & 0x0f) > 2) { |
1233 | c->cputype = CPU_R16000; |
1234 | __cpu_name[cpu] = "R16000" ; |
1235 | } else { |
1236 | c->cputype = CPU_R14000; |
1237 | __cpu_name[cpu] = "R14000" ; |
1238 | } |
1239 | set_isa(c, MIPS_CPU_ISA_IV); |
1240 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
1241 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
1242 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
1243 | MIPS_CPU_LLSC; |
1244 | c->tlbsize = 64; |
1245 | write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST); |
1246 | break; |
1247 | case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */ |
1248 | switch (c->processor_id & PRID_REV_MASK) { |
1249 | case PRID_REV_LOONGSON2E: |
1250 | c->cputype = CPU_LOONGSON2EF; |
1251 | __cpu_name[cpu] = "ICT Loongson-2" ; |
1252 | set_elf_platform(cpu, plat: "loongson2e" ); |
1253 | set_isa(c, MIPS_CPU_ISA_III); |
1254 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1255 | break; |
1256 | case PRID_REV_LOONGSON2F: |
1257 | c->cputype = CPU_LOONGSON2EF; |
1258 | __cpu_name[cpu] = "ICT Loongson-2" ; |
1259 | set_elf_platform(cpu, plat: "loongson2f" ); |
1260 | set_isa(c, MIPS_CPU_ISA_III); |
1261 | c->fpu_msk31 |= FPU_CSR_CONDX; |
1262 | break; |
1263 | case PRID_REV_LOONGSON3A_R1: |
1264 | c->cputype = CPU_LOONGSON64; |
1265 | __cpu_name[cpu] = "ICT Loongson-3" ; |
1266 | set_elf_platform(cpu, plat: "loongson3a" ); |
1267 | set_isa(c, MIPS_CPU_ISA_M64R1); |
1268 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | |
1269 | MIPS_ASE_LOONGSON_EXT); |
1270 | break; |
1271 | case PRID_REV_LOONGSON3B_R1: |
1272 | case PRID_REV_LOONGSON3B_R2: |
1273 | c->cputype = CPU_LOONGSON64; |
1274 | __cpu_name[cpu] = "ICT Loongson-3" ; |
1275 | set_elf_platform(cpu, plat: "loongson3b" ); |
1276 | set_isa(c, MIPS_CPU_ISA_M64R1); |
1277 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | |
1278 | MIPS_ASE_LOONGSON_EXT); |
1279 | break; |
1280 | } |
1281 | |
1282 | c->options = R4K_OPTS | |
1283 | MIPS_CPU_FPU | MIPS_CPU_LLSC | |
1284 | MIPS_CPU_32FPR; |
1285 | c->tlbsize = 64; |
1286 | set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID); |
1287 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
1288 | break; |
1289 | case PRID_IMP_LOONGSON_32: /* Loongson-1 */ |
1290 | decode_configs(c); |
1291 | |
1292 | c->cputype = CPU_LOONGSON32; |
1293 | |
1294 | switch (c->processor_id & PRID_REV_MASK) { |
1295 | case PRID_REV_LOONGSON1B: |
1296 | __cpu_name[cpu] = "Loongson 1B" ; |
1297 | break; |
1298 | } |
1299 | |
1300 | break; |
1301 | } |
1302 | } |
1303 | |
1304 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
1305 | { |
1306 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
1307 | switch (c->processor_id & PRID_IMP_MASK) { |
1308 | case PRID_IMP_QEMU_GENERIC: |
1309 | c->writecombine = _CACHE_UNCACHED; |
1310 | c->cputype = CPU_QEMU_GENERIC; |
1311 | __cpu_name[cpu] = "MIPS GENERIC QEMU" ; |
1312 | break; |
1313 | case PRID_IMP_4KC: |
1314 | c->cputype = CPU_4KC; |
1315 | c->writecombine = _CACHE_UNCACHED; |
1316 | __cpu_name[cpu] = "MIPS 4Kc" ; |
1317 | break; |
1318 | case PRID_IMP_4KEC: |
1319 | case PRID_IMP_4KECR2: |
1320 | c->cputype = CPU_4KEC; |
1321 | c->writecombine = _CACHE_UNCACHED; |
1322 | __cpu_name[cpu] = "MIPS 4KEc" ; |
1323 | break; |
1324 | case PRID_IMP_4KSC: |
1325 | case PRID_IMP_4KSD: |
1326 | c->cputype = CPU_4KSC; |
1327 | c->writecombine = _CACHE_UNCACHED; |
1328 | __cpu_name[cpu] = "MIPS 4KSc" ; |
1329 | break; |
1330 | case PRID_IMP_5KC: |
1331 | c->cputype = CPU_5KC; |
1332 | c->writecombine = _CACHE_UNCACHED; |
1333 | __cpu_name[cpu] = "MIPS 5Kc" ; |
1334 | break; |
1335 | case PRID_IMP_5KE: |
1336 | c->cputype = CPU_5KE; |
1337 | c->writecombine = _CACHE_UNCACHED; |
1338 | __cpu_name[cpu] = "MIPS 5KE" ; |
1339 | break; |
1340 | case PRID_IMP_20KC: |
1341 | c->cputype = CPU_20KC; |
1342 | c->writecombine = _CACHE_UNCACHED; |
1343 | __cpu_name[cpu] = "MIPS 20Kc" ; |
1344 | break; |
1345 | case PRID_IMP_24K: |
1346 | c->cputype = CPU_24K; |
1347 | c->writecombine = _CACHE_UNCACHED; |
1348 | __cpu_name[cpu] = "MIPS 24Kc" ; |
1349 | break; |
1350 | case PRID_IMP_24KE: |
1351 | c->cputype = CPU_24K; |
1352 | c->writecombine = _CACHE_UNCACHED; |
1353 | __cpu_name[cpu] = "MIPS 24KEc" ; |
1354 | break; |
1355 | case PRID_IMP_25KF: |
1356 | c->cputype = CPU_25KF; |
1357 | c->writecombine = _CACHE_UNCACHED; |
1358 | __cpu_name[cpu] = "MIPS 25Kc" ; |
1359 | break; |
1360 | case PRID_IMP_34K: |
1361 | c->cputype = CPU_34K; |
1362 | c->writecombine = _CACHE_UNCACHED; |
1363 | __cpu_name[cpu] = "MIPS 34Kc" ; |
1364 | cpu_set_mt_per_tc_perf(c); |
1365 | break; |
1366 | case PRID_IMP_74K: |
1367 | c->cputype = CPU_74K; |
1368 | c->writecombine = _CACHE_UNCACHED; |
1369 | __cpu_name[cpu] = "MIPS 74Kc" ; |
1370 | break; |
1371 | case PRID_IMP_M14KC: |
1372 | c->cputype = CPU_M14KC; |
1373 | c->writecombine = _CACHE_UNCACHED; |
1374 | __cpu_name[cpu] = "MIPS M14Kc" ; |
1375 | break; |
1376 | case PRID_IMP_M14KEC: |
1377 | c->cputype = CPU_M14KEC; |
1378 | c->writecombine = _CACHE_UNCACHED; |
1379 | __cpu_name[cpu] = "MIPS M14KEc" ; |
1380 | break; |
1381 | case PRID_IMP_1004K: |
1382 | c->cputype = CPU_1004K; |
1383 | c->writecombine = _CACHE_UNCACHED; |
1384 | __cpu_name[cpu] = "MIPS 1004Kc" ; |
1385 | cpu_set_mt_per_tc_perf(c); |
1386 | break; |
1387 | case PRID_IMP_1074K: |
1388 | c->cputype = CPU_1074K; |
1389 | c->writecombine = _CACHE_UNCACHED; |
1390 | __cpu_name[cpu] = "MIPS 1074Kc" ; |
1391 | break; |
1392 | case PRID_IMP_INTERAPTIV_UP: |
1393 | c->cputype = CPU_INTERAPTIV; |
1394 | __cpu_name[cpu] = "MIPS interAptiv" ; |
1395 | cpu_set_mt_per_tc_perf(c); |
1396 | break; |
1397 | case PRID_IMP_INTERAPTIV_MP: |
1398 | c->cputype = CPU_INTERAPTIV; |
1399 | __cpu_name[cpu] = "MIPS interAptiv (multi)" ; |
1400 | cpu_set_mt_per_tc_perf(c); |
1401 | break; |
1402 | case PRID_IMP_PROAPTIV_UP: |
1403 | c->cputype = CPU_PROAPTIV; |
1404 | __cpu_name[cpu] = "MIPS proAptiv" ; |
1405 | break; |
1406 | case PRID_IMP_PROAPTIV_MP: |
1407 | c->cputype = CPU_PROAPTIV; |
1408 | __cpu_name[cpu] = "MIPS proAptiv (multi)" ; |
1409 | break; |
1410 | case PRID_IMP_P5600: |
1411 | c->cputype = CPU_P5600; |
1412 | __cpu_name[cpu] = "MIPS P5600" ; |
1413 | break; |
1414 | case PRID_IMP_P6600: |
1415 | c->cputype = CPU_P6600; |
1416 | __cpu_name[cpu] = "MIPS P6600" ; |
1417 | break; |
1418 | case PRID_IMP_I6400: |
1419 | c->cputype = CPU_I6400; |
1420 | __cpu_name[cpu] = "MIPS I6400" ; |
1421 | break; |
1422 | case PRID_IMP_I6500: |
1423 | c->cputype = CPU_I6500; |
1424 | __cpu_name[cpu] = "MIPS I6500" ; |
1425 | break; |
1426 | case PRID_IMP_M5150: |
1427 | c->cputype = CPU_M5150; |
1428 | __cpu_name[cpu] = "MIPS M5150" ; |
1429 | break; |
1430 | case PRID_IMP_M6250: |
1431 | c->cputype = CPU_M6250; |
1432 | __cpu_name[cpu] = "MIPS M6250" ; |
1433 | break; |
1434 | } |
1435 | |
1436 | decode_configs(c); |
1437 | |
1438 | spram_config(); |
1439 | |
1440 | mm_config(c); |
1441 | |
1442 | switch (__get_cpu_type(c->cputype)) { |
1443 | case CPU_M5150: |
1444 | case CPU_P5600: |
1445 | set_isa(c, MIPS_CPU_ISA_M32R5); |
1446 | break; |
1447 | case CPU_I6500: |
1448 | c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES; |
1449 | fallthrough; |
1450 | case CPU_I6400: |
1451 | c->options |= MIPS_CPU_SHARED_FTLB_RAM; |
1452 | fallthrough; |
1453 | default: |
1454 | break; |
1455 | } |
1456 | |
1457 | /* Recent MIPS cores use the implementation-dependent ExcCode 16 for |
1458 | * cache/FTLB parity exceptions. |
1459 | */ |
1460 | switch (__get_cpu_type(c->cputype)) { |
1461 | case CPU_PROAPTIV: |
1462 | case CPU_P5600: |
1463 | case CPU_P6600: |
1464 | case CPU_I6400: |
1465 | case CPU_I6500: |
1466 | c->options |= MIPS_CPU_FTLBPAREX; |
1467 | break; |
1468 | } |
1469 | } |
1470 | |
1471 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
1472 | { |
1473 | decode_configs(c); |
1474 | switch (c->processor_id & PRID_IMP_MASK) { |
1475 | case PRID_IMP_AU1_REV1: |
1476 | case PRID_IMP_AU1_REV2: |
1477 | c->cputype = CPU_ALCHEMY; |
1478 | switch ((c->processor_id >> 24) & 0xff) { |
1479 | case 0: |
1480 | __cpu_name[cpu] = "Au1000" ; |
1481 | break; |
1482 | case 1: |
1483 | __cpu_name[cpu] = "Au1500" ; |
1484 | break; |
1485 | case 2: |
1486 | __cpu_name[cpu] = "Au1100" ; |
1487 | break; |
1488 | case 3: |
1489 | __cpu_name[cpu] = "Au1550" ; |
1490 | break; |
1491 | case 4: |
1492 | __cpu_name[cpu] = "Au1200" ; |
1493 | if ((c->processor_id & PRID_REV_MASK) == 2) |
1494 | __cpu_name[cpu] = "Au1250" ; |
1495 | break; |
1496 | case 5: |
1497 | __cpu_name[cpu] = "Au1210" ; |
1498 | break; |
1499 | default: |
1500 | __cpu_name[cpu] = "Au1xxx" ; |
1501 | break; |
1502 | } |
1503 | break; |
1504 | case PRID_IMP_NETLOGIC_AU13XX: |
1505 | c->cputype = CPU_ALCHEMY; |
1506 | __cpu_name[cpu] = "Au1300" ; |
1507 | break; |
1508 | } |
1509 | } |
1510 | |
1511 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
1512 | { |
1513 | decode_configs(c); |
1514 | |
1515 | c->writecombine = _CACHE_UNCACHED_ACCELERATED; |
1516 | switch (c->processor_id & PRID_IMP_MASK) { |
1517 | case PRID_IMP_SB1: |
1518 | c->cputype = CPU_SB1; |
1519 | __cpu_name[cpu] = "SiByte SB1" ; |
1520 | /* FPU in pass1 is known to have issues. */ |
1521 | if ((c->processor_id & PRID_REV_MASK) < 0x02) |
1522 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
1523 | break; |
1524 | case PRID_IMP_SB1A: |
1525 | c->cputype = CPU_SB1A; |
1526 | __cpu_name[cpu] = "SiByte SB1A" ; |
1527 | break; |
1528 | } |
1529 | } |
1530 | |
1531 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
1532 | { |
1533 | decode_configs(c); |
1534 | switch (c->processor_id & PRID_IMP_MASK) { |
1535 | case PRID_IMP_SR71000: |
1536 | c->cputype = CPU_SR71000; |
1537 | __cpu_name[cpu] = "Sandcraft SR71000" ; |
1538 | c->scache.ways = 8; |
1539 | c->tlbsize = 64; |
1540 | break; |
1541 | } |
1542 | } |
1543 | |
1544 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
1545 | { |
1546 | decode_configs(c); |
1547 | switch (c->processor_id & PRID_IMP_MASK) { |
1548 | case PRID_IMP_PR4450: |
1549 | c->cputype = CPU_PR4450; |
1550 | __cpu_name[cpu] = "Philips PR4450" ; |
1551 | set_isa(c, MIPS_CPU_ISA_M32R1); |
1552 | break; |
1553 | } |
1554 | } |
1555 | |
1556 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
1557 | { |
1558 | decode_configs(c); |
1559 | switch (c->processor_id & PRID_IMP_MASK) { |
1560 | case PRID_IMP_BMIPS32_REV4: |
1561 | case PRID_IMP_BMIPS32_REV8: |
1562 | c->cputype = CPU_BMIPS32; |
1563 | __cpu_name[cpu] = "Broadcom BMIPS32" ; |
1564 | set_elf_platform(cpu, plat: "bmips32" ); |
1565 | break; |
1566 | case PRID_IMP_BMIPS3300: |
1567 | case PRID_IMP_BMIPS3300_ALT: |
1568 | case PRID_IMP_BMIPS3300_BUG: |
1569 | c->cputype = CPU_BMIPS3300; |
1570 | __cpu_name[cpu] = "Broadcom BMIPS3300" ; |
1571 | set_elf_platform(cpu, plat: "bmips3300" ); |
1572 | reserve_exception_space(0x400, VECTORSPACING * 64); |
1573 | break; |
1574 | case PRID_IMP_BMIPS43XX: { |
1575 | int rev = c->processor_id & PRID_REV_MASK; |
1576 | |
1577 | if (rev >= PRID_REV_BMIPS4380_LO && |
1578 | rev <= PRID_REV_BMIPS4380_HI) { |
1579 | c->cputype = CPU_BMIPS4380; |
1580 | __cpu_name[cpu] = "Broadcom BMIPS4380" ; |
1581 | set_elf_platform(cpu, plat: "bmips4380" ); |
1582 | c->options |= MIPS_CPU_RIXI; |
1583 | reserve_exception_space(0x400, VECTORSPACING * 64); |
1584 | } else { |
1585 | c->cputype = CPU_BMIPS4350; |
1586 | __cpu_name[cpu] = "Broadcom BMIPS4350" ; |
1587 | set_elf_platform(cpu, plat: "bmips4350" ); |
1588 | } |
1589 | break; |
1590 | } |
1591 | case PRID_IMP_BMIPS5000: |
1592 | case PRID_IMP_BMIPS5200: |
1593 | c->cputype = CPU_BMIPS5000; |
1594 | if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200) |
1595 | __cpu_name[cpu] = "Broadcom BMIPS5200" ; |
1596 | else |
1597 | __cpu_name[cpu] = "Broadcom BMIPS5000" ; |
1598 | set_elf_platform(cpu, plat: "bmips5000" ); |
1599 | c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; |
1600 | reserve_exception_space(0x1000, VECTORSPACING * 64); |
1601 | break; |
1602 | } |
1603 | } |
1604 | |
1605 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
1606 | { |
1607 | decode_configs(c); |
1608 | /* Octeon has different cache interface */ |
1609 | c->options &= ~MIPS_CPU_4K_CACHE; |
1610 | switch (c->processor_id & PRID_IMP_MASK) { |
1611 | case PRID_IMP_CAVIUM_CN38XX: |
1612 | case PRID_IMP_CAVIUM_CN31XX: |
1613 | case PRID_IMP_CAVIUM_CN30XX: |
1614 | c->cputype = CPU_CAVIUM_OCTEON; |
1615 | __cpu_name[cpu] = "Cavium Octeon" ; |
1616 | goto platform; |
1617 | case PRID_IMP_CAVIUM_CN58XX: |
1618 | case PRID_IMP_CAVIUM_CN56XX: |
1619 | case PRID_IMP_CAVIUM_CN50XX: |
1620 | case PRID_IMP_CAVIUM_CN52XX: |
1621 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
1622 | __cpu_name[cpu] = "Cavium Octeon+" ; |
1623 | platform: |
1624 | set_elf_platform(cpu, plat: "octeon" ); |
1625 | break; |
1626 | case PRID_IMP_CAVIUM_CN61XX: |
1627 | case PRID_IMP_CAVIUM_CN63XX: |
1628 | case PRID_IMP_CAVIUM_CN66XX: |
1629 | case PRID_IMP_CAVIUM_CN68XX: |
1630 | case PRID_IMP_CAVIUM_CNF71XX: |
1631 | c->cputype = CPU_CAVIUM_OCTEON2; |
1632 | __cpu_name[cpu] = "Cavium Octeon II" ; |
1633 | set_elf_platform(cpu, plat: "octeon2" ); |
1634 | break; |
1635 | case PRID_IMP_CAVIUM_CN70XX: |
1636 | case PRID_IMP_CAVIUM_CN73XX: |
1637 | case PRID_IMP_CAVIUM_CNF75XX: |
1638 | case PRID_IMP_CAVIUM_CN78XX: |
1639 | c->cputype = CPU_CAVIUM_OCTEON3; |
1640 | __cpu_name[cpu] = "Cavium Octeon III" ; |
1641 | set_elf_platform(cpu, plat: "octeon3" ); |
1642 | break; |
1643 | default: |
1644 | printk(KERN_INFO "Unknown Octeon chip!\n" ); |
1645 | c->cputype = CPU_UNKNOWN; |
1646 | break; |
1647 | } |
1648 | } |
1649 | |
1650 | #ifdef CONFIG_CPU_LOONGSON64 |
1651 | #include <loongson_regs.h> |
1652 | |
1653 | static inline void decode_cpucfg(struct cpuinfo_mips *c) |
1654 | { |
1655 | u32 cfg1 = read_cpucfg(LOONGSON_CFG1); |
1656 | u32 cfg2 = read_cpucfg(LOONGSON_CFG2); |
1657 | u32 cfg3 = read_cpucfg(LOONGSON_CFG3); |
1658 | |
1659 | if (cfg1 & LOONGSON_CFG1_MMI) |
1660 | c->ases |= MIPS_ASE_LOONGSON_MMI; |
1661 | |
1662 | if (cfg2 & LOONGSON_CFG2_LEXT1) |
1663 | c->ases |= MIPS_ASE_LOONGSON_EXT; |
1664 | |
1665 | if (cfg2 & LOONGSON_CFG2_LEXT2) |
1666 | c->ases |= MIPS_ASE_LOONGSON_EXT2; |
1667 | |
1668 | if (cfg2 & LOONGSON_CFG2_LSPW) { |
1669 | c->options |= MIPS_CPU_LDPTE; |
1670 | c->guest.options |= MIPS_CPU_LDPTE; |
1671 | } |
1672 | |
1673 | if (cfg3 & LOONGSON_CFG3_LCAMP) |
1674 | c->ases |= MIPS_ASE_LOONGSON_CAM; |
1675 | } |
1676 | |
1677 | static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) |
1678 | { |
1679 | c->cputype = CPU_LOONGSON64; |
1680 | |
1681 | /* All Loongson processors covered here define ExcCode 16 as GSExc. */ |
1682 | decode_configs(c); |
1683 | c->options |= MIPS_CPU_GSEXCEX; |
1684 | |
1685 | switch (c->processor_id & PRID_IMP_MASK) { |
1686 | case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */ |
1687 | switch (c->processor_id & PRID_REV_MASK) { |
1688 | case PRID_REV_LOONGSON2K_R1_0: |
1689 | case PRID_REV_LOONGSON2K_R1_1: |
1690 | case PRID_REV_LOONGSON2K_R1_2: |
1691 | case PRID_REV_LOONGSON2K_R1_3: |
1692 | __cpu_name[cpu] = "Loongson-2K" ; |
1693 | set_elf_platform(cpu, "gs264e" ); |
1694 | set_isa(c, MIPS_CPU_ISA_M64R2); |
1695 | break; |
1696 | } |
1697 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT | |
1698 | MIPS_ASE_LOONGSON_EXT2); |
1699 | break; |
1700 | case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */ |
1701 | switch (c->processor_id & PRID_REV_MASK) { |
1702 | case PRID_REV_LOONGSON3A_R2_0: |
1703 | case PRID_REV_LOONGSON3A_R2_1: |
1704 | __cpu_name[cpu] = "ICT Loongson-3" ; |
1705 | set_elf_platform(cpu, "loongson3a" ); |
1706 | set_isa(c, MIPS_CPU_ISA_M64R2); |
1707 | break; |
1708 | case PRID_REV_LOONGSON3A_R3_0: |
1709 | case PRID_REV_LOONGSON3A_R3_1: |
1710 | __cpu_name[cpu] = "ICT Loongson-3" ; |
1711 | set_elf_platform(cpu, "loongson3a" ); |
1712 | set_isa(c, MIPS_CPU_ISA_M64R2); |
1713 | break; |
1714 | } |
1715 | /* |
1716 | * Loongson-3 Classic did not implement MIPS standard TLBINV |
1717 | * but implemented TLBINVF and EHINV. As currently we're only |
1718 | * using these two features, enable MIPS_CPU_TLBINV as well. |
1719 | * |
1720 | * Also some early Loongson-3A2000 had wrong TLB type in Config |
1721 | * register, we correct it here. |
1722 | */ |
1723 | c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE; |
1724 | c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | |
1725 | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); |
1726 | c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ |
1727 | break; |
1728 | case PRID_IMP_LOONGSON_64G: |
1729 | __cpu_name[cpu] = "ICT Loongson-3" ; |
1730 | set_elf_platform(cpu, "loongson3a" ); |
1731 | set_isa(c, MIPS_CPU_ISA_M64R2); |
1732 | decode_cpucfg(c); |
1733 | break; |
1734 | default: |
1735 | panic("Unknown Loongson Processor ID!" ); |
1736 | break; |
1737 | } |
1738 | } |
1739 | #else |
1740 | static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { } |
1741 | #endif |
1742 | |
1743 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
1744 | { |
1745 | decode_configs(c); |
1746 | |
1747 | /* |
1748 | * XBurst misses a config2 register, so config3 decode was skipped in |
1749 | * decode_configs(). |
1750 | */ |
1751 | decode_config3(c); |
1752 | |
1753 | /* XBurst does not implement the CP0 counter. */ |
1754 | c->options &= ~MIPS_CPU_COUNTER; |
1755 | BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); |
1756 | |
1757 | /* XBurst has virtually tagged icache */ |
1758 | c->icache.flags |= MIPS_CACHE_VTAG; |
1759 | |
1760 | switch (c->processor_id & PRID_IMP_MASK) { |
1761 | |
1762 | /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ |
1763 | case PRID_IMP_XBURST_REV1: |
1764 | |
1765 | /* |
1766 | * The XBurst core by default attempts to avoid branch target |
1767 | * buffer lookups by detecting & special casing loops. This |
1768 | * feature will cause BogoMIPS and lpj calculate in error. |
1769 | * Set cp0 config7 bit 4 to disable this feature. |
1770 | */ |
1771 | set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); |
1772 | |
1773 | switch (c->processor_id & PRID_COMP_MASK) { |
1774 | |
1775 | /* |
1776 | * The config0 register in the XBurst CPUs with a processor ID of |
1777 | * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, |
1778 | * but they don't actually support this ISA. |
1779 | */ |
1780 | case PRID_COMP_INGENIC_D0: |
1781 | c->isa_level &= ~MIPS_CPU_ISA_M32R2; |
1782 | |
1783 | /* FPU is not properly detected on JZ4760(B). */ |
1784 | if (c->processor_id == 0x2ed0024f) |
1785 | c->options |= MIPS_CPU_FPU; |
1786 | |
1787 | fallthrough; |
1788 | |
1789 | /* |
1790 | * The config0 register in the XBurst CPUs with a processor ID of |
1791 | * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned |
1792 | * huge page tlb mode, this mode is not compatible with the MIPS |
1793 | * standard, it will cause tlbmiss and into an infinite loop |
1794 | * (line 21 in the tlb-funcs.S) when starting the init process. |
1795 | * After chip reset, the default is HPTLB mode, Write 0xa9000000 |
1796 | * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent |
1797 | * getting stuck. |
1798 | */ |
1799 | case PRID_COMP_INGENIC_D1: |
1800 | write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); |
1801 | break; |
1802 | |
1803 | default: |
1804 | break; |
1805 | } |
1806 | fallthrough; |
1807 | |
1808 | /* XBurst®1 with MXU2.0 SIMD ISA */ |
1809 | case PRID_IMP_XBURST_REV2: |
1810 | /* Ingenic uses the WA bit to achieve write-combine memory writes */ |
1811 | c->writecombine = _CACHE_CACHABLE_WA; |
1812 | c->cputype = CPU_XBURST; |
1813 | __cpu_name[cpu] = "Ingenic XBurst" ; |
1814 | break; |
1815 | |
1816 | /* XBurst®2 with MXU2.1 SIMD ISA */ |
1817 | case PRID_IMP_XBURST2: |
1818 | c->cputype = CPU_XBURST; |
1819 | __cpu_name[cpu] = "Ingenic XBurst II" ; |
1820 | break; |
1821 | |
1822 | default: |
1823 | panic(fmt: "Unknown Ingenic Processor ID!" ); |
1824 | break; |
1825 | } |
1826 | } |
1827 | |
1828 | #ifdef CONFIG_64BIT |
1829 | /* For use by uaccess.h */ |
1830 | u64 __ua_limit; |
1831 | EXPORT_SYMBOL(__ua_limit); |
1832 | #endif |
1833 | |
1834 | const char *__cpu_name[NR_CPUS]; |
1835 | const char *__elf_platform; |
1836 | const char *__elf_base_platform; |
1837 | |
1838 | void cpu_probe(void) |
1839 | { |
1840 | struct cpuinfo_mips *c = ¤t_cpu_data; |
1841 | unsigned int cpu = smp_processor_id(); |
1842 | |
1843 | /* |
1844 | * Set a default elf platform, cpu probe may later |
1845 | * overwrite it with a more precise value |
1846 | */ |
1847 | set_elf_platform(cpu, plat: "mips" ); |
1848 | |
1849 | c->processor_id = PRID_IMP_UNKNOWN; |
1850 | c->fpu_id = FPIR_IMP_NONE; |
1851 | c->cputype = CPU_UNKNOWN; |
1852 | c->writecombine = _CACHE_UNCACHED; |
1853 | |
1854 | c->fpu_csr31 = FPU_CSR_RN; |
1855 | c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008; |
1856 | |
1857 | c->processor_id = read_c0_prid(); |
1858 | switch (c->processor_id & PRID_COMP_MASK) { |
1859 | case PRID_COMP_LEGACY: |
1860 | cpu_probe_legacy(c, cpu); |
1861 | break; |
1862 | case PRID_COMP_MIPS: |
1863 | cpu_probe_mips(c, cpu); |
1864 | break; |
1865 | case PRID_COMP_ALCHEMY: |
1866 | case PRID_COMP_NETLOGIC: |
1867 | cpu_probe_alchemy(c, cpu); |
1868 | break; |
1869 | case PRID_COMP_SIBYTE: |
1870 | cpu_probe_sibyte(c, cpu); |
1871 | break; |
1872 | case PRID_COMP_BROADCOM: |
1873 | cpu_probe_broadcom(c, cpu); |
1874 | break; |
1875 | case PRID_COMP_SANDCRAFT: |
1876 | cpu_probe_sandcraft(c, cpu); |
1877 | break; |
1878 | case PRID_COMP_NXP: |
1879 | cpu_probe_nxp(c, cpu); |
1880 | break; |
1881 | case PRID_COMP_CAVIUM: |
1882 | cpu_probe_cavium(c, cpu); |
1883 | break; |
1884 | case PRID_COMP_LOONGSON: |
1885 | cpu_probe_loongson(c, cpu); |
1886 | break; |
1887 | case PRID_COMP_INGENIC_13: |
1888 | case PRID_COMP_INGENIC_D0: |
1889 | case PRID_COMP_INGENIC_D1: |
1890 | case PRID_COMP_INGENIC_E1: |
1891 | cpu_probe_ingenic(c, cpu); |
1892 | break; |
1893 | } |
1894 | |
1895 | BUG_ON(!__cpu_name[cpu]); |
1896 | BUG_ON(c->cputype == CPU_UNKNOWN); |
1897 | |
1898 | /* |
1899 | * Platform code can force the cpu type to optimize code |
1900 | * generation. In that case be sure the cpu type is correctly |
1901 | * manually setup otherwise it could trigger some nasty bugs. |
1902 | */ |
1903 | BUG_ON(current_cpu_type() != c->cputype); |
1904 | |
1905 | if (cpu_has_rixi) { |
1906 | /* Enable the RIXI exceptions */ |
1907 | set_c0_pagegrain(PG_IEC); |
1908 | back_to_back_c0_hazard(); |
1909 | /* Verify the IEC bit is set */ |
1910 | if (read_c0_pagegrain() & PG_IEC) |
1911 | c->options |= MIPS_CPU_RIXIEX; |
1912 | } |
1913 | |
1914 | if (mips_fpu_disabled) |
1915 | c->options &= ~MIPS_CPU_FPU; |
1916 | |
1917 | if (mips_dsp_disabled) |
1918 | c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P); |
1919 | |
1920 | if (mips_htw_disabled) { |
1921 | c->options &= ~MIPS_CPU_HTW; |
1922 | write_c0_pwctl(read_c0_pwctl() & |
1923 | ~(1 << MIPS_PWCTL_PWEN_SHIFT)); |
1924 | } |
1925 | |
1926 | if (c->options & MIPS_CPU_FPU) |
1927 | cpu_set_fpu_opts(c); |
1928 | else |
1929 | cpu_set_nofpu_opts(c); |
1930 | |
1931 | if (cpu_has_mips_r2_r6) { |
1932 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
1933 | /* R2 has Performance Counter Interrupt indicator */ |
1934 | c->options |= MIPS_CPU_PCI; |
1935 | } |
1936 | else |
1937 | c->srsets = 1; |
1938 | |
1939 | if (cpu_has_mips_r6) |
1940 | elf_hwcap |= HWCAP_MIPS_R6; |
1941 | |
1942 | if (cpu_has_msa) { |
1943 | c->msa_id = cpu_get_msa_id(); |
1944 | WARN(c->msa_id & MSA_IR_WRPF, |
1945 | "Vector register partitioning unimplemented!" ); |
1946 | elf_hwcap |= HWCAP_MIPS_MSA; |
1947 | } |
1948 | |
1949 | if (cpu_has_mips16) |
1950 | elf_hwcap |= HWCAP_MIPS_MIPS16; |
1951 | |
1952 | if (cpu_has_mdmx) |
1953 | elf_hwcap |= HWCAP_MIPS_MDMX; |
1954 | |
1955 | if (cpu_has_mips3d) |
1956 | elf_hwcap |= HWCAP_MIPS_MIPS3D; |
1957 | |
1958 | if (cpu_has_smartmips) |
1959 | elf_hwcap |= HWCAP_MIPS_SMARTMIPS; |
1960 | |
1961 | if (cpu_has_dsp) |
1962 | elf_hwcap |= HWCAP_MIPS_DSP; |
1963 | |
1964 | if (cpu_has_dsp2) |
1965 | elf_hwcap |= HWCAP_MIPS_DSP2; |
1966 | |
1967 | if (cpu_has_dsp3) |
1968 | elf_hwcap |= HWCAP_MIPS_DSP3; |
1969 | |
1970 | if (cpu_has_mips16e2) |
1971 | elf_hwcap |= HWCAP_MIPS_MIPS16E2; |
1972 | |
1973 | if (cpu_has_loongson_mmi) |
1974 | elf_hwcap |= HWCAP_LOONGSON_MMI; |
1975 | |
1976 | if (cpu_has_loongson_ext) |
1977 | elf_hwcap |= HWCAP_LOONGSON_EXT; |
1978 | |
1979 | if (cpu_has_loongson_ext2) |
1980 | elf_hwcap |= HWCAP_LOONGSON_EXT2; |
1981 | |
1982 | if (cpu_has_vz) |
1983 | cpu_probe_vz(c); |
1984 | |
1985 | cpu_probe_vmbits(c); |
1986 | |
1987 | /* Synthesize CPUCFG data if running on Loongson processors; |
1988 | * no-op otherwise. |
1989 | * |
1990 | * This looks at previously probed features, so keep this at bottom. |
1991 | */ |
1992 | loongson3_cpucfg_synthesize_data(c); |
1993 | |
1994 | #ifdef CONFIG_64BIT |
1995 | if (cpu == 0) |
1996 | __ua_limit = ~((1ull << cpu_vmbits) - 1); |
1997 | #endif |
1998 | |
1999 | reserve_exception_space(0, 0x1000); |
2000 | } |
2001 | |
2002 | void cpu_report(void) |
2003 | { |
2004 | struct cpuinfo_mips *c = ¤t_cpu_data; |
2005 | |
2006 | pr_info("CPU%d revision is: %08x (%s)\n" , |
2007 | smp_processor_id(), c->processor_id, cpu_name_string()); |
2008 | if (c->options & MIPS_CPU_FPU) |
2009 | printk(KERN_INFO "FPU revision is: %08x\n" , c->fpu_id); |
2010 | if (cpu_has_msa) |
2011 | pr_info("MSA revision is: %08x\n" , c->msa_id); |
2012 | } |
2013 | |
2014 | void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster) |
2015 | { |
2016 | /* Ensure the core number fits in the field */ |
2017 | WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >> |
2018 | MIPS_GLOBALNUMBER_CLUSTER_SHF)); |
2019 | |
2020 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER; |
2021 | cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF; |
2022 | } |
2023 | |
2024 | void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core) |
2025 | { |
2026 | /* Ensure the core number fits in the field */ |
2027 | WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF)); |
2028 | |
2029 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE; |
2030 | cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF; |
2031 | } |
2032 | |
2033 | void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe) |
2034 | { |
2035 | /* Ensure the VP(E) ID fits in the field */ |
2036 | WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF)); |
2037 | |
2038 | /* Ensure we're not using VP(E)s without support */ |
2039 | WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) && |
2040 | !IS_ENABLED(CONFIG_CPU_MIPSR6)); |
2041 | |
2042 | cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP; |
2043 | cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF; |
2044 | } |
2045 | |