1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * |
4 | * Copyright (C) 2010 John Crispin <john@phrozen.org> |
5 | */ |
6 | |
7 | #include <linux/export.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/memblock.h> |
10 | #include <linux/of_fdt.h> |
11 | |
12 | #include <asm/bootinfo.h> |
13 | #include <asm/time.h> |
14 | #include <asm/prom.h> |
15 | |
16 | #include <lantiq.h> |
17 | |
18 | #include "prom.h" |
19 | #include "clk.h" |
20 | |
21 | /* access to the ebu needs to be locked between different drivers */ |
22 | DEFINE_SPINLOCK(ebu_lock); |
23 | EXPORT_SYMBOL_GPL(ebu_lock); |
24 | |
25 | /* |
26 | * this struct is filled by the soc specific detection code and holds |
27 | * information about the specific soc type, revision and name |
28 | */ |
29 | static struct ltq_soc_info soc_info; |
30 | |
31 | /* |
32 | * These structs are used to override vsmp_init_secondary() |
33 | */ |
34 | #if defined(CONFIG_MIPS_MT_SMP) |
35 | extern const struct plat_smp_ops vsmp_smp_ops; |
36 | static struct plat_smp_ops lantiq_smp_ops; |
37 | #endif |
38 | |
39 | const char *get_system_type(void) |
40 | { |
41 | return soc_info.sys_type; |
42 | } |
43 | |
44 | int ltq_soc_type(void) |
45 | { |
46 | return soc_info.type; |
47 | } |
48 | |
49 | static void __init prom_init_cmdline(void) |
50 | { |
51 | int argc = fw_arg0; |
52 | char **argv = (char **) KSEG1ADDR(fw_arg1); |
53 | int i; |
54 | |
55 | arcs_cmdline[0] = '\0'; |
56 | |
57 | for (i = 0; i < argc; i++) { |
58 | char *p = (char *) KSEG1ADDR(argv[i]); |
59 | |
60 | if (CPHYSADDR(p) && *p) { |
61 | strlcat(p: arcs_cmdline, q: p, avail: sizeof(arcs_cmdline)); |
62 | strlcat(p: arcs_cmdline, q: " " , avail: sizeof(arcs_cmdline)); |
63 | } |
64 | } |
65 | } |
66 | |
67 | void __init plat_mem_setup(void) |
68 | { |
69 | void *dtb; |
70 | |
71 | ioport_resource.start = IOPORT_RESOURCE_START; |
72 | ioport_resource.end = IOPORT_RESOURCE_END; |
73 | iomem_resource.start = IOMEM_RESOURCE_START; |
74 | iomem_resource.end = IOMEM_RESOURCE_END; |
75 | |
76 | set_io_port_base((unsigned long) KSEG1); |
77 | |
78 | dtb = get_fdt(); |
79 | if (dtb == NULL) |
80 | panic(fmt: "no dtb found" ); |
81 | |
82 | /* |
83 | * Load the devicetree. This causes the chosen node to be |
84 | * parsed resulting in our memory appearing |
85 | */ |
86 | __dt_setup_arch(dtb); |
87 | } |
88 | |
89 | #if defined(CONFIG_MIPS_MT_SMP) |
90 | static void lantiq_init_secondary(void) |
91 | { |
92 | /* |
93 | * MIPS CPU startup function vsmp_init_secondary() will only |
94 | * enable some of the interrupts for the second CPU/VPE. |
95 | */ |
96 | set_c0_status(ST0_IM); |
97 | } |
98 | #endif |
99 | |
100 | void __init prom_init(void) |
101 | { |
102 | /* call the soc specific detetcion code and get it to fill soc_info */ |
103 | ltq_soc_detect(i: &soc_info); |
104 | snprintf(buf: soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, fmt: "%s rev %s" , |
105 | soc_info.name, soc_info.rev_type); |
106 | soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; |
107 | pr_info("SoC: %s\n" , soc_info.sys_type); |
108 | prom_init_cmdline(); |
109 | |
110 | #if defined(CONFIG_MIPS_MT_SMP) |
111 | lantiq_smp_ops = vsmp_smp_ops; |
112 | if (cpu_has_mipsmt) |
113 | lantiq_smp_ops.init_secondary = lantiq_init_secondary; |
114 | register_smp_ops(&lantiq_smp_ops); |
115 | #endif |
116 | } |
117 | |