1 | /* |
2 | * BRIEF MODULE DESCRIPTION |
3 | * PCI initialization for IDT EB434 board |
4 | * |
5 | * Copyright 2004 IDT Inc. (rischelp@idt.com) |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it |
8 | * under the terms of the GNU General Public License as published by the |
9 | * Free Software Foundation; either version 2 of the License, or (at your |
10 | * option) any later version. |
11 | * |
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
22 | * |
23 | * You should have received a copy of the GNU General Public License along |
24 | * with this program; if not, write to the Free Software Foundation, Inc., |
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
26 | */ |
27 | |
28 | #include <linux/types.h> |
29 | #include <linux/pci.h> |
30 | #include <linux/kernel.h> |
31 | #include <linux/init.h> |
32 | |
33 | #include <asm/mach-rc32434/rc32434.h> |
34 | #include <asm/mach-rc32434/pci.h> |
35 | |
36 | #define PCI_ACCESS_READ 0 |
37 | #define PCI_ACCESS_WRITE 1 |
38 | |
39 | /* define an unsigned array for the PCI registers */ |
40 | static unsigned int korina_cnfg_regs[25] = { |
41 | KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, |
42 | KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, |
43 | KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, |
44 | KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, |
45 | KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, |
46 | KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 |
47 | }; |
48 | static struct resource rc32434_res_pci_mem1; |
49 | static struct resource rc32434_res_pci_mem2; |
50 | |
51 | static struct resource rc32434_res_pci_mem1 = { |
52 | .name = "PCI MEM1" , |
53 | .start = 0x50000000, |
54 | .end = 0x5FFFFFFF, |
55 | .flags = IORESOURCE_MEM, |
56 | .sibling = NULL, |
57 | .child = &rc32434_res_pci_mem2 |
58 | }; |
59 | |
60 | static struct resource rc32434_res_pci_mem2 = { |
61 | .name = "PCI Mem2" , |
62 | .start = 0x60000000, |
63 | .end = 0x6FFFFFFF, |
64 | .flags = IORESOURCE_MEM, |
65 | .parent = &rc32434_res_pci_mem1, |
66 | .sibling = NULL, |
67 | .child = NULL |
68 | }; |
69 | |
70 | static struct resource rc32434_res_pci_io1 = { |
71 | .name = "PCI I/O1" , |
72 | .start = 0x18800000, |
73 | .end = 0x188FFFFF, |
74 | .flags = IORESOURCE_IO, |
75 | }; |
76 | |
77 | extern struct pci_ops rc32434_pci_ops; |
78 | |
79 | #define PCI_MEM1_START PCI_ADDR_START |
80 | #define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1) |
81 | #define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN) |
82 | #define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1) |
83 | #define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)) |
84 | #define PCI_IO1_END \ |
85 | (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1) |
86 | #define PCI_IO2_START \ |
87 | (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN) |
88 | #define PCI_IO2_END \ |
89 | (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1) |
90 | |
91 | struct pci_controller rc32434_controller2; |
92 | |
93 | struct pci_controller rc32434_controller = { |
94 | .pci_ops = &rc32434_pci_ops, |
95 | .mem_resource = &rc32434_res_pci_mem1, |
96 | .io_resource = &rc32434_res_pci_io1, |
97 | .mem_offset = 0, |
98 | .io_offset = 0, |
99 | |
100 | }; |
101 | |
102 | #ifdef __MIPSEB__ |
103 | #define PCI_ENDIAN_FLAG PCILBAC_sb_m |
104 | #else |
105 | #define PCI_ENDIAN_FLAG 0 |
106 | #endif |
107 | |
108 | static int __init rc32434_pcibridge_init(void) |
109 | { |
110 | unsigned int pcicvalue, pcicdata = 0; |
111 | unsigned int dummyread, pcicntlval; |
112 | int loopCount; |
113 | unsigned int pci_config_addr; |
114 | |
115 | pcicvalue = rc32434_pci->pcic; |
116 | pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN; |
117 | if (!((pcicvalue == PCIM_H_EA) || |
118 | (pcicvalue == PCIM_H_IA_FIX) || |
119 | (pcicvalue == PCIM_H_IA_RR))) { |
120 | pr_err("PCI init error!!!\n" ); |
121 | /* Not in Host Mode, return ERROR */ |
122 | return -1; |
123 | } |
124 | /* Enables the Idle Grant mode, Arbiter Parking */ |
125 | pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN); |
126 | rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */ |
127 | /* Zero out the PCI status & PCI Status Mask */ |
128 | for (;;) { |
129 | pcicdata = rc32434_pci->pcis; |
130 | if (!(pcicdata & PCI_STAT_RIP)) |
131 | break; |
132 | } |
133 | |
134 | rc32434_pci->pcis = 0; |
135 | rc32434_pci->pcism = 0xFFFFFFFF; |
136 | /* Zero out the PCI decoupled registers */ |
137 | rc32434_pci->pcidac = 0; /* |
138 | * disable PCI decoupled accesses at |
139 | * initialization |
140 | */ |
141 | rc32434_pci->pcidas = 0; /* clear the status */ |
142 | rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */ |
143 | /* Mask PCI Messaging Interrupts */ |
144 | rc32434_pci_msg->pciiic = 0; |
145 | rc32434_pci_msg->pciiim = 0xFFFFFFFF; |
146 | rc32434_pci_msg->pciioic = 0; |
147 | rc32434_pci_msg->pciioim = 0; |
148 | |
149 | |
150 | /* Setup PCILB0 as Memory Window */ |
151 | rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START); |
152 | |
153 | /* setup the PCI map address as same as the local address */ |
154 | |
155 | rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START); |
156 | |
157 | |
158 | /* Setup PCILBA1 as MEM */ |
159 | rc32434_pci->pcilba[0].control = |
160 | (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
161 | dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ |
162 | rc32434_pci->pcilba[1].address = 0x60000000; |
163 | rc32434_pci->pcilba[1].mapping = 0x60000000; |
164 | |
165 | /* setup PCILBA2 as IO Window */ |
166 | rc32434_pci->pcilba[1].control = |
167 | (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
168 | dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ |
169 | rc32434_pci->pcilba[2].address = 0x18C00000; |
170 | rc32434_pci->pcilba[2].mapping = 0x18FFFFFF; |
171 | |
172 | /* setup PCILBA2 as IO Window */ |
173 | rc32434_pci->pcilba[2].control = |
174 | (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
175 | dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ |
176 | |
177 | /* Setup PCILBA3 as IO Window */ |
178 | rc32434_pci->pcilba[3].address = 0x18800000; |
179 | rc32434_pci->pcilba[3].mapping = 0x18800000; |
180 | rc32434_pci->pcilba[3].control = |
181 | ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) | |
182 | PCI_ENDIAN_FLAG); |
183 | dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ |
184 | |
185 | pci_config_addr = (unsigned int) (0x80000004); |
186 | for (loopCount = 0; loopCount < 24; loopCount++) { |
187 | rc32434_pci->pcicfga = pci_config_addr; |
188 | dummyread = rc32434_pci->pcicfga; |
189 | rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount]; |
190 | dummyread = rc32434_pci->pcicfgd; |
191 | pci_config_addr += 4; |
192 | } |
193 | rc32434_pci->pcitc = |
194 | (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) | |
195 | ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT); |
196 | |
197 | pcicntlval = rc32434_pci->pcic; |
198 | pcicntlval &= ~PCI_CTL_TNR; |
199 | rc32434_pci->pcic = pcicntlval; |
200 | pcicntlval = rc32434_pci->pcic; |
201 | |
202 | return 0; |
203 | } |
204 | |
205 | static int __init rc32434_pci_init(void) |
206 | { |
207 | void __iomem *io_map_base; |
208 | |
209 | pr_info("PCI: Initializing PCI\n" ); |
210 | |
211 | ioport_resource.start = rc32434_res_pci_io1.start; |
212 | ioport_resource.end = rc32434_res_pci_io1.end; |
213 | |
214 | rc32434_pcibridge_init(); |
215 | |
216 | io_map_base = ioremap(offset: rc32434_res_pci_io1.start, |
217 | size: resource_size(res: &rc32434_res_pci_io1)); |
218 | |
219 | if (!io_map_base) |
220 | return -ENOMEM; |
221 | |
222 | rc32434_controller.io_map_base = |
223 | (unsigned long)io_map_base - rc32434_res_pci_io1.start; |
224 | |
225 | register_pci_controller(&rc32434_controller); |
226 | rc32434_sync(); |
227 | |
228 | return 0; |
229 | } |
230 | |
231 | arch_initcall(rc32434_pci_init); |
232 | |