1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * |
7 | * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle |
8 | * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) |
9 | * Copyright 1999 Hewlett Packard Co. |
10 | * |
11 | */ |
12 | |
13 | #include <linux/mm.h> |
14 | #include <linux/ptrace.h> |
15 | #include <linux/sched.h> |
16 | #include <linux/sched/debug.h> |
17 | #include <linux/interrupt.h> |
18 | #include <linux/extable.h> |
19 | #include <linux/uaccess.h> |
20 | #include <linux/hugetlb.h> |
21 | #include <linux/perf_event.h> |
22 | |
23 | #include <asm/traps.h> |
24 | |
25 | #define DEBUG_NATLB 0 |
26 | |
27 | /* Various important other fields */ |
28 | #define bit22set(x) (x & 0x00000200) |
29 | #define bits23_25set(x) (x & 0x000001c0) |
30 | #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80) |
31 | /* extended opcode is 0x6a */ |
32 | |
33 | #define BITSSET 0x1c0 /* for identifying LDCW */ |
34 | |
35 | |
36 | int show_unhandled_signals = 1; |
37 | |
38 | /* |
39 | * parisc_acctyp(unsigned int inst) -- |
40 | * Given a PA-RISC memory access instruction, determine if the |
41 | * instruction would perform a memory read or memory write |
42 | * operation. |
43 | * |
44 | * This function assumes that the given instruction is a memory access |
45 | * instruction (i.e. you should really only call it if you know that |
46 | * the instruction has generated some sort of a memory access fault). |
47 | * |
48 | * Returns: |
49 | * VM_READ if read operation |
50 | * VM_WRITE if write operation |
51 | * VM_EXEC if execute operation |
52 | */ |
53 | unsigned long |
54 | parisc_acctyp(unsigned long code, unsigned int inst) |
55 | { |
56 | if (code == 6 || code == 16) |
57 | return VM_EXEC; |
58 | |
59 | switch (inst & 0xf0000000) { |
60 | case 0x40000000: /* load */ |
61 | case 0x50000000: /* new load */ |
62 | return VM_READ; |
63 | |
64 | case 0x60000000: /* store */ |
65 | case 0x70000000: /* new store */ |
66 | return VM_WRITE; |
67 | |
68 | case 0x20000000: /* coproc */ |
69 | case 0x30000000: /* coproc2 */ |
70 | if (bit22set(inst)) |
71 | return VM_WRITE; |
72 | fallthrough; |
73 | |
74 | case 0x0: /* indexed/memory management */ |
75 | if (bit22set(inst)) { |
76 | /* |
77 | * Check for the 'Graphics Flush Read' instruction. |
78 | * It resembles an FDC instruction, except for bits |
79 | * 20 and 21. Any combination other than zero will |
80 | * utilize the block mover functionality on some |
81 | * older PA-RISC platforms. The case where a block |
82 | * move is performed from VM to graphics IO space |
83 | * should be treated as a READ. |
84 | * |
85 | * The significance of bits 20,21 in the FDC |
86 | * instruction is: |
87 | * |
88 | * 00 Flush data cache (normal instruction behavior) |
89 | * 01 Graphics flush write (IO space -> VM) |
90 | * 10 Graphics flush read (VM -> IO space) |
91 | * 11 Graphics flush read/write (VM <-> IO space) |
92 | */ |
93 | if (isGraphicsFlushRead(inst)) |
94 | return VM_READ; |
95 | return VM_WRITE; |
96 | } else { |
97 | /* |
98 | * Check for LDCWX and LDCWS (semaphore instructions). |
99 | * If bits 23 through 25 are all 1's it is one of |
100 | * the above two instructions and is a write. |
101 | * |
102 | * Note: With the limited bits we are looking at, |
103 | * this will also catch PROBEW and PROBEWI. However, |
104 | * these should never get in here because they don't |
105 | * generate exceptions of the type: |
106 | * Data TLB miss fault/data page fault |
107 | * Data memory protection trap |
108 | */ |
109 | if (bits23_25set(inst) == BITSSET) |
110 | return VM_WRITE; |
111 | } |
112 | return VM_READ; /* Default */ |
113 | } |
114 | return VM_READ; /* Default */ |
115 | } |
116 | |
117 | #undef bit22set |
118 | #undef bits23_25set |
119 | #undef isGraphicsFlushRead |
120 | #undef BITSSET |
121 | |
122 | |
123 | #if 0 |
124 | /* This is the treewalk to find a vma which is the highest that has |
125 | * a start < addr. We're using find_vma_prev instead right now, but |
126 | * we might want to use this at some point in the future. Probably |
127 | * not, but I want it committed to CVS so I don't lose it :-) |
128 | */ |
129 | while (tree != vm_avl_empty) { |
130 | if (tree->vm_start > addr) { |
131 | tree = tree->vm_avl_left; |
132 | } else { |
133 | prev = tree; |
134 | if (prev->vm_next == NULL) |
135 | break; |
136 | if (prev->vm_next->vm_start > addr) |
137 | break; |
138 | tree = tree->vm_avl_right; |
139 | } |
140 | } |
141 | #endif |
142 | |
143 | int fixup_exception(struct pt_regs *regs) |
144 | { |
145 | const struct exception_table_entry *fix; |
146 | |
147 | fix = search_exception_tables(add: regs->iaoq[0]); |
148 | if (fix) { |
149 | /* |
150 | * Fix up get_user() and put_user(). |
151 | * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant |
152 | * bit in the relative address of the fixup routine to indicate |
153 | * that the register encoded in the "or %r0,%r0,register" |
154 | * opcode should be loaded with -EFAULT to report a userspace |
155 | * access error. |
156 | */ |
157 | if (fix->fixup & 1) { |
158 | int fault_error_reg = fix->err_opcode & 0x1f; |
159 | if (!WARN_ON(!fault_error_reg)) |
160 | regs->gr[fault_error_reg] = -EFAULT; |
161 | pr_debug("Unalignment fixup of register %d at %pS\n" , |
162 | fault_error_reg, (void*)regs->iaoq[0]); |
163 | |
164 | /* zero target register for get_user() */ |
165 | if (parisc_acctyp(code: 0, inst: regs->iir) == VM_READ) { |
166 | int treg = regs->iir & 0x1f; |
167 | BUG_ON(treg == 0); |
168 | regs->gr[treg] = 0; |
169 | } |
170 | } |
171 | |
172 | regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup; |
173 | regs->iaoq[0] &= ~3; |
174 | /* |
175 | * NOTE: In some cases the faulting instruction |
176 | * may be in the delay slot of a branch. We |
177 | * don't want to take the branch, so we don't |
178 | * increment iaoq[1], instead we set it to be |
179 | * iaoq[0]+4, and clear the B bit in the PSW |
180 | */ |
181 | regs->iaoq[1] = regs->iaoq[0] + 4; |
182 | regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */ |
183 | |
184 | return 1; |
185 | } |
186 | |
187 | return 0; |
188 | } |
189 | |
190 | /* |
191 | * parisc hardware trap list |
192 | * |
193 | * Documented in section 3 "Addressing and Access Control" of the |
194 | * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual" |
195 | * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf |
196 | * |
197 | * For implementation see handle_interruption() in traps.c |
198 | */ |
199 | static const char * const trap_description[] = { |
200 | [1] = "High-priority machine check (HPMC)" , |
201 | [2] = "Power failure interrupt" , |
202 | [3] = "Recovery counter trap" , |
203 | [5] = "Low-priority machine check" , |
204 | [6] = "Instruction TLB miss fault" , |
205 | [7] = "Instruction access rights / protection trap" , |
206 | [8] = "Illegal instruction trap" , |
207 | [9] = "Break instruction trap" , |
208 | [10] = "Privileged operation trap" , |
209 | [11] = "Privileged register trap" , |
210 | [12] = "Overflow trap" , |
211 | [13] = "Conditional trap" , |
212 | [14] = "FP Assist Exception trap" , |
213 | [15] = "Data TLB miss fault" , |
214 | [16] = "Non-access ITLB miss fault" , |
215 | [17] = "Non-access DTLB miss fault" , |
216 | [18] = "Data memory protection/unaligned access trap" , |
217 | [19] = "Data memory break trap" , |
218 | [20] = "TLB dirty bit trap" , |
219 | [21] = "Page reference trap" , |
220 | [22] = "Assist emulation trap" , |
221 | [25] = "Taken branch trap" , |
222 | [26] = "Data memory access rights trap" , |
223 | [27] = "Data memory protection ID trap" , |
224 | [28] = "Unaligned data reference trap" , |
225 | }; |
226 | |
227 | const char *trap_name(unsigned long code) |
228 | { |
229 | const char *t = NULL; |
230 | |
231 | if (code < ARRAY_SIZE(trap_description)) |
232 | t = trap_description[code]; |
233 | |
234 | return t ? t : "Unknown trap" ; |
235 | } |
236 | |
237 | /* |
238 | * Print out info about fatal segfaults, if the show_unhandled_signals |
239 | * sysctl is set: |
240 | */ |
241 | static inline void |
242 | show_signal_msg(struct pt_regs *regs, unsigned long code, |
243 | unsigned long address, struct task_struct *tsk, |
244 | struct vm_area_struct *vma) |
245 | { |
246 | if (!unhandled_signal(tsk, SIGSEGV)) |
247 | return; |
248 | |
249 | if (!printk_ratelimit()) |
250 | return; |
251 | |
252 | pr_warn("\n" ); |
253 | pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx" , |
254 | tsk->comm, code, address); |
255 | print_vma_addr(KERN_CONT " in " , rip: regs->iaoq[0]); |
256 | |
257 | pr_cont("\ntrap #%lu: %s%c" , code, trap_name(code), |
258 | vma ? ',':'\n'); |
259 | |
260 | if (vma) |
261 | pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n" , |
262 | vma->vm_start, vma->vm_end); |
263 | |
264 | show_regs(regs); |
265 | } |
266 | |
267 | void do_page_fault(struct pt_regs *regs, unsigned long code, |
268 | unsigned long address) |
269 | { |
270 | struct vm_area_struct *vma, *prev_vma; |
271 | struct task_struct *tsk; |
272 | struct mm_struct *mm; |
273 | unsigned long acc_type; |
274 | vm_fault_t fault = 0; |
275 | unsigned int flags; |
276 | char *msg; |
277 | |
278 | tsk = current; |
279 | mm = tsk->mm; |
280 | if (!mm) { |
281 | msg = "Page fault: no context" ; |
282 | goto no_context; |
283 | } |
284 | |
285 | flags = FAULT_FLAG_DEFAULT; |
286 | if (user_mode(regs)) |
287 | flags |= FAULT_FLAG_USER; |
288 | |
289 | acc_type = parisc_acctyp(code, inst: regs->iir); |
290 | if (acc_type & VM_WRITE) |
291 | flags |= FAULT_FLAG_WRITE; |
292 | perf_sw_event(event_id: PERF_COUNT_SW_PAGE_FAULTS, nr: 1, regs, addr: address); |
293 | retry: |
294 | mmap_read_lock(mm); |
295 | vma = find_vma_prev(mm, addr: address, pprev: &prev_vma); |
296 | if (!vma || address < vma->vm_start) { |
297 | if (!prev_vma || !(prev_vma->vm_flags & VM_GROWSUP)) |
298 | goto bad_area; |
299 | vma = expand_stack(mm, addr: address); |
300 | if (!vma) |
301 | goto bad_area_nosemaphore; |
302 | } |
303 | |
304 | /* |
305 | * Ok, we have a good vm_area for this memory access. We still need to |
306 | * check the access permissions. |
307 | */ |
308 | |
309 | if ((vma->vm_flags & acc_type) != acc_type) |
310 | goto bad_area; |
311 | |
312 | /* |
313 | * If for any reason at all we couldn't handle the fault, make |
314 | * sure we exit gracefully rather than endlessly redo the |
315 | * fault. |
316 | */ |
317 | |
318 | fault = handle_mm_fault(vma, address, flags, regs); |
319 | |
320 | if (fault_signal_pending(fault_flags: fault, regs)) { |
321 | if (!user_mode(regs)) { |
322 | msg = "Page fault: fault signal on kernel memory" ; |
323 | goto no_context; |
324 | } |
325 | return; |
326 | } |
327 | |
328 | /* The fault is fully completed (including releasing mmap lock) */ |
329 | if (fault & VM_FAULT_COMPLETED) |
330 | return; |
331 | |
332 | if (unlikely(fault & VM_FAULT_ERROR)) { |
333 | /* |
334 | * We hit a shared mapping outside of the file, or some |
335 | * other thing happened to us that made us unable to |
336 | * handle the page fault gracefully. |
337 | */ |
338 | if (fault & VM_FAULT_OOM) |
339 | goto out_of_memory; |
340 | else if (fault & VM_FAULT_SIGSEGV) |
341 | goto bad_area; |
342 | else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON| |
343 | VM_FAULT_HWPOISON_LARGE)) |
344 | goto bad_area; |
345 | BUG(); |
346 | } |
347 | if (fault & VM_FAULT_RETRY) { |
348 | /* |
349 | * No need to mmap_read_unlock(mm) as we would |
350 | * have already released it in __lock_page_or_retry |
351 | * in mm/filemap.c. |
352 | */ |
353 | flags |= FAULT_FLAG_TRIED; |
354 | goto retry; |
355 | } |
356 | mmap_read_unlock(mm); |
357 | return; |
358 | |
359 | /* |
360 | * Something tried to access memory that isn't in our memory map.. |
361 | */ |
362 | bad_area: |
363 | mmap_read_unlock(mm); |
364 | |
365 | bad_area_nosemaphore: |
366 | if (user_mode(regs)) { |
367 | int signo, si_code; |
368 | |
369 | switch (code) { |
370 | case 15: /* Data TLB miss fault/Data page fault */ |
371 | /* send SIGSEGV when outside of vma */ |
372 | if (!vma || |
373 | address < vma->vm_start || address >= vma->vm_end) { |
374 | signo = SIGSEGV; |
375 | si_code = SEGV_MAPERR; |
376 | break; |
377 | } |
378 | |
379 | /* send SIGSEGV for wrong permissions */ |
380 | if ((vma->vm_flags & acc_type) != acc_type) { |
381 | signo = SIGSEGV; |
382 | si_code = SEGV_ACCERR; |
383 | break; |
384 | } |
385 | |
386 | /* probably address is outside of mapped file */ |
387 | fallthrough; |
388 | case 17: /* NA data TLB miss / page fault */ |
389 | case 18: /* Unaligned access - PCXS only */ |
390 | signo = SIGBUS; |
391 | si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR; |
392 | break; |
393 | case 16: /* Non-access instruction TLB miss fault */ |
394 | case 26: /* PCXL: Data memory access rights trap */ |
395 | default: |
396 | signo = SIGSEGV; |
397 | si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR; |
398 | break; |
399 | } |
400 | #ifdef CONFIG_MEMORY_FAILURE |
401 | if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) { |
402 | unsigned int lsb = 0; |
403 | printk(KERN_ERR |
404 | "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n" , |
405 | tsk->comm, tsk->pid, address); |
406 | /* |
407 | * Either small page or large page may be poisoned. |
408 | * In other words, VM_FAULT_HWPOISON_LARGE and |
409 | * VM_FAULT_HWPOISON are mutually exclusive. |
410 | */ |
411 | if (fault & VM_FAULT_HWPOISON_LARGE) |
412 | lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault)); |
413 | else if (fault & VM_FAULT_HWPOISON) |
414 | lsb = PAGE_SHIFT; |
415 | |
416 | force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address, |
417 | lsb); |
418 | return; |
419 | } |
420 | #endif |
421 | show_signal_msg(regs, code, address, tsk, vma); |
422 | |
423 | force_sig_fault(sig: signo, code: si_code, addr: (void __user *) address); |
424 | return; |
425 | } |
426 | msg = "Page fault: bad address" ; |
427 | |
428 | no_context: |
429 | |
430 | if (!user_mode(regs) && fixup_exception(regs)) { |
431 | return; |
432 | } |
433 | |
434 | parisc_terminate(msg, regs, code, address); |
435 | |
436 | out_of_memory: |
437 | mmap_read_unlock(mm); |
438 | if (!user_mode(regs)) { |
439 | msg = "Page fault: out of memory" ; |
440 | goto no_context; |
441 | } |
442 | pagefault_out_of_memory(); |
443 | } |
444 | |
445 | /* Handle non-access data TLB miss faults. |
446 | * |
447 | * For probe instructions, accesses to userspace are considered allowed |
448 | * if they lie in a valid VMA and the access type matches. We are not |
449 | * allowed to handle MM faults here so there may be situations where an |
450 | * actual access would fail even though a probe was successful. |
451 | */ |
452 | int |
453 | handle_nadtlb_fault(struct pt_regs *regs) |
454 | { |
455 | unsigned long insn = regs->iir; |
456 | int breg, treg, xreg, val = 0; |
457 | struct vm_area_struct *vma; |
458 | struct task_struct *tsk; |
459 | struct mm_struct *mm; |
460 | unsigned long address; |
461 | unsigned long acc_type; |
462 | |
463 | switch (insn & 0x380) { |
464 | case 0x280: |
465 | /* FDC instruction */ |
466 | fallthrough; |
467 | case 0x380: |
468 | /* PDC and FIC instructions */ |
469 | if (DEBUG_NATLB && printk_ratelimit()) { |
470 | pr_warn("WARNING: nullifying cache flush/purge instruction\n" ); |
471 | show_regs(regs); |
472 | } |
473 | if (insn & 0x20) { |
474 | /* Base modification */ |
475 | breg = (insn >> 21) & 0x1f; |
476 | xreg = (insn >> 16) & 0x1f; |
477 | if (breg && xreg) |
478 | regs->gr[breg] += regs->gr[xreg]; |
479 | } |
480 | regs->gr[0] |= PSW_N; |
481 | return 1; |
482 | |
483 | case 0x180: |
484 | /* PROBE instruction */ |
485 | treg = insn & 0x1f; |
486 | if (regs->isr) { |
487 | tsk = current; |
488 | mm = tsk->mm; |
489 | if (mm) { |
490 | /* Search for VMA */ |
491 | address = regs->ior; |
492 | mmap_read_lock(mm); |
493 | vma = vma_lookup(mm, addr: address); |
494 | mmap_read_unlock(mm); |
495 | |
496 | /* |
497 | * Check if access to the VMA is okay. |
498 | * We don't allow for stack expansion. |
499 | */ |
500 | acc_type = (insn & 0x40) ? VM_WRITE : VM_READ; |
501 | if (vma |
502 | && (vma->vm_flags & acc_type) == acc_type) |
503 | val = 1; |
504 | } |
505 | } |
506 | if (treg) |
507 | regs->gr[treg] = val; |
508 | regs->gr[0] |= PSW_N; |
509 | return 1; |
510 | |
511 | case 0x300: |
512 | /* LPA instruction */ |
513 | if (insn & 0x20) { |
514 | /* Base modification */ |
515 | breg = (insn >> 21) & 0x1f; |
516 | xreg = (insn >> 16) & 0x1f; |
517 | if (breg && xreg) |
518 | regs->gr[breg] += regs->gr[xreg]; |
519 | } |
520 | treg = insn & 0x1f; |
521 | if (treg) |
522 | regs->gr[treg] = 0; |
523 | regs->gr[0] |= PSW_N; |
524 | return 1; |
525 | |
526 | default: |
527 | break; |
528 | } |
529 | |
530 | return 0; |
531 | } |
532 | |