| 1 | /* |
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| 2 | * TLB miss handler for SH with an MMU. |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Niibe Yutaka |
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| 5 | * Copyright (C) 2003 - 2012 Paul Mundt |
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| 6 | * |
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| 7 | * This file is subject to the terms and conditions of the GNU General Public |
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| 8 | * License. See the file "COPYING" in the main directory of this archive |
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| 9 | * for more details. |
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| 10 | */ |
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| 11 | #include <linux/kernel.h> |
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| 12 | #include <linux/mm.h> |
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| 13 | #include <linux/kprobes.h> |
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| 14 | #include <linux/kdebug.h> |
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| 15 | #include <asm/mmu_context.h> |
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| 16 | #include <asm/thread_info.h> |
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| 17 | |
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| 18 | /* |
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| 19 | * Called with interrupts disabled. |
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| 20 | */ |
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| 21 | asmlinkage int __kprobes |
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| 22 | handle_tlbmiss(struct pt_regs *regs, unsigned long error_code, |
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| 23 | unsigned long address) |
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| 24 | { |
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| 25 | pgd_t *pgd; |
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| 26 | p4d_t *p4d; |
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| 27 | pud_t *pud; |
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| 28 | pmd_t *pmd; |
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| 29 | pte_t *pte; |
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| 30 | pte_t entry; |
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| 31 | |
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| 32 | /* |
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| 33 | * We don't take page faults for P1, P2, and parts of P4, these |
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| 34 | * are always mapped, whether it be due to legacy behaviour in |
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| 35 | * 29-bit mode, or due to PMB configuration in 32-bit mode. |
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| 36 | */ |
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| 37 | if (address >= P3SEG && address < P3_ADDR_MAX) { |
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| 38 | pgd = pgd_offset_k(address); |
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| 39 | } else { |
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| 40 | if (unlikely(address >= TASK_SIZE || !current->mm)) |
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| 41 | return 1; |
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| 42 | |
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| 43 | pgd = pgd_offset(current->mm, address); |
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| 44 | } |
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| 45 | |
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| 46 | p4d = p4d_offset(pgd, address); |
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| 47 | if (p4d_none_or_clear_bad(p4d)) |
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| 48 | return 1; |
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| 49 | pud = pud_offset(p4d, address); |
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| 50 | if (pud_none_or_clear_bad(pud)) |
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| 51 | return 1; |
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| 52 | pmd = pmd_offset(pud, address); |
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| 53 | if (pmd_none_or_clear_bad(pmd)) |
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| 54 | return 1; |
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| 55 | pte = pte_offset_kernel(pmd, address); |
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| 56 | entry = *pte; |
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| 57 | if (unlikely(pte_none(entry) || pte_not_present(entry))) |
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| 58 | return 1; |
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| 59 | if (unlikely(error_code && !pte_write(entry))) |
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| 60 | return 1; |
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| 61 | |
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| 62 | if (error_code) |
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| 63 | entry = pte_mkdirty(pte: entry); |
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| 64 | entry = pte_mkyoung(pte: entry); |
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| 65 | |
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| 66 | set_pte(ptep: pte, pte: entry); |
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| 67 | |
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| 68 | #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SMP) |
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| 69 | /* |
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| 70 | * SH-4 does not set MMUCR.RC to the corresponding TLB entry in |
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| 71 | * the case of an initial page write exception, so we need to |
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| 72 | * flush it in order to avoid potential TLB entry duplication. |
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| 73 | */ |
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| 74 | if (error_code == FAULT_CODE_INITIAL) |
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| 75 | local_flush_tlb_one(get_asid(), address & PAGE_MASK); |
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| 76 | #endif |
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| 77 | |
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| 78 | set_thread_fault_code(error_code); |
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| 79 | update_mmu_cache(NULL, addr: address, ptep: pte); |
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| 80 | |
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| 81 | return 0; |
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| 82 | } |
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| 83 | |
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