| 1 | /* |
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| 2 | * arch/xtensa/kernel/align.S |
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| 3 | * |
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| 4 | * Handle unalignment and load/store exceptions. |
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| 5 | * |
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| 6 | * This file is subject to the terms and conditions of the GNU General |
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| 7 | * Public License. See the file "COPYING" in the main directory of |
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| 8 | * this archive for more details. |
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| 9 | * |
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| 10 | * Copyright (C) 2001 - 2005 Tensilica, Inc. |
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| 11 | * Copyright (C) 2014 Cadence Design Systems Inc. |
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| 12 | * |
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| 13 | * Rewritten by Chris Zankel <chris@zankel.net> |
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| 14 | * |
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| 15 | * Based on work from Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> |
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| 16 | * and Marc Gauthier <marc@tensilica.com, marc@alimni.uwaterloo.ca> |
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| 17 | */ |
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| 18 | |
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| 19 | #include <linux/linkage.h> |
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| 20 | #include <asm/current.h> |
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| 21 | #include <asm/asm-offsets.h> |
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| 22 | #include <asm/asmmacro.h> |
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| 23 | #include <asm/processor.h> |
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| 24 | |
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| 25 | #if XCHAL_UNALIGNED_LOAD_EXCEPTION || defined CONFIG_XTENSA_LOAD_STORE |
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| 26 | #define LOAD_EXCEPTION_HANDLER |
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| 27 | #endif |
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| 28 | |
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| 29 | #if XCHAL_UNALIGNED_STORE_EXCEPTION || defined CONFIG_XTENSA_LOAD_STORE |
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| 30 | #define STORE_EXCEPTION_HANDLER |
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| 31 | #endif |
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| 32 | |
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| 33 | #if defined LOAD_EXCEPTION_HANDLER || defined STORE_EXCEPTION_HANDLER |
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| 34 | #define ANY_EXCEPTION_HANDLER |
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| 35 | #endif |
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| 36 | |
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| 37 | #if XCHAL_HAVE_WINDOWED && defined CONFIG_MMU |
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| 38 | #define UNALIGNED_USER_EXCEPTION |
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| 39 | #endif |
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| 40 | |
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| 41 | /* Big and little endian 16-bit values are located in |
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| 42 | * different halves of a register. HWORD_START helps to |
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| 43 | * abstract the notion of extracting a 16-bit value from a |
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| 44 | * register. |
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| 45 | * We also have to define new shifting instructions because |
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| 46 | * lsb and msb are on 'opposite' ends in a register for |
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| 47 | * different endian machines. |
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| 48 | * |
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| 49 | * Assume a memory region in ascending address: |
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| 50 | * 0 1 2 3|4 5 6 7 |
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| 51 | * |
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| 52 | * When loading one word into a register, the content of that register is: |
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| 53 | * LE 3 2 1 0, 7 6 5 4 |
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| 54 | * BE 0 1 2 3, 4 5 6 7 |
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| 55 | * |
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| 56 | * Masking the bits of the higher/lower address means: |
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| 57 | * LE X X 0 0, 0 0 X X |
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| 58 | * BE 0 0 X X, X X 0 0 |
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| 59 | * |
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| 60 | * Shifting to higher/lower addresses, means: |
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| 61 | * LE shift left / shift right |
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| 62 | * BE shift right / shift left |
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| 63 | * |
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| 64 | * Extracting 16 bits from a 32 bit reg. value to higher/lower address means: |
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| 65 | * LE mask 0 0 X X / shift left |
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| 66 | * BE shift left / mask 0 0 X X |
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| 67 | */ |
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| 68 | |
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| 69 | #if XCHAL_HAVE_BE |
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| 70 | |
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| 71 | #define HWORD_START 16 |
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| 72 | #define INSN_OP0 28 |
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| 73 | #define INSN_T 24 |
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| 74 | #define INSN_OP1 16 |
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| 75 | |
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| 76 | .macro __ssa8r r; ssa8l \r; .endm |
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| 77 | .macro __sh r, s; srl \r, \s; .endm |
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| 78 | .macro __sl r, s; sll \r, \s; .endm |
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| 79 | .macro __exth r, s; extui \r, \s, 0, 16; .endm |
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| 80 | .macro __extl r, s; slli \r, \s, 16; .endm |
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| 81 | |
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| 82 | #else |
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| 83 | |
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| 84 | #define HWORD_START 0 |
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| 85 | #define INSN_OP0 0 |
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| 86 | #define INSN_T 4 |
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| 87 | #define INSN_OP1 12 |
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| 88 | |
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| 89 | .macro __ssa8r r; ssa8b \r; .endm |
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| 90 | .macro __sh r, s; sll \r, \s; .endm |
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| 91 | .macro __sl r, s; srl \r, \s; .endm |
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| 92 | .macro __exth r, s; slli \r, \s, 16; .endm |
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| 93 | .macro __extl r, s; extui \r, \s, 0, 16; .endm |
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| 94 | |
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| 95 | #endif |
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| 96 | |
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| 97 | /* |
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| 98 | * xxxx xxxx = imm8 field |
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| 99 | * yyyy = imm4 field |
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| 100 | * ssss = s field |
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| 101 | * tttt = t field |
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| 102 | * |
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| 103 | * 16 0 |
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| 104 | * ------------------- |
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| 105 | * L32I.N yyyy ssss tttt 1000 |
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| 106 | * S32I.N yyyy ssss tttt 1001 |
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| 107 | * |
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| 108 | * 23 0 |
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| 109 | * ----------------------------- |
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| 110 | * L8UI xxxx xxxx 0000 ssss tttt 0010 |
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| 111 | * L16UI xxxx xxxx 0001 ssss tttt 0010 |
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| 112 | * L32I xxxx xxxx 0010 ssss tttt 0010 |
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| 113 | * XXX 0011 ssss tttt 0010 |
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| 114 | * XXX 0100 ssss tttt 0010 |
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| 115 | * S16I xxxx xxxx 0101 ssss tttt 0010 |
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| 116 | * S32I xxxx xxxx 0110 ssss tttt 0010 |
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| 117 | * XXX 0111 ssss tttt 0010 |
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| 118 | * XXX 1000 ssss tttt 0010 |
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| 119 | * L16SI xxxx xxxx 1001 ssss tttt 0010 |
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| 120 | * XXX 1010 0010 |
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| 121 | * **L32AI xxxx xxxx 1011 ssss tttt 0010 unsupported |
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| 122 | * XXX 1100 0010 |
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| 123 | * XXX 1101 0010 |
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| 124 | * XXX 1110 0010 |
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| 125 | * **S32RI xxxx xxxx 1111 ssss tttt 0010 unsupported |
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| 126 | * ----------------------------- |
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| 127 | * ^ ^ ^ |
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| 128 | * sub-opcode (NIBBLE_R) -+ | | |
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| 129 | * t field (NIBBLE_T) -----------+ | |
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| 130 | * major opcode (NIBBLE_OP0) --------------+ |
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| 131 | */ |
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| 132 | |
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| 133 | #define OP0_L32I_N 0x8 /* load immediate narrow */ |
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| 134 | #define OP0_S32I_N 0x9 /* store immediate narrow */ |
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| 135 | #define OP0_LSAI 0x2 /* load/store */ |
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| 136 | #define OP1_SI_MASK 0x4 /* OP1 bit set for stores */ |
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| 137 | #define OP1_SI_BIT 2 /* OP1 bit number for stores */ |
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| 138 | |
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| 139 | #define OP1_L8UI 0x0 |
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| 140 | #define OP1_L32I 0x2 |
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| 141 | #define OP1_L16UI 0x1 |
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| 142 | #define OP1_L16SI 0x9 |
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| 143 | #define OP1_L32AI 0xb |
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| 144 | |
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| 145 | #define OP1_S32I 0x6 |
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| 146 | #define OP1_S16I 0x5 |
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| 147 | #define OP1_S32RI 0xf |
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| 148 | |
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| 149 | /* |
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| 150 | * Entry condition: |
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| 151 | * |
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| 152 | * a0: trashed, original value saved on stack (PT_AREG0) |
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| 153 | * a1: a1 |
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| 154 | * a2: new stack pointer, original in DEPC |
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| 155 | * a3: a3 |
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| 156 | * depc: a2, original value saved on stack (PT_DEPC) |
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| 157 | * excsave_1: dispatch table |
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| 158 | * |
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| 159 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC |
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| 160 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception |
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| 161 | */ |
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| 162 | |
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| 163 | .literal_position |
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| 164 | #ifdef CONFIG_XTENSA_LOAD_STORE |
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| 165 | ENTRY(fast_load_store) |
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| 166 | |
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| 167 | call0 .Lsave_and_load_instruction |
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| 168 | |
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| 169 | /* Analyze the instruction (load or store?). */ |
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| 170 | |
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| 171 | extui a0, a4, INSN_OP0, 4 # get insn.op0 nibble |
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| 172 | |
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| 173 | #if XCHAL_HAVE_DENSITY |
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| 174 | _beqi a0, OP0_L32I_N, 1f # L32I.N, jump |
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| 175 | #endif |
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| 176 | bnei a0, OP0_LSAI, .Linvalid_instruction |
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| 177 | /* 'store indicator bit' set, jump */ |
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| 178 | bbsi.l a4, OP1_SI_BIT + INSN_OP1, .Linvalid_instruction |
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| 179 | |
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| 180 | 1: |
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| 181 | movi a3, ~3 |
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| 182 | and a3, a3, a8 # align memory address |
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| 183 | |
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| 184 | __ssa8 a8 |
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| 185 | |
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| 186 | #ifdef CONFIG_MMU |
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| 187 | /* l32e can't be used here even when it's available. */ |
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| 188 | /* TODO access_ok(a3) could be used here */ |
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| 189 | j .Linvalid_instruction |
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| 190 | #endif |
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| 191 | l32i a5, a3, 0 |
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| 192 | l32i a6, a3, 4 |
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| 193 | __src_b a3, a5, a6 # a3 has the data word |
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| 194 | |
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| 195 | #if XCHAL_HAVE_DENSITY |
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| 196 | addi a7, a7, 2 # increment PC (assume 16-bit insn) |
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| 197 | _beqi a0, OP0_L32I_N, .Lload_w# l32i.n: jump |
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| 198 | addi a7, a7, 1 |
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| 199 | #else |
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| 200 | addi a7, a7, 3 |
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| 201 | #endif |
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| 202 | |
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| 203 | extui a5, a4, INSN_OP1, 4 |
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| 204 | _beqi a5, OP1_L32I, .Lload_w |
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| 205 | bnei a5, OP1_L8UI, .Lload16 |
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| 206 | extui a3, a3, 0, 8 |
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| 207 | j .Lload_w |
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| 208 | |
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| 209 | ENDPROC(fast_load_store) |
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| 210 | #endif |
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| 211 | |
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| 212 | /* |
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| 213 | * Entry condition: |
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| 214 | * |
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| 215 | * a0: trashed, original value saved on stack (PT_AREG0) |
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| 216 | * a1: a1 |
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| 217 | * a2: new stack pointer, original in DEPC |
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| 218 | * a3: a3 |
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| 219 | * depc: a2, original value saved on stack (PT_DEPC) |
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| 220 | * excsave_1: dispatch table |
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| 221 | * |
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| 222 | * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC |
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| 223 | * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception |
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| 224 | */ |
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| 225 | |
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| 226 | #ifdef ANY_EXCEPTION_HANDLER |
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| 227 | ENTRY(fast_unaligned) |
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| 228 | |
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| 229 | call0 .Lsave_and_load_instruction |
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| 230 | |
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| 231 | /* Analyze the instruction (load or store?). */ |
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| 232 | |
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| 233 | extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble |
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| 234 | |
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| 235 | #if XCHAL_HAVE_DENSITY |
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| 236 | _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump |
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| 237 | addi a6, a5, -OP0_S32I_N |
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| 238 | _beqz a6, .Lstore # S32I.N, do a store |
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| 239 | #endif |
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| 240 | /* 'store indicator bit' not set, jump */ |
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| 241 | _bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload |
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| 242 | |
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| 243 | #ifdef STORE_EXCEPTION_HANDLER |
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| 244 | |
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| 245 | /* Store: Jump to table entry to get the value in the source register.*/ |
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| 246 | |
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| 247 | .Lstore:movi a5, .Lstore_table # table |
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| 248 | extui a6, a4, INSN_T, 4 # get source register |
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| 249 | addx8 a5, a6, a5 |
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| 250 | jx a5 # jump into table |
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| 251 | #endif |
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| 252 | #ifdef LOAD_EXCEPTION_HANDLER |
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| 253 | |
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| 254 | /* Load: Load memory address. */ |
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| 255 | |
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| 256 | .Lload: movi a3, ~3 |
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| 257 | and a3, a3, a8 # align memory address |
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| 258 | |
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| 259 | __ssa8 a8 |
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| 260 | #ifdef UNALIGNED_USER_EXCEPTION |
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| 261 | addi a3, a3, 8 |
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| 262 | l32e a5, a3, -8 |
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| 263 | l32e a6, a3, -4 |
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| 264 | #else |
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| 265 | l32i a5, a3, 0 |
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| 266 | l32i a6, a3, 4 |
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| 267 | #endif |
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| 268 | __src_b a3, a5, a6 # a3 has the data word |
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| 269 | |
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| 270 | #if XCHAL_HAVE_DENSITY |
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| 271 | addi a7, a7, 2 # increment PC (assume 16-bit insn) |
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| 272 | |
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| 273 | extui a5, a4, INSN_OP0, 4 |
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| 274 | _beqi a5, OP0_L32I_N, .Lload_w# l32i.n: jump |
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| 275 | |
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| 276 | addi a7, a7, 1 |
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| 277 | #else |
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| 278 | addi a7, a7, 3 |
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| 279 | #endif |
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| 280 | |
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| 281 | extui a5, a4, INSN_OP1, 4 |
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| 282 | _beqi a5, OP1_L32I, .Lload_w # l32i: jump |
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| 283 | #endif |
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| 284 | #ifdef LOAD_EXCEPTION_HANDLER |
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| 285 | .Lload16: |
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| 286 | extui a3, a3, 0, 16 # extract lower 16 bits |
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| 287 | _beqi a5, OP1_L16UI, .Lload_w |
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| 288 | addi a5, a5, -OP1_L16SI |
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| 289 | _bnez a5, .Linvalid_instruction |
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| 290 | |
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| 291 | /* sign extend value */ |
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| 292 | #if XCHAL_HAVE_SEXT |
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| 293 | sext a3, a3, 15 |
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| 294 | #else |
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| 295 | slli a3, a3, 16 |
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| 296 | srai a3, a3, 16 |
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| 297 | #endif |
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| 298 | |
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| 299 | /* Set target register. */ |
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| 300 | |
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| 301 | .Lload_w: |
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| 302 | extui a4, a4, INSN_T, 4 # extract target register |
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| 303 | movi a5, .Lload_table |
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| 304 | addx8 a4, a4, a5 |
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| 305 | jx a4 # jump to entry for target register |
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| 306 | |
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| 307 | .align 8 |
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| 308 | .Lload_table: |
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| 309 | s32i a3, a2, PT_AREG0; _j .Lexit; .align 8 |
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| 310 | mov a1, a3; _j .Lexit; .align 8 # fishy?? |
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| 311 | s32i a3, a2, PT_AREG2; _j .Lexit; .align 8 |
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| 312 | s32i a3, a2, PT_AREG3; _j .Lexit; .align 8 |
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| 313 | s32i a3, a2, PT_AREG4; _j .Lexit; .align 8 |
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| 314 | s32i a3, a2, PT_AREG5; _j .Lexit; .align 8 |
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| 315 | s32i a3, a2, PT_AREG6; _j .Lexit; .align 8 |
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| 316 | s32i a3, a2, PT_AREG7; _j .Lexit; .align 8 |
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| 317 | s32i a3, a2, PT_AREG8; _j .Lexit; .align 8 |
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| 318 | mov a9, a3 ; _j .Lexit; .align 8 |
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| 319 | mov a10, a3 ; _j .Lexit; .align 8 |
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| 320 | mov a11, a3 ; _j .Lexit; .align 8 |
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| 321 | mov a12, a3 ; _j .Lexit; .align 8 |
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| 322 | mov a13, a3 ; _j .Lexit; .align 8 |
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| 323 | mov a14, a3 ; _j .Lexit; .align 8 |
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| 324 | mov a15, a3 ; _j .Lexit; .align 8 |
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| 325 | #endif |
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| 326 | #ifdef STORE_EXCEPTION_HANDLER |
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| 327 | .Lstore_table: |
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| 328 | l32i a3, a2, PT_AREG0; _j .Lstore_w; .align 8 |
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| 329 | mov a3, a1; _j .Lstore_w; .align 8 # fishy?? |
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| 330 | l32i a3, a2, PT_AREG2; _j .Lstore_w; .align 8 |
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| 331 | l32i a3, a2, PT_AREG3; _j .Lstore_w; .align 8 |
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| 332 | l32i a3, a2, PT_AREG4; _j .Lstore_w; .align 8 |
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| 333 | l32i a3, a2, PT_AREG5; _j .Lstore_w; .align 8 |
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| 334 | l32i a3, a2, PT_AREG6; _j .Lstore_w; .align 8 |
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| 335 | l32i a3, a2, PT_AREG7; _j .Lstore_w; .align 8 |
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| 336 | l32i a3, a2, PT_AREG8; _j .Lstore_w; .align 8 |
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| 337 | mov a3, a9 ; _j .Lstore_w; .align 8 |
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| 338 | mov a3, a10 ; _j .Lstore_w; .align 8 |
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| 339 | mov a3, a11 ; _j .Lstore_w; .align 8 |
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| 340 | mov a3, a12 ; _j .Lstore_w; .align 8 |
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| 341 | mov a3, a13 ; _j .Lstore_w; .align 8 |
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| 342 | mov a3, a14 ; _j .Lstore_w; .align 8 |
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| 343 | mov a3, a15 ; _j .Lstore_w; .align 8 |
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| 344 | #endif |
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| 345 | |
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| 346 | /* We cannot handle this exception. */ |
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| 347 | |
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| 348 | .extern _kernel_exception |
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| 349 | .Linvalid_instruction: |
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| 350 | |
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| 351 | movi a4, 0 |
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| 352 | rsr a3, excsave1 |
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| 353 | s32i a4, a3, EXC_TABLE_FIXUP |
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| 354 | |
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| 355 | /* Restore a4...a8 and SAR, set SP, and jump to default exception. */ |
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| 356 | |
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| 357 | l32i a0, a2, PT_SAR |
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| 358 | l32i a8, a2, PT_AREG8 |
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| 359 | l32i a7, a2, PT_AREG7 |
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| 360 | l32i a6, a2, PT_AREG6 |
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| 361 | l32i a5, a2, PT_AREG5 |
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| 362 | l32i a4, a2, PT_AREG4 |
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| 363 | wsr a0, sar |
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| 364 | mov a1, a2 |
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| 365 | |
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| 366 | rsr a0, ps |
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| 367 | bbsi.l a0, PS_UM_BIT, 2f # jump if user mode |
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| 368 | |
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| 369 | movi a0, _kernel_exception |
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| 370 | jx a0 |
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| 371 | |
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| 372 | 2: movi a0, _user_exception |
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| 373 | jx a0 |
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| 374 | |
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| 375 | #ifdef STORE_EXCEPTION_HANDLER |
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| 376 | |
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| 377 | # a7: instruction pointer, a4: instruction, a3: value |
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| 378 | .Lstore_w: |
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| 379 | movi a6, 0 # mask: ffffffff:00000000 |
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| 380 | |
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| 381 | #if XCHAL_HAVE_DENSITY |
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| 382 | addi a7, a7, 2 # incr. PC,assume 16-bit instruction |
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| 383 | |
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| 384 | extui a5, a4, INSN_OP0, 4 # extract OP0 |
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| 385 | addi a5, a5, -OP0_S32I_N |
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| 386 | _beqz a5, 1f # s32i.n: jump |
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| 387 | |
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| 388 | addi a7, a7, 1 # increment PC, 32-bit instruction |
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| 389 | #else |
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| 390 | addi a7, a7, 3 # increment PC, 32-bit instruction |
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| 391 | #endif |
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| 392 | |
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| 393 | extui a5, a4, INSN_OP1, 4 # extract OP1 |
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| 394 | _beqi a5, OP1_S32I, 1f # jump if 32 bit store |
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| 395 | _bnei a5, OP1_S16I, .Linvalid_instruction |
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| 396 | |
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| 397 | movi a5, -1 |
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| 398 | __extl a3, a3 # get 16-bit value |
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| 399 | __exth a6, a5 # get 16-bit mask ffffffff:ffff0000 |
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| 400 | |
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| 401 | /* Get memory address */ |
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| 402 | |
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| 403 | 1: |
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| 404 | movi a4, ~3 |
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| 405 | and a4, a4, a8 # align memory address |
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| 406 | |
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| 407 | /* Insert value into memory */ |
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| 408 | |
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| 409 | movi a5, -1 # mask: ffffffff:XXXX0000 |
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| 410 | #ifdef UNALIGNED_USER_EXCEPTION |
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| 411 | addi a4, a4, 8 |
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| 412 | #endif |
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| 413 | |
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| 414 | __ssa8r a8 |
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| 415 | __src_b a8, a5, a6 # lo-mask F..F0..0 (BE) 0..0F..F (LE) |
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| 416 | __src_b a6, a6, a5 # hi-mask 0..0F..F (BE) F..F0..0 (LE) |
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| 417 | #ifdef UNALIGNED_USER_EXCEPTION |
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| 418 | l32e a5, a4, -8 |
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| 419 | #else |
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| 420 | l32i a5, a4, 0 # load lower address word |
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| 421 | #endif |
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| 422 | and a5, a5, a8 # mask |
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| 423 | __sh a8, a3 # shift value |
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| 424 | or a5, a5, a8 # or with original value |
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| 425 | #ifdef UNALIGNED_USER_EXCEPTION |
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| 426 | s32e a5, a4, -8 |
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| 427 | l32e a8, a4, -4 |
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| 428 | #else |
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| 429 | s32i a5, a4, 0 # store |
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| 430 | l32i a8, a4, 4 # same for upper address word |
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| 431 | #endif |
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| 432 | __sl a5, a3 |
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| 433 | and a6, a8, a6 |
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| 434 | or a6, a6, a5 |
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| 435 | #ifdef UNALIGNED_USER_EXCEPTION |
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| 436 | s32e a6, a4, -4 |
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| 437 | #else |
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| 438 | s32i a6, a4, 4 |
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| 439 | #endif |
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| 440 | #endif |
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| 441 | |
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| 442 | .Lexit: |
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| 443 | #if XCHAL_HAVE_LOOPS |
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| 444 | rsr a4, lend # check if we reached LEND |
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| 445 | bne a7, a4, 1f |
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| 446 | rsr a4, lcount # and LCOUNT != 0 |
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| 447 | beqz a4, 1f |
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| 448 | addi a4, a4, -1 # decrement LCOUNT and set |
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| 449 | rsr a7, lbeg # set PC to LBEGIN |
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| 450 | wsr a4, lcount |
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| 451 | #endif |
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| 452 | |
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| 453 | 1: wsr a7, epc1 # skip emulated instruction |
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| 454 | |
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| 455 | /* Update icount if we're single-stepping in userspace. */ |
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| 456 | rsr a4, icountlevel |
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| 457 | beqz a4, 1f |
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| 458 | bgeui a4, LOCKLEVEL + 1, 1f |
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| 459 | rsr a4, icount |
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| 460 | addi a4, a4, 1 |
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| 461 | wsr a4, icount |
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| 462 | 1: |
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| 463 | movi a4, 0 |
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| 464 | rsr a3, excsave1 |
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| 465 | s32i a4, a3, EXC_TABLE_FIXUP |
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| 466 | |
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| 467 | /* Restore working register */ |
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| 468 | |
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| 469 | l32i a0, a2, PT_SAR |
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| 470 | l32i a8, a2, PT_AREG8 |
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| 471 | l32i a7, a2, PT_AREG7 |
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| 472 | l32i a6, a2, PT_AREG6 |
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| 473 | l32i a5, a2, PT_AREG5 |
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| 474 | l32i a4, a2, PT_AREG4 |
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| 475 | l32i a3, a2, PT_AREG3 |
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| 476 | |
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| 477 | /* restore SAR and return */ |
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| 478 | |
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| 479 | wsr a0, sar |
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| 480 | l32i a0, a2, PT_AREG0 |
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| 481 | l32i a2, a2, PT_AREG2 |
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| 482 | rfe |
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| 483 | |
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| 484 | .align 4 |
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| 485 | .Lsave_and_load_instruction: |
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| 486 | |
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| 487 | /* Save some working register */ |
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| 488 | |
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| 489 | s32i a3, a2, PT_AREG3 |
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| 490 | s32i a4, a2, PT_AREG4 |
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| 491 | s32i a5, a2, PT_AREG5 |
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| 492 | s32i a6, a2, PT_AREG6 |
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| 493 | s32i a7, a2, PT_AREG7 |
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| 494 | s32i a8, a2, PT_AREG8 |
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| 495 | |
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| 496 | rsr a4, depc |
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| 497 | s32i a4, a2, PT_AREG2 |
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| 498 | |
|---|
| 499 | rsr a5, sar |
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| 500 | s32i a5, a2, PT_SAR |
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| 501 | |
|---|
| 502 | rsr a3, excsave1 |
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| 503 | movi a4, fast_unaligned_fixup |
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| 504 | s32i a4, a3, EXC_TABLE_FIXUP |
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| 505 | |
|---|
| 506 | rsr a8, excvaddr # load unaligned memory address |
|---|
| 507 | |
|---|
| 508 | /* Now, identify one of the following load/store instructions. |
|---|
| 509 | * |
|---|
| 510 | * The only possible danger of a double exception on the |
|---|
| 511 | * following l32i instructions is kernel code in vmalloc |
|---|
| 512 | * memory. The processor was just executing at the EPC_1 |
|---|
| 513 | * address, and indeed, already fetched the instruction. That |
|---|
| 514 | * guarantees a TLB mapping, which hasn't been replaced by |
|---|
| 515 | * this unaligned exception handler that uses only static TLB |
|---|
| 516 | * mappings. However, high-level interrupt handlers might |
|---|
| 517 | * modify TLB entries, so for the generic case, we register a |
|---|
| 518 | * TABLE_FIXUP handler here, too. |
|---|
| 519 | */ |
|---|
| 520 | |
|---|
| 521 | /* a3...a6 saved on stack, a2 = SP */ |
|---|
| 522 | |
|---|
| 523 | /* Extract the instruction that caused the unaligned access. */ |
|---|
| 524 | |
|---|
| 525 | rsr a7, epc1 # load exception address |
|---|
| 526 | movi a3, ~3 |
|---|
| 527 | and a3, a3, a7 # mask lower bits |
|---|
| 528 | |
|---|
| 529 | l32i a4, a3, 0 # load 2 words |
|---|
| 530 | l32i a5, a3, 4 |
|---|
| 531 | |
|---|
| 532 | __ssa8 a7 |
|---|
| 533 | __src_b a4, a4, a5 # a4 has the instruction |
|---|
| 534 | |
|---|
| 535 | ret |
|---|
| 536 | |
|---|
| 537 | ENDPROC(fast_unaligned) |
|---|
| 538 | |
|---|
| 539 | ENTRY(fast_unaligned_fixup) |
|---|
| 540 | |
|---|
| 541 | l32i a2, a3, EXC_TABLE_DOUBLE_SAVE |
|---|
| 542 | wsr a3, excsave1 |
|---|
| 543 | |
|---|
| 544 | l32i a8, a2, PT_AREG8 |
|---|
| 545 | l32i a7, a2, PT_AREG7 |
|---|
| 546 | l32i a6, a2, PT_AREG6 |
|---|
| 547 | l32i a5, a2, PT_AREG5 |
|---|
| 548 | l32i a4, a2, PT_SAR |
|---|
| 549 | l32i a0, a2, PT_AREG2 |
|---|
| 550 | wsr a4, sar |
|---|
| 551 | wsr a0, depc # restore depc and a0 |
|---|
| 552 | l32i a4, a2, PT_AREG4 |
|---|
| 553 | |
|---|
| 554 | rsr a0, exccause |
|---|
| 555 | s32i a0, a2, PT_DEPC # mark as a regular exception |
|---|
| 556 | |
|---|
| 557 | rsr a0, ps |
|---|
| 558 | bbsi.l a0, PS_UM_BIT, 1f # jump if user mode |
|---|
| 559 | |
|---|
| 560 | rsr a0, exccause |
|---|
| 561 | addx4 a0, a0, a3 # find entry in table |
|---|
| 562 | l32i a0, a0, EXC_TABLE_FAST_KERNEL # load handler |
|---|
| 563 | l32i a3, a2, PT_AREG3 |
|---|
| 564 | jx a0 |
|---|
| 565 | 1: |
|---|
| 566 | rsr a0, exccause |
|---|
| 567 | addx4 a0, a0, a3 # find entry in table |
|---|
| 568 | l32i a0, a0, EXC_TABLE_FAST_USER # load handler |
|---|
| 569 | l32i a3, a2, PT_AREG3 |
|---|
| 570 | jx a0 |
|---|
| 571 | |
|---|
| 572 | ENDPROC(fast_unaligned_fixup) |
|---|
| 573 | #endif |
|---|
| 574 | |
|---|
