1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Driver for IDT Versaclock 5 |
4 | * |
5 | * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> |
6 | */ |
7 | |
8 | /* |
9 | * Possible optimizations: |
10 | * - Use spread spectrum |
11 | * - Use integer divider in FOD if applicable |
12 | */ |
13 | |
14 | #include <linux/clk.h> |
15 | #include <linux/clk-provider.h> |
16 | #include <linux/delay.h> |
17 | #include <linux/i2c.h> |
18 | #include <linux/interrupt.h> |
19 | #include <linux/mod_devicetable.h> |
20 | #include <linux/module.h> |
21 | #include <linux/of.h> |
22 | #include <linux/property.h> |
23 | #include <linux/regmap.h> |
24 | #include <linux/slab.h> |
25 | |
26 | #include <dt-bindings/clock/versaclock.h> |
27 | |
28 | /* VersaClock5 registers */ |
29 | #define VC5_OTP_CONTROL 0x00 |
30 | |
31 | /* Factory-reserved register block */ |
32 | #define VC5_RSVD_DEVICE_ID 0x01 |
33 | #define VC5_RSVD_ADC_GAIN_7_0 0x02 |
34 | #define VC5_RSVD_ADC_GAIN_15_8 0x03 |
35 | #define VC5_RSVD_ADC_OFFSET_7_0 0x04 |
36 | #define VC5_RSVD_ADC_OFFSET_15_8 0x05 |
37 | #define VC5_RSVD_TEMPY 0x06 |
38 | #define VC5_RSVD_OFFSET_TBIN 0x07 |
39 | #define VC5_RSVD_GAIN 0x08 |
40 | #define VC5_RSVD_TEST_NP 0x09 |
41 | #define VC5_RSVD_UNUSED 0x0a |
42 | #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b |
43 | #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c |
44 | #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d |
45 | #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e |
46 | #define VC5_RSVD_CLK_AMP_123 0x0f |
47 | |
48 | /* Configuration register block */ |
49 | #define VC5_PRIM_SRC_SHDN 0x10 |
50 | #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7) |
51 | #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6) |
52 | #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3) |
53 | #define VC5_PRIM_SRC_SHDN_SP BIT(1) |
54 | #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0) |
55 | |
56 | #define VC5_VCO_BAND 0x11 |
57 | #define VC5_XTAL_X1_LOAD_CAP 0x12 |
58 | #define VC5_XTAL_X2_LOAD_CAP 0x13 |
59 | #define VC5_REF_DIVIDER 0x15 |
60 | #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7) |
61 | #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f) |
62 | |
63 | #define VC5_VCO_CTRL_AND_PREDIV 0x16 |
64 | #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7) |
65 | |
66 | #define VC5_FEEDBACK_INT_DIV 0x17 |
67 | #define VC5_FEEDBACK_INT_DIV_BITS 0x18 |
68 | #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n)) |
69 | #define VC5_RC_CONTROL0 0x1e |
70 | #define VC5_RC_CONTROL1 0x1f |
71 | |
72 | /* These registers are named "Unused Factory Reserved Registers" */ |
73 | #define VC5_RESERVED_X0(idx) (0x20 + ((idx) * 0x10)) |
74 | #define VC5_RESERVED_X0_BYPASS_SYNC BIT(7) /* bypass_sync<idx> bit */ |
75 | |
76 | /* Output divider control for divider 1,2,3,4 */ |
77 | #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10)) |
78 | #define VC5_OUT_DIV_CONTROL_RESET BIT(7) |
79 | #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3) |
80 | #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2) |
81 | #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1) |
82 | #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0) |
83 | |
84 | #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n)) |
85 | #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1) |
86 | |
87 | #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n)) |
88 | #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n)) |
89 | #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n)) |
90 | #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n)) |
91 | #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10)) |
92 | |
93 | /* Clock control register for clock 1,2 */ |
94 | #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n)) |
95 | #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5 |
96 | #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT) |
97 | |
98 | #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL) |
99 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS) |
100 | #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33) |
101 | #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS) |
102 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2) |
103 | #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD) |
104 | #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25) |
105 | |
106 | #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3 |
107 | #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) |
108 | #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) |
109 | #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) |
110 | #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3<<VC5_CLK_OUTPUT_CFG0_PWR_SHIFT) |
111 | #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0 |
112 | #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) |
113 | #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) |
114 | #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) |
115 | #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) |
116 | #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3<<VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT) |
117 | #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0) |
118 | |
119 | #define VC5_CLK_OE_SHDN 0x68 |
120 | #define VC5_CLK_OS_SHDN 0x69 |
121 | |
122 | #define VC5_GLOBAL_REGISTER 0x76 |
123 | #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5) |
124 | |
125 | /* The minimum VCO frequency is 2.5 GHz. The maximum is variant specific. */ |
126 | #define VC5_PLL_VCO_MIN 2500000000UL |
127 | |
128 | /* VC5 Input mux settings */ |
129 | #define VC5_MUX_IN_XIN BIT(0) |
130 | #define VC5_MUX_IN_CLKIN BIT(1) |
131 | |
132 | /* Maximum number of clk_out supported by this driver */ |
133 | #define VC5_MAX_CLK_OUT_NUM 5 |
134 | |
135 | /* Maximum number of FODs supported by this driver */ |
136 | #define VC5_MAX_FOD_NUM 4 |
137 | |
138 | /* flags to describe chip features */ |
139 | /* chip has built-in oscilator */ |
140 | #define VC5_HAS_INTERNAL_XTAL BIT(0) |
141 | /* chip has PFD requency doubler */ |
142 | #define VC5_HAS_PFD_FREQ_DBL BIT(1) |
143 | /* chip has bits to disable FOD sync */ |
144 | #define VC5_HAS_BYPASS_SYNC_BIT BIT(2) |
145 | |
146 | /* Supported IDT VC5 models. */ |
147 | enum vc5_model { |
148 | IDT_VC5_5P49V5923, |
149 | IDT_VC5_5P49V5925, |
150 | IDT_VC5_5P49V5933, |
151 | IDT_VC5_5P49V5935, |
152 | IDT_VC6_5P49V60, |
153 | IDT_VC6_5P49V6901, |
154 | IDT_VC6_5P49V6965, |
155 | IDT_VC6_5P49V6975, |
156 | }; |
157 | |
158 | /* Structure to describe features of a particular VC5 model */ |
159 | struct vc5_chip_info { |
160 | const enum vc5_model model; |
161 | const unsigned int clk_fod_cnt; |
162 | const unsigned int clk_out_cnt; |
163 | const u32 flags; |
164 | const unsigned long vco_max; |
165 | }; |
166 | |
167 | struct vc5_driver_data; |
168 | |
169 | struct vc5_hw_data { |
170 | struct clk_hw hw; |
171 | struct vc5_driver_data *vc5; |
172 | u32 div_int; |
173 | u32 div_frc; |
174 | unsigned int num; |
175 | }; |
176 | |
177 | struct vc5_out_data { |
178 | struct clk_hw hw; |
179 | struct vc5_driver_data *vc5; |
180 | unsigned int num; |
181 | unsigned int clk_output_cfg0; |
182 | unsigned int clk_output_cfg0_mask; |
183 | }; |
184 | |
185 | struct vc5_driver_data { |
186 | struct i2c_client *client; |
187 | struct regmap *regmap; |
188 | const struct vc5_chip_info *chip_info; |
189 | |
190 | struct clk *pin_xin; |
191 | struct clk *pin_clkin; |
192 | unsigned char clk_mux_ins; |
193 | struct clk_hw clk_mux; |
194 | struct clk_hw clk_mul; |
195 | struct clk_hw clk_pfd; |
196 | struct vc5_hw_data clk_pll; |
197 | struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM]; |
198 | struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM]; |
199 | }; |
200 | |
201 | /* |
202 | * VersaClock5 i2c regmap |
203 | */ |
204 | static bool vc5_regmap_is_writeable(struct device *dev, unsigned int reg) |
205 | { |
206 | /* Factory reserved regs, make them read-only */ |
207 | if (reg <= 0xf) |
208 | return false; |
209 | |
210 | /* Factory reserved regs, make them read-only */ |
211 | if (reg == 0x14 || reg == 0x1c || reg == 0x1d) |
212 | return false; |
213 | |
214 | return true; |
215 | } |
216 | |
217 | static const struct regmap_config vc5_regmap_config = { |
218 | .reg_bits = 8, |
219 | .val_bits = 8, |
220 | .cache_type = REGCACHE_MAPLE, |
221 | .max_register = 0x76, |
222 | .writeable_reg = vc5_regmap_is_writeable, |
223 | }; |
224 | |
225 | /* |
226 | * VersaClock5 input multiplexer between XTAL and CLKIN divider |
227 | */ |
228 | static unsigned char vc5_mux_get_parent(struct clk_hw *hw) |
229 | { |
230 | struct vc5_driver_data *vc5 = |
231 | container_of(hw, struct vc5_driver_data, clk_mux); |
232 | const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; |
233 | unsigned int src; |
234 | int ret; |
235 | |
236 | ret = regmap_read(map: vc5->regmap, VC5_PRIM_SRC_SHDN, val: &src); |
237 | if (ret) |
238 | return 0; |
239 | |
240 | src &= mask; |
241 | |
242 | if (src == VC5_PRIM_SRC_SHDN_EN_XTAL) |
243 | return 0; |
244 | |
245 | if (src == VC5_PRIM_SRC_SHDN_EN_CLKIN) |
246 | return 1; |
247 | |
248 | dev_warn(&vc5->client->dev, |
249 | "Invalid clock input configuration (%02x)\n" , src); |
250 | return 0; |
251 | } |
252 | |
253 | static int vc5_mux_set_parent(struct clk_hw *hw, u8 index) |
254 | { |
255 | struct vc5_driver_data *vc5 = |
256 | container_of(hw, struct vc5_driver_data, clk_mux); |
257 | const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN; |
258 | u8 src; |
259 | |
260 | if ((index > 1) || !vc5->clk_mux_ins) |
261 | return -EINVAL; |
262 | |
263 | if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) { |
264 | if (index == 0) |
265 | src = VC5_PRIM_SRC_SHDN_EN_XTAL; |
266 | if (index == 1) |
267 | src = VC5_PRIM_SRC_SHDN_EN_CLKIN; |
268 | } else { |
269 | if (index != 0) |
270 | return -EINVAL; |
271 | |
272 | if (vc5->clk_mux_ins == VC5_MUX_IN_XIN) |
273 | src = VC5_PRIM_SRC_SHDN_EN_XTAL; |
274 | else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN) |
275 | src = VC5_PRIM_SRC_SHDN_EN_CLKIN; |
276 | else /* Invalid; should have been caught by vc5_probe() */ |
277 | return -EINVAL; |
278 | } |
279 | |
280 | return regmap_update_bits(map: vc5->regmap, VC5_PRIM_SRC_SHDN, mask, val: src); |
281 | } |
282 | |
283 | static const struct clk_ops vc5_mux_ops = { |
284 | .determine_rate = clk_hw_determine_rate_no_reparent, |
285 | .set_parent = vc5_mux_set_parent, |
286 | .get_parent = vc5_mux_get_parent, |
287 | }; |
288 | |
289 | static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw, |
290 | unsigned long parent_rate) |
291 | { |
292 | struct vc5_driver_data *vc5 = |
293 | container_of(hw, struct vc5_driver_data, clk_mul); |
294 | unsigned int premul; |
295 | int ret; |
296 | |
297 | ret = regmap_read(map: vc5->regmap, VC5_PRIM_SRC_SHDN, val: &premul); |
298 | if (ret) |
299 | return 0; |
300 | |
301 | if (premul & VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ) |
302 | parent_rate *= 2; |
303 | |
304 | return parent_rate; |
305 | } |
306 | |
307 | static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate, |
308 | unsigned long *parent_rate) |
309 | { |
310 | if ((*parent_rate == rate) || ((*parent_rate * 2) == rate)) |
311 | return rate; |
312 | else |
313 | return -EINVAL; |
314 | } |
315 | |
316 | static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate, |
317 | unsigned long parent_rate) |
318 | { |
319 | struct vc5_driver_data *vc5 = |
320 | container_of(hw, struct vc5_driver_data, clk_mul); |
321 | u32 mask; |
322 | |
323 | if ((parent_rate * 2) == rate) |
324 | mask = VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ; |
325 | else |
326 | mask = 0; |
327 | |
328 | return regmap_update_bits(map: vc5->regmap, VC5_PRIM_SRC_SHDN, |
329 | VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ, |
330 | val: mask); |
331 | } |
332 | |
333 | static const struct clk_ops vc5_dbl_ops = { |
334 | .recalc_rate = vc5_dbl_recalc_rate, |
335 | .round_rate = vc5_dbl_round_rate, |
336 | .set_rate = vc5_dbl_set_rate, |
337 | }; |
338 | |
339 | static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw, |
340 | unsigned long parent_rate) |
341 | { |
342 | struct vc5_driver_data *vc5 = |
343 | container_of(hw, struct vc5_driver_data, clk_pfd); |
344 | unsigned int prediv, div; |
345 | int ret; |
346 | |
347 | ret = regmap_read(map: vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, val: &prediv); |
348 | if (ret) |
349 | return 0; |
350 | |
351 | /* The bypass_prediv is set, PLL fed from Ref_in directly. */ |
352 | if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) |
353 | return parent_rate; |
354 | |
355 | ret = regmap_read(map: vc5->regmap, VC5_REF_DIVIDER, val: &div); |
356 | if (ret) |
357 | return 0; |
358 | |
359 | /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */ |
360 | if (div & VC5_REF_DIVIDER_SEL_PREDIV2) |
361 | return parent_rate / 2; |
362 | else |
363 | return parent_rate / VC5_REF_DIVIDER_REF_DIV(div); |
364 | } |
365 | |
366 | static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate, |
367 | unsigned long *parent_rate) |
368 | { |
369 | unsigned long idiv; |
370 | |
371 | /* PLL cannot operate with input clock above 50 MHz. */ |
372 | if (rate > 50000000) |
373 | return -EINVAL; |
374 | |
375 | /* CLKIN within range of PLL input, feed directly to PLL. */ |
376 | if (*parent_rate <= 50000000) |
377 | return *parent_rate; |
378 | |
379 | idiv = DIV_ROUND_UP(*parent_rate, rate); |
380 | if (idiv > 127) |
381 | return -EINVAL; |
382 | |
383 | return *parent_rate / idiv; |
384 | } |
385 | |
386 | static int vc5_pfd_set_rate(struct clk_hw *hw, unsigned long rate, |
387 | unsigned long parent_rate) |
388 | { |
389 | struct vc5_driver_data *vc5 = |
390 | container_of(hw, struct vc5_driver_data, clk_pfd); |
391 | unsigned long idiv; |
392 | int ret; |
393 | u8 div; |
394 | |
395 | /* CLKIN within range of PLL input, feed directly to PLL. */ |
396 | if (parent_rate <= 50000000) { |
397 | ret = regmap_set_bits(map: vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, |
398 | VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); |
399 | if (ret) |
400 | return ret; |
401 | |
402 | return regmap_update_bits(map: vc5->regmap, VC5_REF_DIVIDER, mask: 0xff, val: 0x00); |
403 | } |
404 | |
405 | idiv = DIV_ROUND_UP(parent_rate, rate); |
406 | |
407 | /* We have dedicated div-2 predivider. */ |
408 | if (idiv == 2) |
409 | div = VC5_REF_DIVIDER_SEL_PREDIV2; |
410 | else |
411 | div = VC5_REF_DIVIDER_REF_DIV(idiv); |
412 | |
413 | ret = regmap_update_bits(map: vc5->regmap, VC5_REF_DIVIDER, mask: 0xff, val: div); |
414 | if (ret) |
415 | return ret; |
416 | |
417 | return regmap_clear_bits(map: vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, |
418 | VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV); |
419 | } |
420 | |
421 | static const struct clk_ops vc5_pfd_ops = { |
422 | .recalc_rate = vc5_pfd_recalc_rate, |
423 | .round_rate = vc5_pfd_round_rate, |
424 | .set_rate = vc5_pfd_set_rate, |
425 | }; |
426 | |
427 | /* |
428 | * VersaClock5 PLL/VCO |
429 | */ |
430 | static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw, |
431 | unsigned long parent_rate) |
432 | { |
433 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
434 | struct vc5_driver_data *vc5 = hwdata->vc5; |
435 | u32 div_int, div_frc; |
436 | u8 fb[5]; |
437 | |
438 | regmap_bulk_read(map: vc5->regmap, VC5_FEEDBACK_INT_DIV, val: fb, val_count: 5); |
439 | |
440 | div_int = (fb[0] << 4) | (fb[1] >> 4); |
441 | div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4]; |
442 | |
443 | /* The PLL divider has 12 integer bits and 24 fractional bits */ |
444 | return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24); |
445 | } |
446 | |
447 | static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
448 | unsigned long *parent_rate) |
449 | { |
450 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
451 | struct vc5_driver_data *vc5 = hwdata->vc5; |
452 | u32 div_int; |
453 | u64 div_frc; |
454 | |
455 | rate = clamp(rate, VC5_PLL_VCO_MIN, vc5->chip_info->vco_max); |
456 | |
457 | /* Determine integer part, which is 12 bit wide */ |
458 | div_int = rate / *parent_rate; |
459 | if (div_int > 0xfff) |
460 | rate = *parent_rate * 0xfff; |
461 | |
462 | /* Determine best fractional part, which is 24 bit wide */ |
463 | div_frc = rate % *parent_rate; |
464 | div_frc *= BIT(24) - 1; |
465 | do_div(div_frc, *parent_rate); |
466 | |
467 | hwdata->div_int = div_int; |
468 | hwdata->div_frc = (u32)div_frc; |
469 | |
470 | return (*parent_rate * div_int) + ((*parent_rate * div_frc) >> 24); |
471 | } |
472 | |
473 | static int vc5_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
474 | unsigned long parent_rate) |
475 | { |
476 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
477 | struct vc5_driver_data *vc5 = hwdata->vc5; |
478 | u8 fb[5]; |
479 | |
480 | fb[0] = hwdata->div_int >> 4; |
481 | fb[1] = hwdata->div_int << 4; |
482 | fb[2] = hwdata->div_frc >> 16; |
483 | fb[3] = hwdata->div_frc >> 8; |
484 | fb[4] = hwdata->div_frc; |
485 | |
486 | return regmap_bulk_write(map: vc5->regmap, VC5_FEEDBACK_INT_DIV, val: fb, val_count: 5); |
487 | } |
488 | |
489 | static const struct clk_ops vc5_pll_ops = { |
490 | .recalc_rate = vc5_pll_recalc_rate, |
491 | .round_rate = vc5_pll_round_rate, |
492 | .set_rate = vc5_pll_set_rate, |
493 | }; |
494 | |
495 | static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw, |
496 | unsigned long parent_rate) |
497 | { |
498 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
499 | struct vc5_driver_data *vc5 = hwdata->vc5; |
500 | /* VCO frequency is divided by two before entering FOD */ |
501 | u32 f_in = parent_rate / 2; |
502 | u32 div_int, div_frc; |
503 | u8 od_int[2]; |
504 | u8 od_frc[4]; |
505 | |
506 | regmap_bulk_read(map: vc5->regmap, VC5_OUT_DIV_INT(hwdata->num, 0), |
507 | val: od_int, val_count: 2); |
508 | regmap_bulk_read(map: vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), |
509 | val: od_frc, val_count: 4); |
510 | |
511 | div_int = (od_int[0] << 4) | (od_int[1] >> 4); |
512 | div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) | |
513 | (od_frc[2] << 6) | (od_frc[3] >> 2); |
514 | |
515 | /* Avoid division by zero if the output is not configured. */ |
516 | if (div_int == 0 && div_frc == 0) |
517 | return 0; |
518 | |
519 | /* The PLL divider has 12 integer bits and 30 fractional bits */ |
520 | return div64_u64(dividend: (u64)f_in << 24ULL, divisor: ((u64)div_int << 24ULL) + div_frc); |
521 | } |
522 | |
523 | static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate, |
524 | unsigned long *parent_rate) |
525 | { |
526 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
527 | /* VCO frequency is divided by two before entering FOD */ |
528 | u32 f_in = *parent_rate / 2; |
529 | u32 div_int; |
530 | u64 div_frc; |
531 | |
532 | /* Determine integer part, which is 12 bit wide */ |
533 | div_int = f_in / rate; |
534 | /* |
535 | * WARNING: The clock chip does not output signal if the integer part |
536 | * of the divider is 0xfff and fractional part is non-zero. |
537 | * Clamp the divider at 0xffe to keep the code simple. |
538 | */ |
539 | if (div_int > 0xffe) { |
540 | div_int = 0xffe; |
541 | rate = f_in / div_int; |
542 | } |
543 | |
544 | /* Determine best fractional part, which is 30 bit wide */ |
545 | div_frc = f_in % rate; |
546 | div_frc <<= 24; |
547 | do_div(div_frc, rate); |
548 | |
549 | hwdata->div_int = div_int; |
550 | hwdata->div_frc = (u32)div_frc; |
551 | |
552 | return div64_u64(dividend: (u64)f_in << 24ULL, divisor: ((u64)div_int << 24ULL) + div_frc); |
553 | } |
554 | |
555 | static int vc5_fod_set_rate(struct clk_hw *hw, unsigned long rate, |
556 | unsigned long parent_rate) |
557 | { |
558 | struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw); |
559 | struct vc5_driver_data *vc5 = hwdata->vc5; |
560 | u8 data[14] = { |
561 | hwdata->div_frc >> 22, hwdata->div_frc >> 14, |
562 | hwdata->div_frc >> 6, hwdata->div_frc << 2, |
563 | 0, 0, 0, 0, 0, |
564 | 0, 0, |
565 | hwdata->div_int >> 4, hwdata->div_int << 4, |
566 | 0 |
567 | }; |
568 | int ret; |
569 | |
570 | ret = regmap_bulk_write(map: vc5->regmap, VC5_OUT_DIV_FRAC(hwdata->num, 0), |
571 | val: data, val_count: 14); |
572 | if (ret) |
573 | return ret; |
574 | |
575 | /* |
576 | * Toggle magic bit in undocumented register for unknown reason. |
577 | * This is what the IDT timing commander tool does and the chip |
578 | * datasheet somewhat implies this is needed, but the register |
579 | * and the bit is not documented. |
580 | */ |
581 | ret = regmap_clear_bits(map: vc5->regmap, VC5_GLOBAL_REGISTER, |
582 | VC5_GLOBAL_REGISTER_GLOBAL_RESET); |
583 | if (ret) |
584 | return ret; |
585 | |
586 | return regmap_set_bits(map: vc5->regmap, VC5_GLOBAL_REGISTER, |
587 | VC5_GLOBAL_REGISTER_GLOBAL_RESET); |
588 | } |
589 | |
590 | static const struct clk_ops vc5_fod_ops = { |
591 | .recalc_rate = vc5_fod_recalc_rate, |
592 | .round_rate = vc5_fod_round_rate, |
593 | .set_rate = vc5_fod_set_rate, |
594 | }; |
595 | |
596 | static int vc5_clk_out_prepare(struct clk_hw *hw) |
597 | { |
598 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
599 | struct vc5_driver_data *vc5 = hwdata->vc5; |
600 | const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | |
601 | VC5_OUT_DIV_CONTROL_SEL_EXT | |
602 | VC5_OUT_DIV_CONTROL_EN_FOD; |
603 | unsigned int src; |
604 | int ret; |
605 | |
606 | /* |
607 | * When enabling a FOD, all currently enabled FODs are briefly |
608 | * stopped in order to synchronize all of them. This causes a clock |
609 | * disruption to any unrelated chips that might be already using |
610 | * other clock outputs. Bypass the sync feature to avoid the issue, |
611 | * which is possible on the VersaClock 6E family via reserved |
612 | * registers. |
613 | */ |
614 | if (vc5->chip_info->flags & VC5_HAS_BYPASS_SYNC_BIT) { |
615 | ret = regmap_set_bits(map: vc5->regmap, |
616 | VC5_RESERVED_X0(hwdata->num), |
617 | VC5_RESERVED_X0_BYPASS_SYNC); |
618 | if (ret) |
619 | return ret; |
620 | } |
621 | |
622 | /* |
623 | * If the input mux is disabled, enable it first and |
624 | * select source from matching FOD. |
625 | */ |
626 | ret = regmap_read(map: vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), val: &src); |
627 | if (ret) |
628 | return ret; |
629 | |
630 | if ((src & mask) == 0) { |
631 | src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD; |
632 | ret = regmap_update_bits(map: vc5->regmap, |
633 | VC5_OUT_DIV_CONTROL(hwdata->num), |
634 | mask: mask | VC5_OUT_DIV_CONTROL_RESET, val: src); |
635 | if (ret) |
636 | return ret; |
637 | } |
638 | |
639 | /* Enable the clock buffer */ |
640 | ret = regmap_set_bits(map: vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), |
641 | VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); |
642 | if (ret) |
643 | return ret; |
644 | |
645 | if (hwdata->clk_output_cfg0_mask) { |
646 | dev_dbg(&vc5->client->dev, "Update output %d mask 0x%0X val 0x%0X\n" , |
647 | hwdata->num, hwdata->clk_output_cfg0_mask, |
648 | hwdata->clk_output_cfg0); |
649 | |
650 | ret = regmap_update_bits(map: vc5->regmap, |
651 | VC5_CLK_OUTPUT_CFG(hwdata->num, 0), |
652 | mask: hwdata->clk_output_cfg0_mask, |
653 | val: hwdata->clk_output_cfg0); |
654 | if (ret) |
655 | return ret; |
656 | } |
657 | |
658 | return 0; |
659 | } |
660 | |
661 | static void vc5_clk_out_unprepare(struct clk_hw *hw) |
662 | { |
663 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
664 | struct vc5_driver_data *vc5 = hwdata->vc5; |
665 | |
666 | /* Disable the clock buffer */ |
667 | regmap_clear_bits(map: vc5->regmap, VC5_CLK_OUTPUT_CFG(hwdata->num, 1), |
668 | VC5_CLK_OUTPUT_CFG1_EN_CLKBUF); |
669 | } |
670 | |
671 | static unsigned char vc5_clk_out_get_parent(struct clk_hw *hw) |
672 | { |
673 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
674 | struct vc5_driver_data *vc5 = hwdata->vc5; |
675 | const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM | |
676 | VC5_OUT_DIV_CONTROL_SEL_EXT | |
677 | VC5_OUT_DIV_CONTROL_EN_FOD; |
678 | const u8 fodclkmask = VC5_OUT_DIV_CONTROL_SELB_NORM | |
679 | VC5_OUT_DIV_CONTROL_EN_FOD; |
680 | const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | |
681 | VC5_OUT_DIV_CONTROL_SEL_EXT; |
682 | unsigned int src; |
683 | int ret; |
684 | |
685 | ret = regmap_read(map: vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), val: &src); |
686 | if (ret) |
687 | return 0; |
688 | |
689 | src &= mask; |
690 | |
691 | if (src == 0) /* Input mux set to DISABLED */ |
692 | return 0; |
693 | |
694 | if ((src & fodclkmask) == VC5_OUT_DIV_CONTROL_EN_FOD) |
695 | return 0; |
696 | |
697 | if (src == extclk) |
698 | return 1; |
699 | |
700 | dev_warn(&vc5->client->dev, |
701 | "Invalid clock output configuration (%02x)\n" , src); |
702 | return 0; |
703 | } |
704 | |
705 | static int vc5_clk_out_set_parent(struct clk_hw *hw, u8 index) |
706 | { |
707 | struct vc5_out_data *hwdata = container_of(hw, struct vc5_out_data, hw); |
708 | struct vc5_driver_data *vc5 = hwdata->vc5; |
709 | const u8 mask = VC5_OUT_DIV_CONTROL_RESET | |
710 | VC5_OUT_DIV_CONTROL_SELB_NORM | |
711 | VC5_OUT_DIV_CONTROL_SEL_EXT | |
712 | VC5_OUT_DIV_CONTROL_EN_FOD; |
713 | const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM | |
714 | VC5_OUT_DIV_CONTROL_SEL_EXT; |
715 | u8 src = VC5_OUT_DIV_CONTROL_RESET; |
716 | |
717 | if (index == 0) |
718 | src |= VC5_OUT_DIV_CONTROL_EN_FOD; |
719 | else |
720 | src |= extclk; |
721 | |
722 | return regmap_update_bits(map: vc5->regmap, VC5_OUT_DIV_CONTROL(hwdata->num), |
723 | mask, val: src); |
724 | } |
725 | |
726 | static const struct clk_ops vc5_clk_out_ops = { |
727 | .prepare = vc5_clk_out_prepare, |
728 | .unprepare = vc5_clk_out_unprepare, |
729 | .determine_rate = clk_hw_determine_rate_no_reparent, |
730 | .set_parent = vc5_clk_out_set_parent, |
731 | .get_parent = vc5_clk_out_get_parent, |
732 | }; |
733 | |
734 | static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec, |
735 | void *data) |
736 | { |
737 | struct vc5_driver_data *vc5 = data; |
738 | unsigned int idx = clkspec->args[0]; |
739 | |
740 | if (idx >= vc5->chip_info->clk_out_cnt) |
741 | return ERR_PTR(error: -EINVAL); |
742 | |
743 | return &vc5->clk_out[idx].hw; |
744 | } |
745 | |
746 | static int vc5_map_index_to_output(const enum vc5_model model, |
747 | const unsigned int n) |
748 | { |
749 | switch (model) { |
750 | case IDT_VC5_5P49V5933: |
751 | return (n == 0) ? 0 : 3; |
752 | case IDT_VC5_5P49V5923: |
753 | case IDT_VC5_5P49V5925: |
754 | case IDT_VC5_5P49V5935: |
755 | case IDT_VC6_5P49V6901: |
756 | case IDT_VC6_5P49V6965: |
757 | case IDT_VC6_5P49V6975: |
758 | default: |
759 | return n; |
760 | } |
761 | } |
762 | |
763 | static int vc5_update_mode(struct device_node *np_output, |
764 | struct vc5_out_data *clk_out) |
765 | { |
766 | u32 value; |
767 | |
768 | if (!of_property_read_u32(np: np_output, propname: "idt,mode" , out_value: &value)) { |
769 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK; |
770 | switch (value) { |
771 | case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL: |
772 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOS: |
773 | case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33: |
774 | case VC5_CLK_OUTPUT_CFG0_CFG_LVDS: |
775 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2: |
776 | case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD: |
777 | case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25: |
778 | clk_out->clk_output_cfg0 |= |
779 | value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT; |
780 | break; |
781 | default: |
782 | return -EINVAL; |
783 | } |
784 | } |
785 | return 0; |
786 | } |
787 | |
788 | static int vc5_update_power(struct device_node *np_output, |
789 | struct vc5_out_data *clk_out) |
790 | { |
791 | u32 value; |
792 | |
793 | if (!of_property_read_u32(np: np_output, propname: "idt,voltage-microvolt" , |
794 | out_value: &value)) { |
795 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK; |
796 | switch (value) { |
797 | case 1800000: |
798 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18; |
799 | break; |
800 | case 2500000: |
801 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25; |
802 | break; |
803 | case 3300000: |
804 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33; |
805 | break; |
806 | default: |
807 | return -EINVAL; |
808 | } |
809 | } |
810 | return 0; |
811 | } |
812 | |
813 | static int vc5_map_cap_value(u32 femtofarads) |
814 | { |
815 | int mapped_value; |
816 | |
817 | /* |
818 | * The datasheet explicitly states 9000 - 25000 with 0.5pF |
819 | * steps, but the Programmer's guide shows the steps are 0.430pF. |
820 | * After getting feedback from Renesas, the .5pF steps were the |
821 | * goal, but 430nF was the actual values. |
822 | * Because of this, the actual range goes to 22760 instead of 25000 |
823 | */ |
824 | if (femtofarads < 9000 || femtofarads > 22760) |
825 | return -EINVAL; |
826 | |
827 | /* |
828 | * The Programmer's guide shows XTAL[5:0] but in reality, |
829 | * XTAL[0] and XTAL[1] are both LSB which makes the math |
830 | * strange. With clarfication from Renesas, setting the |
831 | * values should be simpler by ignoring XTAL[0] |
832 | */ |
833 | mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430); |
834 | |
835 | /* |
836 | * Since the calculation ignores XTAL[0], there is one |
837 | * special case where mapped_value = 32. In reality, this means |
838 | * the real mapped value should be 111111b. In other cases, |
839 | * the mapped_value needs to be shifted 1 to the left. |
840 | */ |
841 | if (mapped_value > 31) |
842 | mapped_value = 0x3f; |
843 | else |
844 | mapped_value <<= 1; |
845 | |
846 | return mapped_value; |
847 | } |
848 | static int vc5_update_cap_load(struct device_node *node, struct vc5_driver_data *vc5) |
849 | { |
850 | u32 value; |
851 | int mapped_value; |
852 | int ret; |
853 | |
854 | if (of_property_read_u32(np: node, propname: "idt,xtal-load-femtofarads" , out_value: &value)) |
855 | return 0; |
856 | |
857 | mapped_value = vc5_map_cap_value(femtofarads: value); |
858 | if (mapped_value < 0) |
859 | return mapped_value; |
860 | |
861 | /* |
862 | * The mapped_value is really the high 6 bits of |
863 | * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so |
864 | * shift the value 2 places. |
865 | */ |
866 | ret = regmap_update_bits(map: vc5->regmap, VC5_XTAL_X1_LOAD_CAP, mask: ~0x03, |
867 | val: mapped_value << 2); |
868 | if (ret) |
869 | return ret; |
870 | |
871 | return regmap_update_bits(map: vc5->regmap, VC5_XTAL_X2_LOAD_CAP, mask: ~0x03, |
872 | val: mapped_value << 2); |
873 | } |
874 | |
875 | static int vc5_update_slew(struct device_node *np_output, |
876 | struct vc5_out_data *clk_out) |
877 | { |
878 | u32 value; |
879 | |
880 | if (!of_property_read_u32(np: np_output, propname: "idt,slew-percent" , out_value: &value)) { |
881 | clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK; |
882 | switch (value) { |
883 | case 80: |
884 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80; |
885 | break; |
886 | case 85: |
887 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85; |
888 | break; |
889 | case 90: |
890 | clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90; |
891 | break; |
892 | case 100: |
893 | clk_out->clk_output_cfg0 |= |
894 | VC5_CLK_OUTPUT_CFG0_SLEW_100; |
895 | break; |
896 | default: |
897 | return -EINVAL; |
898 | } |
899 | } |
900 | return 0; |
901 | } |
902 | |
903 | static int vc5_get_output_config(struct i2c_client *client, |
904 | struct vc5_out_data *clk_out) |
905 | { |
906 | struct device_node *np_output; |
907 | char *child_name; |
908 | int ret = 0; |
909 | |
910 | child_name = kasprintf(GFP_KERNEL, fmt: "OUT%d" , clk_out->num + 1); |
911 | if (!child_name) |
912 | return -ENOMEM; |
913 | |
914 | np_output = of_get_child_by_name(node: client->dev.of_node, name: child_name); |
915 | kfree(objp: child_name); |
916 | if (!np_output) |
917 | return 0; |
918 | |
919 | ret = vc5_update_mode(np_output, clk_out); |
920 | if (ret) |
921 | goto output_error; |
922 | |
923 | ret = vc5_update_power(np_output, clk_out); |
924 | if (ret) |
925 | goto output_error; |
926 | |
927 | ret = vc5_update_slew(np_output, clk_out); |
928 | |
929 | output_error: |
930 | if (ret) { |
931 | dev_err(&client->dev, |
932 | "Invalid clock output configuration OUT%d\n" , |
933 | clk_out->num + 1); |
934 | } |
935 | |
936 | of_node_put(node: np_output); |
937 | |
938 | return ret; |
939 | } |
940 | |
941 | static const struct of_device_id clk_vc5_of_match[]; |
942 | |
943 | static int vc5_probe(struct i2c_client *client) |
944 | { |
945 | unsigned int oe, sd, src_mask = 0, src_val = 0; |
946 | struct vc5_driver_data *vc5; |
947 | struct clk_init_data init; |
948 | const char *parent_names[2]; |
949 | unsigned int n, idx = 0; |
950 | int ret; |
951 | |
952 | vc5 = devm_kzalloc(dev: &client->dev, size: sizeof(*vc5), GFP_KERNEL); |
953 | if (!vc5) |
954 | return -ENOMEM; |
955 | |
956 | i2c_set_clientdata(client, data: vc5); |
957 | vc5->client = client; |
958 | vc5->chip_info = i2c_get_match_data(client); |
959 | |
960 | vc5->pin_xin = devm_clk_get(dev: &client->dev, id: "xin" ); |
961 | if (PTR_ERR(ptr: vc5->pin_xin) == -EPROBE_DEFER) |
962 | return -EPROBE_DEFER; |
963 | |
964 | vc5->pin_clkin = devm_clk_get(dev: &client->dev, id: "clkin" ); |
965 | if (PTR_ERR(ptr: vc5->pin_clkin) == -EPROBE_DEFER) |
966 | return -EPROBE_DEFER; |
967 | |
968 | vc5->regmap = devm_regmap_init_i2c(client, &vc5_regmap_config); |
969 | if (IS_ERR(ptr: vc5->regmap)) |
970 | return dev_err_probe(dev: &client->dev, err: PTR_ERR(ptr: vc5->regmap), |
971 | fmt: "failed to allocate register map\n" ); |
972 | |
973 | ret = of_property_read_u32(np: client->dev.of_node, propname: "idt,shutdown" , out_value: &sd); |
974 | if (!ret) { |
975 | src_mask |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; |
976 | if (sd) |
977 | src_val |= VC5_PRIM_SRC_SHDN_EN_GBL_SHDN; |
978 | } else if (ret != -EINVAL) { |
979 | return dev_err_probe(dev: &client->dev, err: ret, |
980 | fmt: "could not read idt,shutdown\n" ); |
981 | } |
982 | |
983 | ret = of_property_read_u32(np: client->dev.of_node, |
984 | propname: "idt,output-enable-active" , out_value: &oe); |
985 | if (!ret) { |
986 | src_mask |= VC5_PRIM_SRC_SHDN_SP; |
987 | if (oe) |
988 | src_val |= VC5_PRIM_SRC_SHDN_SP; |
989 | } else if (ret != -EINVAL) { |
990 | return dev_err_probe(dev: &client->dev, err: ret, |
991 | fmt: "could not read idt,output-enable-active\n" ); |
992 | } |
993 | |
994 | ret = regmap_update_bits(map: vc5->regmap, VC5_PRIM_SRC_SHDN, mask: src_mask, |
995 | val: src_val); |
996 | if (ret) |
997 | return ret; |
998 | |
999 | /* Register clock input mux */ |
1000 | memset(&init, 0, sizeof(init)); |
1001 | |
1002 | if (!IS_ERR(ptr: vc5->pin_xin)) { |
1003 | vc5->clk_mux_ins |= VC5_MUX_IN_XIN; |
1004 | parent_names[init.num_parents++] = __clk_get_name(clk: vc5->pin_xin); |
1005 | } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) { |
1006 | vc5->pin_xin = clk_register_fixed_rate(dev: &client->dev, |
1007 | name: "internal-xtal" , NULL, |
1008 | flags: 0, fixed_rate: 25000000); |
1009 | if (IS_ERR(ptr: vc5->pin_xin)) |
1010 | return PTR_ERR(ptr: vc5->pin_xin); |
1011 | vc5->clk_mux_ins |= VC5_MUX_IN_XIN; |
1012 | parent_names[init.num_parents++] = __clk_get_name(clk: vc5->pin_xin); |
1013 | } |
1014 | |
1015 | if (!IS_ERR(ptr: vc5->pin_clkin)) { |
1016 | vc5->clk_mux_ins |= VC5_MUX_IN_CLKIN; |
1017 | parent_names[init.num_parents++] = |
1018 | __clk_get_name(clk: vc5->pin_clkin); |
1019 | } |
1020 | |
1021 | if (!init.num_parents) |
1022 | return dev_err_probe(dev: &client->dev, err: -EINVAL, |
1023 | fmt: "no input clock specified!\n" ); |
1024 | |
1025 | /* Configure Optional Loading Capacitance for external XTAL */ |
1026 | if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) { |
1027 | ret = vc5_update_cap_load(node: client->dev.of_node, vc5); |
1028 | if (ret) |
1029 | goto err_clk_register; |
1030 | } |
1031 | |
1032 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.mux" , client->dev.of_node); |
1033 | if (!init.name) { |
1034 | ret = -ENOMEM; |
1035 | goto err_clk; |
1036 | } |
1037 | |
1038 | init.ops = &vc5_mux_ops; |
1039 | init.flags = 0; |
1040 | init.parent_names = parent_names; |
1041 | vc5->clk_mux.init = &init; |
1042 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_mux); |
1043 | if (ret) |
1044 | goto err_clk_register; |
1045 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1046 | |
1047 | if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) { |
1048 | /* Register frequency doubler */ |
1049 | memset(&init, 0, sizeof(init)); |
1050 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.dbl" , |
1051 | client->dev.of_node); |
1052 | if (!init.name) { |
1053 | ret = -ENOMEM; |
1054 | goto err_clk; |
1055 | } |
1056 | init.ops = &vc5_dbl_ops; |
1057 | init.flags = CLK_SET_RATE_PARENT; |
1058 | init.parent_names = parent_names; |
1059 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_mux); |
1060 | init.num_parents = 1; |
1061 | vc5->clk_mul.init = &init; |
1062 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_mul); |
1063 | if (ret) |
1064 | goto err_clk_register; |
1065 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1066 | } |
1067 | |
1068 | /* Register PFD */ |
1069 | memset(&init, 0, sizeof(init)); |
1070 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.pfd" , client->dev.of_node); |
1071 | if (!init.name) { |
1072 | ret = -ENOMEM; |
1073 | goto err_clk; |
1074 | } |
1075 | init.ops = &vc5_pfd_ops; |
1076 | init.flags = CLK_SET_RATE_PARENT; |
1077 | init.parent_names = parent_names; |
1078 | if (vc5->chip_info->flags & VC5_HAS_PFD_FREQ_DBL) |
1079 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_mul); |
1080 | else |
1081 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_mux); |
1082 | init.num_parents = 1; |
1083 | vc5->clk_pfd.init = &init; |
1084 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_pfd); |
1085 | if (ret) |
1086 | goto err_clk_register; |
1087 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1088 | |
1089 | /* Register PLL */ |
1090 | memset(&init, 0, sizeof(init)); |
1091 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.pll" , client->dev.of_node); |
1092 | if (!init.name) { |
1093 | ret = -ENOMEM; |
1094 | goto err_clk; |
1095 | } |
1096 | init.ops = &vc5_pll_ops; |
1097 | init.flags = CLK_SET_RATE_PARENT; |
1098 | init.parent_names = parent_names; |
1099 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_pfd); |
1100 | init.num_parents = 1; |
1101 | vc5->clk_pll.num = 0; |
1102 | vc5->clk_pll.vc5 = vc5; |
1103 | vc5->clk_pll.hw.init = &init; |
1104 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_pll.hw); |
1105 | if (ret) |
1106 | goto err_clk_register; |
1107 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1108 | |
1109 | /* Register FODs */ |
1110 | for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) { |
1111 | idx = vc5_map_index_to_output(model: vc5->chip_info->model, n); |
1112 | memset(&init, 0, sizeof(init)); |
1113 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.fod%d" , |
1114 | client->dev.of_node, idx); |
1115 | if (!init.name) { |
1116 | ret = -ENOMEM; |
1117 | goto err_clk; |
1118 | } |
1119 | init.ops = &vc5_fod_ops; |
1120 | init.flags = CLK_SET_RATE_PARENT; |
1121 | init.parent_names = parent_names; |
1122 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_pll.hw); |
1123 | init.num_parents = 1; |
1124 | vc5->clk_fod[n].num = idx; |
1125 | vc5->clk_fod[n].vc5 = vc5; |
1126 | vc5->clk_fod[n].hw.init = &init; |
1127 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_fod[n].hw); |
1128 | if (ret) |
1129 | goto err_clk_register; |
1130 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1131 | } |
1132 | |
1133 | /* Register MUX-connected OUT0_I2C_SELB output */ |
1134 | memset(&init, 0, sizeof(init)); |
1135 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.out0_sel_i2cb" , |
1136 | client->dev.of_node); |
1137 | if (!init.name) { |
1138 | ret = -ENOMEM; |
1139 | goto err_clk; |
1140 | } |
1141 | init.ops = &vc5_clk_out_ops; |
1142 | init.flags = CLK_SET_RATE_PARENT; |
1143 | init.parent_names = parent_names; |
1144 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_mux); |
1145 | init.num_parents = 1; |
1146 | vc5->clk_out[0].num = idx; |
1147 | vc5->clk_out[0].vc5 = vc5; |
1148 | vc5->clk_out[0].hw.init = &init; |
1149 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_out[0].hw); |
1150 | if (ret) |
1151 | goto err_clk_register; |
1152 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1153 | |
1154 | /* Register FOD-connected OUTx outputs */ |
1155 | for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) { |
1156 | idx = vc5_map_index_to_output(model: vc5->chip_info->model, n: n - 1); |
1157 | parent_names[0] = clk_hw_get_name(hw: &vc5->clk_fod[idx].hw); |
1158 | if (n == 1) |
1159 | parent_names[1] = clk_hw_get_name(hw: &vc5->clk_mux); |
1160 | else |
1161 | parent_names[1] = |
1162 | clk_hw_get_name(hw: &vc5->clk_out[n - 1].hw); |
1163 | |
1164 | memset(&init, 0, sizeof(init)); |
1165 | init.name = kasprintf(GFP_KERNEL, fmt: "%pOFn.out%d" , |
1166 | client->dev.of_node, idx + 1); |
1167 | if (!init.name) { |
1168 | ret = -ENOMEM; |
1169 | goto err_clk; |
1170 | } |
1171 | init.ops = &vc5_clk_out_ops; |
1172 | init.flags = CLK_SET_RATE_PARENT; |
1173 | init.parent_names = parent_names; |
1174 | init.num_parents = 2; |
1175 | vc5->clk_out[n].num = idx; |
1176 | vc5->clk_out[n].vc5 = vc5; |
1177 | vc5->clk_out[n].hw.init = &init; |
1178 | ret = devm_clk_hw_register(dev: &client->dev, hw: &vc5->clk_out[n].hw); |
1179 | if (ret) |
1180 | goto err_clk_register; |
1181 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1182 | |
1183 | /* Fetch Clock Output configuration from DT (if specified) */ |
1184 | ret = vc5_get_output_config(client, clk_out: &vc5->clk_out[n]); |
1185 | if (ret) |
1186 | goto err_clk; |
1187 | } |
1188 | |
1189 | ret = of_clk_add_hw_provider(np: client->dev.of_node, get: vc5_of_clk_get, data: vc5); |
1190 | if (ret) { |
1191 | dev_err_probe(dev: &client->dev, err: ret, |
1192 | fmt: "unable to add clk provider\n" ); |
1193 | goto err_clk; |
1194 | } |
1195 | |
1196 | return 0; |
1197 | |
1198 | err_clk_register: |
1199 | dev_err_probe(dev: &client->dev, err: ret, |
1200 | fmt: "unable to register %s\n" , init.name); |
1201 | kfree(objp: init.name); /* clock framework made a copy of the name */ |
1202 | err_clk: |
1203 | if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) |
1204 | clk_unregister_fixed_rate(clk: vc5->pin_xin); |
1205 | return ret; |
1206 | } |
1207 | |
1208 | static void vc5_remove(struct i2c_client *client) |
1209 | { |
1210 | struct vc5_driver_data *vc5 = i2c_get_clientdata(client); |
1211 | |
1212 | of_clk_del_provider(np: client->dev.of_node); |
1213 | |
1214 | if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) |
1215 | clk_unregister_fixed_rate(clk: vc5->pin_xin); |
1216 | } |
1217 | |
1218 | static int __maybe_unused vc5_suspend(struct device *dev) |
1219 | { |
1220 | struct vc5_driver_data *vc5 = dev_get_drvdata(dev); |
1221 | |
1222 | regcache_cache_only(map: vc5->regmap, enable: true); |
1223 | regcache_mark_dirty(map: vc5->regmap); |
1224 | |
1225 | return 0; |
1226 | } |
1227 | |
1228 | static int __maybe_unused vc5_resume(struct device *dev) |
1229 | { |
1230 | struct vc5_driver_data *vc5 = dev_get_drvdata(dev); |
1231 | int ret; |
1232 | |
1233 | regcache_cache_only(map: vc5->regmap, enable: false); |
1234 | ret = regcache_sync(map: vc5->regmap); |
1235 | if (ret) |
1236 | dev_err(dev, "Failed to restore register map: %d\n" , ret); |
1237 | return ret; |
1238 | } |
1239 | |
1240 | static const struct vc5_chip_info idt_5p49v5923_info = { |
1241 | .model = IDT_VC5_5P49V5923, |
1242 | .clk_fod_cnt = 2, |
1243 | .clk_out_cnt = 3, |
1244 | .flags = 0, |
1245 | .vco_max = 3000000000UL, |
1246 | }; |
1247 | |
1248 | static const struct vc5_chip_info idt_5p49v5925_info = { |
1249 | .model = IDT_VC5_5P49V5925, |
1250 | .clk_fod_cnt = 4, |
1251 | .clk_out_cnt = 5, |
1252 | .flags = 0, |
1253 | .vco_max = 3000000000UL, |
1254 | }; |
1255 | |
1256 | static const struct vc5_chip_info idt_5p49v5933_info = { |
1257 | .model = IDT_VC5_5P49V5933, |
1258 | .clk_fod_cnt = 2, |
1259 | .clk_out_cnt = 3, |
1260 | .flags = VC5_HAS_INTERNAL_XTAL, |
1261 | .vco_max = 3000000000UL, |
1262 | }; |
1263 | |
1264 | static const struct vc5_chip_info idt_5p49v5935_info = { |
1265 | .model = IDT_VC5_5P49V5935, |
1266 | .clk_fod_cnt = 4, |
1267 | .clk_out_cnt = 5, |
1268 | .flags = VC5_HAS_INTERNAL_XTAL, |
1269 | .vco_max = 3000000000UL, |
1270 | }; |
1271 | |
1272 | static const struct vc5_chip_info idt_5p49v60_info = { |
1273 | .model = IDT_VC6_5P49V60, |
1274 | .clk_fod_cnt = 4, |
1275 | .clk_out_cnt = 5, |
1276 | .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, |
1277 | .vco_max = 2700000000UL, |
1278 | }; |
1279 | |
1280 | static const struct vc5_chip_info idt_5p49v6901_info = { |
1281 | .model = IDT_VC6_5P49V6901, |
1282 | .clk_fod_cnt = 4, |
1283 | .clk_out_cnt = 5, |
1284 | .flags = VC5_HAS_PFD_FREQ_DBL | VC5_HAS_BYPASS_SYNC_BIT, |
1285 | .vco_max = 3000000000UL, |
1286 | }; |
1287 | |
1288 | static const struct vc5_chip_info idt_5p49v6965_info = { |
1289 | .model = IDT_VC6_5P49V6965, |
1290 | .clk_fod_cnt = 4, |
1291 | .clk_out_cnt = 5, |
1292 | .flags = VC5_HAS_BYPASS_SYNC_BIT, |
1293 | .vco_max = 3000000000UL, |
1294 | }; |
1295 | |
1296 | static const struct vc5_chip_info idt_5p49v6975_info = { |
1297 | .model = IDT_VC6_5P49V6975, |
1298 | .clk_fod_cnt = 4, |
1299 | .clk_out_cnt = 5, |
1300 | .flags = VC5_HAS_BYPASS_SYNC_BIT | VC5_HAS_INTERNAL_XTAL, |
1301 | .vco_max = 3000000000UL, |
1302 | }; |
1303 | |
1304 | static const struct i2c_device_id vc5_id[] = { |
1305 | { "5p49v5923" , .driver_data = (kernel_ulong_t)&idt_5p49v5923_info }, |
1306 | { "5p49v5925" , .driver_data = (kernel_ulong_t)&idt_5p49v5925_info }, |
1307 | { "5p49v5933" , .driver_data = (kernel_ulong_t)&idt_5p49v5933_info }, |
1308 | { "5p49v5935" , .driver_data = (kernel_ulong_t)&idt_5p49v5935_info }, |
1309 | { "5p49v60" , .driver_data = (kernel_ulong_t)&idt_5p49v60_info }, |
1310 | { "5p49v6901" , .driver_data = (kernel_ulong_t)&idt_5p49v6901_info }, |
1311 | { "5p49v6965" , .driver_data = (kernel_ulong_t)&idt_5p49v6965_info }, |
1312 | { "5p49v6975" , .driver_data = (kernel_ulong_t)&idt_5p49v6975_info }, |
1313 | { } |
1314 | }; |
1315 | MODULE_DEVICE_TABLE(i2c, vc5_id); |
1316 | |
1317 | static const struct of_device_id clk_vc5_of_match[] = { |
1318 | { .compatible = "idt,5p49v5923" , .data = &idt_5p49v5923_info }, |
1319 | { .compatible = "idt,5p49v5925" , .data = &idt_5p49v5925_info }, |
1320 | { .compatible = "idt,5p49v5933" , .data = &idt_5p49v5933_info }, |
1321 | { .compatible = "idt,5p49v5935" , .data = &idt_5p49v5935_info }, |
1322 | { .compatible = "idt,5p49v60" , .data = &idt_5p49v60_info }, |
1323 | { .compatible = "idt,5p49v6901" , .data = &idt_5p49v6901_info }, |
1324 | { .compatible = "idt,5p49v6965" , .data = &idt_5p49v6965_info }, |
1325 | { .compatible = "idt,5p49v6975" , .data = &idt_5p49v6975_info }, |
1326 | { }, |
1327 | }; |
1328 | MODULE_DEVICE_TABLE(of, clk_vc5_of_match); |
1329 | |
1330 | static SIMPLE_DEV_PM_OPS(vc5_pm_ops, vc5_suspend, vc5_resume); |
1331 | |
1332 | static struct i2c_driver vc5_driver = { |
1333 | .driver = { |
1334 | .name = "vc5" , |
1335 | .pm = &vc5_pm_ops, |
1336 | .of_match_table = clk_vc5_of_match, |
1337 | }, |
1338 | .probe = vc5_probe, |
1339 | .remove = vc5_remove, |
1340 | .id_table = vc5_id, |
1341 | }; |
1342 | module_i2c_driver(vc5_driver); |
1343 | |
1344 | MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>" ); |
1345 | MODULE_DESCRIPTION("IDT VersaClock 5 driver" ); |
1346 | MODULE_LICENSE("GPL" ); |
1347 | |