1 | // SPDX-License-Identifier: GPL-2.0 |
2 | #include <linux/clk.h> |
3 | #include <linux/clk-provider.h> |
4 | #include <linux/clkdev.h> |
5 | #include <linux/err.h> |
6 | #include <linux/io.h> |
7 | #include <linux/of.h> |
8 | #include <linux/of_address.h> |
9 | #include <dt-bindings/clock/imx27-clock.h> |
10 | #include <soc/imx/revision.h> |
11 | #include <asm/irq.h> |
12 | |
13 | #include "clk.h" |
14 | |
15 | #define MX27_CCM_BASE_ADDR 0x10027000 |
16 | #define MX27_GPT1_BASE_ADDR 0x10003000 |
17 | #define MX27_INT_GPT1 (NR_IRQS_LEGACY + 26) |
18 | |
19 | static void __iomem *ccm __initdata; |
20 | |
21 | /* Register offsets */ |
22 | #define CCM_CSCR (ccm + 0x00) |
23 | #define CCM_MPCTL0 (ccm + 0x04) |
24 | #define CCM_MPCTL1 (ccm + 0x08) |
25 | #define CCM_SPCTL0 (ccm + 0x0c) |
26 | #define CCM_SPCTL1 (ccm + 0x10) |
27 | #define CCM_PCDR0 (ccm + 0x18) |
28 | #define CCM_PCDR1 (ccm + 0x1c) |
29 | #define CCM_PCCR0 (ccm + 0x20) |
30 | #define CCM_PCCR1 (ccm + 0x24) |
31 | #define CCM_CCSR (ccm + 0x28) |
32 | |
33 | static const char *vpu_sel_clks[] = { "spll" , "mpll_main2" , }; |
34 | static const char *cpu_sel_clks[] = { "mpll_main2" , "mpll" , }; |
35 | static const char *mpll_sel_clks[] = { "fpm" , "mpll_osc_sel" , }; |
36 | static const char *mpll_osc_sel_clks[] = { "ckih_gate" , "ckih_div1p5" , }; |
37 | static const char *clko_sel_clks[] = { |
38 | "ckil" , "fpm" , "ckih_gate" , "ckih_gate" , |
39 | "ckih_gate" , "mpll" , "spll" , "cpu_div" , |
40 | "ahb" , "ipg" , "per1_div" , "per2_div" , |
41 | "per3_div" , "per4_div" , "ssi1_div" , "ssi2_div" , |
42 | "nfc_div" , "mshc_div" , "vpu_div" , "60m" , |
43 | "32k" , "usb_div" , "dptc" , |
44 | }; |
45 | |
46 | static const char *ssi_sel_clks[] = { "spll_gate" , "mpll" , }; |
47 | |
48 | static struct clk *clk[IMX27_CLK_MAX]; |
49 | static struct clk_onecell_data clk_data; |
50 | |
51 | static void __init _mx27_clocks_init(unsigned long fref) |
52 | { |
53 | BUG_ON(!ccm); |
54 | |
55 | clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy" , 0); |
56 | clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih" , fref); |
57 | clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil" , 32768); |
58 | clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm" , "ckil" , 1024, 1); |
59 | clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5" , "ckih_gate" , 2, 3); |
60 | clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate" , "ckih" , CCM_CSCR, 3); |
61 | clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel" , CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); |
62 | clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel" , CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); |
63 | clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll" , "mpll_sel" , CCM_MPCTL0); |
64 | clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll" , "ckih_gate" , CCM_SPCTL0); |
65 | clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate" , "spll" , CCM_CSCR, 1); |
66 | clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2" , "mpll" , 2, 3); |
67 | |
68 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) { |
69 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb" , "mpll_main2" , CCM_CSCR, 8, 2); |
70 | clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg" , "ahb" , 1, 2); |
71 | } else { |
72 | clk[IMX27_CLK_AHB] = imx_clk_divider("ahb" , "mpll_main2" , CCM_CSCR, 9, 4); |
73 | clk[IMX27_CLK_IPG] = imx_clk_divider("ipg" , "ahb" , CCM_CSCR, 8, 1); |
74 | } |
75 | |
76 | clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div" , "ahb" , CCM_PCDR0, 0, 6); |
77 | clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div" , "ahb" , CCM_PCDR0, 6, 4); |
78 | clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div" , "mpll_main2" , CCM_PCDR1, 0, 6); |
79 | clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div" , "mpll_main2" , CCM_PCDR1, 8, 6); |
80 | clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div" , "mpll_main2" , CCM_PCDR1, 16, 6); |
81 | clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div" , "mpll_main2" , CCM_PCDR1, 24, 6); |
82 | clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel" , CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); |
83 | clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div" , "vpu_sel" , CCM_PCDR0, 10, 6); |
84 | clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div" , "spll_gate" , CCM_CSCR, 28, 3); |
85 | clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel" , CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); |
86 | clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel" , CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); |
87 | |
88 | if (mx27_revision() >= IMX_CHIP_REVISION_2_0) |
89 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div" , "cpu_sel" , CCM_CSCR, 12, 2); |
90 | else |
91 | clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div" , "cpu_sel" , CCM_CSCR, 13, 3); |
92 | |
93 | clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div" , "clko_sel" , CCM_PCDR0, 22, 3); |
94 | clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel" , CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
95 | clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel" , CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); |
96 | clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div" , "ssi1_sel" , CCM_PCDR0, 16, 6); |
97 | clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div" , "ssi2_sel" , CCM_PCDR0, 26, 6); |
98 | clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en" , "clko_div" , CCM_PCCR0, 0); |
99 | clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate" , "ipg" , CCM_PCCR0, 0); |
100 | clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate" , "ipg" , CCM_PCCR0, 1); |
101 | clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate" , "ipg" , CCM_PCCR0, 2); |
102 | clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate" , "ipg" , CCM_PCCR0, 3); |
103 | clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate" , "ipg" , CCM_PCCR0, 4); |
104 | clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate" , "ipg" , CCM_PCCR0, 5); |
105 | clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate" , "ipg" , CCM_PCCR0, 6); |
106 | clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate" , "ipg" , CCM_PCCR0, 7); |
107 | clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate" , "ipg" , CCM_PCCR0, 8); |
108 | clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate" , "ipg" , CCM_PCCR0, 9); |
109 | clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate" , "ipg" , CCM_PCCR0, 11); |
110 | clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate" , "ipg" , CCM_PCCR0, 12); |
111 | clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate" , "ipg" , CCM_PCCR0, 13); |
112 | clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate" , "ipg" , CCM_PCCR0, 14); |
113 | clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate" , "ipg" , CCM_PCCR0, 15); |
114 | clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate" , "ipg" , CCM_PCCR0, 16); |
115 | clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate" , "ipg" , CCM_PCCR0, 17); |
116 | clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate" , "ipg" , CCM_PCCR0, 18); |
117 | clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate" , "ipg" , CCM_PCCR0, 19); |
118 | clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate" , "ipg" , CCM_PCCR0, 20); |
119 | clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate" , "ipg" , CCM_PCCR0, 21); |
120 | clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate" , "ipg" , CCM_PCCR0, 22); |
121 | clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate" , "ipg" , CCM_PCCR0, 23); |
122 | clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate" , "ipg" , CCM_PCCR0, 24); |
123 | clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate" , "ipg" , CCM_PCCR0, 25); |
124 | clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate" , "ipg" , CCM_PCCR0, 26); |
125 | clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate" , "ipg" , CCM_PCCR0, 27); |
126 | clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate" , "ipg" , CCM_PCCR0, 28); |
127 | clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate" , "ipg" , CCM_PCCR0, 29); |
128 | clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate" , "ipg" , CCM_PCCR0, 30); |
129 | clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate" , "ipg" , CCM_PCCR0, 31); |
130 | clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate" , "mshc_div" , CCM_PCCR1, 2); |
131 | clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate" , "nfc_div" , CCM_PCCR1, 3); |
132 | clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate" , "ssi2_div" , CCM_PCCR1, 4); |
133 | clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate" , "ssi1_div" , CCM_PCCR1, 5); |
134 | clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate" , "vpu_div" , CCM_PCCR1, 6); |
135 | clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate" , "per4_div" , CCM_PCCR1, 7); |
136 | clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate" , "per3_div" , CCM_PCCR1, 8); |
137 | clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate" , "per2_div" , CCM_PCCR1, 9); |
138 | clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate" , "per1_div" , CCM_PCCR1, 10); |
139 | clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate" , "ahb" , CCM_PCCR1, 11); |
140 | clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate" , "ahb" , CCM_PCCR1, 12); |
141 | clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate" , "ahb" , CCM_PCCR1, 13); |
142 | clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate" , "ahb" , CCM_PCCR1, 14); |
143 | clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate" , "ahb" , CCM_PCCR1, 15); |
144 | clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate" , "ahb" , CCM_PCCR1, 16); |
145 | clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate" , "ahb" , CCM_PCCR1, 17); |
146 | clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate" , "ahb" , CCM_PCCR1, 18); |
147 | clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate" , "ahb" , CCM_PCCR1, 19); |
148 | clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate" , "ahb" , CCM_PCCR1, 20); |
149 | clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate" , "ahb" , CCM_PCCR1, 21); |
150 | clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate" , "ahb" , CCM_PCCR1, 22); |
151 | clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate" , "ahb" , CCM_PCCR1, 23); |
152 | clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate" , "ipg" , CCM_PCCR1, 24); |
153 | clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate" , "ipg" , CCM_PCCR1, 25); |
154 | clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate" , "ipg" , CCM_PCCR1, 26); |
155 | clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate" , "ipg" , CCM_PCCR1, 27); |
156 | clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate" , "ipg" , CCM_PCCR1, 28); |
157 | clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate" , "ipg" , CCM_PCCR1, 29); |
158 | clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate" , "ipg" , CCM_PCCR1, 30); |
159 | clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate" , "ipg" , CCM_PCCR1, 31); |
160 | |
161 | imx_check_clocks(clks: clk, ARRAY_SIZE(clk)); |
162 | |
163 | clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0" ); |
164 | |
165 | clk_prepare_enable(clk: clk[IMX27_CLK_EMI_AHB_GATE]); |
166 | |
167 | imx_register_uart_clocks(); |
168 | |
169 | imx_print_silicon_rev(cpu: "i.MX27" , srev: mx27_revision()); |
170 | } |
171 | |
172 | static void __init mx27_clocks_init_dt(struct device_node *np) |
173 | { |
174 | struct device_node *refnp; |
175 | u32 fref = 26000000; /* default */ |
176 | |
177 | for_each_compatible_node(refnp, NULL, "fixed-clock" ) { |
178 | if (!of_device_is_compatible(device: refnp, "fsl,imx-osc26m" )) |
179 | continue; |
180 | |
181 | if (!of_property_read_u32(np: refnp, propname: "clock-frequency" , out_value: &fref)) { |
182 | of_node_put(node: refnp); |
183 | break; |
184 | } |
185 | } |
186 | |
187 | ccm = of_iomap(node: np, index: 0); |
188 | |
189 | _mx27_clocks_init(fref); |
190 | |
191 | clk_data.clks = clk; |
192 | clk_data.clk_num = ARRAY_SIZE(clk); |
193 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &clk_data); |
194 | } |
195 | CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm" , mx27_clocks_init_dt); |
196 | |