1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright 2018-2019 NXP. |
4 | */ |
5 | |
6 | #include <dt-bindings/clock/imx8mn-clock.h> |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/err.h> |
9 | #include <linux/io.h> |
10 | #include <linux/module.h> |
11 | #include <linux/of_address.h> |
12 | #include <linux/platform_device.h> |
13 | #include <linux/slab.h> |
14 | #include <linux/types.h> |
15 | |
16 | #include "clk.h" |
17 | |
18 | static u32 share_count_sai2; |
19 | static u32 share_count_sai3; |
20 | static u32 share_count_sai5; |
21 | static u32 share_count_sai6; |
22 | static u32 share_count_sai7; |
23 | static u32 share_count_disp; |
24 | static u32 share_count_pdm; |
25 | static u32 share_count_nand; |
26 | |
27 | static const char * const pll_ref_sels[] = { "osc_24m" , "dummy" , "dummy" , "dummy" , }; |
28 | static const char * const audio_pll1_bypass_sels[] = {"audio_pll1" , "audio_pll1_ref_sel" , }; |
29 | static const char * const audio_pll2_bypass_sels[] = {"audio_pll2" , "audio_pll2_ref_sel" , }; |
30 | static const char * const video_pll_bypass_sels[] = {"video_pll" , "video_pll_ref_sel" , }; |
31 | static const char * const dram_pll_bypass_sels[] = {"dram_pll" , "dram_pll_ref_sel" , }; |
32 | static const char * const gpu_pll_bypass_sels[] = {"gpu_pll" , "gpu_pll_ref_sel" , }; |
33 | static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll" , "m7_alt_pll_ref_sel" , }; |
34 | static const char * const arm_pll_bypass_sels[] = {"arm_pll" , "arm_pll_ref_sel" , }; |
35 | static const char * const sys_pll3_bypass_sels[] = {"sys_pll3" , "sys_pll3_ref_sel" , }; |
36 | |
37 | static const char * const imx8mn_a53_sels[] = {"osc_24m" , "arm_pll_out" , "sys_pll2_500m" , |
38 | "sys_pll2_1000m" , "sys_pll1_800m" , "sys_pll1_400m" , |
39 | "audio_pll1_out" , "sys_pll3_out" , }; |
40 | |
41 | static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div" , "arm_pll_out" , }; |
42 | |
43 | static const char * const imx8mn_m7_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll2_250m" , "m7_alt_pll_out" , |
44 | "sys_pll1_800m" , "audio_pll1_out" , "video_pll_out" , "sys_pll3_out" , }; |
45 | |
46 | static const char * const imx8mn_gpu_core_sels[] = {"osc_24m" , "gpu_pll_out" , "sys_pll1_800m" , |
47 | "sys_pll3_out" , "sys_pll2_1000m" , "audio_pll1_out" , |
48 | "video_pll_out" , "audio_pll2_out" , }; |
49 | |
50 | static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m" , "gpu_pll_out" , "sys_pll1_800m" , |
51 | "sys_pll3_out" , "sys_pll2_1000m" , "audio_pll1_out" , |
52 | "video_pll_out" , "audio_pll2_out" , }; |
53 | |
54 | static const char * const imx8mn_main_axi_sels[] = {"osc_24m" , "sys_pll2_333m" , "sys_pll1_800m" , |
55 | "sys_pll2_250m" , "sys_pll2_1000m" , "audio_pll1_out" , |
56 | "video_pll_out" , "sys_pll1_100m" ,}; |
57 | |
58 | static const char * const imx8mn_enet_axi_sels[] = {"osc_24m" , "sys_pll1_266m" , "sys_pll1_800m" , |
59 | "sys_pll2_250m" , "sys_pll2_200m" , "audio_pll1_out" , |
60 | "video_pll_out" , "sys_pll3_out" , }; |
61 | |
62 | static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m" , "sys_pll1_266m" , "sys_pll1_800m" , |
63 | "sys_pll2_200m" , "sys_pll1_133m" , "sys_pll3_out" , |
64 | "sys_pll2_250m" , "audio_pll1_out" , }; |
65 | |
66 | static const char * const imx8mn_disp_axi_sels[] = {"osc_24m" , "sys_pll2_1000m" , "sys_pll1_800m" , |
67 | "sys_pll3_out" , "sys_pll1_40m" , "audio_pll2_out" , |
68 | "clk_ext1" , "clk_ext4" , }; |
69 | |
70 | static const char * const imx8mn_disp_apb_sels[] = {"osc_24m" , "sys_pll2_125m" , "sys_pll1_800m" , |
71 | "sys_pll3_out" , "sys_pll1_40m" , "audio_pll2_out" , |
72 | "clk_ext1" , "clk_ext3" , }; |
73 | |
74 | static const char * const imx8mn_usb_bus_sels[] = {"osc_24m" , "sys_pll2_500m" , "sys_pll1_800m" , |
75 | "sys_pll2_100m" , "sys_pll2_200m" , "clk_ext2" , |
76 | "clk_ext4" , "audio_pll2_out" , }; |
77 | |
78 | static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m" , "sys_pll1_800m" , "gpu_pll_out" , |
79 | "sys_pll3_out" , "sys_pll2_1000m" , "audio_pll1_out" , |
80 | "video_pll_out" , "audio_pll2_out" , }; |
81 | |
82 | static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m" , "sys_pll1_800m" , "gpu_pll_out" , |
83 | "sys_pll3_out" , "sys_pll2_1000m" , "audio_pll1_out" , |
84 | "video_pll_out" , "audio_pll2_out" , }; |
85 | |
86 | static const char * const imx8mn_noc_sels[] = {"osc_24m" , "sys_pll1_800m" , "sys_pll3_out" , |
87 | "sys_pll2_1000m" , "sys_pll2_500m" , "audio_pll1_out" , |
88 | "video_pll_out" , "audio_pll2_out" , }; |
89 | |
90 | static const char * const imx8mn_ahb_sels[] = {"osc_24m" , "sys_pll1_133m" , "sys_pll1_800m" , |
91 | "sys_pll1_400m" , "sys_pll2_125m" , "sys_pll3_out" , |
92 | "audio_pll1_out" , "video_pll_out" , }; |
93 | |
94 | static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m" , "sys_pll2_500m" , "sys_pll1_800m" , |
95 | "sys_pll2_1000m" , "sys_pll2_166m" , "sys_pll3_out" , |
96 | "audio_pll1_out" , "video_pll_out" , }; |
97 | |
98 | static const char * const imx8mn_dram_alt_sels[] = {"osc_24m" , "sys_pll1_800m" , "sys_pll1_100m" , |
99 | "sys_pll2_500m" , "sys_pll2_1000m" , "sys_pll3_out" , |
100 | "audio_pll1_out" , "sys_pll1_266m" , }; |
101 | |
102 | static const char * const imx8mn_dram_apb_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_40m" , |
103 | "sys_pll1_160m" , "sys_pll1_800m" , "sys_pll3_out" , |
104 | "sys_pll2_250m" , "audio_pll2_out" , }; |
105 | |
106 | static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m" , "video_pll_out" , "audio_pll2_out" , |
107 | "audio_pll1_out" , "sys_pll1_800m" , "sys_pll2_1000m" , |
108 | "sys_pll3_out" , "clk_ext4" , }; |
109 | |
110 | static const char * const imx8mn_sai2_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
111 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
112 | "clk_ext2" , "clk_ext3" , }; |
113 | |
114 | static const char * const imx8mn_sai3_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
115 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
116 | "clk_ext3" , "clk_ext4" , }; |
117 | |
118 | static const char * const imx8mn_sai5_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
119 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
120 | "clk_ext2" , "clk_ext3" , }; |
121 | |
122 | static const char * const imx8mn_sai6_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
123 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
124 | "clk_ext3" , "clk_ext4" , }; |
125 | |
126 | static const char * const imx8mn_sai7_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
127 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
128 | "clk_ext3" , "clk_ext4" , }; |
129 | |
130 | static const char * const imx8mn_spdif1_sels[] = {"osc_24m" , "audio_pll1_out" , "audio_pll2_out" , |
131 | "video_pll_out" , "sys_pll1_133m" , "dummy" , |
132 | "clk_ext2" , "clk_ext3" , }; |
133 | |
134 | static const char * const imx8mn_enet_ref_sels[] = {"osc_24m" , "sys_pll2_125m" , "sys_pll2_50m" , |
135 | "sys_pll2_100m" , "sys_pll1_160m" , "audio_pll1_out" , |
136 | "video_pll_out" , "clk_ext4" , }; |
137 | |
138 | static const char * const imx8mn_enet_timer_sels[] = {"osc_24m" , "sys_pll2_100m" , "audio_pll1_out" , |
139 | "clk_ext1" , "clk_ext2" , "clk_ext3" , |
140 | "clk_ext4" , "video_pll_out" , }; |
141 | |
142 | static const char * const imx8mn_enet_phy_sels[] = {"osc_24m" , "sys_pll2_50m" , "sys_pll2_125m" , |
143 | "sys_pll2_200m" , "sys_pll2_500m" , "audio_pll1_out" , |
144 | "video_pll_out" , "audio_pll2_out" , }; |
145 | |
146 | static const char * const imx8mn_nand_sels[] = {"osc_24m" , "sys_pll2_500m" , "audio_pll1_out" , |
147 | "sys_pll1_400m" , "audio_pll2_out" , "sys_pll3_out" , |
148 | "sys_pll2_250m" , "video_pll_out" , }; |
149 | |
150 | static const char * const imx8mn_qspi_sels[] = {"osc_24m" , "sys_pll1_400m" , "sys_pll2_333m" , |
151 | "sys_pll2_500m" , "audio_pll2_out" , "sys_pll1_266m" , |
152 | "sys_pll3_out" , "sys_pll1_100m" , }; |
153 | |
154 | static const char * const imx8mn_usdhc1_sels[] = {"osc_24m" , "sys_pll1_400m" , "sys_pll1_800m" , |
155 | "sys_pll2_500m" , "sys_pll3_out" , "sys_pll1_266m" , |
156 | "audio_pll2_out" , "sys_pll1_100m" , }; |
157 | |
158 | static const char * const imx8mn_usdhc2_sels[] = {"osc_24m" , "sys_pll1_400m" , "sys_pll1_800m" , |
159 | "sys_pll2_500m" , "sys_pll3_out" , "sys_pll1_266m" , |
160 | "audio_pll2_out" , "sys_pll1_100m" , }; |
161 | |
162 | static const char * const imx8mn_i2c1_sels[] = {"osc_24m" , "sys_pll1_160m" , "sys_pll2_50m" , |
163 | "sys_pll3_out" , "audio_pll1_out" , "video_pll_out" , |
164 | "audio_pll2_out" , "sys_pll1_133m" , }; |
165 | |
166 | static const char * const imx8mn_i2c2_sels[] = {"osc_24m" , "sys_pll1_160m" , "sys_pll2_50m" , |
167 | "sys_pll3_out" , "audio_pll1_out" , "video_pll_out" , |
168 | "audio_pll2_out" , "sys_pll1_133m" , }; |
169 | |
170 | static const char * const imx8mn_i2c3_sels[] = {"osc_24m" , "sys_pll1_160m" , "sys_pll2_50m" , |
171 | "sys_pll3_out" , "audio_pll1_out" , "video_pll_out" , |
172 | "audio_pll2_out" , "sys_pll1_133m" , }; |
173 | |
174 | static const char * const imx8mn_i2c4_sels[] = {"osc_24m" , "sys_pll1_160m" , "sys_pll2_50m" , |
175 | "sys_pll3_out" , "audio_pll1_out" , "video_pll_out" , |
176 | "audio_pll2_out" , "sys_pll1_133m" , }; |
177 | |
178 | static const char * const imx8mn_uart1_sels[] = {"osc_24m" , "sys_pll1_80m" , "sys_pll2_200m" , |
179 | "sys_pll2_100m" , "sys_pll3_out" , "clk_ext2" , |
180 | "clk_ext4" , "audio_pll2_out" , }; |
181 | |
182 | static const char * const imx8mn_uart2_sels[] = {"osc_24m" , "sys_pll1_80m" , "sys_pll2_200m" , |
183 | "sys_pll2_100m" , "sys_pll3_out" , "clk_ext2" , |
184 | "clk_ext3" , "audio_pll2_out" , }; |
185 | |
186 | static const char * const imx8mn_uart3_sels[] = {"osc_24m" , "sys_pll1_80m" , "sys_pll2_200m" , |
187 | "sys_pll2_100m" , "sys_pll3_out" , "clk_ext2" , |
188 | "clk_ext4" , "audio_pll2_out" , }; |
189 | |
190 | static const char * const imx8mn_uart4_sels[] = {"osc_24m" , "sys_pll1_80m" , "sys_pll2_200m" , |
191 | "sys_pll2_100m" , "sys_pll3_out" , "clk_ext2" , |
192 | "clk_ext3" , "audio_pll2_out" , }; |
193 | |
194 | static const char * const imx8mn_usb_core_sels[] = {"osc_24m" , "sys_pll1_100m" , "sys_pll1_40m" , |
195 | "sys_pll2_100m" , "sys_pll2_200m" , "clk_ext2" , |
196 | "clk_ext3" , "audio_pll2_out" , }; |
197 | |
198 | static const char * const imx8mn_usb_phy_sels[] = {"osc_24m" , "sys_pll1_100m" , "sys_pll1_40m" , |
199 | "sys_pll2_100m" , "sys_pll2_200m" , "clk_ext2" , |
200 | "clk_ext3" , "audio_pll2_out" , }; |
201 | |
202 | static const char * const imx8mn_gic_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_40m" , |
203 | "sys_pll2_100m" , "sys_pll1_800m" , "clk_ext2" , |
204 | "clk_ext4" , "audio_pll2_out" }; |
205 | |
206 | static const char * const imx8mn_ecspi1_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_40m" , |
207 | "sys_pll1_160m" , "sys_pll1_800m" , "sys_pll3_out" , |
208 | "sys_pll2_250m" , "audio_pll2_out" , }; |
209 | |
210 | static const char * const imx8mn_ecspi2_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_40m" , |
211 | "sys_pll1_160m" , "sys_pll1_800m" , "sys_pll3_out" , |
212 | "sys_pll2_250m" , "audio_pll2_out" , }; |
213 | |
214 | static const char * const imx8mn_pwm1_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_160m" , |
215 | "sys_pll1_40m" , "sys_pll3_out" , "clk_ext1" , |
216 | "sys_pll1_80m" , "video_pll_out" , }; |
217 | |
218 | static const char * const imx8mn_pwm2_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_160m" , |
219 | "sys_pll1_40m" , "sys_pll3_out" , "clk_ext1" , |
220 | "sys_pll1_80m" , "video_pll_out" , }; |
221 | |
222 | static const char * const imx8mn_pwm3_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_160m" , |
223 | "sys_pll1_40m" , "sys_pll3_out" , "clk_ext2" , |
224 | "sys_pll1_80m" , "video_pll_out" , }; |
225 | |
226 | static const char * const imx8mn_pwm4_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_160m" , |
227 | "sys_pll1_40m" , "sys_pll3_out" , "clk_ext2" , |
228 | "sys_pll1_80m" , "video_pll_out" , }; |
229 | |
230 | static const char * const imx8mn_gpt1_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
231 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
232 | "audio_pll1_out" , "clk_ext1" , }; |
233 | |
234 | static const char * const imx8mn_gpt2_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
235 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
236 | "audio_pll1_out" , "clk_ext1" , }; |
237 | |
238 | static const char * const imx8mn_gpt3_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
239 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
240 | "audio_pll1_out" , "clk_ext1" , }; |
241 | |
242 | static const char * const imx8mn_gpt4_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
243 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
244 | "audio_pll1_out" , "clk_ext1" , }; |
245 | |
246 | static const char * const imx8mn_gpt5_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
247 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
248 | "audio_pll1_out" , "clk_ext1" , }; |
249 | |
250 | static const char * const imx8mn_gpt6_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_400m" , |
251 | "sys_pll1_40m" , "video_pll_out" , "sys_pll1_80m" , |
252 | "audio_pll1_out" , "clk_ext1" , }; |
253 | |
254 | static const char * const imx8mn_wdog_sels[] = {"osc_24m" , "sys_pll1_133m" , "sys_pll1_160m" , |
255 | "m7_alt_pll_out" , "sys_pll2_125m" , "sys_pll3_out" , |
256 | "sys_pll1_80m" , "sys_pll2_166m" , }; |
257 | |
258 | static const char * const imx8mn_wrclk_sels[] = {"osc_24m" , "sys_pll1_40m" , "m7_alt_pll_out" , |
259 | "sys_pll3_out" , "sys_pll2_200m" , "sys_pll1_266m" , |
260 | "sys_pll2_500m" , "sys_pll1_100m" , }; |
261 | |
262 | static const char * const imx8mn_dsi_core_sels[] = {"osc_24m" , "sys_pll1_266m" , "sys_pll2_250m" , |
263 | "sys_pll1_800m" , "sys_pll2_1000m" , "sys_pll3_out" , |
264 | "audio_pll2_out" , "video_pll_out" , }; |
265 | |
266 | static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m" , "sys_pll2_125m" , "sys_pll2_100m" , |
267 | "sys_pll1_800m" , "sys_pll2_1000m" , "clk_ext2" , |
268 | "audio_pll2_out" , "video_pll_out" , }; |
269 | |
270 | static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m" , "sys_pll1_266m" , "sys_pll2_100m" , |
271 | "sys_pll1_800m" , "sys_pll2_1000m" , "sys_pll3_out" , |
272 | "audio_pll2_out" , "video_pll_out" , }; |
273 | |
274 | static const char * const imx8mn_usdhc3_sels[] = {"osc_24m" , "sys_pll1_400m" , "sys_pll1_800m" , |
275 | "sys_pll2_500m" , "sys_pll3_out" , "sys_pll1_266m" , |
276 | "audio_pll2_out" , "sys_pll1_100m" , }; |
277 | |
278 | static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m" , "sys_pll1_266m" , "sys_pll2_250m" , |
279 | "sys_pll1_800m" , "sys_pll2_1000m" , "sys_pll3_out" , |
280 | "audio_pll2_out" , "video_pll_out" , }; |
281 | |
282 | static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m" , "sys_pll2_333m" , "sys_pll2_100m" , |
283 | "sys_pll1_800m" , "sys_pll2_1000m" , "clk_ext2" , |
284 | "audio_pll2_out" , "video_pll_out" , }; |
285 | |
286 | static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m" , "sys_pll2_333m" , "sys_pll2_100m" , |
287 | "sys_pll1_800m" , "sys_pll2_1000m" , "clk_ext2" , |
288 | "audio_pll2_out" , "video_pll_out" , }; |
289 | |
290 | static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m" , "sys_pll2_100m" , "sys_pll1_80m" , |
291 | "sys_pll1_800m" , "sys_pll2_1000m" , "sys_pll3_out" , |
292 | "clk_ext3" , "audio_pll2_out" , }; |
293 | |
294 | static const char * const imx8mn_ecspi3_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_40m" , |
295 | "sys_pll1_160m" , "sys_pll1_800m" , "sys_pll3_out" , |
296 | "sys_pll2_250m" , "audio_pll2_out" , }; |
297 | |
298 | static const char * const imx8mn_pdm_sels[] = {"osc_24m" , "sys_pll2_100m" , "audio_pll1_out" , |
299 | "sys_pll1_800m" , "sys_pll2_1000m" , "sys_pll3_out" , |
300 | "clk_ext3" , "audio_pll2_out" , }; |
301 | |
302 | static const char * const imx8mn_dram_core_sels[] = {"dram_pll_out" , "dram_alt_root" , }; |
303 | |
304 | static const char * const imx8mn_clko1_sels[] = {"osc_24m" , "sys_pll1_800m" , "dummy" , |
305 | "sys_pll1_200m" , "audio_pll2_out" , "sys_pll2_500m" , |
306 | "dummy" , "sys_pll1_80m" , }; |
307 | static const char * const imx8mn_clko2_sels[] = {"osc_24m" , "sys_pll2_200m" , "sys_pll1_400m" , |
308 | "sys_pll2_166m" , "sys_pll3_out" , "audio_pll1_out" , |
309 | "video_pll_out" , "osc_32k" , }; |
310 | |
311 | static const char * const clkout_sels[] = {"audio_pll1_out" , "audio_pll2_out" , "video_pll_out" , |
312 | "dummy" , "dummy" , "gpu_pll_out" , "dummy" , |
313 | "arm_pll_out" , "sys_pll1" , "sys_pll2" , "sys_pll3" , |
314 | "dummy" , "dummy" , "osc_24m" , "dummy" , "osc_32k" }; |
315 | |
316 | static struct clk_hw_onecell_data *clk_hw_data; |
317 | static struct clk_hw **hws; |
318 | |
319 | static int imx8mn_clocks_probe(struct platform_device *pdev) |
320 | { |
321 | struct device *dev = &pdev->dev; |
322 | struct device_node *np = dev->of_node; |
323 | void __iomem *base; |
324 | int ret; |
325 | |
326 | clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, |
327 | IMX8MN_CLK_END), GFP_KERNEL); |
328 | if (WARN_ON(!clk_hw_data)) |
329 | return -ENOMEM; |
330 | |
331 | clk_hw_data->num = IMX8MN_CLK_END; |
332 | hws = clk_hw_data->hws; |
333 | |
334 | hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy" , rate: 0); |
335 | hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, name: "osc_24m" ); |
336 | hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, name: "osc_32k" ); |
337 | hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, name: "clk_ext1" ); |
338 | hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, name: "clk_ext2" ); |
339 | hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, name: "clk_ext3" ); |
340 | hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, name: "clk_ext4" ); |
341 | |
342 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx8mn-anatop" ); |
343 | base = devm_of_iomap(dev, node: np, index: 0, NULL); |
344 | of_node_put(node: np); |
345 | if (WARN_ON(IS_ERR(base))) { |
346 | ret = PTR_ERR(ptr: base); |
347 | goto unregister_hws; |
348 | } |
349 | |
350 | hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel" , base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
351 | hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel" , base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
352 | hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel" , base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
353 | hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel" , base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
354 | hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel" , base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
355 | hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel" , base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
356 | hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel" , base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
357 | hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel" , base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
358 | |
359 | hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1" , "audio_pll1_ref_sel" , base, &imx_1443x_pll); |
360 | hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2" , "audio_pll2_ref_sel" , base + 0x14, &imx_1443x_pll); |
361 | hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll" , "video_pll_ref_sel" , base + 0x28, &imx_1443x_pll); |
362 | hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll" , "dram_pll_ref_sel" , base + 0x50, &imx_1443x_dram_pll); |
363 | hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll" , "gpu_pll_ref_sel" , base + 0x64, &imx_1416x_pll); |
364 | hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll" , "m7_alt_pll_ref_sel" , base + 0x74, &imx_1416x_pll); |
365 | hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll" , "arm_pll_ref_sel" , base + 0x84, &imx_1416x_pll); |
366 | hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed(name: "sys_pll1" , rate: 800000000); |
367 | hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed(name: "sys_pll2" , rate: 1000000000); |
368 | hws[IMX8MN_SYS_PLL3] = imx_clk_hw_pll14xx("sys_pll3" , "sys_pll3_ref_sel" , base + 0x114, &imx_1416x_pll); |
369 | |
370 | /* PLL bypass out */ |
371 | hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass" , base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT); |
372 | hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass" , base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT); |
373 | hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass" , base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT); |
374 | hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass" , base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT); |
375 | hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass" , base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT); |
376 | hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass" , base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT); |
377 | hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass" , base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); |
378 | hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass" , base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT); |
379 | |
380 | /* PLL out gate */ |
381 | hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out" , "audio_pll1_bypass" , base, 13); |
382 | hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out" , "audio_pll2_bypass" , base + 0x14, 13); |
383 | hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out" , "video_pll_bypass" , base + 0x28, 13); |
384 | hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out" , "dram_pll_bypass" , base + 0x50, 13); |
385 | hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out" , "gpu_pll_bypass" , base + 0x64, 11); |
386 | hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out" , "m7_alt_pll_bypass" , base + 0x74, 11); |
387 | hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out" , "arm_pll_bypass" , base + 0x84, 11); |
388 | hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out" , "sys_pll3_bypass" , base + 0x114, 11); |
389 | |
390 | /* SYS PLL1 fixed output */ |
391 | hws[IMX8MN_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out" , "sys_pll1" , base + 0x94, 11); |
392 | hws[IMX8MN_SYS_PLL1_40M] = imx_clk_hw_fixed_factor(name: "sys_pll1_40m" , parent: "sys_pll1_out" , mult: 1, div: 20); |
393 | hws[IMX8MN_SYS_PLL1_80M] = imx_clk_hw_fixed_factor(name: "sys_pll1_80m" , parent: "sys_pll1_out" , mult: 1, div: 10); |
394 | hws[IMX8MN_SYS_PLL1_100M] = imx_clk_hw_fixed_factor(name: "sys_pll1_100m" , parent: "sys_pll1_out" , mult: 1, div: 8); |
395 | hws[IMX8MN_SYS_PLL1_133M] = imx_clk_hw_fixed_factor(name: "sys_pll1_133m" , parent: "sys_pll1_out" , mult: 1, div: 6); |
396 | hws[IMX8MN_SYS_PLL1_160M] = imx_clk_hw_fixed_factor(name: "sys_pll1_160m" , parent: "sys_pll1_out" , mult: 1, div: 5); |
397 | hws[IMX8MN_SYS_PLL1_200M] = imx_clk_hw_fixed_factor(name: "sys_pll1_200m" , parent: "sys_pll1_out" , mult: 1, div: 4); |
398 | hws[IMX8MN_SYS_PLL1_266M] = imx_clk_hw_fixed_factor(name: "sys_pll1_266m" , parent: "sys_pll1_out" , mult: 1, div: 3); |
399 | hws[IMX8MN_SYS_PLL1_400M] = imx_clk_hw_fixed_factor(name: "sys_pll1_400m" , parent: "sys_pll1_out" , mult: 1, div: 2); |
400 | hws[IMX8MN_SYS_PLL1_800M] = imx_clk_hw_fixed_factor(name: "sys_pll1_800m" , parent: "sys_pll1_out" , mult: 1, div: 1); |
401 | |
402 | /* SYS PLL2 fixed output */ |
403 | hws[IMX8MN_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out" , "sys_pll2" , base + 0x104, 11); |
404 | hws[IMX8MN_SYS_PLL2_50M] = imx_clk_hw_fixed_factor(name: "sys_pll2_50m" , parent: "sys_pll2_out" , mult: 1, div: 20); |
405 | hws[IMX8MN_SYS_PLL2_100M] = imx_clk_hw_fixed_factor(name: "sys_pll2_100m" , parent: "sys_pll2_out" , mult: 1, div: 10); |
406 | hws[IMX8MN_SYS_PLL2_125M] = imx_clk_hw_fixed_factor(name: "sys_pll2_125m" , parent: "sys_pll2_out" , mult: 1, div: 8); |
407 | hws[IMX8MN_SYS_PLL2_166M] = imx_clk_hw_fixed_factor(name: "sys_pll2_166m" , parent: "sys_pll2_out" , mult: 1, div: 6); |
408 | hws[IMX8MN_SYS_PLL2_200M] = imx_clk_hw_fixed_factor(name: "sys_pll2_200m" , parent: "sys_pll2_out" , mult: 1, div: 5); |
409 | hws[IMX8MN_SYS_PLL2_250M] = imx_clk_hw_fixed_factor(name: "sys_pll2_250m" , parent: "sys_pll2_out" , mult: 1, div: 4); |
410 | hws[IMX8MN_SYS_PLL2_333M] = imx_clk_hw_fixed_factor(name: "sys_pll2_333m" , parent: "sys_pll2_out" , mult: 1, div: 3); |
411 | hws[IMX8MN_SYS_PLL2_500M] = imx_clk_hw_fixed_factor(name: "sys_pll2_500m" , parent: "sys_pll2_out" , mult: 1, div: 2); |
412 | hws[IMX8MN_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor(name: "sys_pll2_1000m" , parent: "sys_pll2_out" , mult: 1, div: 1); |
413 | |
414 | hws[IMX8MN_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel" , base + 0x128, 4, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); |
415 | hws[IMX8MN_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div" , "clkout1_sel" , base + 0x128, 0, 4); |
416 | hws[IMX8MN_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1" , "clkout1_div" , base + 0x128, 8); |
417 | hws[IMX8MN_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel" , base + 0x128, 20, 4, clkout_sels, ARRAY_SIZE(clkout_sels)); |
418 | hws[IMX8MN_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div" , "clkout2_sel" , base + 0x128, 16, 4); |
419 | hws[IMX8MN_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2" , "clkout2_div" , base + 0x128, 24); |
420 | |
421 | np = dev->of_node; |
422 | base = devm_platform_ioremap_resource(pdev, index: 0); |
423 | if (WARN_ON(IS_ERR(base))) { |
424 | ret = PTR_ERR(ptr: base); |
425 | goto unregister_hws; |
426 | } |
427 | |
428 | /* CORE */ |
429 | hws[IMX8MN_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div" , imx8mn_a53_sels, base + 0x8000); |
430 | hws[IMX8MN_CLK_A53_SRC] = hws[IMX8MN_CLK_A53_DIV]; |
431 | hws[IMX8MN_CLK_A53_CG] = hws[IMX8MN_CLK_A53_DIV]; |
432 | |
433 | hws[IMX8MN_CLK_M7_CORE] = imx8m_clk_hw_composite_core("arm_m7_core" , imx8mn_m7_sels, base + 0x8080); |
434 | |
435 | hws[IMX8MN_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core" , imx8mn_gpu_core_sels, base + 0x8180); |
436 | hws[IMX8MN_CLK_GPU_SHADER] = imx8m_clk_hw_composite_core("gpu_shader" , imx8mn_gpu_shader_sels, base + 0x8200); |
437 | |
438 | hws[IMX8MN_CLK_GPU_CORE_SRC] = hws[IMX8MN_CLK_GPU_CORE]; |
439 | hws[IMX8MN_CLK_GPU_CORE_CG] = hws[IMX8MN_CLK_GPU_CORE]; |
440 | hws[IMX8MN_CLK_GPU_CORE_DIV] = hws[IMX8MN_CLK_GPU_CORE]; |
441 | hws[IMX8MN_CLK_GPU_SHADER_SRC] = hws[IMX8MN_CLK_GPU_SHADER]; |
442 | hws[IMX8MN_CLK_GPU_SHADER_CG] = hws[IMX8MN_CLK_GPU_SHADER]; |
443 | hws[IMX8MN_CLK_GPU_SHADER_DIV] = hws[IMX8MN_CLK_GPU_SHADER]; |
444 | |
445 | /* CORE SEL */ |
446 | hws[IMX8MN_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core" , base + 0x9880, 24, 1, imx8mn_a53_core_sels, ARRAY_SIZE(imx8mn_a53_core_sels)); |
447 | |
448 | /* BUS */ |
449 | hws[IMX8MN_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi" , imx8mn_main_axi_sels, base + 0x8800); |
450 | hws[IMX8MN_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi" , imx8mn_enet_axi_sels, base + 0x8880); |
451 | hws[IMX8MN_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus" , imx8mn_nand_usdhc_sels, base + 0x8900); |
452 | hws[IMX8MN_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi" , imx8mn_disp_axi_sels, base + 0x8a00); |
453 | hws[IMX8MN_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb" , imx8mn_disp_apb_sels, base + 0x8a80); |
454 | hws[IMX8MN_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus" , imx8mn_usb_bus_sels, base + 0x8b80); |
455 | hws[IMX8MN_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi" , imx8mn_gpu_axi_sels, base + 0x8c00); |
456 | hws[IMX8MN_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb" , imx8mn_gpu_ahb_sels, base + 0x8c80); |
457 | hws[IMX8MN_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc" , imx8mn_noc_sels, base + 0x8d00); |
458 | |
459 | hws[IMX8MN_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb" , imx8mn_ahb_sels, base + 0x9000); |
460 | hws[IMX8MN_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb" , imx8mn_audio_ahb_sels, base + 0x9100); |
461 | hws[IMX8MN_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root" , "ahb" , base + 0x9080, 0, 1); |
462 | hws[IMX8MN_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root" , "audio_ahb" , base + 0x9180, 0, 1); |
463 | hws[IMX8MN_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk" , base + 0x9800, 24, 1, imx8mn_dram_core_sels, ARRAY_SIZE(imx8mn_dram_core_sels), CLK_IS_CRITICAL); |
464 | |
465 | /* |
466 | * DRAM clocks are manipulated from TF-A outside clock framework. |
467 | * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE |
468 | * as div value should always be read from hardware |
469 | */ |
470 | hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt" , imx8mn_dram_alt_sels, base + 0xa000); |
471 | hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb" , imx8mn_dram_apb_sels, base + 0xa080); |
472 | |
473 | hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel" , imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); |
474 | hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2" , imx8mn_sai2_sels, base + 0xa600); |
475 | hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3" , imx8mn_sai3_sels, base + 0xa680); |
476 | hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5" , imx8mn_sai5_sels, base + 0xa780); |
477 | hws[IMX8MN_CLK_SAI6] = imx8m_clk_hw_composite("sai6" , imx8mn_sai6_sels, base + 0xa800); |
478 | hws[IMX8MN_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1" , imx8mn_spdif1_sels, base + 0xa880); |
479 | hws[IMX8MN_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref" , imx8mn_enet_ref_sels, base + 0xa980); |
480 | hws[IMX8MN_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer" , imx8mn_enet_timer_sels, base + 0xaa00); |
481 | hws[IMX8MN_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy" , imx8mn_enet_phy_sels, base + 0xaa80); |
482 | hws[IMX8MN_CLK_NAND] = imx8m_clk_hw_composite("nand" , imx8mn_nand_sels, base + 0xab00); |
483 | hws[IMX8MN_CLK_QSPI] = imx8m_clk_hw_composite("qspi" , imx8mn_qspi_sels, base + 0xab80); |
484 | hws[IMX8MN_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1" , imx8mn_usdhc1_sels, base + 0xac00); |
485 | hws[IMX8MN_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2" , imx8mn_usdhc2_sels, base + 0xac80); |
486 | hws[IMX8MN_CLK_I2C1] = imx8m_clk_hw_composite("i2c1" , imx8mn_i2c1_sels, base + 0xad00); |
487 | hws[IMX8MN_CLK_I2C2] = imx8m_clk_hw_composite("i2c2" , imx8mn_i2c2_sels, base + 0xad80); |
488 | hws[IMX8MN_CLK_I2C3] = imx8m_clk_hw_composite("i2c3" , imx8mn_i2c3_sels, base + 0xae00); |
489 | hws[IMX8MN_CLK_I2C4] = imx8m_clk_hw_composite("i2c4" , imx8mn_i2c4_sels, base + 0xae80); |
490 | hws[IMX8MN_CLK_UART1] = imx8m_clk_hw_composite("uart1" , imx8mn_uart1_sels, base + 0xaf00); |
491 | hws[IMX8MN_CLK_UART2] = imx8m_clk_hw_composite("uart2" , imx8mn_uart2_sels, base + 0xaf80); |
492 | hws[IMX8MN_CLK_UART3] = imx8m_clk_hw_composite("uart3" , imx8mn_uart3_sels, base + 0xb000); |
493 | hws[IMX8MN_CLK_UART4] = imx8m_clk_hw_composite("uart4" , imx8mn_uart4_sels, base + 0xb080); |
494 | hws[IMX8MN_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref" , imx8mn_usb_core_sels, base + 0xb100); |
495 | hws[IMX8MN_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref" , imx8mn_usb_phy_sels, base + 0xb180); |
496 | hws[IMX8MN_CLK_GIC] = imx8m_clk_hw_composite_critical("gic" , imx8mn_gic_sels, base + 0xb200); |
497 | hws[IMX8MN_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1" , imx8mn_ecspi1_sels, base + 0xb280); |
498 | hws[IMX8MN_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2" , imx8mn_ecspi2_sels, base + 0xb300); |
499 | hws[IMX8MN_CLK_PWM1] = imx8m_clk_hw_composite("pwm1" , imx8mn_pwm1_sels, base + 0xb380); |
500 | hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2" , imx8mn_pwm2_sels, base + 0xb400); |
501 | hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3" , imx8mn_pwm3_sels, base + 0xb480); |
502 | hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4" , imx8mn_pwm4_sels, base + 0xb500); |
503 | hws[IMX8MN_CLK_GPT1] = imx8m_clk_hw_composite("gpt1" , imx8mn_gpt1_sels, base + 0xb580); |
504 | hws[IMX8MN_CLK_GPT2] = imx8m_clk_hw_composite("gpt2" , imx8mn_gpt2_sels, base + 0xb600); |
505 | hws[IMX8MN_CLK_GPT3] = imx8m_clk_hw_composite("gpt3" , imx8mn_gpt3_sels, base + 0xb680); |
506 | hws[IMX8MN_CLK_GPT4] = imx8m_clk_hw_composite("gpt4" , imx8mn_gpt4_sels, base + 0xb700); |
507 | hws[IMX8MN_CLK_GPT5] = imx8m_clk_hw_composite("gpt5" , imx8mn_gpt5_sels, base + 0xb780); |
508 | hws[IMX8MN_CLK_GPT6] = imx8m_clk_hw_composite("gpt6" , imx8mn_gpt6_sels, base + 0xb800); |
509 | hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog" , imx8mn_wdog_sels, base + 0xb900); |
510 | hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk" , imx8mn_wrclk_sels, base + 0xb980); |
511 | hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1" , imx8mn_clko1_sels, base + 0xba00); |
512 | hws[IMX8MN_CLK_CLKO2] = imx8m_clk_hw_composite("clko2" , imx8mn_clko2_sels, base + 0xba80); |
513 | hws[IMX8MN_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core" , imx8mn_dsi_core_sels, base + 0xbb00); |
514 | hws[IMX8MN_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref" , imx8mn_dsi_phy_sels, base + 0xbb80); |
515 | hws[IMX8MN_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi" , imx8mn_dsi_dbi_sels, base + 0xbc00); |
516 | hws[IMX8MN_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3" , imx8mn_usdhc3_sels, base + 0xbc80); |
517 | hws[IMX8MN_CLK_CAMERA_PIXEL] = imx8m_clk_hw_composite("camera_pixel" , imx8mn_camera_pixel_sels, base + 0xbd00); |
518 | hws[IMX8MN_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref" , imx8mn_csi1_phy_sels, base + 0xbd80); |
519 | hws[IMX8MN_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref" , imx8mn_csi2_phy_sels, base + 0xbf00); |
520 | hws[IMX8MN_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc" , imx8mn_csi2_esc_sels, base + 0xbf80); |
521 | hws[IMX8MN_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3" , imx8mn_ecspi3_sels, base + 0xc180); |
522 | hws[IMX8MN_CLK_PDM] = imx8m_clk_hw_composite("pdm" , imx8mn_pdm_sels, base + 0xc200); |
523 | hws[IMX8MN_CLK_SAI7] = imx8m_clk_hw_composite("sai7" , imx8mn_sai7_sels, base + 0xc300); |
524 | |
525 | hws[IMX8MN_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk" , "ecspi1" , base + 0x4070, 0); |
526 | hws[IMX8MN_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk" , "ecspi2" , base + 0x4080, 0); |
527 | hws[IMX8MN_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk" , "ecspi3" , base + 0x4090, 0); |
528 | hws[IMX8MN_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk" , "enet_axi" , base + 0x40a0, 0); |
529 | hws[IMX8MN_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk" , "ipg_root" , base + 0x40b0, 0); |
530 | hws[IMX8MN_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk" , "ipg_root" , base + 0x40c0, 0); |
531 | hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk" , "ipg_root" , base + 0x40d0, 0); |
532 | hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk" , "ipg_root" , base + 0x40e0, 0); |
533 | hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk" , "ipg_root" , base + 0x40f0, 0); |
534 | hws[IMX8MN_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk" , "gpt1" , base + 0x4100, 0); |
535 | hws[IMX8MN_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk" , "gpt2" , base + 0x4110, 0); |
536 | hws[IMX8MN_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk" , "gpt3" , base + 0x4120, 0); |
537 | hws[IMX8MN_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk" , "gpt4" , base + 0x4130, 0); |
538 | hws[IMX8MN_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk" , "gpt5" , base + 0x4140, 0); |
539 | hws[IMX8MN_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk" , "gpt6" , base + 0x4150, 0); |
540 | hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk" , "i2c1" , base + 0x4170, 0); |
541 | hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk" , "i2c2" , base + 0x4180, 0); |
542 | hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk" , "i2c3" , base + 0x4190, 0); |
543 | hws[IMX8MN_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk" , "i2c4" , base + 0x41a0, 0); |
544 | hws[IMX8MN_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk" , "ipg_root" , base + 0x4210, 0); |
545 | hws[IMX8MN_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk" , "ipg_root" , base + 0x4220, 0); |
546 | hws[IMX8MN_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk" , "pwm1" , base + 0x4280, 0); |
547 | hws[IMX8MN_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk" , "pwm2" , base + 0x4290, 0); |
548 | hws[IMX8MN_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk" , "pwm3" , base + 0x42a0, 0); |
549 | hws[IMX8MN_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk" , "pwm4" , base + 0x42b0, 0); |
550 | hws[IMX8MN_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk" , "qspi" , base + 0x42f0, 0); |
551 | hws[IMX8MN_CLK_NAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk" , "nand" , base + 0x4300, 0, &share_count_nand); |
552 | hws[IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk" , "nand_usdhc_bus" , base + 0x4300, 0, &share_count_nand); |
553 | hws[IMX8MN_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk" , "sai2" , base + 0x4340, 0, &share_count_sai2); |
554 | hws[IMX8MN_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk" , "ipg_audio_root" , base + 0x4340, 0, &share_count_sai2); |
555 | hws[IMX8MN_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk" , "sai3" , base + 0x4350, 0, &share_count_sai3); |
556 | hws[IMX8MN_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk" , "ipg_audio_root" , base + 0x4350, 0, &share_count_sai3); |
557 | hws[IMX8MN_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk" , "sai5" , base + 0x4370, 0, &share_count_sai5); |
558 | hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk" , "ipg_audio_root" , base + 0x4370, 0, &share_count_sai5); |
559 | hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk" , "sai6" , base + 0x4380, 0, &share_count_sai6); |
560 | hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk" , "ipg_audio_root" , base + 0x4380, 0, &share_count_sai6); |
561 | hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk" , "uart1" , base + 0x4490, 0); |
562 | hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk" , "uart2" , base + 0x44a0, 0); |
563 | hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk" , "uart3" , base + 0x44b0, 0); |
564 | hws[IMX8MN_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk" , "uart4" , base + 0x44c0, 0); |
565 | hws[IMX8MN_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk" , "usb_bus" , base + 0x44d0, 0); |
566 | hws[IMX8MN_CLK_GPU_CORE_ROOT] = imx_clk_hw_gate4("gpu_core_root_clk" , "gpu_core" , base + 0x44f0, 0); |
567 | hws[IMX8MN_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk" , "usdhc1" , base + 0x4510, 0); |
568 | hws[IMX8MN_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk" , "usdhc2" , base + 0x4520, 0); |
569 | hws[IMX8MN_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk" , "wdog" , base + 0x4530, 0); |
570 | hws[IMX8MN_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk" , "wdog" , base + 0x4540, 0); |
571 | hws[IMX8MN_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk" , "wdog" , base + 0x4550, 0); |
572 | hws[IMX8MN_CLK_GPU_BUS_ROOT] = imx_clk_hw_gate4("gpu_root_clk" , "gpu_axi" , base + 0x4570, 0); |
573 | hws[IMX8MN_CLK_ASRC_ROOT] = imx_clk_hw_gate4("asrc_root_clk" , "audio_ahb" , base + 0x4580, 0); |
574 | hws[IMX8MN_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root_clk" , "pdm" , base + 0x45b0, 0, &share_count_pdm); |
575 | hws[IMX8MN_CLK_PDM_IPG] = imx_clk_hw_gate2_shared2("pdm_ipg_clk" , "ipg_audio_root" , base + 0x45b0, 0, &share_count_pdm); |
576 | hws[IMX8MN_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk" , "disp_axi" , base + 0x45d0, 0, &share_count_disp); |
577 | hws[IMX8MN_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk" , "disp_apb" , base + 0x45d0, 0, &share_count_disp); |
578 | hws[IMX8MN_CLK_CAMERA_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("camera_pixel_clk" , "camera_pixel" , base + 0x45d0, 0, &share_count_disp); |
579 | hws[IMX8MN_CLK_DISP_PIXEL_ROOT] = imx_clk_hw_gate2_shared2("disp_pixel_clk" , "disp_pixel" , base + 0x45d0, 0, &share_count_disp); |
580 | hws[IMX8MN_CLK_USDHC3_ROOT] = imx_clk_hw_gate4("usdhc3_root_clk" , "usdhc3" , base + 0x45e0, 0); |
581 | hws[IMX8MN_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk" , "ipg_root" , base + 0x4620, 0); |
582 | hws[IMX8MN_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk" , "ipg_root" , base + 0x43a0, 0); |
583 | hws[IMX8MN_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk" , "ipg_audio_root" , base + 0x43b0, 0); |
584 | hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk" , "ipg_audio_root" , base + 0x45f0, 0); |
585 | hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk" , "sai7" , base + 0x4650, 0, &share_count_sai7); |
586 | |
587 | hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor(name: "gpt_3m" , parent: "osc_24m" , mult: 1, div: 8); |
588 | |
589 | hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor(name: "dram_alt_root" , parent: "dram_alt" , mult: 1, div: 4); |
590 | |
591 | hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu(name: "arm" , parent_name: "arm_a53_core" , |
592 | div: hws[IMX8MN_CLK_A53_CORE]->clk, |
593 | mux: hws[IMX8MN_CLK_A53_CORE]->clk, |
594 | pll: hws[IMX8MN_ARM_PLL_OUT]->clk, |
595 | step: hws[IMX8MN_CLK_A53_DIV]->clk); |
596 | |
597 | imx_check_clk_hws(clks: hws, IMX8MN_CLK_END); |
598 | |
599 | ret = of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data); |
600 | if (ret < 0) { |
601 | dev_err(dev, "failed to register hws for i.MX8MN\n" ); |
602 | goto unregister_hws; |
603 | } |
604 | |
605 | imx_register_uart_clocks(); |
606 | |
607 | return 0; |
608 | |
609 | unregister_hws: |
610 | imx_unregister_hw_clocks(hws, IMX8MN_CLK_END); |
611 | |
612 | return ret; |
613 | } |
614 | |
615 | static const struct of_device_id imx8mn_clk_of_match[] = { |
616 | { .compatible = "fsl,imx8mn-ccm" }, |
617 | { /* Sentinel */ }, |
618 | }; |
619 | MODULE_DEVICE_TABLE(of, imx8mn_clk_of_match); |
620 | |
621 | static struct platform_driver imx8mn_clk_driver = { |
622 | .probe = imx8mn_clocks_probe, |
623 | .driver = { |
624 | .name = "imx8mn-ccm" , |
625 | /* |
626 | * Disable bind attributes: clocks are not removed and |
627 | * reloading the driver will crash or break devices. |
628 | */ |
629 | .suppress_bind_attrs = true, |
630 | .of_match_table = imx8mn_clk_of_match, |
631 | }, |
632 | }; |
633 | module_platform_driver(imx8mn_clk_driver); |
634 | module_param(mcore_booted, bool, S_IRUGO); |
635 | MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not" ); |
636 | |
637 | MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>" ); |
638 | MODULE_DESCRIPTION("NXP i.MX8MN clock driver" ); |
639 | MODULE_LICENSE("GPL v2" ); |
640 | |