1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright 2018 NXP. |
4 | * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de> |
5 | */ |
6 | |
7 | #include <dt-bindings/clock/imx8mq-clock.h> |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/err.h> |
10 | #include <linux/io.h> |
11 | #include <linux/module.h> |
12 | #include <linux/of_address.h> |
13 | #include <linux/types.h> |
14 | #include <linux/slab.h> |
15 | #include <linux/platform_device.h> |
16 | |
17 | #include "clk.h" |
18 | |
19 | static u32 share_count_sai1; |
20 | static u32 share_count_sai2; |
21 | static u32 share_count_sai3; |
22 | static u32 share_count_sai4; |
23 | static u32 share_count_sai5; |
24 | static u32 share_count_sai6; |
25 | static u32 share_count_dcss; |
26 | static u32 share_count_nand; |
27 | |
28 | static const char * const pll_ref_sels[] = { "osc_25m" , "osc_27m" , "hdmi_phy_27m" , "dummy" , }; |
29 | static const char * const arm_pll_bypass_sels[] = {"arm_pll" , "arm_pll_ref_sel" , }; |
30 | static const char * const gpu_pll_bypass_sels[] = {"gpu_pll" , "gpu_pll_ref_sel" , }; |
31 | static const char * const vpu_pll_bypass_sels[] = {"vpu_pll" , "vpu_pll_ref_sel" , }; |
32 | static const char * const audio_pll1_bypass_sels[] = {"audio_pll1" , "audio_pll1_ref_sel" , }; |
33 | static const char * const audio_pll2_bypass_sels[] = {"audio_pll2" , "audio_pll2_ref_sel" , }; |
34 | static const char * const video_pll1_bypass_sels[] = {"video_pll1" , "video_pll1_ref_sel" , }; |
35 | |
36 | static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel" , }; |
37 | static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel" , }; |
38 | static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel" , }; |
39 | |
40 | /* CCM ROOT */ |
41 | static const char * const imx8mq_a53_sels[] = {"osc_25m" , "arm_pll_out" , "sys2_pll_500m" , "sys2_pll_1000m" , |
42 | "sys1_pll_800m" , "sys1_pll_400m" , "audio_pll1_out" , "sys3_pll_out" , }; |
43 | |
44 | static const char * const imx8mq_a53_core_sels[] = {"arm_a53_div" , "arm_pll_out" , }; |
45 | |
46 | static const char * const imx8mq_arm_m4_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys2_pll_250m" , "sys1_pll_266m" , |
47 | "sys1_pll_800m" , "audio_pll1_out" , "video_pll1_out" , "sys3_pll_out" , }; |
48 | |
49 | static const char * const imx8mq_vpu_sels[] = {"osc_25m" , "arm_pll_out" , "sys2_pll_500m" , "sys2_pll_1000m" , |
50 | "sys1_pll_800m" , "sys1_pll_400m" , "audio_pll1_out" , "vpu_pll_out" , }; |
51 | |
52 | static const char * const imx8mq_gpu_core_sels[] = {"osc_25m" , "gpu_pll_out" , "sys1_pll_800m" , "sys3_pll_out" , |
53 | "sys2_pll_1000m" , "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
54 | |
55 | static const char * const imx8mq_gpu_shader_sels[] = {"osc_25m" , "gpu_pll_out" , "sys1_pll_800m" , "sys3_pll_out" , |
56 | "sys2_pll_1000m" , "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
57 | |
58 | static const char * const imx8mq_main_axi_sels[] = {"osc_25m" , "sys2_pll_333m" , "sys1_pll_800m" , "sys2_pll_250m" , |
59 | "sys2_pll_1000m" , "audio_pll1_out" , "video_pll1_out" , "sys1_pll_100m" ,}; |
60 | |
61 | static const char * const imx8mq_enet_axi_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys1_pll_800m" , "sys2_pll_250m" , |
62 | "sys2_pll_200m" , "audio_pll1_out" , "video_pll1_out" , "sys3_pll_out" , }; |
63 | |
64 | static const char * const imx8mq_nand_usdhc_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys1_pll_800m" , "sys2_pll_200m" , |
65 | "sys1_pll_133m" , "sys3_pll_out" , "sys2_pll_250m" , "audio_pll1_out" , }; |
66 | |
67 | static const char * const imx8mq_vpu_bus_sels[] = {"osc_25m" , "sys1_pll_800m" , "vpu_pll_out" , "audio_pll2_out" , "sys3_pll_out" , "sys2_pll_1000m" , "sys2_pll_200m" , "sys1_pll_100m" , }; |
68 | |
69 | static const char * const imx8mq_disp_axi_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys1_pll_800m" , "sys3_pll_out" , "sys1_pll_400m" , "audio_pll2_out" , "clk_ext1" , "clk_ext4" , }; |
70 | |
71 | static const char * const imx8mq_disp_apb_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys1_pll_800m" , "sys3_pll_out" , |
72 | "sys1_pll_40m" , "audio_pll2_out" , "clk_ext1" , "clk_ext3" , }; |
73 | |
74 | static const char * const imx8mq_disp_rtrm_sels[] = {"osc_25m" , "sys1_pll_800m" , "sys2_pll_200m" , "sys1_pll_400m" , |
75 | "audio_pll1_out" , "video_pll1_out" , "clk_ext2" , "clk_ext3" , }; |
76 | |
77 | static const char * const imx8mq_usb_bus_sels[] = {"osc_25m" , "sys2_pll_500m" , "sys1_pll_800m" , "sys2_pll_100m" , |
78 | "sys2_pll_200m" , "clk_ext2" , "clk_ext4" , "audio_pll2_out" , }; |
79 | |
80 | static const char * const imx8mq_gpu_axi_sels[] = {"osc_25m" , "sys1_pll_800m" , "gpu_pll_out" , "sys3_pll_out" , "sys2_pll_1000m" , |
81 | "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
82 | |
83 | static const char * const imx8mq_gpu_ahb_sels[] = {"osc_25m" , "sys1_pll_800m" , "gpu_pll_out" , "sys3_pll_out" , "sys2_pll_1000m" , |
84 | "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
85 | |
86 | static const char * const imx8mq_noc_sels[] = {"osc_25m" , "sys1_pll_800m" , "sys3_pll_out" , "sys2_pll_1000m" , "sys2_pll_500m" , |
87 | "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
88 | |
89 | static const char * const imx8mq_noc_apb_sels[] = {"osc_25m" , "sys1_pll_400m" , "sys3_pll_out" , "sys2_pll_333m" , "sys2_pll_200m" , |
90 | "sys1_pll_800m" , "audio_pll1_out" , "video_pll1_out" , }; |
91 | |
92 | static const char * const imx8mq_ahb_sels[] = {"osc_25m" , "sys1_pll_133m" , "sys1_pll_800m" , "sys1_pll_400m" , |
93 | "sys2_pll_125m" , "sys3_pll_out" , "audio_pll1_out" , "video_pll1_out" , }; |
94 | |
95 | static const char * const imx8mq_audio_ahb_sels[] = {"osc_25m" , "sys2_pll_500m" , "sys1_pll_800m" , "sys2_pll_1000m" , |
96 | "sys2_pll_166m" , "sys3_pll_out" , "audio_pll1_out" , "video_pll1_out" , }; |
97 | |
98 | static const char * const imx8mq_dsi_ahb_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_800m" , |
99 | "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext3" , "audio_pll2_out" }; |
100 | |
101 | static const char * const imx8mq_dram_alt_sels[] = {"osc_25m" , "sys1_pll_800m" , "sys1_pll_100m" , "sys2_pll_500m" , |
102 | "sys2_pll_250m" , "sys1_pll_400m" , "audio_pll1_out" , "sys1_pll_266m" , }; |
103 | |
104 | static const char * const imx8mq_dram_apb_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_40m" , "sys1_pll_160m" , |
105 | "sys1_pll_800m" , "sys3_pll_out" , "sys2_pll_250m" , "audio_pll2_out" , }; |
106 | |
107 | static const char * const imx8mq_vpu_g1_sels[] = {"osc_25m" , "vpu_pll_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys1_pll_100m" , "sys2_pll_125m" , "sys3_pll_out" , "audio_pll1_out" , }; |
108 | |
109 | static const char * const imx8mq_vpu_g2_sels[] = {"osc_25m" , "vpu_pll_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys1_pll_100m" , "sys2_pll_125m" , "sys3_pll_out" , "audio_pll1_out" , }; |
110 | |
111 | static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m" , "vpu_pll_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys1_pll_160m" , "sys2_pll_100m" , "sys3_pll_out" , "audio_pll2_out" , }; |
112 | |
113 | static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m" , "vpu_pll_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys1_pll_160m" , "sys2_pll_100m" , "sys3_pll_out" , "audio_pll2_out" , }; |
114 | |
115 | static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m" , "sys2_pll_250m" , "sys2_pll_200m" , "sys1_pll_266m" , |
116 | "sys1_pll_800m" , "sys2_pll_500m" , "sys2_pll_333m" , "sys3_pll_out" , }; |
117 | |
118 | static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys2_pll_500m" , "clk_ext1" , "clk_ext2" , |
119 | "clk_ext3" , "clk_ext4" , }; |
120 | |
121 | static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys2_pll_50m" , "sys3_pll_out" , |
122 | "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_160m" , "sys1_pll_200m" , }; |
123 | |
124 | static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m" , "video_pll1_out" , "audio_pll2_out" , "audio_pll1_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext4" , }; |
125 | |
126 | static const char * const imx8mq_lcdif_pixel_sels[] = {"osc_25m" , "video_pll1_out" , "audio_pll2_out" , "audio_pll1_out" , "sys1_pll_800m" , "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext4" , }; |
127 | |
128 | static const char * const imx8mq_sai1_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext1" , "clk_ext2" , }; |
129 | |
130 | static const char * const imx8mq_sai2_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext2" , "clk_ext3" , }; |
131 | |
132 | static const char * const imx8mq_sai3_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext3" , "clk_ext4" , }; |
133 | |
134 | static const char * const imx8mq_sai4_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext1" , "clk_ext2" , }; |
135 | |
136 | static const char * const imx8mq_sai5_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext2" , "clk_ext3" , }; |
137 | |
138 | static const char * const imx8mq_sai6_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext3" , "clk_ext4" , }; |
139 | |
140 | static const char * const imx8mq_spdif1_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext2" , "clk_ext3" , }; |
141 | |
142 | static const char * const imx8mq_spdif2_sels[] = {"osc_25m" , "audio_pll1_out" , "audio_pll2_out" , "video_pll1_out" , "sys1_pll_133m" , "osc_27m" , "clk_ext3" , "clk_ext4" , }; |
143 | |
144 | static const char * const imx8mq_enet_ref_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys2_pll_500m" , "sys2_pll_100m" , |
145 | "sys1_pll_160m" , "audio_pll1_out" , "video_pll1_out" , "clk_ext4" , }; |
146 | |
147 | static const char * const imx8mq_enet_timer_sels[] = {"osc_25m" , "sys2_pll_100m" , "audio_pll1_out" , "clk_ext1" , "clk_ext2" , |
148 | "clk_ext3" , "clk_ext4" , "video_pll1_out" , }; |
149 | |
150 | static const char * const imx8mq_enet_phy_sels[] = {"osc_25m" , "sys2_pll_50m" , "sys2_pll_125m" , "sys2_pll_500m" , |
151 | "audio_pll1_out" , "video_pll1_out" , "audio_pll2_out" , }; |
152 | |
153 | static const char * const imx8mq_nand_sels[] = {"osc_25m" , "sys2_pll_500m" , "audio_pll1_out" , "sys1_pll_400m" , |
154 | "audio_pll2_out" , "sys3_pll_out" , "sys2_pll_250m" , "video_pll1_out" , }; |
155 | |
156 | static const char * const imx8mq_qspi_sels[] = {"osc_25m" , "sys1_pll_400m" , "sys1_pll_800m" , "sys2_pll_500m" , |
157 | "audio_pll2_out" , "sys1_pll_266m" , "sys3_pll_out" , "sys1_pll_100m" , }; |
158 | |
159 | static const char * const imx8mq_usdhc1_sels[] = {"osc_25m" , "sys1_pll_400m" , "sys1_pll_800m" , "sys2_pll_500m" , |
160 | "sys3_pll_out" , "sys1_pll_266m" , "audio_pll2_out" , "sys1_pll_100m" , }; |
161 | |
162 | static const char * const imx8mq_usdhc2_sels[] = {"osc_25m" , "sys1_pll_400m" , "sys1_pll_800m" , "sys2_pll_500m" , |
163 | "sys3_pll_out" , "sys1_pll_266m" , "audio_pll2_out" , "sys1_pll_100m" , }; |
164 | |
165 | static const char * const imx8mq_i2c1_sels[] = {"osc_25m" , "sys1_pll_160m" , "sys2_pll_50m" , "sys3_pll_out" , "audio_pll1_out" , |
166 | "video_pll1_out" , "audio_pll2_out" , "sys1_pll_133m" , }; |
167 | |
168 | static const char * const imx8mq_i2c2_sels[] = {"osc_25m" , "sys1_pll_160m" , "sys2_pll_50m" , "sys3_pll_out" , "audio_pll1_out" , |
169 | "video_pll1_out" , "audio_pll2_out" , "sys1_pll_133m" , }; |
170 | |
171 | static const char * const imx8mq_i2c3_sels[] = {"osc_25m" , "sys1_pll_160m" , "sys2_pll_50m" , "sys3_pll_out" , "audio_pll1_out" , |
172 | "video_pll1_out" , "audio_pll2_out" , "sys1_pll_133m" , }; |
173 | |
174 | static const char * const imx8mq_i2c4_sels[] = {"osc_25m" , "sys1_pll_160m" , "sys2_pll_50m" , "sys3_pll_out" , "audio_pll1_out" , |
175 | "video_pll1_out" , "audio_pll2_out" , "sys1_pll_133m" , }; |
176 | |
177 | static const char * const imx8mq_uart1_sels[] = {"osc_25m" , "sys1_pll_80m" , "sys2_pll_200m" , "sys2_pll_100m" , |
178 | "sys3_pll_out" , "clk_ext2" , "clk_ext4" , "audio_pll2_out" , }; |
179 | |
180 | static const char * const imx8mq_uart2_sels[] = {"osc_25m" , "sys1_pll_80m" , "sys2_pll_200m" , "sys2_pll_100m" , |
181 | "sys3_pll_out" , "clk_ext2" , "clk_ext3" , "audio_pll2_out" , }; |
182 | |
183 | static const char * const imx8mq_uart3_sels[] = {"osc_25m" , "sys1_pll_80m" , "sys2_pll_200m" , "sys2_pll_100m" , |
184 | "sys3_pll_out" , "clk_ext2" , "clk_ext4" , "audio_pll2_out" , }; |
185 | |
186 | static const char * const imx8mq_uart4_sels[] = {"osc_25m" , "sys1_pll_80m" , "sys2_pll_200m" , "sys2_pll_100m" , |
187 | "sys3_pll_out" , "clk_ext2" , "clk_ext3" , "audio_pll2_out" , }; |
188 | |
189 | static const char * const imx8mq_usb_core_sels[] = {"osc_25m" , "sys1_pll_100m" , "sys1_pll_40m" , "sys2_pll_100m" , |
190 | "sys2_pll_200m" , "clk_ext2" , "clk_ext3" , "audio_pll2_out" , }; |
191 | |
192 | static const char * const imx8mq_usb_phy_sels[] = {"osc_25m" , "sys1_pll_100m" , "sys1_pll_40m" , "sys2_pll_100m" , |
193 | "sys2_pll_200m" , "clk_ext2" , "clk_ext3" , "audio_pll2_out" , }; |
194 | |
195 | static const char * const imx8mq_gic_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_40m" , "sys2_pll_100m" , |
196 | "sys2_pll_200m" , "clk_ext2" , "clk_ext3" , "audio_pll2_out" }; |
197 | |
198 | static const char * const imx8mq_ecspi1_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_40m" , "sys1_pll_160m" , |
199 | "sys1_pll_800m" , "sys3_pll_out" , "sys2_pll_250m" , "audio_pll2_out" , }; |
200 | |
201 | static const char * const imx8mq_ecspi2_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_40m" , "sys1_pll_160m" , |
202 | "sys1_pll_800m" , "sys3_pll_out" , "sys2_pll_250m" , "audio_pll2_out" , }; |
203 | |
204 | static const char * const imx8mq_pwm1_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_160m" , "sys1_pll_40m" , |
205 | "sys3_pll_out" , "clk_ext1" , "sys1_pll_80m" , "video_pll1_out" , }; |
206 | |
207 | static const char * const imx8mq_pwm2_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_160m" , "sys1_pll_40m" , |
208 | "sys3_pll_out" , "clk_ext1" , "sys1_pll_80m" , "video_pll1_out" , }; |
209 | |
210 | static const char * const imx8mq_pwm3_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_160m" , "sys1_pll_40m" , |
211 | "sys3_pll_out" , "clk_ext2" , "sys1_pll_80m" , "video_pll1_out" , }; |
212 | |
213 | static const char * const imx8mq_pwm4_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_160m" , "sys1_pll_40m" , |
214 | "sys3_pll_out" , "clk_ext2" , "sys1_pll_80m" , "video_pll1_out" , }; |
215 | |
216 | static const char * const imx8mq_gpt1_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_400m" , "sys1_pll_40m" , |
217 | "sys1_pll_80m" , "audio_pll1_out" , "clk_ext1" , }; |
218 | |
219 | static const char * const imx8mq_wdog_sels[] = {"osc_25m" , "sys1_pll_133m" , "sys1_pll_160m" , "vpu_pll_out" , |
220 | "sys2_pll_125m" , "sys3_pll_out" , "sys1_pll_80m" , "sys2_pll_166m" , }; |
221 | |
222 | static const char * const imx8mq_wrclk_sels[] = {"osc_25m" , "sys1_pll_40m" , "vpu_pll_out" , "sys3_pll_out" , "sys2_pll_200m" , |
223 | "sys1_pll_266m" , "sys2_pll_500m" , "sys1_pll_100m" , }; |
224 | |
225 | static const char * const imx8mq_dsi_core_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys2_pll_250m" , "sys1_pll_800m" , |
226 | "sys2_pll_1000m" , "sys3_pll_out" , "audio_pll2_out" , "video_pll1_out" , }; |
227 | |
228 | static const char * const imx8mq_dsi_phy_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys2_pll_100m" , "sys1_pll_800m" , |
229 | "sys2_pll_1000m" , "clk_ext2" , "audio_pll2_out" , "video_pll1_out" , }; |
230 | |
231 | static const char * const imx8mq_dsi_dbi_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys2_pll_100m" , "sys1_pll_800m" , |
232 | "sys2_pll_1000m" , "sys3_pll_out" , "audio_pll2_out" , "video_pll1_out" , }; |
233 | |
234 | static const char * const imx8mq_dsi_esc_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_800m" , |
235 | "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext3" , "audio_pll2_out" , }; |
236 | |
237 | static const char * const imx8mq_csi1_core_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys2_pll_250m" , "sys1_pll_800m" , |
238 | "sys2_pll_1000m" , "sys3_pll_out" , "audio_pll2_out" , "video_pll1_out" , }; |
239 | |
240 | static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys2_pll_100m" , "sys1_pll_800m" , |
241 | "sys2_pll_1000m" , "clk_ext2" , "audio_pll2_out" , "video_pll1_out" , }; |
242 | |
243 | static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_800m" , |
244 | "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext3" , "audio_pll2_out" , }; |
245 | |
246 | static const char * const imx8mq_csi2_core_sels[] = {"osc_25m" , "sys1_pll_266m" , "sys2_pll_250m" , "sys1_pll_800m" , |
247 | "sys2_pll_1000m" , "sys3_pll_out" , "audio_pll2_out" , "video_pll1_out" , }; |
248 | |
249 | static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m" , "sys2_pll_125m" , "sys2_pll_100m" , "sys1_pll_800m" , |
250 | "sys2_pll_1000m" , "clk_ext2" , "audio_pll2_out" , "video_pll1_out" , }; |
251 | |
252 | static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_800m" , |
253 | "sys2_pll_1000m" , "sys3_pll_out" , "clk_ext3" , "audio_pll2_out" , }; |
254 | |
255 | static const char * const imx8mq_pcie2_ctrl_sels[] = {"osc_25m" , "sys2_pll_250m" , "sys2_pll_200m" , "sys1_pll_266m" , |
256 | "sys1_pll_800m" , "sys2_pll_500m" , "sys2_pll_333m" , "sys3_pll_out" , }; |
257 | |
258 | static const char * const imx8mq_pcie2_phy_sels[] = {"osc_25m" , "sys2_pll_100m" , "sys2_pll_500m" , "clk_ext1" , |
259 | "clk_ext2" , "clk_ext3" , "clk_ext4" , "sys1_pll_400m" , }; |
260 | |
261 | static const char * const imx8mq_pcie2_aux_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys2_pll_50m" , "sys3_pll_out" , |
262 | "sys2_pll_100m" , "sys1_pll_80m" , "sys1_pll_160m" , "sys1_pll_200m" , }; |
263 | |
264 | static const char * const imx8mq_ecspi3_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_40m" , "sys1_pll_160m" , |
265 | "sys1_pll_800m" , "sys3_pll_out" , "sys2_pll_250m" , "audio_pll2_out" , }; |
266 | static const char * const imx8mq_dram_core_sels[] = {"dram_pll_out" , "dram_alt_root" , }; |
267 | |
268 | static const char * const imx8mq_clko1_sels[] = {"osc_25m" , "sys1_pll_800m" , "osc_27m" , "sys1_pll_200m" , |
269 | "audio_pll2_out" , "sys2_pll_500m" , "vpu_pll_out" , "sys1_pll_80m" , }; |
270 | static const char * const imx8mq_clko2_sels[] = {"osc_25m" , "sys2_pll_200m" , "sys1_pll_400m" , "sys2_pll_166m" , |
271 | "sys3_pll_out" , "audio_pll1_out" , "video_pll1_out" , "ckil" , }; |
272 | |
273 | static const char * const pllout_monitor_sels[] = {"osc_25m" , "osc_27m" , "dummy" , "dummy" , "ckil" , |
274 | "audio_pll1_out_monitor" , "audio_pll2_out_monitor" , |
275 | "video_pll1_out_monitor" , "gpu_pll_out_monitor" , |
276 | "vpu_pll_out_monitor" , "arm_pll_out_monitor" , |
277 | "sys_pll1_out_monitor" , "sys_pll2_out_monitor" , |
278 | "sys_pll3_out_monitor" , "dram_pll_out_monitor" , |
279 | "video_pll2_out_monitor" , }; |
280 | |
281 | static struct clk_hw_onecell_data *clk_hw_data; |
282 | static struct clk_hw **hws; |
283 | |
284 | static int imx8mq_clocks_probe(struct platform_device *pdev) |
285 | { |
286 | struct device *dev = &pdev->dev; |
287 | struct device_node *np = dev->of_node; |
288 | void __iomem *base; |
289 | int err; |
290 | |
291 | clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL); |
292 | if (WARN_ON(!clk_hw_data)) |
293 | return -ENOMEM; |
294 | |
295 | clk_hw_data->num = IMX8MQ_CLK_END; |
296 | hws = clk_hw_data->hws; |
297 | |
298 | hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy" , rate: 0); |
299 | hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, name: "ckil" ); |
300 | hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, name: "osc_25m" ); |
301 | hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, name: "osc_27m" ); |
302 | hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, name: "clk_ext1" ); |
303 | hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, name: "clk_ext2" ); |
304 | hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, name: "clk_ext3" ); |
305 | hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, name: "clk_ext4" ); |
306 | |
307 | np = of_find_compatible_node(NULL, NULL, compat: "fsl,imx8mq-anatop" ); |
308 | base = devm_of_iomap(dev, node: np, index: 0, NULL); |
309 | of_node_put(node: np); |
310 | if (WARN_ON(IS_ERR(base))) { |
311 | err = PTR_ERR(ptr: base); |
312 | goto unregister_hws; |
313 | } |
314 | |
315 | hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel" , base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
316 | hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel" , base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
317 | hws[IMX8MQ_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel" , base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
318 | hws[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel" , base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
319 | hws[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel" , base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
320 | hws[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel" , base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
321 | hws[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_hw_mux("sys3_pll1_ref_sel" , base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
322 | hws[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_hw_mux("dram_pll1_ref_sel" , base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
323 | hws[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_hw_mux("video2_pll1_ref_sel" , base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
324 | |
325 | hws[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_hw_divider("arm_pll_ref_div" , "arm_pll_ref_sel" , base + 0x28, 5, 6); |
326 | hws[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_hw_divider("gpu_pll_ref_div" , "gpu_pll_ref_sel" , base + 0x18, 5, 6); |
327 | hws[IMX8MQ_VPU_PLL_REF_DIV] = imx_clk_hw_divider("vpu_pll_ref_div" , "vpu_pll_ref_sel" , base + 0x20, 5, 6); |
328 | hws[IMX8MQ_AUDIO_PLL1_REF_DIV] = imx_clk_hw_divider("audio_pll1_ref_div" , "audio_pll1_ref_sel" , base + 0x0, 5, 6); |
329 | hws[IMX8MQ_AUDIO_PLL2_REF_DIV] = imx_clk_hw_divider("audio_pll2_ref_div" , "audio_pll2_ref_sel" , base + 0x8, 5, 6); |
330 | hws[IMX8MQ_VIDEO_PLL1_REF_DIV] = imx_clk_hw_divider("video_pll1_ref_div" , "video_pll1_ref_sel" , base + 0x10, 5, 6); |
331 | |
332 | hws[IMX8MQ_ARM_PLL] = imx_clk_hw_frac_pll(name: "arm_pll" , parent_name: "arm_pll_ref_div" , base: base + 0x28); |
333 | hws[IMX8MQ_GPU_PLL] = imx_clk_hw_frac_pll(name: "gpu_pll" , parent_name: "gpu_pll_ref_div" , base: base + 0x18); |
334 | hws[IMX8MQ_VPU_PLL] = imx_clk_hw_frac_pll(name: "vpu_pll" , parent_name: "vpu_pll_ref_div" , base: base + 0x20); |
335 | hws[IMX8MQ_AUDIO_PLL1] = imx_clk_hw_frac_pll(name: "audio_pll1" , parent_name: "audio_pll1_ref_div" , base: base + 0x0); |
336 | hws[IMX8MQ_AUDIO_PLL2] = imx_clk_hw_frac_pll(name: "audio_pll2" , parent_name: "audio_pll2_ref_div" , base: base + 0x8); |
337 | hws[IMX8MQ_VIDEO_PLL1] = imx_clk_hw_frac_pll(name: "video_pll1" , parent_name: "video_pll1_ref_div" , base: base + 0x10); |
338 | |
339 | /* PLL bypass out */ |
340 | hws[IMX8MQ_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass" , base + 0x28, 14, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT); |
341 | hws[IMX8MQ_GPU_PLL_BYPASS] = imx_clk_hw_mux("gpu_pll_bypass" , base + 0x18, 14, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels)); |
342 | hws[IMX8MQ_VPU_PLL_BYPASS] = imx_clk_hw_mux("vpu_pll_bypass" , base + 0x20, 14, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels)); |
343 | hws[IMX8MQ_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux("audio_pll1_bypass" , base + 0x0, 14, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels)); |
344 | hws[IMX8MQ_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux("audio_pll2_bypass" , base + 0x8, 14, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels)); |
345 | hws[IMX8MQ_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux("video_pll1_bypass" , base + 0x10, 14, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels)); |
346 | |
347 | /* PLL OUT GATE */ |
348 | hws[IMX8MQ_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out" , "arm_pll_bypass" , base + 0x28, 21); |
349 | hws[IMX8MQ_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out" , "gpu_pll_bypass" , base + 0x18, 21); |
350 | hws[IMX8MQ_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out" , "vpu_pll_bypass" , base + 0x20, 21); |
351 | hws[IMX8MQ_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out" , "audio_pll1_bypass" , base + 0x0, 21); |
352 | hws[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out" , "audio_pll2_bypass" , base + 0x8, 21); |
353 | hws[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out" , "video_pll1_bypass" , base + 0x10, 21); |
354 | |
355 | hws[IMX8MQ_SYS1_PLL_OUT] = imx_clk_hw_fixed(name: "sys1_pll_out" , rate: 800000000); |
356 | hws[IMX8MQ_SYS2_PLL_OUT] = imx_clk_hw_fixed(name: "sys2_pll_out" , rate: 1000000000); |
357 | hws[IMX8MQ_SYS3_PLL_OUT] = imx_clk_hw_sscg_pll(name: "sys3_pll_out" , parent_names: sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), parent: 0, bypass1: 0, bypass2: 0, base: base + 0x48, CLK_IS_CRITICAL); |
358 | hws[IMX8MQ_DRAM_PLL_OUT] = imx_clk_hw_sscg_pll(name: "dram_pll_out" , parent_names: dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), parent: 0, bypass1: 0, bypass2: 0, base: base + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE); |
359 | hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll(name: "video2_pll_out" , parent_names: video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), parent: 0, bypass1: 0, bypass2: 0, base: base + 0x54, flags: 0); |
360 | |
361 | /* SYS PLL1 fixed output */ |
362 | hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor(name: "sys1_pll_40m" , parent: "sys1_pll_out" , mult: 1, div: 20); |
363 | hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor(name: "sys1_pll_80m" , parent: "sys1_pll_out" , mult: 1, div: 10); |
364 | hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor(name: "sys1_pll_100m" , parent: "sys1_pll_out" , mult: 1, div: 8); |
365 | hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor(name: "sys1_pll_133m" , parent: "sys1_pll_out" , mult: 1, div: 6); |
366 | hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor(name: "sys1_pll_160m" , parent: "sys1_pll_out" , mult: 1, div: 5); |
367 | hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor(name: "sys1_pll_200m" , parent: "sys1_pll_out" , mult: 1, div: 4); |
368 | hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor(name: "sys1_pll_266m" , parent: "sys1_pll_out" , mult: 1, div: 3); |
369 | hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor(name: "sys1_pll_400m" , parent: "sys1_pll_out" , mult: 1, div: 2); |
370 | hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor(name: "sys1_pll_800m" , parent: "sys1_pll_out" , mult: 1, div: 1); |
371 | |
372 | /* SYS PLL2 fixed output */ |
373 | hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor(name: "sys2_pll_50m" , parent: "sys2_pll_out" , mult: 1, div: 20); |
374 | hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor(name: "sys2_pll_100m" , parent: "sys2_pll_out" , mult: 1, div: 10); |
375 | hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor(name: "sys2_pll_125m" , parent: "sys2_pll_out" , mult: 1, div: 8); |
376 | hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor(name: "sys2_pll_166m" , parent: "sys2_pll_out" , mult: 1, div: 6); |
377 | hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor(name: "sys2_pll_200m" , parent: "sys2_pll_out" , mult: 1, div: 5); |
378 | hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor(name: "sys2_pll_250m" , parent: "sys2_pll_out" , mult: 1, div: 4); |
379 | hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor(name: "sys2_pll_333m" , parent: "sys2_pll_out" , mult: 1, div: 3); |
380 | hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor(name: "sys2_pll_500m" , parent: "sys2_pll_out" , mult: 1, div: 2); |
381 | hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor(name: "sys2_pll_1000m" , parent: "sys2_pll_out" , mult: 1, div: 1); |
382 | |
383 | hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor" , "audio_pll1_bypass" , base + 0x78, 0, 3); |
384 | hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor" , "audio_pll2_bypass" , base + 0x78, 4, 3); |
385 | hws[IMX8MQ_CLK_MON_VIDEO_PLL1_DIV] = imx_clk_hw_divider("video_pll1_out_monitor" , "video_pll1_bypass" , base + 0x78, 8, 3); |
386 | hws[IMX8MQ_CLK_MON_GPU_PLL_DIV] = imx_clk_hw_divider("gpu_pll_out_monitor" , "gpu_pll_bypass" , base + 0x78, 12, 3); |
387 | hws[IMX8MQ_CLK_MON_VPU_PLL_DIV] = imx_clk_hw_divider("vpu_pll_out_monitor" , "vpu_pll_bypass" , base + 0x78, 16, 3); |
388 | hws[IMX8MQ_CLK_MON_ARM_PLL_DIV] = imx_clk_hw_divider("arm_pll_out_monitor" , "arm_pll_bypass" , base + 0x78, 20, 3); |
389 | hws[IMX8MQ_CLK_MON_SYS_PLL1_DIV] = imx_clk_hw_divider("sys_pll1_out_monitor" , "sys1_pll_out" , base + 0x7c, 0, 3); |
390 | hws[IMX8MQ_CLK_MON_SYS_PLL2_DIV] = imx_clk_hw_divider("sys_pll2_out_monitor" , "sys2_pll_out" , base + 0x7c, 4, 3); |
391 | hws[IMX8MQ_CLK_MON_SYS_PLL3_DIV] = imx_clk_hw_divider("sys_pll3_out_monitor" , "sys3_pll_out" , base + 0x7c, 8, 3); |
392 | hws[IMX8MQ_CLK_MON_DRAM_PLL_DIV] = imx_clk_hw_divider("dram_pll_out_monitor" , "dram_pll_out" , base + 0x7c, 12, 3); |
393 | hws[IMX8MQ_CLK_MON_VIDEO_PLL2_DIV] = imx_clk_hw_divider("video_pll2_out_monitor" , "video2_pll_out" , base + 0x7c, 16, 3); |
394 | hws[IMX8MQ_CLK_MON_SEL] = imx_clk_hw_mux("pllout_monitor_sel" , base + 0x74, 0, 4, pllout_monitor_sels, ARRAY_SIZE(pllout_monitor_sels)); |
395 | hws[IMX8MQ_CLK_MON_CLK2_OUT] = imx_clk_hw_gate("pllout_monitor_clk2" , "pllout_monitor_sel" , base + 0x74, 4); |
396 | |
397 | np = dev->of_node; |
398 | base = devm_platform_ioremap_resource(pdev, index: 0); |
399 | if (WARN_ON(IS_ERR(base))) { |
400 | err = PTR_ERR(ptr: base); |
401 | goto unregister_hws; |
402 | } |
403 | |
404 | /* CORE */ |
405 | hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div" , imx8mq_a53_sels, base + 0x8000); |
406 | hws[IMX8MQ_CLK_A53_CG] = hws[IMX8MQ_CLK_A53_DIV]; |
407 | hws[IMX8MQ_CLK_A53_SRC] = hws[IMX8MQ_CLK_A53_DIV]; |
408 | |
409 | hws[IMX8MQ_CLK_M4_CORE] = imx8m_clk_hw_composite_core("arm_m4_core" , imx8mq_arm_m4_sels, base + 0x8080); |
410 | hws[IMX8MQ_CLK_VPU_CORE] = imx8m_clk_hw_composite_core("vpu_core" , imx8mq_vpu_sels, base + 0x8100); |
411 | hws[IMX8MQ_CLK_GPU_CORE] = imx8m_clk_hw_composite_core("gpu_core" , imx8mq_gpu_core_sels, base + 0x8180); |
412 | hws[IMX8MQ_CLK_GPU_SHADER] = imx8m_clk_hw_composite("gpu_shader" , imx8mq_gpu_shader_sels, base + 0x8200); |
413 | /* For backwards compatibility */ |
414 | hws[IMX8MQ_CLK_M4_SRC] = hws[IMX8MQ_CLK_M4_CORE]; |
415 | hws[IMX8MQ_CLK_M4_CG] = hws[IMX8MQ_CLK_M4_CORE]; |
416 | hws[IMX8MQ_CLK_M4_DIV] = hws[IMX8MQ_CLK_M4_CORE]; |
417 | hws[IMX8MQ_CLK_VPU_SRC] = hws[IMX8MQ_CLK_VPU_CORE]; |
418 | hws[IMX8MQ_CLK_VPU_CG] = hws[IMX8MQ_CLK_VPU_CORE]; |
419 | hws[IMX8MQ_CLK_VPU_DIV] = hws[IMX8MQ_CLK_VPU_CORE]; |
420 | hws[IMX8MQ_CLK_GPU_CORE_SRC] = hws[IMX8MQ_CLK_GPU_CORE]; |
421 | hws[IMX8MQ_CLK_GPU_CORE_CG] = hws[IMX8MQ_CLK_GPU_CORE]; |
422 | hws[IMX8MQ_CLK_GPU_CORE_DIV] = hws[IMX8MQ_CLK_GPU_CORE]; |
423 | hws[IMX8MQ_CLK_GPU_SHADER_SRC] = hws[IMX8MQ_CLK_GPU_SHADER]; |
424 | hws[IMX8MQ_CLK_GPU_SHADER_CG] = hws[IMX8MQ_CLK_GPU_SHADER]; |
425 | hws[IMX8MQ_CLK_GPU_SHADER_DIV] = hws[IMX8MQ_CLK_GPU_SHADER]; |
426 | |
427 | /* CORE SEL */ |
428 | hws[IMX8MQ_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core" , base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels)); |
429 | |
430 | /* BUS */ |
431 | hws[IMX8MQ_CLK_MAIN_AXI] = imx8m_clk_hw_composite_bus_critical("main_axi" , imx8mq_main_axi_sels, base + 0x8800); |
432 | hws[IMX8MQ_CLK_ENET_AXI] = imx8m_clk_hw_composite_bus("enet_axi" , imx8mq_enet_axi_sels, base + 0x8880); |
433 | hws[IMX8MQ_CLK_NAND_USDHC_BUS] = imx8m_clk_hw_composite_bus("nand_usdhc_bus" , imx8mq_nand_usdhc_sels, base + 0x8900); |
434 | hws[IMX8MQ_CLK_VPU_BUS] = imx8m_clk_hw_composite_bus("vpu_bus" , imx8mq_vpu_bus_sels, base + 0x8980); |
435 | hws[IMX8MQ_CLK_DISP_AXI] = imx8m_clk_hw_composite_bus("disp_axi" , imx8mq_disp_axi_sels, base + 0x8a00); |
436 | hws[IMX8MQ_CLK_DISP_APB] = imx8m_clk_hw_composite_bus("disp_apb" , imx8mq_disp_apb_sels, base + 0x8a80); |
437 | hws[IMX8MQ_CLK_DISP_RTRM] = imx8m_clk_hw_composite_bus("disp_rtrm" , imx8mq_disp_rtrm_sels, base + 0x8b00); |
438 | hws[IMX8MQ_CLK_USB_BUS] = imx8m_clk_hw_composite_bus("usb_bus" , imx8mq_usb_bus_sels, base + 0x8b80); |
439 | hws[IMX8MQ_CLK_GPU_AXI] = imx8m_clk_hw_composite_bus("gpu_axi" , imx8mq_gpu_axi_sels, base + 0x8c00); |
440 | hws[IMX8MQ_CLK_GPU_AHB] = imx8m_clk_hw_composite_bus("gpu_ahb" , imx8mq_gpu_ahb_sels, base + 0x8c80); |
441 | hws[IMX8MQ_CLK_NOC] = imx8m_clk_hw_composite_bus_critical("noc" , imx8mq_noc_sels, base + 0x8d00); |
442 | hws[IMX8MQ_CLK_NOC_APB] = imx8m_clk_hw_composite_bus_critical("noc_apb" , imx8mq_noc_apb_sels, base + 0x8d80); |
443 | |
444 | /* AHB */ |
445 | /* AHB clock is used by the AHB bus therefore marked as critical */ |
446 | hws[IMX8MQ_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb" , imx8mq_ahb_sels, base + 0x9000); |
447 | hws[IMX8MQ_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb" , imx8mq_audio_ahb_sels, base + 0x9100); |
448 | |
449 | /* IPG */ |
450 | hws[IMX8MQ_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root" , "ahb" , base + 0x9080, 0, 1); |
451 | hws[IMX8MQ_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root" , "audio_ahb" , base + 0x9180, 0, 1); |
452 | |
453 | /* |
454 | * DRAM clocks are manipulated from TF-A outside clock framework. |
455 | * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE |
456 | * as div value should always be read from hardware |
457 | */ |
458 | hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk" , base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL); |
459 | hws[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt" , imx8mq_dram_alt_sels, base + 0xa000); |
460 | hws[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb" , imx8mq_dram_apb_sels, base + 0xa080); |
461 | |
462 | /* IP */ |
463 | hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1" , imx8mq_vpu_g1_sels, base + 0xa100); |
464 | hws[IMX8MQ_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2" , imx8mq_vpu_g2_sels, base + 0xa180); |
465 | hws[IMX8MQ_CLK_DISP_DTRC] = imx8m_clk_hw_composite("disp_dtrc" , imx8mq_disp_dtrc_sels, base + 0xa200); |
466 | hws[IMX8MQ_CLK_DISP_DC8000] = imx8m_clk_hw_composite("disp_dc8000" , imx8mq_disp_dc8000_sels, base + 0xa280); |
467 | hws[IMX8MQ_CLK_PCIE1_CTRL] = imx8m_clk_hw_composite("pcie1_ctrl" , imx8mq_pcie1_ctrl_sels, base + 0xa300); |
468 | hws[IMX8MQ_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy" , imx8mq_pcie1_phy_sels, base + 0xa380); |
469 | hws[IMX8MQ_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux" , imx8mq_pcie1_aux_sels, base + 0xa400); |
470 | hws[IMX8MQ_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel" , imx8mq_dc_pixel_sels, base + 0xa480); |
471 | hws[IMX8MQ_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel" , imx8mq_lcdif_pixel_sels, base + 0xa500); |
472 | hws[IMX8MQ_CLK_SAI1] = imx8m_clk_hw_composite("sai1" , imx8mq_sai1_sels, base + 0xa580); |
473 | hws[IMX8MQ_CLK_SAI2] = imx8m_clk_hw_composite("sai2" , imx8mq_sai2_sels, base + 0xa600); |
474 | hws[IMX8MQ_CLK_SAI3] = imx8m_clk_hw_composite("sai3" , imx8mq_sai3_sels, base + 0xa680); |
475 | hws[IMX8MQ_CLK_SAI4] = imx8m_clk_hw_composite("sai4" , imx8mq_sai4_sels, base + 0xa700); |
476 | hws[IMX8MQ_CLK_SAI5] = imx8m_clk_hw_composite("sai5" , imx8mq_sai5_sels, base + 0xa780); |
477 | hws[IMX8MQ_CLK_SAI6] = imx8m_clk_hw_composite("sai6" , imx8mq_sai6_sels, base + 0xa800); |
478 | hws[IMX8MQ_CLK_SPDIF1] = imx8m_clk_hw_composite("spdif1" , imx8mq_spdif1_sels, base + 0xa880); |
479 | hws[IMX8MQ_CLK_SPDIF2] = imx8m_clk_hw_composite("spdif2" , imx8mq_spdif2_sels, base + 0xa900); |
480 | hws[IMX8MQ_CLK_ENET_REF] = imx8m_clk_hw_composite("enet_ref" , imx8mq_enet_ref_sels, base + 0xa980); |
481 | hws[IMX8MQ_CLK_ENET_TIMER] = imx8m_clk_hw_composite("enet_timer" , imx8mq_enet_timer_sels, base + 0xaa00); |
482 | hws[IMX8MQ_CLK_ENET_PHY_REF] = imx8m_clk_hw_composite("enet_phy" , imx8mq_enet_phy_sels, base + 0xaa80); |
483 | hws[IMX8MQ_CLK_NAND] = imx8m_clk_hw_composite("nand" , imx8mq_nand_sels, base + 0xab00); |
484 | hws[IMX8MQ_CLK_QSPI] = imx8m_clk_hw_composite("qspi" , imx8mq_qspi_sels, base + 0xab80); |
485 | hws[IMX8MQ_CLK_USDHC1] = imx8m_clk_hw_composite("usdhc1" , imx8mq_usdhc1_sels, base + 0xac00); |
486 | hws[IMX8MQ_CLK_USDHC2] = imx8m_clk_hw_composite("usdhc2" , imx8mq_usdhc2_sels, base + 0xac80); |
487 | hws[IMX8MQ_CLK_I2C1] = imx8m_clk_hw_composite("i2c1" , imx8mq_i2c1_sels, base + 0xad00); |
488 | hws[IMX8MQ_CLK_I2C2] = imx8m_clk_hw_composite("i2c2" , imx8mq_i2c2_sels, base + 0xad80); |
489 | hws[IMX8MQ_CLK_I2C3] = imx8m_clk_hw_composite("i2c3" , imx8mq_i2c3_sels, base + 0xae00); |
490 | hws[IMX8MQ_CLK_I2C4] = imx8m_clk_hw_composite("i2c4" , imx8mq_i2c4_sels, base + 0xae80); |
491 | hws[IMX8MQ_CLK_UART1] = imx8m_clk_hw_composite("uart1" , imx8mq_uart1_sels, base + 0xaf00); |
492 | hws[IMX8MQ_CLK_UART2] = imx8m_clk_hw_composite("uart2" , imx8mq_uart2_sels, base + 0xaf80); |
493 | hws[IMX8MQ_CLK_UART3] = imx8m_clk_hw_composite("uart3" , imx8mq_uart3_sels, base + 0xb000); |
494 | hws[IMX8MQ_CLK_UART4] = imx8m_clk_hw_composite("uart4" , imx8mq_uart4_sels, base + 0xb080); |
495 | hws[IMX8MQ_CLK_USB_CORE_REF] = imx8m_clk_hw_composite("usb_core_ref" , imx8mq_usb_core_sels, base + 0xb100); |
496 | hws[IMX8MQ_CLK_USB_PHY_REF] = imx8m_clk_hw_composite("usb_phy_ref" , imx8mq_usb_phy_sels, base + 0xb180); |
497 | hws[IMX8MQ_CLK_GIC] = imx8m_clk_hw_composite_critical("gic" , imx8mq_gic_sels, base + 0xb200); |
498 | hws[IMX8MQ_CLK_ECSPI1] = imx8m_clk_hw_composite("ecspi1" , imx8mq_ecspi1_sels, base + 0xb280); |
499 | hws[IMX8MQ_CLK_ECSPI2] = imx8m_clk_hw_composite("ecspi2" , imx8mq_ecspi2_sels, base + 0xb300); |
500 | hws[IMX8MQ_CLK_PWM1] = imx8m_clk_hw_composite("pwm1" , imx8mq_pwm1_sels, base + 0xb380); |
501 | hws[IMX8MQ_CLK_PWM2] = imx8m_clk_hw_composite("pwm2" , imx8mq_pwm2_sels, base + 0xb400); |
502 | hws[IMX8MQ_CLK_PWM3] = imx8m_clk_hw_composite("pwm3" , imx8mq_pwm3_sels, base + 0xb480); |
503 | hws[IMX8MQ_CLK_PWM4] = imx8m_clk_hw_composite("pwm4" , imx8mq_pwm4_sels, base + 0xb500); |
504 | hws[IMX8MQ_CLK_GPT1] = imx8m_clk_hw_composite("gpt1" , imx8mq_gpt1_sels, base + 0xb580); |
505 | hws[IMX8MQ_CLK_WDOG] = imx8m_clk_hw_composite("wdog" , imx8mq_wdog_sels, base + 0xb900); |
506 | hws[IMX8MQ_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk" , imx8mq_wrclk_sels, base + 0xb980); |
507 | hws[IMX8MQ_CLK_CLKO1] = imx8m_clk_hw_composite("clko1" , imx8mq_clko1_sels, base + 0xba00); |
508 | hws[IMX8MQ_CLK_CLKO2] = imx8m_clk_hw_composite("clko2" , imx8mq_clko2_sels, base + 0xba80); |
509 | hws[IMX8MQ_CLK_DSI_CORE] = imx8m_clk_hw_composite("dsi_core" , imx8mq_dsi_core_sels, base + 0xbb00); |
510 | hws[IMX8MQ_CLK_DSI_PHY_REF] = imx8m_clk_hw_composite("dsi_phy_ref" , imx8mq_dsi_phy_sels, base + 0xbb80); |
511 | hws[IMX8MQ_CLK_DSI_DBI] = imx8m_clk_hw_composite("dsi_dbi" , imx8mq_dsi_dbi_sels, base + 0xbc00); |
512 | hws[IMX8MQ_CLK_DSI_ESC] = imx8m_clk_hw_composite("dsi_esc" , imx8mq_dsi_esc_sels, base + 0xbc80); |
513 | hws[IMX8MQ_CLK_DSI_AHB] = imx8m_clk_hw_composite("dsi_ahb" , imx8mq_dsi_ahb_sels, base + 0x9200); |
514 | hws[IMX8MQ_CLK_DSI_IPG_DIV] = imx_clk_hw_divider2("dsi_ipg_div" , "dsi_ahb" , base + 0x9280, 0, 6); |
515 | hws[IMX8MQ_CLK_CSI1_CORE] = imx8m_clk_hw_composite("csi1_core" , imx8mq_csi1_core_sels, base + 0xbd00); |
516 | hws[IMX8MQ_CLK_CSI1_PHY_REF] = imx8m_clk_hw_composite("csi1_phy_ref" , imx8mq_csi1_phy_sels, base + 0xbd80); |
517 | hws[IMX8MQ_CLK_CSI1_ESC] = imx8m_clk_hw_composite("csi1_esc" , imx8mq_csi1_esc_sels, base + 0xbe00); |
518 | hws[IMX8MQ_CLK_CSI2_CORE] = imx8m_clk_hw_composite("csi2_core" , imx8mq_csi2_core_sels, base + 0xbe80); |
519 | hws[IMX8MQ_CLK_CSI2_PHY_REF] = imx8m_clk_hw_composite("csi2_phy_ref" , imx8mq_csi2_phy_sels, base + 0xbf00); |
520 | hws[IMX8MQ_CLK_CSI2_ESC] = imx8m_clk_hw_composite("csi2_esc" , imx8mq_csi2_esc_sels, base + 0xbf80); |
521 | hws[IMX8MQ_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl" , imx8mq_pcie2_ctrl_sels, base + 0xc000); |
522 | hws[IMX8MQ_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy" , imx8mq_pcie2_phy_sels, base + 0xc080); |
523 | hws[IMX8MQ_CLK_PCIE2_AUX] = imx8m_clk_hw_composite("pcie2_aux" , imx8mq_pcie2_aux_sels, base + 0xc100); |
524 | hws[IMX8MQ_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3" , imx8mq_ecspi3_sels, base + 0xc180); |
525 | |
526 | hws[IMX8MQ_CLK_ECSPI1_ROOT] = imx_clk_hw_gate4("ecspi1_root_clk" , "ecspi1" , base + 0x4070, 0); |
527 | hws[IMX8MQ_CLK_ECSPI2_ROOT] = imx_clk_hw_gate4("ecspi2_root_clk" , "ecspi2" , base + 0x4080, 0); |
528 | hws[IMX8MQ_CLK_ECSPI3_ROOT] = imx_clk_hw_gate4("ecspi3_root_clk" , "ecspi3" , base + 0x4090, 0); |
529 | hws[IMX8MQ_CLK_ENET1_ROOT] = imx_clk_hw_gate4("enet1_root_clk" , "enet_axi" , base + 0x40a0, 0); |
530 | hws[IMX8MQ_CLK_GPIO1_ROOT] = imx_clk_hw_gate4("gpio1_root_clk" , "ipg_root" , base + 0x40b0, 0); |
531 | hws[IMX8MQ_CLK_GPIO2_ROOT] = imx_clk_hw_gate4("gpio2_root_clk" , "ipg_root" , base + 0x40c0, 0); |
532 | hws[IMX8MQ_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk" , "ipg_root" , base + 0x40d0, 0); |
533 | hws[IMX8MQ_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk" , "ipg_root" , base + 0x40e0, 0); |
534 | hws[IMX8MQ_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk" , "ipg_root" , base + 0x40f0, 0); |
535 | hws[IMX8MQ_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk" , "gpt1" , base + 0x4100, 0); |
536 | hws[IMX8MQ_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk" , "i2c1" , base + 0x4170, 0); |
537 | hws[IMX8MQ_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk" , "i2c2" , base + 0x4180, 0); |
538 | hws[IMX8MQ_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk" , "i2c3" , base + 0x4190, 0); |
539 | hws[IMX8MQ_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk" , "i2c4" , base + 0x41a0, 0); |
540 | hws[IMX8MQ_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk" , "ipg_root" , base + 0x4210, 0); |
541 | hws[IMX8MQ_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk" , "ipg_root" , base + 0x4220, 0); |
542 | hws[IMX8MQ_CLK_PCIE1_ROOT] = imx_clk_hw_gate4("pcie1_root_clk" , "pcie1_ctrl" , base + 0x4250, 0); |
543 | hws[IMX8MQ_CLK_PCIE2_ROOT] = imx_clk_hw_gate4("pcie2_root_clk" , "pcie2_ctrl" , base + 0x4640, 0); |
544 | hws[IMX8MQ_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk" , "pwm1" , base + 0x4280, 0); |
545 | hws[IMX8MQ_CLK_PWM2_ROOT] = imx_clk_hw_gate4("pwm2_root_clk" , "pwm2" , base + 0x4290, 0); |
546 | hws[IMX8MQ_CLK_PWM3_ROOT] = imx_clk_hw_gate4("pwm3_root_clk" , "pwm3" , base + 0x42a0, 0); |
547 | hws[IMX8MQ_CLK_PWM4_ROOT] = imx_clk_hw_gate4("pwm4_root_clk" , "pwm4" , base + 0x42b0, 0); |
548 | hws[IMX8MQ_CLK_QSPI_ROOT] = imx_clk_hw_gate4("qspi_root_clk" , "qspi" , base + 0x42f0, 0); |
549 | hws[IMX8MQ_CLK_RAWNAND_ROOT] = imx_clk_hw_gate2_shared2("nand_root_clk" , "nand" , base + 0x4300, 0, &share_count_nand); |
550 | hws[IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk" , "nand_usdhc_bus" , base + 0x4300, 0, &share_count_nand); |
551 | hws[IMX8MQ_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root_clk" , "sai1" , base + 0x4330, 0, &share_count_sai1); |
552 | hws[IMX8MQ_CLK_SAI1_IPG] = imx_clk_hw_gate2_shared2("sai1_ipg_clk" , "ipg_audio_root" , base + 0x4330, 0, &share_count_sai1); |
553 | hws[IMX8MQ_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root_clk" , "sai2" , base + 0x4340, 0, &share_count_sai2); |
554 | hws[IMX8MQ_CLK_SAI2_IPG] = imx_clk_hw_gate2_shared2("sai2_ipg_clk" , "ipg_root" , base + 0x4340, 0, &share_count_sai2); |
555 | hws[IMX8MQ_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root_clk" , "sai3" , base + 0x4350, 0, &share_count_sai3); |
556 | hws[IMX8MQ_CLK_SAI3_IPG] = imx_clk_hw_gate2_shared2("sai3_ipg_clk" , "ipg_root" , base + 0x4350, 0, &share_count_sai3); |
557 | hws[IMX8MQ_CLK_SAI4_ROOT] = imx_clk_hw_gate2_shared2("sai4_root_clk" , "sai4" , base + 0x4360, 0, &share_count_sai4); |
558 | hws[IMX8MQ_CLK_SAI4_IPG] = imx_clk_hw_gate2_shared2("sai4_ipg_clk" , "ipg_audio_root" , base + 0x4360, 0, &share_count_sai4); |
559 | hws[IMX8MQ_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root_clk" , "sai5" , base + 0x4370, 0, &share_count_sai5); |
560 | hws[IMX8MQ_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk" , "ipg_audio_root" , base + 0x4370, 0, &share_count_sai5); |
561 | hws[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk" , "sai6" , base + 0x4380, 0, &share_count_sai6); |
562 | hws[IMX8MQ_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk" , "ipg_audio_root" , base + 0x4380, 0, &share_count_sai6); |
563 | hws[IMX8MQ_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk" , "uart1" , base + 0x4490, 0); |
564 | hws[IMX8MQ_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk" , "uart2" , base + 0x44a0, 0); |
565 | hws[IMX8MQ_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk" , "uart3" , base + 0x44b0, 0); |
566 | hws[IMX8MQ_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk" , "uart4" , base + 0x44c0, 0); |
567 | hws[IMX8MQ_CLK_USB1_CTRL_ROOT] = imx_clk_hw_gate4("usb1_ctrl_root_clk" , "usb_bus" , base + 0x44d0, 0); |
568 | hws[IMX8MQ_CLK_USB2_CTRL_ROOT] = imx_clk_hw_gate4("usb2_ctrl_root_clk" , "usb_bus" , base + 0x44e0, 0); |
569 | hws[IMX8MQ_CLK_USB1_PHY_ROOT] = imx_clk_hw_gate4("usb1_phy_root_clk" , "usb_phy_ref" , base + 0x44f0, 0); |
570 | hws[IMX8MQ_CLK_USB2_PHY_ROOT] = imx_clk_hw_gate4("usb2_phy_root_clk" , "usb_phy_ref" , base + 0x4500, 0); |
571 | hws[IMX8MQ_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk" , "usdhc1" , base + 0x4510, 0); |
572 | hws[IMX8MQ_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk" , "usdhc2" , base + 0x4520, 0); |
573 | hws[IMX8MQ_CLK_WDOG1_ROOT] = imx_clk_hw_gate4("wdog1_root_clk" , "wdog" , base + 0x4530, 0); |
574 | hws[IMX8MQ_CLK_WDOG2_ROOT] = imx_clk_hw_gate4("wdog2_root_clk" , "wdog" , base + 0x4540, 0); |
575 | hws[IMX8MQ_CLK_WDOG3_ROOT] = imx_clk_hw_gate4("wdog3_root_clk" , "wdog" , base + 0x4550, 0); |
576 | hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk" , "vpu_g1" , base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); |
577 | hws[IMX8MQ_CLK_GPU_ROOT] = imx_clk_hw_gate4("gpu_root_clk" , "gpu_core" , base + 0x4570, 0); |
578 | hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk" , "vpu_g2" , base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); |
579 | hws[IMX8MQ_CLK_DISP_ROOT] = imx_clk_hw_gate2_shared2("disp_root_clk" , "disp_dc8000" , base + 0x45d0, 0, &share_count_dcss); |
580 | hws[IMX8MQ_CLK_DISP_AXI_ROOT] = imx_clk_hw_gate2_shared2("disp_axi_root_clk" , "disp_axi" , base + 0x45d0, 0, &share_count_dcss); |
581 | hws[IMX8MQ_CLK_DISP_APB_ROOT] = imx_clk_hw_gate2_shared2("disp_apb_root_clk" , "disp_apb" , base + 0x45d0, 0, &share_count_dcss); |
582 | hws[IMX8MQ_CLK_DISP_RTRM_ROOT] = imx_clk_hw_gate2_shared2("disp_rtrm_root_clk" , "disp_rtrm" , base + 0x45d0, 0, &share_count_dcss); |
583 | hws[IMX8MQ_CLK_TMU_ROOT] = imx_clk_hw_gate4("tmu_root_clk" , "ipg_root" , base + 0x4620, 0); |
584 | hws[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_hw_gate2_flags("vpu_dec_root_clk" , "vpu_bus" , base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE); |
585 | hws[IMX8MQ_CLK_CSI1_ROOT] = imx_clk_hw_gate4("csi1_root_clk" , "csi1_core" , base + 0x4650, 0); |
586 | hws[IMX8MQ_CLK_CSI2_ROOT] = imx_clk_hw_gate4("csi2_root_clk" , "csi2_core" , base + 0x4660, 0); |
587 | hws[IMX8MQ_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_clk" , "ipg_root" , base + 0x43a0, 0); |
588 | hws[IMX8MQ_CLK_SDMA2_ROOT] = imx_clk_hw_gate4("sdma2_clk" , "ipg_audio_root" , base + 0x43b0, 0); |
589 | |
590 | hws[IMX8MQ_GPT_3M_CLK] = imx_clk_hw_fixed_factor(name: "gpt_3m" , parent: "osc_25m" , mult: 1, div: 8); |
591 | hws[IMX8MQ_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor(name: "dram_alt_root" , parent: "dram_alt" , mult: 1, div: 4); |
592 | |
593 | hws[IMX8MQ_CLK_ARM] = imx_clk_hw_cpu(name: "arm" , parent_name: "arm_a53_core" , |
594 | div: hws[IMX8MQ_CLK_A53_CORE]->clk, |
595 | mux: hws[IMX8MQ_CLK_A53_CORE]->clk, |
596 | pll: hws[IMX8MQ_ARM_PLL_OUT]->clk, |
597 | step: hws[IMX8MQ_CLK_A53_DIV]->clk); |
598 | |
599 | imx_check_clk_hws(clks: hws, IMX8MQ_CLK_END); |
600 | |
601 | err = of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data); |
602 | if (err < 0) { |
603 | dev_err(dev, "failed to register hws for i.MX8MQ\n" ); |
604 | goto unregister_hws; |
605 | } |
606 | |
607 | imx_register_uart_clocks(); |
608 | |
609 | return 0; |
610 | |
611 | unregister_hws: |
612 | imx_unregister_hw_clocks(hws, IMX8MQ_CLK_END); |
613 | |
614 | return err; |
615 | } |
616 | |
617 | static const struct of_device_id imx8mq_clk_of_match[] = { |
618 | { .compatible = "fsl,imx8mq-ccm" }, |
619 | { /* Sentinel */ }, |
620 | }; |
621 | MODULE_DEVICE_TABLE(of, imx8mq_clk_of_match); |
622 | |
623 | |
624 | static struct platform_driver imx8mq_clk_driver = { |
625 | .probe = imx8mq_clocks_probe, |
626 | .driver = { |
627 | .name = "imx8mq-ccm" , |
628 | /* |
629 | * Disable bind attributes: clocks are not removed and |
630 | * reloading the driver will crash or break devices. |
631 | */ |
632 | .suppress_bind_attrs = true, |
633 | .of_match_table = imx8mq_clk_of_match, |
634 | }, |
635 | }; |
636 | module_platform_driver(imx8mq_clk_driver); |
637 | module_param(mcore_booted, bool, S_IRUGO); |
638 | MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not" ); |
639 | |
640 | MODULE_AUTHOR("Abel Vesa <abel.vesa@nxp.com>" ); |
641 | MODULE_DESCRIPTION("NXP i.MX8MQ clock driver" ); |
642 | MODULE_LICENSE("GPL v2" ); |
643 | |