1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
2 | /* |
3 | * Copyright (C) 2021 |
4 | * Author(s): |
5 | * Jesse Taube <Mr.Bossman075@gmail.com> |
6 | * Giulio Benetti <giulio.benetti@benettiengineering.com> |
7 | */ |
8 | #include <linux/clk.h> |
9 | #include <linux/of_address.h> |
10 | #include <linux/of_irq.h> |
11 | #include <linux/platform_device.h> |
12 | #include <dt-bindings/clock/imxrt1050-clock.h> |
13 | |
14 | #include "clk.h" |
15 | |
16 | static const char * const pll_ref_sels[] = {"osc" , "dummy" , }; |
17 | static const char * const per_sels[] = {"ipg_pdof" , "osc" , }; |
18 | static const char * const pll1_bypass_sels[] = {"pll1_arm" , "pll1_arm_ref_sel" , }; |
19 | static const char * const pll2_bypass_sels[] = {"pll2_sys" , "pll2_sys_ref_sel" , }; |
20 | static const char * const pll3_bypass_sels[] = {"pll3_usb_otg" , "pll3_usb_otg_ref_sel" , }; |
21 | static const char * const pll5_bypass_sels[] = {"pll5_video" , "pll5_video_ref_sel" , }; |
22 | static const char *const pre_periph_sels[] = { |
23 | "pll2_sys" , "pll2_pfd2_396m" , "pll2_pfd0_352m" , "arm_podf" , }; |
24 | static const char *const periph_sels[] = { "pre_periph_sel" , "todo" , }; |
25 | static const char *const usdhc_sels[] = { "pll2_pfd2_396m" , "pll2_pfd0_352m" , }; |
26 | static const char *const lpuart_sels[] = { "pll3_80m" , "osc" , }; |
27 | static const char *const lcdif_sels[] = { |
28 | "pll2_sys" , "pll3_pfd3_454_74m" , "pll5_video" , "pll2_pfd0_352m" , |
29 | "pll2_pfd1_594m" , "pll3_pfd1_664_62m" , }; |
30 | static const char *const semc_alt_sels[] = { "pll2_pfd2_396m" , "pll3_pfd1_664_62m" , }; |
31 | static const char *const semc_sels[] = { "periph_sel" , "semc_alt_sel" , }; |
32 | |
33 | static struct clk_hw **hws; |
34 | static struct clk_hw_onecell_data *clk_hw_data; |
35 | |
36 | static int imxrt1050_clocks_probe(struct platform_device *pdev) |
37 | { |
38 | void __iomem *ccm_base; |
39 | void __iomem *pll_base; |
40 | struct device *dev = &pdev->dev; |
41 | struct device_node *np = dev->of_node; |
42 | struct device_node *anp; |
43 | int ret; |
44 | |
45 | clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, |
46 | IMXRT1050_CLK_END), GFP_KERNEL); |
47 | if (WARN_ON(!clk_hw_data)) |
48 | return -ENOMEM; |
49 | |
50 | clk_hw_data->num = IMXRT1050_CLK_END; |
51 | hws = clk_hw_data->hws; |
52 | |
53 | hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, name: "osc" ); |
54 | |
55 | anp = of_find_compatible_node(NULL, NULL, compat: "fsl,imxrt-anatop" ); |
56 | pll_base = devm_of_iomap(dev, node: anp, index: 0, NULL); |
57 | of_node_put(node: anp); |
58 | if (WARN_ON(IS_ERR(pll_base))) { |
59 | ret = PTR_ERR(ptr: pll_base); |
60 | goto unregister_hws; |
61 | } |
62 | |
63 | /* Anatop clocks */ |
64 | hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed(name: "dummy" , rate: 0UL); |
65 | |
66 | hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel" , |
67 | pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
68 | hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel" , |
69 | pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
70 | hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel" , |
71 | pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
72 | hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel" , |
73 | pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); |
74 | |
75 | hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(type: IMX_PLLV3_SYS, name: "pll1_arm" , |
76 | parent_name: "pll1_arm_ref_sel" , base: pll_base + 0x0, div_mask: 0x7f); |
77 | hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(type: IMX_PLLV3_GENERIC, name: "pll2_sys" , |
78 | parent_name: "pll2_sys_ref_sel" , base: pll_base + 0x30, div_mask: 0x1); |
79 | hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(type: IMX_PLLV3_USB, name: "pll3_usb_otg" , |
80 | parent_name: "pll3_usb_otg_ref_sel" , base: pll_base + 0x10, div_mask: 0x1); |
81 | hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(type: IMX_PLLV3_AV, name: "pll5_video" , |
82 | parent_name: "pll5_video_ref_sel" , base: pll_base + 0xa0, div_mask: 0x7f); |
83 | |
84 | /* PLL bypass out */ |
85 | hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass" , pll_base + 0x0, 16, 1, |
86 | pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); |
87 | hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass" , pll_base + 0x30, 16, 1, |
88 | pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); |
89 | hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass" , pll_base + 0x10, 16, 1, |
90 | pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); |
91 | hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass" , pll_base + 0xa0, 16, 1, |
92 | pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); |
93 | |
94 | hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel" , |
95 | "pll5_video" , pll_base + 0xa0, 19, 2); |
96 | hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div" , |
97 | "video_post_div_sel" , pll_base + 0x170, 30, 2); |
98 | |
99 | hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor(name: "pll3_80m" , parent: "pll3_usb_otg" , mult: 1, div: 6); |
100 | |
101 | hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd(name: "pll2_pfd0_352m" , parent_name: "pll2_sys" , reg: pll_base + 0x100, idx: 0); |
102 | hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd(name: "pll2_pfd1_594m" , parent_name: "pll2_sys" , reg: pll_base + 0x100, idx: 1); |
103 | hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd(name: "pll2_pfd2_396m" , parent_name: "pll2_sys" , reg: pll_base + 0x100, idx: 2); |
104 | hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd(name: "pll3_pfd1_664_62m" , parent_name: "pll3_usb_otg" , reg: pll_base + 0xf0, idx: 1); |
105 | hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd(name: "pll3_pfd3_454_74m" , parent_name: "pll3_usb_otg" , reg: pll_base + 0xf0, idx: 3); |
106 | |
107 | /* CCM clocks */ |
108 | ccm_base = devm_platform_ioremap_resource(pdev, index: 0); |
109 | if (WARN_ON(IS_ERR(ccm_base))) { |
110 | ret = PTR_ERR(ptr: ccm_base); |
111 | goto unregister_hws; |
112 | } |
113 | |
114 | hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf" , "pll1_arm" , ccm_base + 0x10, 0, 3); |
115 | hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel" , ccm_base + 0x18, 18, 2, |
116 | pre_periph_sels, ARRAY_SIZE(pre_periph_sels)); |
117 | hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel" , ccm_base + 0x14, 25, 1, |
118 | periph_sels, ARRAY_SIZE(periph_sels)); |
119 | hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel" , ccm_base + 0x1c, 16, 1, |
120 | usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
121 | hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel" , ccm_base + 0x1c, 17, 1, |
122 | usdhc_sels, ARRAY_SIZE(usdhc_sels)); |
123 | hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel" , ccm_base + 0x24, 6, 1, |
124 | lpuart_sels, ARRAY_SIZE(lpuart_sels)); |
125 | hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel" , ccm_base + 0x38, 15, 3, |
126 | lcdif_sels, ARRAY_SIZE(lcdif_sels)); |
127 | hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel" , ccm_base + 0x1C, 6, 1, |
128 | per_sels, ARRAY_SIZE(per_sels)); |
129 | hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel" , ccm_base + 0x14, 7, 1, |
130 | semc_alt_sels, ARRAY_SIZE(semc_alt_sels)); |
131 | hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel" , ccm_base + 0x14, 6, 1, |
132 | semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL); |
133 | |
134 | hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb" , "periph_sel" , ccm_base + 0x14, 10, 3); |
135 | hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg" , "ahb" , ccm_base + 0x14, 8, 2); |
136 | hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per" , "per_sel" , ccm_base + 0x1C, 0, 5); |
137 | |
138 | hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf" , "usdhc1_sel" , ccm_base + 0x24, 11, 3); |
139 | hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf" , "usdhc2_sel" , ccm_base + 0x24, 16, 3); |
140 | hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf" , "lpuart_sel" , ccm_base + 0x24, 0, 6); |
141 | hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred" , "lcdif_sel" , ccm_base + 0x38, 12, 3); |
142 | hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf" , "lcdif_pred" , ccm_base + 0x18, 23, 3); |
143 | |
144 | hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1" , "usdhc1_podf" , ccm_base + 0x80, 2); |
145 | hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2" , "usdhc2_podf" , ccm_base + 0x80, 4); |
146 | hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1" , "lpuart_podf" , ccm_base + 0x7c, 24); |
147 | hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif" , "lcdif_podf" , ccm_base + 0x70, 28); |
148 | hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix" , "lcdif" , ccm_base + 0x74, 10); |
149 | hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma" , "ipg" , ccm_base + 0x7C, 6); |
150 | hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0" , "ipg" , ccm_base + 0x7C, 7); |
151 | imx_check_clk_hws(clks: hws, IMXRT1050_CLK_END); |
152 | |
153 | ret = of_clk_add_hw_provider(np, get: of_clk_hw_onecell_get, data: clk_hw_data); |
154 | if (ret < 0) { |
155 | dev_err(dev, "Failed to register clks for i.MXRT1050.\n" ); |
156 | goto unregister_hws; |
157 | } |
158 | return 0; |
159 | |
160 | unregister_hws: |
161 | imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END); |
162 | return ret; |
163 | } |
164 | static const struct of_device_id imxrt1050_clk_of_match[] = { |
165 | { .compatible = "fsl,imxrt1050-ccm" }, |
166 | { /* Sentinel */ } |
167 | }; |
168 | MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match); |
169 | |
170 | static struct platform_driver imxrt1050_clk_driver = { |
171 | .probe = imxrt1050_clocks_probe, |
172 | .driver = { |
173 | .name = "imxrt1050-ccm" , |
174 | .of_match_table = imxrt1050_clk_of_match, |
175 | }, |
176 | }; |
177 | module_platform_driver(imxrt1050_clk_driver); |
178 | |
179 | MODULE_LICENSE("Dual BSD/GPL" ); |
180 | MODULE_AUTHOR("Jesse Taube <Mr.Bossman075@gmail.com>" ); |
181 | MODULE_AUTHOR("Giulio Benetti <giulio.benetti@benettiengineering.com>" ); |
182 | |