1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com> |
4 | */ |
5 | |
6 | #include <linux/clk.h> |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/io.h> |
9 | #include <linux/of_address.h> |
10 | #include <linux/regmap.h> |
11 | |
12 | #include <dt-bindings/clock/lpc32xx-clock.h> |
13 | |
14 | #undef pr_fmt |
15 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
16 | |
17 | /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */ |
18 | #define PLL_CTRL_ENABLE BIT(16) |
19 | #define PLL_CTRL_BYPASS BIT(15) |
20 | #define PLL_CTRL_DIRECT BIT(14) |
21 | #define PLL_CTRL_FEEDBACK BIT(13) |
22 | #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11)) |
23 | #define PLL_CTRL_PREDIV (BIT(10)|BIT(9)) |
24 | #define PLL_CTRL_FEEDDIV (0xFF << 1) |
25 | #define PLL_CTRL_LOCK BIT(0) |
26 | |
27 | /* Clock registers on System Control Block */ |
28 | #define LPC32XX_CLKPWR_DEBUG_CTRL 0x00 |
29 | #define LPC32XX_CLKPWR_USB_DIV 0x1C |
30 | #define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40 |
31 | #define LPC32XX_CLKPWR_PWR_CTRL 0x44 |
32 | #define LPC32XX_CLKPWR_PLL397_CTRL 0x48 |
33 | #define LPC32XX_CLKPWR_OSC_CTRL 0x4C |
34 | #define LPC32XX_CLKPWR_SYSCLK_CTRL 0x50 |
35 | #define LPC32XX_CLKPWR_LCDCLK_CTRL 0x54 |
36 | #define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58 |
37 | #define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60 |
38 | #define LPC32XX_CLKPWR_USB_CTRL 0x64 |
39 | #define LPC32XX_CLKPWR_SSP_CTRL 0x78 |
40 | #define LPC32XX_CLKPWR_I2S_CTRL 0x7C |
41 | #define LPC32XX_CLKPWR_MS_CTRL 0x80 |
42 | #define LPC32XX_CLKPWR_MACCLK_CTRL 0x90 |
43 | #define LPC32XX_CLKPWR_TEST_CLK_CTRL 0xA4 |
44 | #define LPC32XX_CLKPWR_I2CCLK_CTRL 0xAC |
45 | #define LPC32XX_CLKPWR_KEYCLK_CTRL 0xB0 |
46 | #define LPC32XX_CLKPWR_ADCCLK_CTRL 0xB4 |
47 | #define LPC32XX_CLKPWR_PWMCLK_CTRL 0xB8 |
48 | #define LPC32XX_CLKPWR_TIMCLK_CTRL 0xBC |
49 | #define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0 |
50 | #define LPC32XX_CLKPWR_SPI_CTRL 0xC4 |
51 | #define LPC32XX_CLKPWR_FLASHCLK_CTRL 0xC8 |
52 | #define LPC32XX_CLKPWR_UART3_CLK_CTRL 0xD0 |
53 | #define LPC32XX_CLKPWR_UART4_CLK_CTRL 0xD4 |
54 | #define LPC32XX_CLKPWR_UART5_CLK_CTRL 0xD8 |
55 | #define LPC32XX_CLKPWR_UART6_CLK_CTRL 0xDC |
56 | #define LPC32XX_CLKPWR_IRDA_CLK_CTRL 0xE0 |
57 | #define LPC32XX_CLKPWR_UART_CLK_CTRL 0xE4 |
58 | #define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8 |
59 | |
60 | /* Clock registers on USB controller */ |
61 | #define LPC32XX_USB_CLK_CTRL 0xF4 |
62 | #define LPC32XX_USB_CLK_STS 0xF8 |
63 | |
64 | static struct regmap_config lpc32xx_scb_regmap_config = { |
65 | .name = "scb" , |
66 | .reg_bits = 32, |
67 | .val_bits = 32, |
68 | .reg_stride = 4, |
69 | .val_format_endian = REGMAP_ENDIAN_LITTLE, |
70 | .max_register = 0x114, |
71 | .fast_io = true, |
72 | }; |
73 | |
74 | static struct regmap *clk_regmap; |
75 | static void __iomem *usb_clk_vbase; |
76 | |
77 | enum { |
78 | LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1, |
79 | LPC32XX_USB_CLK_AHB, |
80 | |
81 | LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1, |
82 | }; |
83 | |
84 | enum { |
85 | /* Start from the last defined clock in dt bindings */ |
86 | LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1, |
87 | LPC32XX_CLK_ADC_RTC, |
88 | LPC32XX_CLK_TEST1, |
89 | LPC32XX_CLK_TEST2, |
90 | |
91 | /* System clocks, PLL 397x and HCLK PLL clocks */ |
92 | LPC32XX_CLK_OSC, |
93 | LPC32XX_CLK_SYS, |
94 | LPC32XX_CLK_PLL397X, |
95 | LPC32XX_CLK_HCLK_DIV_PERIPH, |
96 | LPC32XX_CLK_HCLK_DIV, |
97 | LPC32XX_CLK_HCLK, |
98 | LPC32XX_CLK_ARM, |
99 | LPC32XX_CLK_ARM_VFP, |
100 | |
101 | /* USB clocks */ |
102 | LPC32XX_CLK_USB_PLL, |
103 | LPC32XX_CLK_USB_DIV, |
104 | LPC32XX_CLK_USB, |
105 | |
106 | /* Only one control PWR_CTRL[10] for both muxes */ |
107 | LPC32XX_CLK_PERIPH_HCLK_MUX, |
108 | LPC32XX_CLK_PERIPH_ARM_MUX, |
109 | |
110 | /* Only one control PWR_CTRL[2] for all three muxes */ |
111 | LPC32XX_CLK_SYSCLK_PERIPH_MUX, |
112 | LPC32XX_CLK_SYSCLK_HCLK_MUX, |
113 | LPC32XX_CLK_SYSCLK_ARM_MUX, |
114 | |
115 | /* Two clock sources external to the driver */ |
116 | LPC32XX_CLK_XTAL_32K, |
117 | LPC32XX_CLK_XTAL, |
118 | |
119 | /* Renumbered USB clocks, may have a parent from SCB table */ |
120 | LPC32XX_CLK_USB_OFFSET, |
121 | LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET, |
122 | LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET, |
123 | LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET, |
124 | LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET, |
125 | LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET, |
126 | |
127 | /* Stub for composite clocks */ |
128 | LPC32XX_CLK__NULL, |
129 | |
130 | /* Subclocks of composite clocks, clocks above are for CCF */ |
131 | LPC32XX_CLK_PWM1_MUX, |
132 | LPC32XX_CLK_PWM1_DIV, |
133 | LPC32XX_CLK_PWM1_GATE, |
134 | LPC32XX_CLK_PWM2_MUX, |
135 | LPC32XX_CLK_PWM2_DIV, |
136 | LPC32XX_CLK_PWM2_GATE, |
137 | LPC32XX_CLK_UART3_MUX, |
138 | LPC32XX_CLK_UART3_DIV, |
139 | LPC32XX_CLK_UART3_GATE, |
140 | LPC32XX_CLK_UART4_MUX, |
141 | LPC32XX_CLK_UART4_DIV, |
142 | LPC32XX_CLK_UART4_GATE, |
143 | LPC32XX_CLK_UART5_MUX, |
144 | LPC32XX_CLK_UART5_DIV, |
145 | LPC32XX_CLK_UART5_GATE, |
146 | LPC32XX_CLK_UART6_MUX, |
147 | LPC32XX_CLK_UART6_DIV, |
148 | LPC32XX_CLK_UART6_GATE, |
149 | LPC32XX_CLK_TEST1_MUX, |
150 | LPC32XX_CLK_TEST1_GATE, |
151 | LPC32XX_CLK_TEST2_MUX, |
152 | LPC32XX_CLK_TEST2_GATE, |
153 | LPC32XX_CLK_USB_DIV_DIV, |
154 | LPC32XX_CLK_USB_DIV_GATE, |
155 | LPC32XX_CLK_SD_DIV, |
156 | LPC32XX_CLK_SD_GATE, |
157 | LPC32XX_CLK_LCD_DIV, |
158 | LPC32XX_CLK_LCD_GATE, |
159 | |
160 | LPC32XX_CLK_HW_MAX, |
161 | LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1, |
162 | LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1, |
163 | }; |
164 | |
165 | static struct clk *clk[LPC32XX_CLK_MAX]; |
166 | static struct clk_onecell_data clk_data = { |
167 | .clks = clk, |
168 | .clk_num = LPC32XX_CLK_MAX, |
169 | }; |
170 | |
171 | static struct clk *usb_clk[LPC32XX_USB_CLK_MAX]; |
172 | static struct clk_onecell_data usb_clk_data = { |
173 | .clks = usb_clk, |
174 | .clk_num = LPC32XX_USB_CLK_MAX, |
175 | }; |
176 | |
177 | #define LPC32XX_CLK_PARENTS_MAX 5 |
178 | |
179 | struct clk_proto_t { |
180 | const char *name; |
181 | const u8 parents[LPC32XX_CLK_PARENTS_MAX]; |
182 | u8 num_parents; |
183 | unsigned long flags; |
184 | }; |
185 | |
186 | #define CLK_PREFIX(LITERAL) LPC32XX_CLK_ ## LITERAL |
187 | #define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int)) |
188 | |
189 | #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \ |
190 | [CLK_PREFIX(_idx)] = { \ |
191 | .name = _name, \ |
192 | .flags = _flags, \ |
193 | .parents = { __VA_ARGS__ }, \ |
194 | .num_parents = NUMARGS(__VA_ARGS__), \ |
195 | } |
196 | |
197 | static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = { |
198 | LPC32XX_CLK_DEFINE(XTAL, "xtal" , 0x0), |
199 | LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k" , 0x0), |
200 | |
201 | LPC32XX_CLK_DEFINE(RTC, "rtc" , 0x0, LPC32XX_CLK_XTAL_32K), |
202 | LPC32XX_CLK_DEFINE(OSC, "osc" , CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL), |
203 | LPC32XX_CLK_DEFINE(SYS, "sys" , CLK_IGNORE_UNUSED, |
204 | LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X), |
205 | LPC32XX_CLK_DEFINE(PLL397X, "pll_397x" , CLK_IGNORE_UNUSED, |
206 | LPC32XX_CLK_RTC), |
207 | LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll" , CLK_IGNORE_UNUSED, |
208 | LPC32XX_CLK_SYS), |
209 | LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph" , |
210 | CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL), |
211 | LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div" , CLK_IGNORE_UNUSED, |
212 | LPC32XX_CLK_HCLK_PLL), |
213 | LPC32XX_CLK_DEFINE(HCLK, "hclk" , CLK_IGNORE_UNUSED, |
214 | LPC32XX_CLK_PERIPH_HCLK_MUX), |
215 | LPC32XX_CLK_DEFINE(PERIPH, "pclk" , CLK_IGNORE_UNUSED, |
216 | LPC32XX_CLK_SYSCLK_PERIPH_MUX), |
217 | LPC32XX_CLK_DEFINE(ARM, "arm" , CLK_IGNORE_UNUSED, |
218 | LPC32XX_CLK_PERIPH_ARM_MUX), |
219 | |
220 | LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux" , |
221 | CLK_IGNORE_UNUSED, |
222 | LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX), |
223 | LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux" , CLK_IGNORE_UNUSED, |
224 | LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX), |
225 | LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux" , |
226 | CLK_IGNORE_UNUSED, |
227 | LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH), |
228 | LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux" , |
229 | CLK_IGNORE_UNUSED, |
230 | LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV), |
231 | LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux" , CLK_IGNORE_UNUSED, |
232 | LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL), |
233 | |
234 | LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9" , CLK_IGNORE_UNUSED, |
235 | LPC32XX_CLK_ARM), |
236 | LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll" , |
237 | CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV), |
238 | LPC32XX_CLK_DEFINE(USB_DIV, "usb_div" , 0x0, LPC32XX_CLK_OSC), |
239 | LPC32XX_CLK_DEFINE(USB, "usb" , 0x0, LPC32XX_CLK_USB_PLL), |
240 | LPC32XX_CLK_DEFINE(DMA, "dma" , 0x0, LPC32XX_CLK_HCLK), |
241 | LPC32XX_CLK_DEFINE(MLC, "mlc" , 0x0, LPC32XX_CLK_HCLK), |
242 | LPC32XX_CLK_DEFINE(SLC, "slc" , 0x0, LPC32XX_CLK_HCLK), |
243 | LPC32XX_CLK_DEFINE(LCD, "lcd" , 0x0, LPC32XX_CLK_HCLK), |
244 | LPC32XX_CLK_DEFINE(MAC, "mac" , 0x0, LPC32XX_CLK_HCLK), |
245 | LPC32XX_CLK_DEFINE(SD, "sd" , 0x0, LPC32XX_CLK_ARM), |
246 | LPC32XX_CLK_DEFINE(DDRAM, "ddram" , CLK_GET_RATE_NOCACHE, |
247 | LPC32XX_CLK_SYSCLK_ARM_MUX), |
248 | LPC32XX_CLK_DEFINE(SSP0, "ssp0" , 0x0, LPC32XX_CLK_HCLK), |
249 | LPC32XX_CLK_DEFINE(SSP1, "ssp1" , 0x0, LPC32XX_CLK_HCLK), |
250 | |
251 | /* |
252 | * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its |
253 | * divider register does not contain information about selected rate. |
254 | */ |
255 | LPC32XX_CLK_DEFINE(UART3, "uart3" , CLK_GET_RATE_NOCACHE, |
256 | LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), |
257 | LPC32XX_CLK_DEFINE(UART4, "uart4" , CLK_GET_RATE_NOCACHE, |
258 | LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), |
259 | LPC32XX_CLK_DEFINE(UART5, "uart5" , CLK_GET_RATE_NOCACHE, |
260 | LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), |
261 | LPC32XX_CLK_DEFINE(UART6, "uart6" , CLK_GET_RATE_NOCACHE, |
262 | LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK), |
263 | LPC32XX_CLK_DEFINE(IRDA, "irda" , 0x0, LPC32XX_CLK_PERIPH), |
264 | LPC32XX_CLK_DEFINE(I2C1, "i2c1" , 0x0, LPC32XX_CLK_HCLK), |
265 | LPC32XX_CLK_DEFINE(I2C2, "i2c2" , 0x0, LPC32XX_CLK_HCLK), |
266 | LPC32XX_CLK_DEFINE(TIMER0, "timer0" , 0x0, LPC32XX_CLK_PERIPH), |
267 | LPC32XX_CLK_DEFINE(TIMER1, "timer1" , 0x0, LPC32XX_CLK_PERIPH), |
268 | LPC32XX_CLK_DEFINE(TIMER2, "timer2" , 0x0, LPC32XX_CLK_PERIPH), |
269 | LPC32XX_CLK_DEFINE(TIMER3, "timer3" , 0x0, LPC32XX_CLK_PERIPH), |
270 | LPC32XX_CLK_DEFINE(TIMER4, "timer4" , 0x0, LPC32XX_CLK_PERIPH), |
271 | LPC32XX_CLK_DEFINE(TIMER5, "timer5" , 0x0, LPC32XX_CLK_PERIPH), |
272 | LPC32XX_CLK_DEFINE(WDOG, "watchdog" , 0x0, LPC32XX_CLK_PERIPH), |
273 | LPC32XX_CLK_DEFINE(I2S0, "i2s0" , 0x0, LPC32XX_CLK_HCLK), |
274 | LPC32XX_CLK_DEFINE(I2S1, "i2s1" , 0x0, LPC32XX_CLK_HCLK), |
275 | LPC32XX_CLK_DEFINE(SPI1, "spi1" , 0x0, LPC32XX_CLK_HCLK), |
276 | LPC32XX_CLK_DEFINE(SPI2, "spi2" , 0x0, LPC32XX_CLK_HCLK), |
277 | LPC32XX_CLK_DEFINE(MCPWM, "mcpwm" , 0x0, LPC32XX_CLK_HCLK), |
278 | LPC32XX_CLK_DEFINE(HSTIMER, "hstimer" , 0x0, LPC32XX_CLK_PERIPH), |
279 | LPC32XX_CLK_DEFINE(KEY, "key" , 0x0, LPC32XX_CLK_RTC), |
280 | LPC32XX_CLK_DEFINE(PWM1, "pwm1" , 0x0, |
281 | LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH), |
282 | LPC32XX_CLK_DEFINE(PWM2, "pwm2" , 0x0, |
283 | LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH), |
284 | LPC32XX_CLK_DEFINE(ADC, "adc" , 0x0, |
285 | LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV), |
286 | LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div" , 0x0, LPC32XX_CLK_PERIPH), |
287 | LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc" , 0x0, LPC32XX_CLK_RTC), |
288 | LPC32XX_CLK_DEFINE(TEST1, "test1" , 0x0, |
289 | LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC), |
290 | LPC32XX_CLK_DEFINE(TEST2, "test2" , 0x0, |
291 | LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB, |
292 | LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X), |
293 | |
294 | /* USB controller clocks */ |
295 | LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb" , 0x0, LPC32XX_CLK_USB), |
296 | LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg" , 0x0, LPC32XX_CLK_USB_AHB), |
297 | LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c" , 0x0, LPC32XX_CLK_USB_AHB), |
298 | LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev" , 0x0, LPC32XX_CLK_USB_OTG), |
299 | LPC32XX_CLK_DEFINE(USB_HOST, "usb_host" , 0x0, LPC32XX_CLK_USB_OTG), |
300 | }; |
301 | |
302 | struct lpc32xx_clk { |
303 | struct clk_hw hw; |
304 | u32 reg; |
305 | u32 enable; |
306 | u32 enable_mask; |
307 | u32 disable; |
308 | u32 disable_mask; |
309 | u32 busy; |
310 | u32 busy_mask; |
311 | }; |
312 | |
313 | enum clk_pll_mode { |
314 | PLL_UNKNOWN, |
315 | PLL_DIRECT, |
316 | PLL_BYPASS, |
317 | PLL_DIRECT_BYPASS, |
318 | PLL_INTEGER, |
319 | PLL_NON_INTEGER, |
320 | }; |
321 | |
322 | struct lpc32xx_pll_clk { |
323 | struct clk_hw hw; |
324 | u32 reg; |
325 | u32 enable; |
326 | unsigned long m_div; |
327 | unsigned long n_div; |
328 | unsigned long p_div; |
329 | enum clk_pll_mode mode; |
330 | }; |
331 | |
332 | struct lpc32xx_usb_clk { |
333 | struct clk_hw hw; |
334 | u32 ctrl_enable; |
335 | u32 ctrl_disable; |
336 | u32 ctrl_mask; |
337 | u32 enable; |
338 | u32 busy; |
339 | }; |
340 | |
341 | struct lpc32xx_clk_mux { |
342 | struct clk_hw hw; |
343 | u32 reg; |
344 | u32 mask; |
345 | u8 shift; |
346 | u32 *table; |
347 | u8 flags; |
348 | }; |
349 | |
350 | struct lpc32xx_clk_div { |
351 | struct clk_hw hw; |
352 | u32 reg; |
353 | u8 shift; |
354 | u8 width; |
355 | const struct clk_div_table *table; |
356 | u8 flags; |
357 | }; |
358 | |
359 | struct lpc32xx_clk_gate { |
360 | struct clk_hw hw; |
361 | u32 reg; |
362 | u8 bit_idx; |
363 | u8 flags; |
364 | }; |
365 | |
366 | #define to_lpc32xx_clk(_hw) container_of(_hw, struct lpc32xx_clk, hw) |
367 | #define to_lpc32xx_pll_clk(_hw) container_of(_hw, struct lpc32xx_pll_clk, hw) |
368 | #define to_lpc32xx_usb_clk(_hw) container_of(_hw, struct lpc32xx_usb_clk, hw) |
369 | #define to_lpc32xx_mux(_hw) container_of(_hw, struct lpc32xx_clk_mux, hw) |
370 | #define to_lpc32xx_div(_hw) container_of(_hw, struct lpc32xx_clk_div, hw) |
371 | #define to_lpc32xx_gate(_hw) container_of(_hw, struct lpc32xx_clk_gate, hw) |
372 | |
373 | static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max) |
374 | { |
375 | return (val0 >= (val1 * min) && val0 <= (val1 * max)); |
376 | } |
377 | |
378 | static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) |
379 | { |
380 | return readl(addr: usb_clk_vbase + LPC32XX_USB_CLK_STS); |
381 | } |
382 | |
383 | static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val) |
384 | { |
385 | writel(val, addr: usb_clk_vbase + LPC32XX_USB_CLK_CTRL); |
386 | } |
387 | |
388 | static int clk_mask_enable(struct clk_hw *hw) |
389 | { |
390 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
391 | u32 val; |
392 | |
393 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
394 | |
395 | if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) |
396 | return -EBUSY; |
397 | |
398 | return regmap_update_bits(map: clk_regmap, reg: clk->reg, |
399 | mask: clk->enable_mask, val: clk->enable); |
400 | } |
401 | |
402 | static void clk_mask_disable(struct clk_hw *hw) |
403 | { |
404 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
405 | |
406 | regmap_update_bits(map: clk_regmap, reg: clk->reg, |
407 | mask: clk->disable_mask, val: clk->disable); |
408 | } |
409 | |
410 | static int clk_mask_is_enabled(struct clk_hw *hw) |
411 | { |
412 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
413 | u32 val; |
414 | |
415 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
416 | |
417 | return ((val & clk->enable_mask) == clk->enable); |
418 | } |
419 | |
420 | static const struct clk_ops clk_mask_ops = { |
421 | .enable = clk_mask_enable, |
422 | .disable = clk_mask_disable, |
423 | .is_enabled = clk_mask_is_enabled, |
424 | }; |
425 | |
426 | static int clk_pll_enable(struct clk_hw *hw) |
427 | { |
428 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
429 | u32 val, count; |
430 | |
431 | regmap_update_bits(map: clk_regmap, reg: clk->reg, mask: clk->enable, val: clk->enable); |
432 | |
433 | for (count = 0; count < 1000; count++) { |
434 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
435 | if (val & PLL_CTRL_LOCK) |
436 | break; |
437 | } |
438 | |
439 | if (val & PLL_CTRL_LOCK) |
440 | return 0; |
441 | |
442 | return -ETIMEDOUT; |
443 | } |
444 | |
445 | static void clk_pll_disable(struct clk_hw *hw) |
446 | { |
447 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
448 | |
449 | regmap_update_bits(map: clk_regmap, reg: clk->reg, mask: clk->enable, val: 0x0); |
450 | } |
451 | |
452 | static int clk_pll_is_enabled(struct clk_hw *hw) |
453 | { |
454 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
455 | u32 val; |
456 | |
457 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
458 | |
459 | val &= clk->enable | PLL_CTRL_LOCK; |
460 | if (val == (clk->enable | PLL_CTRL_LOCK)) |
461 | return 1; |
462 | |
463 | return 0; |
464 | } |
465 | |
466 | static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw, |
467 | unsigned long parent_rate) |
468 | { |
469 | return parent_rate * 397; |
470 | } |
471 | |
472 | static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, |
473 | unsigned long parent_rate) |
474 | { |
475 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
476 | bool is_direct, is_bypass, is_feedback; |
477 | unsigned long rate, cco_rate, ref_rate; |
478 | u32 val; |
479 | |
480 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
481 | is_direct = val & PLL_CTRL_DIRECT; |
482 | is_bypass = val & PLL_CTRL_BYPASS; |
483 | is_feedback = val & PLL_CTRL_FEEDBACK; |
484 | |
485 | clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1; |
486 | clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1; |
487 | clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1; |
488 | |
489 | if (is_direct && is_bypass) { |
490 | clk->p_div = 0; |
491 | clk->mode = PLL_DIRECT_BYPASS; |
492 | return parent_rate; |
493 | } |
494 | if (is_bypass) { |
495 | clk->mode = PLL_BYPASS; |
496 | return parent_rate / (1 << clk->p_div); |
497 | } |
498 | if (is_direct) { |
499 | clk->p_div = 0; |
500 | clk->mode = PLL_DIRECT; |
501 | } |
502 | |
503 | ref_rate = parent_rate / clk->n_div; |
504 | rate = cco_rate = ref_rate * clk->m_div; |
505 | |
506 | if (!is_direct) { |
507 | if (is_feedback) { |
508 | cco_rate *= (1 << clk->p_div); |
509 | clk->mode = PLL_INTEGER; |
510 | } else { |
511 | rate /= (1 << clk->p_div); |
512 | clk->mode = PLL_NON_INTEGER; |
513 | } |
514 | } |
515 | |
516 | pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n" , |
517 | clk_hw_get_name(hw), |
518 | parent_rate, val, is_direct, is_bypass, is_feedback, |
519 | clk->n_div, clk->m_div, (1 << clk->p_div), rate); |
520 | |
521 | if (clk_pll_is_enabled(hw) && |
522 | !(pll_is_valid(val0: parent_rate, val1: 1, min: 1000000, max: 20000000) |
523 | && pll_is_valid(val0: cco_rate, val1: 1, min: 156000000, max: 320000000) |
524 | && pll_is_valid(val0: ref_rate, val1: 1, min: 1000000, max: 27000000))) |
525 | pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n" , |
526 | clk_hw_get_name(hw), |
527 | parent_rate, cco_rate, ref_rate); |
528 | |
529 | return rate; |
530 | } |
531 | |
532 | static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
533 | unsigned long parent_rate) |
534 | { |
535 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
536 | u32 val; |
537 | unsigned long new_rate; |
538 | |
539 | /* Validate PLL clock parameters computed on round rate stage */ |
540 | switch (clk->mode) { |
541 | case PLL_DIRECT: |
542 | val = PLL_CTRL_DIRECT; |
543 | val |= (clk->m_div - 1) << 1; |
544 | val |= (clk->n_div - 1) << 9; |
545 | new_rate = (parent_rate * clk->m_div) / clk->n_div; |
546 | break; |
547 | case PLL_BYPASS: |
548 | val = PLL_CTRL_BYPASS; |
549 | val |= (clk->p_div - 1) << 11; |
550 | new_rate = parent_rate / (1 << (clk->p_div)); |
551 | break; |
552 | case PLL_DIRECT_BYPASS: |
553 | val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS; |
554 | new_rate = parent_rate; |
555 | break; |
556 | case PLL_INTEGER: |
557 | val = PLL_CTRL_FEEDBACK; |
558 | val |= (clk->m_div - 1) << 1; |
559 | val |= (clk->n_div - 1) << 9; |
560 | val |= (clk->p_div - 1) << 11; |
561 | new_rate = (parent_rate * clk->m_div) / clk->n_div; |
562 | break; |
563 | case PLL_NON_INTEGER: |
564 | val = 0x0; |
565 | val |= (clk->m_div - 1) << 1; |
566 | val |= (clk->n_div - 1) << 9; |
567 | val |= (clk->p_div - 1) << 11; |
568 | new_rate = (parent_rate * clk->m_div) / |
569 | (clk->n_div * (1 << clk->p_div)); |
570 | break; |
571 | default: |
572 | return -EINVAL; |
573 | } |
574 | |
575 | /* Sanity check that round rate is equal to the requested one */ |
576 | if (new_rate != rate) |
577 | return -EINVAL; |
578 | |
579 | return regmap_update_bits(map: clk_regmap, reg: clk->reg, mask: 0x1FFFF, val); |
580 | } |
581 | |
582 | static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
583 | unsigned long *parent_rate) |
584 | { |
585 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
586 | u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6; |
587 | u64 m = 0, n = 0, p = 0; |
588 | int p_i, n_i; |
589 | |
590 | pr_debug("%s: %lu/%lu\n" , clk_hw_get_name(hw), *parent_rate, rate); |
591 | |
592 | if (rate > 266500000) |
593 | return -EINVAL; |
594 | |
595 | /* Have to check all 20 possibilities to find the minimal M */ |
596 | for (p_i = 4; p_i >= 0; p_i--) { |
597 | for (n_i = 4; n_i > 0; n_i--) { |
598 | m_i = div64_u64(dividend: o * n_i * (1 << p_i), divisor: i); |
599 | |
600 | /* Check for valid PLL parameter constraints */ |
601 | if (!(m_i && m_i <= 256 |
602 | && pll_is_valid(val0: i, val1: n_i, min: 1000000, max: 27000000) |
603 | && pll_is_valid(val0: i * m_i * (1 << p_i), val1: n_i, |
604 | min: 156000000, max: 320000000))) |
605 | continue; |
606 | |
607 | /* Store some intermediate valid parameters */ |
608 | if (o * n_i * (1 << p_i) - i * m_i <= d) { |
609 | m = m_i; |
610 | n = n_i; |
611 | p = p_i; |
612 | d = o * n_i * (1 << p_i) - i * m_i; |
613 | } |
614 | } |
615 | } |
616 | |
617 | if (d == (u64)rate << 6) { |
618 | pr_err("%s: %lu: no valid PLL parameters are found\n" , |
619 | clk_hw_get_name(hw), rate); |
620 | return -EINVAL; |
621 | } |
622 | |
623 | clk->m_div = m; |
624 | clk->n_div = n; |
625 | clk->p_div = p; |
626 | |
627 | /* Set only direct or non-integer mode of PLL */ |
628 | if (!p) |
629 | clk->mode = PLL_DIRECT; |
630 | else |
631 | clk->mode = PLL_NON_INTEGER; |
632 | |
633 | o = div64_u64(dividend: i * m, divisor: n * (1 << p)); |
634 | |
635 | if (!d) |
636 | pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n" , |
637 | clk_hw_get_name(hw), rate, m, n, p); |
638 | else |
639 | pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n" , |
640 | clk_hw_get_name(hw), rate, m, n, p, o); |
641 | |
642 | return o; |
643 | } |
644 | |
645 | static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
646 | unsigned long *parent_rate) |
647 | { |
648 | struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw); |
649 | struct clk_hw *usb_div_hw, *osc_hw; |
650 | u64 d_i, n_i, m, o; |
651 | |
652 | pr_debug("%s: %lu/%lu\n" , clk_hw_get_name(hw), *parent_rate, rate); |
653 | |
654 | /* |
655 | * The only supported USB clock is 48MHz, with PLL internal constraints |
656 | * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz |
657 | * and post-divider must be 4, this slightly simplifies calculation of |
658 | * USB divider, USB PLL N and M parameters. |
659 | */ |
660 | if (rate != 48000000) |
661 | return -EINVAL; |
662 | |
663 | /* USB divider clock */ |
664 | usb_div_hw = clk_hw_get_parent_by_index(hw, index: 0); |
665 | if (!usb_div_hw) |
666 | return -EINVAL; |
667 | |
668 | /* Main oscillator clock */ |
669 | osc_hw = clk_hw_get_parent_by_index(hw: usb_div_hw, index: 0); |
670 | if (!osc_hw) |
671 | return -EINVAL; |
672 | o = clk_hw_get_rate(hw: osc_hw); /* must be in range 1..20 MHz */ |
673 | |
674 | /* Check if valid USB divider and USB PLL parameters exists */ |
675 | for (d_i = 16; d_i >= 1; d_i--) { |
676 | for (n_i = 1; n_i <= 4; n_i++) { |
677 | m = div64_u64(dividend: 192000000 * d_i * n_i, divisor: o); |
678 | if (!(m && m <= 256 |
679 | && m * o == 192000000 * d_i * n_i |
680 | && pll_is_valid(val0: o, val1: d_i, min: 1000000, max: 20000000) |
681 | && pll_is_valid(val0: o, val1: d_i * n_i, min: 1000000, max: 27000000))) |
682 | continue; |
683 | |
684 | clk->n_div = n_i; |
685 | clk->m_div = m; |
686 | clk->p_div = 2; |
687 | clk->mode = PLL_NON_INTEGER; |
688 | *parent_rate = div64_u64(dividend: o, divisor: d_i); |
689 | |
690 | return rate; |
691 | } |
692 | } |
693 | |
694 | return -EINVAL; |
695 | } |
696 | |
697 | #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \ |
698 | static const struct clk_ops clk_ ##_name ## _ops = { \ |
699 | .enable = clk_pll_enable, \ |
700 | .disable = clk_pll_disable, \ |
701 | .is_enabled = clk_pll_is_enabled, \ |
702 | .recalc_rate = _rc, \ |
703 | .set_rate = _sr, \ |
704 | .round_rate = _rr, \ |
705 | } |
706 | |
707 | LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL); |
708 | LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate, |
709 | clk_pll_set_rate, clk_hclk_pll_round_rate); |
710 | LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate, |
711 | clk_pll_set_rate, clk_usb_pll_round_rate); |
712 | |
713 | static int clk_ddram_is_enabled(struct clk_hw *hw) |
714 | { |
715 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
716 | u32 val; |
717 | |
718 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
719 | val &= clk->enable_mask | clk->busy_mask; |
720 | |
721 | return (val == (BIT(7) | BIT(0)) || |
722 | val == (BIT(8) | BIT(1))); |
723 | } |
724 | |
725 | static int clk_ddram_enable(struct clk_hw *hw) |
726 | { |
727 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
728 | u32 val, hclk_div; |
729 | |
730 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
731 | hclk_div = val & clk->busy_mask; |
732 | |
733 | /* |
734 | * DDRAM clock must be 2 times higher than HCLK, |
735 | * this implies DDRAM clock can not be enabled, |
736 | * if HCLK clock rate is equal to ARM clock rate |
737 | */ |
738 | if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0))) |
739 | return -EINVAL; |
740 | |
741 | return regmap_update_bits(map: clk_regmap, reg: clk->reg, |
742 | mask: clk->enable_mask, val: hclk_div << 7); |
743 | } |
744 | |
745 | static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw, |
746 | unsigned long parent_rate) |
747 | { |
748 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
749 | u32 val; |
750 | |
751 | if (!clk_ddram_is_enabled(hw)) |
752 | return 0; |
753 | |
754 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
755 | val &= clk->enable_mask; |
756 | |
757 | return parent_rate / (val >> 7); |
758 | } |
759 | |
760 | static const struct clk_ops clk_ddram_ops = { |
761 | .enable = clk_ddram_enable, |
762 | .disable = clk_mask_disable, |
763 | .is_enabled = clk_ddram_is_enabled, |
764 | .recalc_rate = clk_ddram_recalc_rate, |
765 | }; |
766 | |
767 | static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw, |
768 | unsigned long parent_rate) |
769 | { |
770 | struct lpc32xx_clk *clk = to_lpc32xx_clk(hw); |
771 | u32 val, x, y; |
772 | |
773 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
774 | x = (val & 0xFF00) >> 8; |
775 | y = val & 0xFF; |
776 | |
777 | if (x && y) |
778 | return (parent_rate * x) / y; |
779 | else |
780 | return 0; |
781 | } |
782 | |
783 | static const struct clk_ops lpc32xx_uart_div_ops = { |
784 | .recalc_rate = lpc32xx_clk_uart_recalc_rate, |
785 | }; |
786 | |
787 | static const struct clk_div_table clk_hclk_div_table[] = { |
788 | { .val = 0, .div = 1 }, |
789 | { .val = 1, .div = 2 }, |
790 | { .val = 2, .div = 4 }, |
791 | { }, |
792 | }; |
793 | |
794 | static u32 test1_mux_table[] = { 0, 1, 2, }; |
795 | static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, }; |
796 | |
797 | static int clk_usb_enable(struct clk_hw *hw) |
798 | { |
799 | struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); |
800 | u32 val, ctrl_val, count; |
801 | |
802 | pr_debug("%s: 0x%x\n" , clk_hw_get_name(hw), clk->enable); |
803 | |
804 | if (clk->ctrl_mask) { |
805 | regmap_read(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, val: &ctrl_val); |
806 | regmap_update_bits(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, |
807 | mask: clk->ctrl_mask, val: clk->ctrl_enable); |
808 | } |
809 | |
810 | val = lpc32xx_usb_clk_read(clk); |
811 | if (clk->busy && (val & clk->busy) == clk->busy) { |
812 | if (clk->ctrl_mask) |
813 | regmap_write(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, |
814 | val: ctrl_val); |
815 | return -EBUSY; |
816 | } |
817 | |
818 | val |= clk->enable; |
819 | lpc32xx_usb_clk_write(clk, val); |
820 | |
821 | for (count = 0; count < 1000; count++) { |
822 | val = lpc32xx_usb_clk_read(clk); |
823 | if ((val & clk->enable) == clk->enable) |
824 | break; |
825 | } |
826 | |
827 | if ((val & clk->enable) == clk->enable) |
828 | return 0; |
829 | |
830 | if (clk->ctrl_mask) |
831 | regmap_write(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, val: ctrl_val); |
832 | |
833 | return -ETIMEDOUT; |
834 | } |
835 | |
836 | static void clk_usb_disable(struct clk_hw *hw) |
837 | { |
838 | struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); |
839 | u32 val = lpc32xx_usb_clk_read(clk); |
840 | |
841 | val &= ~clk->enable; |
842 | lpc32xx_usb_clk_write(clk, val); |
843 | |
844 | if (clk->ctrl_mask) |
845 | regmap_update_bits(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, |
846 | mask: clk->ctrl_mask, val: clk->ctrl_disable); |
847 | } |
848 | |
849 | static int clk_usb_is_enabled(struct clk_hw *hw) |
850 | { |
851 | struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw); |
852 | u32 ctrl_val, val; |
853 | |
854 | if (clk->ctrl_mask) { |
855 | regmap_read(map: clk_regmap, LPC32XX_CLKPWR_USB_CTRL, val: &ctrl_val); |
856 | if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable) |
857 | return 0; |
858 | } |
859 | |
860 | val = lpc32xx_usb_clk_read(clk); |
861 | |
862 | return ((val & clk->enable) == clk->enable); |
863 | } |
864 | |
865 | static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw, |
866 | unsigned long parent_rate) |
867 | { |
868 | return clk_get_rate(clk: clk[LPC32XX_CLK_PERIPH]); |
869 | } |
870 | |
871 | static const struct clk_ops clk_usb_ops = { |
872 | .enable = clk_usb_enable, |
873 | .disable = clk_usb_disable, |
874 | .is_enabled = clk_usb_is_enabled, |
875 | }; |
876 | |
877 | static const struct clk_ops clk_usb_i2c_ops = { |
878 | .enable = clk_usb_enable, |
879 | .disable = clk_usb_disable, |
880 | .is_enabled = clk_usb_is_enabled, |
881 | .recalc_rate = clk_usb_i2c_recalc_rate, |
882 | }; |
883 | |
884 | static int lpc32xx_clk_gate_enable(struct clk_hw *hw) |
885 | { |
886 | struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); |
887 | u32 mask = BIT(clk->bit_idx); |
888 | u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask); |
889 | |
890 | return regmap_update_bits(map: clk_regmap, reg: clk->reg, mask, val); |
891 | } |
892 | |
893 | static void lpc32xx_clk_gate_disable(struct clk_hw *hw) |
894 | { |
895 | struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); |
896 | u32 mask = BIT(clk->bit_idx); |
897 | u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0); |
898 | |
899 | regmap_update_bits(map: clk_regmap, reg: clk->reg, mask, val); |
900 | } |
901 | |
902 | static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw) |
903 | { |
904 | struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw); |
905 | u32 val; |
906 | bool is_set; |
907 | |
908 | regmap_read(map: clk_regmap, reg: clk->reg, val: &val); |
909 | is_set = val & BIT(clk->bit_idx); |
910 | |
911 | return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set); |
912 | } |
913 | |
914 | static const struct clk_ops lpc32xx_clk_gate_ops = { |
915 | .enable = lpc32xx_clk_gate_enable, |
916 | .disable = lpc32xx_clk_gate_disable, |
917 | .is_enabled = lpc32xx_clk_gate_is_enabled, |
918 | }; |
919 | |
920 | #define div_mask(width) ((1 << (width)) - 1) |
921 | |
922 | static unsigned int _get_table_div(const struct clk_div_table *table, |
923 | unsigned int val) |
924 | { |
925 | const struct clk_div_table *clkt; |
926 | |
927 | for (clkt = table; clkt->div; clkt++) |
928 | if (clkt->val == val) |
929 | return clkt->div; |
930 | return 0; |
931 | } |
932 | |
933 | static unsigned int _get_div(const struct clk_div_table *table, |
934 | unsigned int val, unsigned long flags, u8 width) |
935 | { |
936 | if (flags & CLK_DIVIDER_ONE_BASED) |
937 | return val; |
938 | if (table) |
939 | return _get_table_div(table, val); |
940 | return val + 1; |
941 | } |
942 | |
943 | static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, |
944 | unsigned long parent_rate) |
945 | { |
946 | struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); |
947 | unsigned int val; |
948 | |
949 | regmap_read(map: clk_regmap, reg: divider->reg, val: &val); |
950 | |
951 | val >>= divider->shift; |
952 | val &= div_mask(divider->width); |
953 | |
954 | return divider_recalc_rate(hw, parent_rate, val, table: divider->table, |
955 | flags: divider->flags, width: divider->width); |
956 | } |
957 | |
958 | static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, |
959 | unsigned long *prate) |
960 | { |
961 | struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); |
962 | unsigned int bestdiv; |
963 | |
964 | /* if read only, just return current value */ |
965 | if (divider->flags & CLK_DIVIDER_READ_ONLY) { |
966 | regmap_read(map: clk_regmap, reg: divider->reg, val: &bestdiv); |
967 | bestdiv >>= divider->shift; |
968 | bestdiv &= div_mask(divider->width); |
969 | bestdiv = _get_div(table: divider->table, val: bestdiv, flags: divider->flags, |
970 | width: divider->width); |
971 | return DIV_ROUND_UP(*prate, bestdiv); |
972 | } |
973 | |
974 | return divider_round_rate(hw, rate, prate, table: divider->table, |
975 | width: divider->width, flags: divider->flags); |
976 | } |
977 | |
978 | static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
979 | unsigned long parent_rate) |
980 | { |
981 | struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw); |
982 | unsigned int value; |
983 | |
984 | value = divider_get_val(rate, parent_rate, table: divider->table, |
985 | width: divider->width, flags: divider->flags); |
986 | |
987 | return regmap_update_bits(map: clk_regmap, reg: divider->reg, |
988 | div_mask(divider->width) << divider->shift, |
989 | val: value << divider->shift); |
990 | } |
991 | |
992 | static const struct clk_ops lpc32xx_clk_divider_ops = { |
993 | .recalc_rate = clk_divider_recalc_rate, |
994 | .round_rate = clk_divider_round_rate, |
995 | .set_rate = clk_divider_set_rate, |
996 | }; |
997 | |
998 | static u8 clk_mux_get_parent(struct clk_hw *hw) |
999 | { |
1000 | struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw); |
1001 | u32 num_parents = clk_hw_get_num_parents(hw); |
1002 | u32 val; |
1003 | |
1004 | regmap_read(map: clk_regmap, reg: mux->reg, val: &val); |
1005 | val >>= mux->shift; |
1006 | val &= mux->mask; |
1007 | |
1008 | if (mux->table) { |
1009 | u32 i; |
1010 | |
1011 | for (i = 0; i < num_parents; i++) |
1012 | if (mux->table[i] == val) |
1013 | return i; |
1014 | return -EINVAL; |
1015 | } |
1016 | |
1017 | if (val >= num_parents) |
1018 | return -EINVAL; |
1019 | |
1020 | return val; |
1021 | } |
1022 | |
1023 | static int clk_mux_set_parent(struct clk_hw *hw, u8 index) |
1024 | { |
1025 | struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw); |
1026 | |
1027 | if (mux->table) |
1028 | index = mux->table[index]; |
1029 | |
1030 | return regmap_update_bits(map: clk_regmap, reg: mux->reg, |
1031 | mask: mux->mask << mux->shift, val: index << mux->shift); |
1032 | } |
1033 | |
1034 | static const struct clk_ops lpc32xx_clk_mux_ro_ops = { |
1035 | .get_parent = clk_mux_get_parent, |
1036 | }; |
1037 | |
1038 | static const struct clk_ops lpc32xx_clk_mux_ops = { |
1039 | .get_parent = clk_mux_get_parent, |
1040 | .set_parent = clk_mux_set_parent, |
1041 | .determine_rate = __clk_mux_determine_rate, |
1042 | }; |
1043 | |
1044 | enum lpc32xx_clk_type { |
1045 | CLK_FIXED, |
1046 | CLK_MUX, |
1047 | CLK_DIV, |
1048 | CLK_GATE, |
1049 | CLK_COMPOSITE, |
1050 | CLK_LPC32XX, |
1051 | CLK_LPC32XX_PLL, |
1052 | CLK_LPC32XX_USB, |
1053 | }; |
1054 | |
1055 | struct clk_hw_proto0 { |
1056 | const struct clk_ops *ops; |
1057 | union { |
1058 | struct lpc32xx_pll_clk pll; |
1059 | struct lpc32xx_clk clk; |
1060 | struct lpc32xx_usb_clk usb_clk; |
1061 | struct lpc32xx_clk_mux mux; |
1062 | struct lpc32xx_clk_div div; |
1063 | struct lpc32xx_clk_gate gate; |
1064 | }; |
1065 | }; |
1066 | |
1067 | struct clk_hw_proto1 { |
1068 | struct clk_hw_proto0 *mux; |
1069 | struct clk_hw_proto0 *div; |
1070 | struct clk_hw_proto0 *gate; |
1071 | }; |
1072 | |
1073 | struct clk_hw_proto { |
1074 | enum lpc32xx_clk_type type; |
1075 | |
1076 | union { |
1077 | struct clk_fixed_rate f; |
1078 | struct clk_hw_proto0 hw0; |
1079 | struct clk_hw_proto1 hw1; |
1080 | }; |
1081 | }; |
1082 | |
1083 | #define LPC32XX_DEFINE_FIXED(_idx, _rate) \ |
1084 | [CLK_PREFIX(_idx)] = { \ |
1085 | .type = CLK_FIXED, \ |
1086 | { \ |
1087 | .f = { \ |
1088 | .fixed_rate = (_rate), \ |
1089 | }, \ |
1090 | }, \ |
1091 | } |
1092 | |
1093 | #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \ |
1094 | [CLK_PREFIX(_idx)] = { \ |
1095 | .type = CLK_LPC32XX_PLL, \ |
1096 | { \ |
1097 | .hw0 = { \ |
1098 | .ops = &clk_ ##_name ## _ops, \ |
1099 | { \ |
1100 | .pll = { \ |
1101 | .reg = LPC32XX_CLKPWR_ ## _reg, \ |
1102 | .enable = (_enable), \ |
1103 | }, \ |
1104 | }, \ |
1105 | }, \ |
1106 | }, \ |
1107 | } |
1108 | |
1109 | #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \ |
1110 | [CLK_PREFIX(_idx)] = { \ |
1111 | .type = CLK_MUX, \ |
1112 | { \ |
1113 | .hw0 = { \ |
1114 | .ops = (_flags & CLK_MUX_READ_ONLY ? \ |
1115 | &lpc32xx_clk_mux_ro_ops : \ |
1116 | &lpc32xx_clk_mux_ops), \ |
1117 | { \ |
1118 | .mux = { \ |
1119 | .reg = LPC32XX_CLKPWR_ ## _reg, \ |
1120 | .mask = (_mask), \ |
1121 | .shift = (_shift), \ |
1122 | .table = (_table), \ |
1123 | .flags = (_flags), \ |
1124 | }, \ |
1125 | }, \ |
1126 | }, \ |
1127 | }, \ |
1128 | } |
1129 | |
1130 | #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \ |
1131 | [CLK_PREFIX(_idx)] = { \ |
1132 | .type = CLK_DIV, \ |
1133 | { \ |
1134 | .hw0 = { \ |
1135 | .ops = &lpc32xx_clk_divider_ops, \ |
1136 | { \ |
1137 | .div = { \ |
1138 | .reg = LPC32XX_CLKPWR_ ## _reg, \ |
1139 | .shift = (_shift), \ |
1140 | .width = (_width), \ |
1141 | .table = (_table), \ |
1142 | .flags = (_flags), \ |
1143 | }, \ |
1144 | }, \ |
1145 | }, \ |
1146 | }, \ |
1147 | } |
1148 | |
1149 | #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \ |
1150 | [CLK_PREFIX(_idx)] = { \ |
1151 | .type = CLK_GATE, \ |
1152 | { \ |
1153 | .hw0 = { \ |
1154 | .ops = &lpc32xx_clk_gate_ops, \ |
1155 | { \ |
1156 | .gate = { \ |
1157 | .reg = LPC32XX_CLKPWR_ ## _reg, \ |
1158 | .bit_idx = (_bit), \ |
1159 | .flags = (_flags), \ |
1160 | }, \ |
1161 | }, \ |
1162 | }, \ |
1163 | }, \ |
1164 | } |
1165 | |
1166 | #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \ |
1167 | [CLK_PREFIX(_idx)] = { \ |
1168 | .type = CLK_LPC32XX, \ |
1169 | { \ |
1170 | .hw0 = { \ |
1171 | .ops = &(_ops), \ |
1172 | { \ |
1173 | .clk = { \ |
1174 | .reg = LPC32XX_CLKPWR_ ## _reg, \ |
1175 | .enable = (_e), \ |
1176 | .enable_mask = (_em), \ |
1177 | .disable = (_d), \ |
1178 | .disable_mask = (_dm), \ |
1179 | .busy = (_b), \ |
1180 | .busy_mask = (_bm), \ |
1181 | }, \ |
1182 | }, \ |
1183 | }, \ |
1184 | }, \ |
1185 | } |
1186 | |
1187 | #define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \ |
1188 | [CLK_PREFIX(_idx)] = { \ |
1189 | .type = CLK_LPC32XX_USB, \ |
1190 | { \ |
1191 | .hw0 = { \ |
1192 | .ops = &(_ops), \ |
1193 | { \ |
1194 | .usb_clk = { \ |
1195 | .ctrl_enable = (_ce), \ |
1196 | .ctrl_disable = (_cd), \ |
1197 | .ctrl_mask = (_cm), \ |
1198 | .enable = (_e), \ |
1199 | .busy = (_b), \ |
1200 | } \ |
1201 | }, \ |
1202 | } \ |
1203 | }, \ |
1204 | } |
1205 | |
1206 | #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \ |
1207 | [CLK_PREFIX(_idx)] = { \ |
1208 | .type = CLK_COMPOSITE, \ |
1209 | { \ |
1210 | .hw1 = { \ |
1211 | .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \ |
1212 | &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \ |
1213 | .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \ |
1214 | &clk_hw_proto[CLK_PREFIX(_div)].hw0), \ |
1215 | .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\ |
1216 | &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \ |
1217 | }, \ |
1218 | }, \ |
1219 | } |
1220 | |
1221 | static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = { |
1222 | LPC32XX_DEFINE_FIXED(RTC, 32768), |
1223 | LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)), |
1224 | LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE), |
1225 | LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE), |
1226 | LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE), |
1227 | LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0), |
1228 | |
1229 | LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL, |
1230 | CLK_DIVIDER_READ_ONLY), |
1231 | LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table, |
1232 | CLK_DIVIDER_READ_ONLY), |
1233 | |
1234 | /* Register 3 read-only muxes with a single control PWR_CTRL[2] */ |
1235 | LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL, |
1236 | CLK_MUX_READ_ONLY), |
1237 | LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL, |
1238 | CLK_MUX_READ_ONLY), |
1239 | LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL, |
1240 | CLK_MUX_READ_ONLY), |
1241 | /* Register 2 read-only muxes with a single control PWR_CTRL[10] */ |
1242 | LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL, |
1243 | CLK_MUX_READ_ONLY), |
1244 | LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL, |
1245 | CLK_MUX_READ_ONLY), |
1246 | |
1247 | /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */ |
1248 | LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), |
1249 | LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), |
1250 | LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE), |
1251 | |
1252 | LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0), |
1253 | LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0), |
1254 | LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7), |
1255 | 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops), |
1256 | |
1257 | LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0), |
1258 | LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0), |
1259 | LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0), |
1260 | LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0), |
1261 | LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0), |
1262 | LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0), |
1263 | |
1264 | LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0), |
1265 | LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0), |
1266 | LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0), |
1267 | LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0), |
1268 | LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0), |
1269 | LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0), |
1270 | LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0), |
1271 | LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0), |
1272 | LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0), |
1273 | LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0), |
1274 | |
1275 | LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0), |
1276 | LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0), |
1277 | |
1278 | LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0), |
1279 | LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL, |
1280 | CLK_DIVIDER_ONE_BASED), |
1281 | LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0), |
1282 | LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE), |
1283 | |
1284 | LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0), |
1285 | LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL, |
1286 | CLK_DIVIDER_ONE_BASED), |
1287 | LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0), |
1288 | LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE), |
1289 | |
1290 | LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0), |
1291 | LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL, |
1292 | 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), |
1293 | LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0), |
1294 | LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE), |
1295 | |
1296 | LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0), |
1297 | LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL, |
1298 | 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), |
1299 | LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0), |
1300 | LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE), |
1301 | |
1302 | LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0), |
1303 | LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL, |
1304 | 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), |
1305 | LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0), |
1306 | LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE), |
1307 | |
1308 | LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0), |
1309 | LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL, |
1310 | 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), |
1311 | LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0), |
1312 | LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE), |
1313 | |
1314 | LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL, |
1315 | 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops), |
1316 | |
1317 | LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3, |
1318 | test1_mux_table, 0), |
1319 | LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0), |
1320 | LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE), |
1321 | |
1322 | LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7, |
1323 | test2_mux_table, 0), |
1324 | LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0), |
1325 | LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE), |
1326 | |
1327 | LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY), |
1328 | |
1329 | LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0), |
1330 | LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0), |
1331 | LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE), |
1332 | |
1333 | LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED), |
1334 | LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9), |
1335 | 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops), |
1336 | LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE), |
1337 | |
1338 | LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0), |
1339 | LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0), |
1340 | LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE), |
1341 | |
1342 | LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL, |
1343 | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), |
1344 | BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0), |
1345 | 0x0, 0x0, clk_mask_ops), |
1346 | LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL, |
1347 | BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0, |
1348 | BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops), |
1349 | LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL, |
1350 | BIT(1), BIT(2) | BIT(1), 0x0, BIT(1), |
1351 | BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops), |
1352 | /* |
1353 | * ADC/TS clock unfortunately cannot be registered as a composite one |
1354 | * due to a different connection of gate, div and mux, e.g. gating it |
1355 | * won't mean that the clock is off, if peripheral clock is its parent: |
1356 | * |
1357 | * rtc-->[gate]-->| | |
1358 | * | mux |--> adc/ts |
1359 | * pclk-->[div]-->| | |
1360 | * |
1361 | * Constraints: |
1362 | * ADC --- resulting clock must be <= 4.5 MHz |
1363 | * TS --- resulting clock must be <= 400 KHz |
1364 | */ |
1365 | LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0), |
1366 | LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0), |
1367 | LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0), |
1368 | |
1369 | /* USB controller clocks */ |
1370 | LPC32XX_DEFINE_USB(USB_AHB, |
1371 | BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops), |
1372 | LPC32XX_DEFINE_USB(USB_OTG, |
1373 | 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops), |
1374 | LPC32XX_DEFINE_USB(USB_I2C, |
1375 | 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops), |
1376 | LPC32XX_DEFINE_USB(USB_DEV, |
1377 | BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops), |
1378 | LPC32XX_DEFINE_USB(USB_HOST, |
1379 | BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops), |
1380 | }; |
1381 | |
1382 | static struct clk * __init lpc32xx_clk_register(u32 id) |
1383 | { |
1384 | const struct clk_proto_t *lpc32xx_clk = &clk_proto[id]; |
1385 | struct clk_hw_proto *clk_hw = &clk_hw_proto[id]; |
1386 | const char *parents[LPC32XX_CLK_PARENTS_MAX]; |
1387 | struct clk *clk; |
1388 | unsigned int i; |
1389 | |
1390 | for (i = 0; i < lpc32xx_clk->num_parents; i++) |
1391 | parents[i] = clk_proto[lpc32xx_clk->parents[i]].name; |
1392 | |
1393 | pr_debug("%s: derived from '%s', clock type %d\n" , lpc32xx_clk->name, |
1394 | parents[0], clk_hw->type); |
1395 | |
1396 | switch (clk_hw->type) { |
1397 | case CLK_LPC32XX: |
1398 | case CLK_LPC32XX_PLL: |
1399 | case CLK_LPC32XX_USB: |
1400 | case CLK_MUX: |
1401 | case CLK_DIV: |
1402 | case CLK_GATE: |
1403 | { |
1404 | struct clk_init_data clk_init = { |
1405 | .name = lpc32xx_clk->name, |
1406 | .parent_names = parents, |
1407 | .num_parents = lpc32xx_clk->num_parents, |
1408 | .flags = lpc32xx_clk->flags, |
1409 | .ops = clk_hw->hw0.ops, |
1410 | }; |
1411 | struct clk_hw *hw; |
1412 | |
1413 | if (clk_hw->type == CLK_LPC32XX) |
1414 | hw = &clk_hw->hw0.clk.hw; |
1415 | else if (clk_hw->type == CLK_LPC32XX_PLL) |
1416 | hw = &clk_hw->hw0.pll.hw; |
1417 | else if (clk_hw->type == CLK_LPC32XX_USB) |
1418 | hw = &clk_hw->hw0.usb_clk.hw; |
1419 | else if (clk_hw->type == CLK_MUX) |
1420 | hw = &clk_hw->hw0.mux.hw; |
1421 | else if (clk_hw->type == CLK_DIV) |
1422 | hw = &clk_hw->hw0.div.hw; |
1423 | else if (clk_hw->type == CLK_GATE) |
1424 | hw = &clk_hw->hw0.gate.hw; |
1425 | else |
1426 | return ERR_PTR(error: -EINVAL); |
1427 | |
1428 | hw->init = &clk_init; |
1429 | clk = clk_register(NULL, hw); |
1430 | break; |
1431 | } |
1432 | case CLK_COMPOSITE: |
1433 | { |
1434 | struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL; |
1435 | const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL; |
1436 | struct clk_hw_proto0 *mux0, *div0, *gate0; |
1437 | |
1438 | mux0 = clk_hw->hw1.mux; |
1439 | div0 = clk_hw->hw1.div; |
1440 | gate0 = clk_hw->hw1.gate; |
1441 | if (mux0) { |
1442 | mops = mux0->ops; |
1443 | mux_hw = &mux0->clk.hw; |
1444 | } |
1445 | if (div0) { |
1446 | dops = div0->ops; |
1447 | div_hw = &div0->clk.hw; |
1448 | } |
1449 | if (gate0) { |
1450 | gops = gate0->ops; |
1451 | gate_hw = &gate0->clk.hw; |
1452 | } |
1453 | |
1454 | clk = clk_register_composite(NULL, name: lpc32xx_clk->name, |
1455 | parent_names: parents, num_parents: lpc32xx_clk->num_parents, |
1456 | mux_hw, mux_ops: mops, rate_hw: div_hw, rate_ops: dops, |
1457 | gate_hw, gate_ops: gops, flags: lpc32xx_clk->flags); |
1458 | break; |
1459 | } |
1460 | case CLK_FIXED: |
1461 | { |
1462 | struct clk_fixed_rate *fixed = &clk_hw->f; |
1463 | |
1464 | clk = clk_register_fixed_rate(NULL, name: lpc32xx_clk->name, |
1465 | parent_name: parents[0], flags: 0, fixed_rate: fixed->fixed_rate); |
1466 | break; |
1467 | } |
1468 | default: |
1469 | clk = ERR_PTR(error: -EINVAL); |
1470 | } |
1471 | |
1472 | return clk; |
1473 | } |
1474 | |
1475 | static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate) |
1476 | { |
1477 | u32 val; |
1478 | |
1479 | regmap_read(map: clk_regmap, reg, val: &val); |
1480 | |
1481 | if (!(val & div_mask)) { |
1482 | val &= ~gate; |
1483 | val |= BIT(__ffs(div_mask)); |
1484 | } |
1485 | |
1486 | regmap_update_bits(map: clk_regmap, reg, mask: gate | div_mask, val); |
1487 | } |
1488 | |
1489 | static void __init lpc32xx_clk_init(struct device_node *np) |
1490 | { |
1491 | unsigned int i; |
1492 | struct clk *clk_osc, *clk_32k; |
1493 | void __iomem *base = NULL; |
1494 | |
1495 | /* Ensure that parent clocks are available and valid */ |
1496 | clk_32k = of_clk_get_by_name(np, name: clk_proto[LPC32XX_CLK_XTAL_32K].name); |
1497 | if (IS_ERR(ptr: clk_32k)) { |
1498 | pr_err("failed to find external 32KHz clock: %ld\n" , |
1499 | PTR_ERR(clk_32k)); |
1500 | return; |
1501 | } |
1502 | if (clk_get_rate(clk: clk_32k) != 32768) { |
1503 | pr_err("invalid clock rate of external 32KHz oscillator\n" ); |
1504 | return; |
1505 | } |
1506 | |
1507 | clk_osc = of_clk_get_by_name(np, name: clk_proto[LPC32XX_CLK_XTAL].name); |
1508 | if (IS_ERR(ptr: clk_osc)) { |
1509 | pr_err("failed to find external main oscillator clock: %ld\n" , |
1510 | PTR_ERR(clk_osc)); |
1511 | return; |
1512 | } |
1513 | |
1514 | base = of_iomap(node: np, index: 0); |
1515 | if (!base) { |
1516 | pr_err("failed to map system control block registers\n" ); |
1517 | return; |
1518 | } |
1519 | |
1520 | clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config); |
1521 | if (IS_ERR(ptr: clk_regmap)) { |
1522 | pr_err("failed to regmap system control block: %ld\n" , |
1523 | PTR_ERR(clk_regmap)); |
1524 | iounmap(addr: base); |
1525 | return; |
1526 | } |
1527 | |
1528 | /* |
1529 | * Divider part of PWM and MS clocks requires a quirk to avoid |
1530 | * a misinterpretation of formally valid zero value in register |
1531 | * bitfield, which indicates another clock gate. Instead of |
1532 | * adding complexity to a gate clock ensure that zero value in |
1533 | * divider clock is never met in runtime. |
1534 | */ |
1535 | lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, div_mask: 0xf0, BIT(0)); |
1536 | lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, div_mask: 0xf00, BIT(2)); |
1537 | lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, div_mask: 0xf, BIT(5) | BIT(9)); |
1538 | |
1539 | for (i = 1; i < LPC32XX_CLK_MAX; i++) { |
1540 | clk[i] = lpc32xx_clk_register(id: i); |
1541 | if (IS_ERR(ptr: clk[i])) { |
1542 | pr_err("failed to register %s clock: %ld\n" , |
1543 | clk_proto[i].name, PTR_ERR(clk[i])); |
1544 | clk[i] = NULL; |
1545 | } |
1546 | } |
1547 | |
1548 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &clk_data); |
1549 | |
1550 | /* Set 48MHz rate of USB PLL clock */ |
1551 | clk_set_rate(clk: clk[LPC32XX_CLK_USB_PLL], rate: 48000000); |
1552 | |
1553 | /* These two clocks must be always on independently on consumers */ |
1554 | clk_prepare_enable(clk: clk[LPC32XX_CLK_ARM]); |
1555 | clk_prepare_enable(clk: clk[LPC32XX_CLK_HCLK]); |
1556 | |
1557 | /* Enable ARM VFP by default */ |
1558 | clk_prepare_enable(clk: clk[LPC32XX_CLK_ARM_VFP]); |
1559 | |
1560 | /* Disable enabled by default clocks for NAND MLC and SLC */ |
1561 | clk_mask_disable(hw: &clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw); |
1562 | clk_mask_disable(hw: &clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw); |
1563 | } |
1564 | CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk" , lpc32xx_clk_init); |
1565 | |
1566 | static void __init lpc32xx_usb_clk_init(struct device_node *np) |
1567 | { |
1568 | unsigned int i; |
1569 | |
1570 | usb_clk_vbase = of_iomap(node: np, index: 0); |
1571 | if (!usb_clk_vbase) { |
1572 | pr_err("failed to map address range\n" ); |
1573 | return; |
1574 | } |
1575 | |
1576 | for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) { |
1577 | usb_clk[i] = lpc32xx_clk_register(id: i + LPC32XX_CLK_USB_OFFSET); |
1578 | if (IS_ERR(ptr: usb_clk[i])) { |
1579 | pr_err("failed to register %s clock: %ld\n" , |
1580 | clk_proto[i].name, PTR_ERR(usb_clk[i])); |
1581 | usb_clk[i] = NULL; |
1582 | } |
1583 | } |
1584 | |
1585 | of_clk_add_provider(np, clk_src_get: of_clk_src_onecell_get, data: &usb_clk_data); |
1586 | } |
1587 | CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk" , lpc32xx_usb_clk_init); |
1588 | |