1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>
9#include <linux/pm_runtime.h>
10#include <linux/regmap.h>
11#include <linux/reset-controller.h>
12
13#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
14
15#include "clk-alpha-pll.h"
16#include "clk-branch.h"
17#include "clk-rcg.h"
18#include "clk-regmap-divider.h"
19#include "common.h"
20#include "gdsc.h"
21#include "reset.h"
22
23enum {
24 P_BI_TCXO,
25 P_DISP_CC_PLL0_OUT_MAIN,
26 P_DISP_CC_PLL1_OUT_EVEN,
27 P_DISP_CC_PLL1_OUT_MAIN,
28 P_DP_PHY_PLL_LINK_CLK,
29 P_DP_PHY_PLL_VCO_DIV_CLK,
30 P_DPTX1_PHY_PLL_LINK_CLK,
31 P_DPTX1_PHY_PLL_VCO_DIV_CLK,
32 P_DPTX2_PHY_PLL_LINK_CLK,
33 P_DPTX2_PHY_PLL_VCO_DIV_CLK,
34 P_EDP_PHY_PLL_LINK_CLK,
35 P_EDP_PHY_PLL_VCO_DIV_CLK,
36 P_DSI0_PHY_PLL_OUT_BYTECLK,
37 P_DSI0_PHY_PLL_OUT_DSICLK,
38 P_DSI1_PHY_PLL_OUT_BYTECLK,
39 P_DSI1_PHY_PLL_OUT_DSICLK,
40};
41
42static const struct pll_vco vco_table[] = {
43 { 249600000, 2000000000, 0 },
44};
45
46static const struct pll_vco lucid_5lpe_vco[] = {
47 { 249600000, 1750000000, 0 },
48};
49
50static struct alpha_pll_config disp_cc_pll0_config = {
51 .l = 0x47,
52 .alpha = 0xE000,
53 .config_ctl_val = 0x20485699,
54 .config_ctl_hi_val = 0x00002261,
55 .config_ctl_hi1_val = 0x329A699C,
56 .user_ctl_val = 0x00000000,
57 .user_ctl_hi_val = 0x00000805,
58 .user_ctl_hi1_val = 0x00000000,
59};
60
61static struct clk_init_data disp_cc_pll0_init = {
62 .name = "disp_cc_pll0",
63 .parent_data = &(const struct clk_parent_data){
64 .fw_name = "bi_tcxo",
65 },
66 .num_parents = 1,
67 .ops = &clk_alpha_pll_lucid_ops,
68};
69
70static struct clk_alpha_pll disp_cc_pll0 = {
71 .offset = 0x0,
72 .vco_table = vco_table,
73 .num_vco = ARRAY_SIZE(vco_table),
74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
75 .clkr.hw.init = &disp_cc_pll0_init
76};
77
78static struct alpha_pll_config disp_cc_pll1_config = {
79 .l = 0x1F,
80 .alpha = 0x4000,
81 .config_ctl_val = 0x20485699,
82 .config_ctl_hi_val = 0x00002261,
83 .config_ctl_hi1_val = 0x329A699C,
84 .user_ctl_val = 0x00000000,
85 .user_ctl_hi_val = 0x00000805,
86 .user_ctl_hi1_val = 0x00000000,
87};
88
89static struct clk_init_data disp_cc_pll1_init = {
90 .name = "disp_cc_pll1",
91 .parent_data = &(const struct clk_parent_data){
92 .fw_name = "bi_tcxo",
93 },
94 .num_parents = 1,
95 .ops = &clk_alpha_pll_lucid_ops,
96};
97
98static struct clk_alpha_pll disp_cc_pll1 = {
99 .offset = 0x1000,
100 .vco_table = vco_table,
101 .num_vco = ARRAY_SIZE(vco_table),
102 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103 .clkr.hw.init = &disp_cc_pll1_init
104};
105
106static const struct parent_map disp_cc_parent_map_0[] = {
107 { P_BI_TCXO, 0 },
108 { P_DP_PHY_PLL_LINK_CLK, 1 },
109 { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
110 { P_DPTX1_PHY_PLL_LINK_CLK, 3 },
111 { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
112 { P_DPTX2_PHY_PLL_LINK_CLK, 5 },
113 { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
114};
115
116static const struct clk_parent_data disp_cc_parent_data_0[] = {
117 { .fw_name = "bi_tcxo" },
118 { .fw_name = "dp_phy_pll_link_clk" },
119 { .fw_name = "dp_phy_pll_vco_div_clk" },
120 { .fw_name = "dptx1_phy_pll_link_clk" },
121 { .fw_name = "dptx1_phy_pll_vco_div_clk" },
122 { .fw_name = "dptx2_phy_pll_link_clk" },
123 { .fw_name = "dptx2_phy_pll_vco_div_clk" },
124};
125
126static const struct parent_map disp_cc_parent_map_1[] = {
127 { P_BI_TCXO, 0 },
128};
129
130static const struct clk_parent_data disp_cc_parent_data_1[] = {
131 { .fw_name = "bi_tcxo" },
132};
133
134static const struct parent_map disp_cc_parent_map_2[] = {
135 { P_BI_TCXO, 0 },
136 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
137 { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
138};
139
140static const struct clk_parent_data disp_cc_parent_data_2[] = {
141 { .fw_name = "bi_tcxo" },
142 { .fw_name = "dsi0_phy_pll_out_byteclk" },
143 { .fw_name = "dsi1_phy_pll_out_byteclk" },
144};
145
146static const struct parent_map disp_cc_parent_map_3[] = {
147 { P_BI_TCXO, 0 },
148 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
149};
150
151static const struct clk_parent_data disp_cc_parent_data_3[] = {
152 { .fw_name = "bi_tcxo" },
153 { .hw = &disp_cc_pll1.clkr.hw },
154};
155
156static const struct parent_map disp_cc_parent_map_4[] = {
157 { P_BI_TCXO, 0 },
158 { P_EDP_PHY_PLL_LINK_CLK, 1 },
159 { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
160};
161
162static const struct clk_parent_data disp_cc_parent_data_4[] = {
163 { .fw_name = "bi_tcxo" },
164 { .fw_name = "edp_phy_pll_link_clk" },
165 { .fw_name = "edp_phy_pll_vco_div_clk" },
166};
167
168static const struct parent_map disp_cc_parent_map_5[] = {
169 { P_BI_TCXO, 0 },
170 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
171 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
172};
173
174static const struct clk_parent_data disp_cc_parent_data_5[] = {
175 { .fw_name = "bi_tcxo" },
176 { .hw = &disp_cc_pll0.clkr.hw },
177 { .hw = &disp_cc_pll1.clkr.hw },
178};
179
180static const struct parent_map disp_cc_parent_map_6[] = {
181 { P_BI_TCXO, 0 },
182 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
183 { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
184};
185
186static const struct clk_parent_data disp_cc_parent_data_6[] = {
187 { .fw_name = "bi_tcxo" },
188 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
189 { .fw_name = "dsi1_phy_pll_out_dsiclk" },
190};
191
192static const struct parent_map disp_cc_parent_map_7[] = {
193 { P_BI_TCXO, 0 },
194 { P_DISP_CC_PLL1_OUT_MAIN, 4 },
195 /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
196};
197
198static const struct clk_parent_data disp_cc_parent_data_7[] = {
199 { .fw_name = "bi_tcxo" },
200 { .hw = &disp_cc_pll1.clkr.hw },
201 /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
202};
203
204static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
205 F(19200000, P_BI_TCXO, 1, 0, 0),
206 F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
207 F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
208 { }
209};
210
211static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
212 .cmd_rcgr = 0x22bc,
213 .mnd_width = 0,
214 .hid_width = 5,
215 .parent_map = disp_cc_parent_map_3,
216 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
217 .clkr.hw.init = &(const struct clk_init_data) {
218 .name = "disp_cc_mdss_ahb_clk_src",
219 .parent_data = disp_cc_parent_data_3,
220 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
221 .flags = CLK_SET_RATE_PARENT,
222 .ops = &clk_rcg2_shared_ops,
223 },
224};
225
226static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
227 F(19200000, P_BI_TCXO, 1, 0, 0),
228 { }
229};
230
231static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
232 .cmd_rcgr = 0x2110,
233 .mnd_width = 0,
234 .hid_width = 5,
235 .parent_map = disp_cc_parent_map_2,
236 .clkr.hw.init = &(const struct clk_init_data) {
237 .name = "disp_cc_mdss_byte0_clk_src",
238 .parent_data = disp_cc_parent_data_2,
239 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
240 .flags = CLK_SET_RATE_PARENT,
241 .ops = &clk_byte2_ops,
242 },
243};
244
245static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
246 .cmd_rcgr = 0x212c,
247 .mnd_width = 0,
248 .hid_width = 5,
249 .parent_map = disp_cc_parent_map_2,
250 .clkr.hw.init = &(const struct clk_init_data) {
251 .name = "disp_cc_mdss_byte1_clk_src",
252 .parent_data = disp_cc_parent_data_2,
253 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
254 .flags = CLK_SET_RATE_PARENT,
255 .ops = &clk_byte2_ops,
256 },
257};
258
259static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
260 .cmd_rcgr = 0x2240,
261 .mnd_width = 0,
262 .hid_width = 5,
263 .parent_map = disp_cc_parent_map_1,
264 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
265 .clkr.hw.init = &(const struct clk_init_data) {
266 .name = "disp_cc_mdss_dp_aux1_clk_src",
267 .parent_data = disp_cc_parent_data_1,
268 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
269 .flags = CLK_SET_RATE_PARENT,
270 .ops = &clk_rcg2_ops,
271 },
272};
273
274static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
275 .cmd_rcgr = 0x21dc,
276 .mnd_width = 0,
277 .hid_width = 5,
278 .parent_map = disp_cc_parent_map_1,
279 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
280 .clkr.hw.init = &(const struct clk_init_data) {
281 .name = "disp_cc_mdss_dp_aux_clk_src",
282 .parent_data = disp_cc_parent_data_1,
283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_rcg2_ops,
286 },
287};
288
289static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
290 .cmd_rcgr = 0x220c,
291 .mnd_width = 0,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_0,
294 .clkr.hw.init = &(const struct clk_init_data) {
295 .name = "disp_cc_mdss_dp_link1_clk_src",
296 .parent_data = disp_cc_parent_data_0,
297 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
298 .ops = &clk_byte2_ops,
299 },
300};
301
302static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
303 .cmd_rcgr = 0x2178,
304 .mnd_width = 0,
305 .hid_width = 5,
306 .parent_map = disp_cc_parent_map_0,
307 .clkr.hw.init = &(const struct clk_init_data) {
308 .name = "disp_cc_mdss_dp_link_clk_src",
309 .parent_data = disp_cc_parent_data_0,
310 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
311 .ops = &clk_byte2_ops,
312 },
313};
314
315static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
316 .cmd_rcgr = 0x21c4,
317 .mnd_width = 16,
318 .hid_width = 5,
319 .parent_map = disp_cc_parent_map_0,
320 .clkr.hw.init = &(const struct clk_init_data) {
321 .name = "disp_cc_mdss_dp_pixel1_clk_src",
322 .parent_data = disp_cc_parent_data_0,
323 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
324 .ops = &clk_dp_ops,
325 },
326};
327
328static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
329 .cmd_rcgr = 0x21f4,
330 .mnd_width = 16,
331 .hid_width = 5,
332 .parent_map = disp_cc_parent_map_0,
333 .clkr.hw.init = &(const struct clk_init_data) {
334 .name = "disp_cc_mdss_dp_pixel2_clk_src",
335 .parent_data = disp_cc_parent_data_0,
336 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
337 .ops = &clk_dp_ops,
338 },
339};
340
341static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
342 .cmd_rcgr = 0x21ac,
343 .mnd_width = 16,
344 .hid_width = 5,
345 .parent_map = disp_cc_parent_map_0,
346 .clkr.hw.init = &(const struct clk_init_data) {
347 .name = "disp_cc_mdss_dp_pixel_clk_src",
348 .parent_data = disp_cc_parent_data_0,
349 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
350 .ops = &clk_dp_ops,
351 },
352};
353
354static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
355 .cmd_rcgr = 0x228c,
356 .mnd_width = 0,
357 .hid_width = 5,
358 .parent_map = disp_cc_parent_map_1,
359 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
360 .clkr.hw.init = &(const struct clk_init_data) {
361 .name = "disp_cc_mdss_edp_aux_clk_src",
362 .parent_data = disp_cc_parent_data_1,
363 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
364 .flags = CLK_SET_RATE_PARENT,
365 .ops = &clk_rcg2_ops,
366 },
367};
368
369static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
370 .cmd_rcgr = 0x22a4,
371 .mnd_width = 0,
372 .hid_width = 5,
373 .parent_map = disp_cc_parent_map_7,
374 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
375 .clkr.hw.init = &(const struct clk_init_data) {
376 .name = "disp_cc_mdss_edp_gtc_clk_src",
377 .parent_data = disp_cc_parent_data_7,
378 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
381 },
382};
383
384static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
385 .cmd_rcgr = 0x2270,
386 .mnd_width = 0,
387 .hid_width = 5,
388 .parent_map = disp_cc_parent_map_4,
389 .clkr.hw.init = &(const struct clk_init_data) {
390 .name = "disp_cc_mdss_edp_link_clk_src",
391 .parent_data = disp_cc_parent_data_4,
392 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
393 .flags = CLK_SET_RATE_PARENT,
394 .ops = &clk_byte2_ops,
395 },
396};
397
398static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
399 .cmd_rcgr = 0x2258,
400 .mnd_width = 16,
401 .hid_width = 5,
402 .parent_map = disp_cc_parent_map_4,
403 .clkr.hw.init = &(const struct clk_init_data) {
404 .name = "disp_cc_mdss_edp_pixel_clk_src",
405 .parent_data = disp_cc_parent_data_4,
406 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
407 .ops = &clk_dp_ops,
408 },
409};
410
411static struct clk_branch disp_cc_mdss_edp_aux_clk = {
412 .halt_reg = 0x2078,
413 .halt_check = BRANCH_HALT,
414 .clkr = {
415 .enable_reg = 0x2078,
416 .enable_mask = BIT(0),
417 .hw.init = &(const struct clk_init_data) {
418 .name = "disp_cc_mdss_edp_aux_clk",
419 .parent_hws = (const struct clk_hw*[]){
420 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
421 },
422 .num_parents = 1,
423 .flags = CLK_SET_RATE_PARENT,
424 .ops = &clk_branch2_ops,
425 },
426 },
427};
428
429static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
430 .halt_reg = 0x207c,
431 .halt_check = BRANCH_HALT,
432 .clkr = {
433 .enable_reg = 0x207c,
434 .enable_mask = BIT(0),
435 .hw.init = &(const struct clk_init_data) {
436 .name = "disp_cc_mdss_edp_gtc_clk",
437 .parent_hws = (const struct clk_hw*[]){
438 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
439 },
440 .num_parents = 1,
441 .flags = CLK_SET_RATE_PARENT,
442 .ops = &clk_branch2_ops,
443 },
444 },
445};
446
447static struct clk_branch disp_cc_mdss_edp_link_clk = {
448 .halt_reg = 0x2070,
449 .halt_check = BRANCH_HALT,
450 .clkr = {
451 .enable_reg = 0x2070,
452 .enable_mask = BIT(0),
453 .hw.init = &(const struct clk_init_data) {
454 .name = "disp_cc_mdss_edp_link_clk",
455 .parent_hws = (const struct clk_hw*[]){
456 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
457 },
458 .num_parents = 1,
459 .flags = CLK_SET_RATE_PARENT,
460 .ops = &clk_branch2_ops,
461 },
462 },
463};
464
465static struct clk_regmap_div disp_cc_mdss_edp_link_div_clk_src = {
466 .reg = 0x2288,
467 .shift = 0,
468 .width = 2,
469 .clkr.hw.init = &(const struct clk_init_data) {
470 .name = "disp_cc_mdss_edp_link_div_clk_src",
471 .parent_hws = (const struct clk_hw*[]){
472 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
473 },
474 .num_parents = 1,
475 .ops = &clk_regmap_div_ro_ops,
476 },
477};
478
479static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
480 .halt_reg = 0x2074,
481 .halt_check = BRANCH_HALT,
482 .clkr = {
483 .enable_reg = 0x2074,
484 .enable_mask = BIT(0),
485 .hw.init = &(const struct clk_init_data) {
486 .name = "disp_cc_mdss_edp_link_intf_clk",
487 .parent_hws = (const struct clk_hw*[]){
488 &disp_cc_mdss_edp_link_div_clk_src.clkr.hw,
489 },
490 .num_parents = 1,
491 .flags = CLK_GET_RATE_NOCACHE,
492 .ops = &clk_branch2_ops,
493 },
494 },
495};
496
497static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
498 .halt_reg = 0x206c,
499 .halt_check = BRANCH_HALT,
500 .clkr = {
501 .enable_reg = 0x206c,
502 .enable_mask = BIT(0),
503 .hw.init = &(const struct clk_init_data) {
504 .name = "disp_cc_mdss_edp_pixel_clk",
505 .parent_hws = (const struct clk_hw*[]){
506 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
507 },
508 .num_parents = 1,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_branch2_ops,
511 },
512 },
513};
514
515static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
516 .cmd_rcgr = 0x2148,
517 .mnd_width = 0,
518 .hid_width = 5,
519 .parent_map = disp_cc_parent_map_2,
520 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
521 .clkr.hw.init = &(const struct clk_init_data) {
522 .name = "disp_cc_mdss_esc0_clk_src",
523 .parent_data = disp_cc_parent_data_2,
524 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
525 .flags = CLK_SET_RATE_PARENT,
526 .ops = &clk_rcg2_ops,
527 },
528};
529
530static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
531 .cmd_rcgr = 0x2160,
532 .mnd_width = 0,
533 .hid_width = 5,
534 .parent_map = disp_cc_parent_map_2,
535 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
536 .clkr.hw.init = &(const struct clk_init_data) {
537 .name = "disp_cc_mdss_esc1_clk_src",
538 .parent_data = disp_cc_parent_data_2,
539 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
540 .flags = CLK_SET_RATE_PARENT,
541 .ops = &clk_rcg2_ops,
542 },
543};
544
545static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
546 F(19200000, P_BI_TCXO, 1, 0, 0),
547 F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
548 F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
549 F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
550 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
551 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
552 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
553 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
554 { }
555};
556
557static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
558 .cmd_rcgr = 0x20c8,
559 .mnd_width = 0,
560 .hid_width = 5,
561 .parent_map = disp_cc_parent_map_5,
562 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
563 .clkr.hw.init = &(const struct clk_init_data) {
564 .name = "disp_cc_mdss_mdp_clk_src",
565 .parent_data = disp_cc_parent_data_5,
566 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
567 .flags = CLK_SET_RATE_PARENT,
568 .ops = &clk_rcg2_shared_ops,
569 },
570};
571
572static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
573 .cmd_rcgr = 0x2098,
574 .mnd_width = 8,
575 .hid_width = 5,
576 .parent_map = disp_cc_parent_map_6,
577 .clkr.hw.init = &(const struct clk_init_data) {
578 .name = "disp_cc_mdss_pclk0_clk_src",
579 .parent_data = disp_cc_parent_data_6,
580 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
581 .flags = CLK_SET_RATE_PARENT,
582 .ops = &clk_pixel_ops,
583 },
584};
585
586static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
587 .cmd_rcgr = 0x20b0,
588 .mnd_width = 8,
589 .hid_width = 5,
590 .parent_map = disp_cc_parent_map_6,
591 .clkr.hw.init = &(const struct clk_init_data) {
592 .name = "disp_cc_mdss_pclk1_clk_src",
593 .parent_data = disp_cc_parent_data_6,
594 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
595 .flags = CLK_SET_RATE_PARENT,
596 .ops = &clk_pixel_ops,
597 },
598};
599
600static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
601 F(19200000, P_BI_TCXO, 1, 0, 0),
602 F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
603 F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
604 F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
605 F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
606 { }
607};
608
609static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
610 .cmd_rcgr = 0x20e0,
611 .mnd_width = 0,
612 .hid_width = 5,
613 .parent_map = disp_cc_parent_map_5,
614 .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
615 .clkr.hw.init = &(const struct clk_init_data) {
616 .name = "disp_cc_mdss_rot_clk_src",
617 .parent_data = disp_cc_parent_data_5,
618 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
619 .flags = CLK_SET_RATE_PARENT,
620 .ops = &clk_rcg2_shared_ops,
621 },
622};
623
624static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
625 .cmd_rcgr = 0x20f8,
626 .mnd_width = 0,
627 .hid_width = 5,
628 .parent_map = disp_cc_parent_map_1,
629 .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
630 .clkr.hw.init = &(const struct clk_init_data) {
631 .name = "disp_cc_mdss_vsync_clk_src",
632 .parent_data = disp_cc_parent_data_1,
633 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
634 .flags = CLK_SET_RATE_PARENT,
635 .ops = &clk_rcg2_ops,
636 },
637};
638
639static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
640 .reg = 0x2128,
641 .shift = 0,
642 .width = 2,
643 .clkr.hw.init = &(const struct clk_init_data) {
644 .name = "disp_cc_mdss_byte0_div_clk_src",
645 .parent_hws = (const struct clk_hw*[]){
646 &disp_cc_mdss_byte0_clk_src.clkr.hw,
647 },
648 .num_parents = 1,
649 .ops = &clk_regmap_div_ops,
650 },
651};
652
653
654static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
655 .reg = 0x2144,
656 .shift = 0,
657 .width = 2,
658 .clkr.hw.init = &(const struct clk_init_data) {
659 .name = "disp_cc_mdss_byte1_div_clk_src",
660 .parent_hws = (const struct clk_hw*[]){
661 &disp_cc_mdss_byte1_clk_src.clkr.hw,
662 },
663 .num_parents = 1,
664 .ops = &clk_regmap_div_ops,
665 },
666};
667
668static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
669 .reg = 0x2224,
670 .shift = 0,
671 .width = 2,
672 .clkr.hw.init = &(const struct clk_init_data) {
673 .name = "disp_cc_mdss_dp_link1_div_clk_src",
674 .parent_hws = (const struct clk_hw*[]){
675 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
676 },
677 .num_parents = 1,
678 .ops = &clk_regmap_div_ro_ops,
679 },
680};
681
682static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
683 .reg = 0x2190,
684 .shift = 0,
685 .width = 2,
686 .clkr.hw.init = &(const struct clk_init_data) {
687 .name = "disp_cc_mdss_dp_link_div_clk_src",
688 .parent_hws = (const struct clk_hw*[]){
689 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
690 },
691 .num_parents = 1,
692 .ops = &clk_regmap_div_ro_ops,
693 },
694};
695
696static struct clk_branch disp_cc_mdss_ahb_clk = {
697 .halt_reg = 0x2080,
698 .halt_check = BRANCH_HALT,
699 .clkr = {
700 .enable_reg = 0x2080,
701 .enable_mask = BIT(0),
702 .hw.init = &(const struct clk_init_data) {
703 .name = "disp_cc_mdss_ahb_clk",
704 .parent_hws = (const struct clk_hw*[]){
705 &disp_cc_mdss_ahb_clk_src.clkr.hw,
706 },
707 .num_parents = 1,
708 .flags = CLK_SET_RATE_PARENT,
709 .ops = &clk_branch2_ops,
710 },
711 },
712};
713
714static struct clk_branch disp_cc_mdss_byte0_clk = {
715 .halt_reg = 0x2028,
716 .halt_check = BRANCH_HALT,
717 .clkr = {
718 .enable_reg = 0x2028,
719 .enable_mask = BIT(0),
720 .hw.init = &(const struct clk_init_data) {
721 .name = "disp_cc_mdss_byte0_clk",
722 .parent_hws = (const struct clk_hw*[]){
723 &disp_cc_mdss_byte0_clk_src.clkr.hw,
724 },
725 .num_parents = 1,
726 .flags = CLK_SET_RATE_PARENT,
727 .ops = &clk_branch2_ops,
728 },
729 },
730};
731
732static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
733 .halt_reg = 0x202c,
734 .halt_check = BRANCH_HALT,
735 .clkr = {
736 .enable_reg = 0x202c,
737 .enable_mask = BIT(0),
738 .hw.init = &(const struct clk_init_data) {
739 .name = "disp_cc_mdss_byte0_intf_clk",
740 .parent_hws = (const struct clk_hw*[]){
741 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
742 },
743 .num_parents = 1,
744 .flags = CLK_SET_RATE_PARENT,
745 .ops = &clk_branch2_ops,
746 },
747 },
748};
749
750static struct clk_branch disp_cc_mdss_byte1_clk = {
751 .halt_reg = 0x2030,
752 .halt_check = BRANCH_HALT,
753 .clkr = {
754 .enable_reg = 0x2030,
755 .enable_mask = BIT(0),
756 .hw.init = &(const struct clk_init_data) {
757 .name = "disp_cc_mdss_byte1_clk",
758 .parent_hws = (const struct clk_hw*[]){
759 &disp_cc_mdss_byte1_clk_src.clkr.hw,
760 },
761 .num_parents = 1,
762 .flags = CLK_SET_RATE_PARENT,
763 .ops = &clk_branch2_ops,
764 },
765 },
766};
767
768static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
769 .halt_reg = 0x2034,
770 .halt_check = BRANCH_HALT,
771 .clkr = {
772 .enable_reg = 0x2034,
773 .enable_mask = BIT(0),
774 .hw.init = &(const struct clk_init_data) {
775 .name = "disp_cc_mdss_byte1_intf_clk",
776 .parent_hws = (const struct clk_hw*[]){
777 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
778 },
779 .num_parents = 1,
780 .flags = CLK_SET_RATE_PARENT,
781 .ops = &clk_branch2_ops,
782 },
783 },
784};
785
786static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
787 .halt_reg = 0x2068,
788 .halt_check = BRANCH_HALT,
789 .clkr = {
790 .enable_reg = 0x2068,
791 .enable_mask = BIT(0),
792 .hw.init = &(const struct clk_init_data) {
793 .name = "disp_cc_mdss_dp_aux1_clk",
794 .parent_hws = (const struct clk_hw*[]){
795 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
796 },
797 .num_parents = 1,
798 .flags = CLK_SET_RATE_PARENT,
799 .ops = &clk_branch2_ops,
800 },
801 },
802};
803
804static struct clk_branch disp_cc_mdss_dp_aux_clk = {
805 .halt_reg = 0x2054,
806 .halt_check = BRANCH_HALT,
807 .clkr = {
808 .enable_reg = 0x2054,
809 .enable_mask = BIT(0),
810 .hw.init = &(const struct clk_init_data) {
811 .name = "disp_cc_mdss_dp_aux_clk",
812 .parent_hws = (const struct clk_hw*[]){
813 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
814 },
815 .num_parents = 1,
816 .flags = CLK_SET_RATE_PARENT,
817 .ops = &clk_branch2_ops,
818 },
819 },
820};
821
822static struct clk_branch disp_cc_mdss_dp_link1_clk = {
823 .halt_reg = 0x205c,
824 .halt_check = BRANCH_HALT,
825 .clkr = {
826 .enable_reg = 0x205c,
827 .enable_mask = BIT(0),
828 .hw.init = &(const struct clk_init_data) {
829 .name = "disp_cc_mdss_dp_link1_clk",
830 .parent_hws = (const struct clk_hw*[]){
831 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
832 },
833 .num_parents = 1,
834 .flags = CLK_SET_RATE_PARENT,
835 .ops = &clk_branch2_ops,
836 },
837 },
838};
839
840static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
841 .halt_reg = 0x2060,
842 .halt_check = BRANCH_HALT,
843 .clkr = {
844 .enable_reg = 0x2060,
845 .enable_mask = BIT(0),
846 .hw.init = &(const struct clk_init_data) {
847 .name = "disp_cc_mdss_dp_link1_intf_clk",
848 .parent_hws = (const struct clk_hw*[]){
849 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
850 },
851 .num_parents = 1,
852 .ops = &clk_branch2_ops,
853 },
854 },
855};
856
857static struct clk_branch disp_cc_mdss_dp_link_clk = {
858 .halt_reg = 0x2040,
859 .halt_check = BRANCH_HALT,
860 .clkr = {
861 .enable_reg = 0x2040,
862 .enable_mask = BIT(0),
863 .hw.init = &(const struct clk_init_data) {
864 .name = "disp_cc_mdss_dp_link_clk",
865 .parent_hws = (const struct clk_hw*[]){
866 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
867 },
868 .num_parents = 1,
869 .flags = CLK_SET_RATE_PARENT,
870 .ops = &clk_branch2_ops,
871 },
872 },
873};
874
875static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
876 .halt_reg = 0x2044,
877 .halt_check = BRANCH_HALT,
878 .clkr = {
879 .enable_reg = 0x2044,
880 .enable_mask = BIT(0),
881 .hw.init = &(const struct clk_init_data) {
882 .name = "disp_cc_mdss_dp_link_intf_clk",
883 .parent_hws = (const struct clk_hw*[]){
884 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
885 },
886 .num_parents = 1,
887 .ops = &clk_branch2_ops,
888 },
889 },
890};
891
892static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
893 .halt_reg = 0x2050,
894 .halt_check = BRANCH_HALT,
895 .clkr = {
896 .enable_reg = 0x2050,
897 .enable_mask = BIT(0),
898 .hw.init = &(const struct clk_init_data) {
899 .name = "disp_cc_mdss_dp_pixel1_clk",
900 .parent_hws = (const struct clk_hw*[]){
901 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
902 },
903 .num_parents = 1,
904 .flags = CLK_SET_RATE_PARENT,
905 .ops = &clk_branch2_ops,
906 },
907 },
908};
909
910static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
911 .halt_reg = 0x2058,
912 .halt_check = BRANCH_HALT,
913 .clkr = {
914 .enable_reg = 0x2058,
915 .enable_mask = BIT(0),
916 .hw.init = &(const struct clk_init_data) {
917 .name = "disp_cc_mdss_dp_pixel2_clk",
918 .parent_hws = (const struct clk_hw*[]){
919 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
920 },
921 .num_parents = 1,
922 .flags = CLK_SET_RATE_PARENT,
923 .ops = &clk_branch2_ops,
924 },
925 },
926};
927
928static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
929 .halt_reg = 0x204c,
930 .halt_check = BRANCH_HALT,
931 .clkr = {
932 .enable_reg = 0x204c,
933 .enable_mask = BIT(0),
934 .hw.init = &(const struct clk_init_data) {
935 .name = "disp_cc_mdss_dp_pixel_clk",
936 .parent_hws = (const struct clk_hw*[]){
937 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
938 },
939 .num_parents = 1,
940 .flags = CLK_SET_RATE_PARENT,
941 .ops = &clk_branch2_ops,
942 },
943 },
944};
945
946static struct clk_branch disp_cc_mdss_esc0_clk = {
947 .halt_reg = 0x2038,
948 .halt_check = BRANCH_HALT,
949 .clkr = {
950 .enable_reg = 0x2038,
951 .enable_mask = BIT(0),
952 .hw.init = &(const struct clk_init_data) {
953 .name = "disp_cc_mdss_esc0_clk",
954 .parent_hws = (const struct clk_hw*[]){
955 &disp_cc_mdss_esc0_clk_src.clkr.hw,
956 },
957 .num_parents = 1,
958 .flags = CLK_SET_RATE_PARENT,
959 .ops = &clk_branch2_ops,
960 },
961 },
962};
963
964static struct clk_branch disp_cc_mdss_esc1_clk = {
965 .halt_reg = 0x203c,
966 .halt_check = BRANCH_HALT,
967 .clkr = {
968 .enable_reg = 0x203c,
969 .enable_mask = BIT(0),
970 .hw.init = &(const struct clk_init_data) {
971 .name = "disp_cc_mdss_esc1_clk",
972 .parent_hws = (const struct clk_hw*[]){
973 &disp_cc_mdss_esc1_clk_src.clkr.hw,
974 },
975 .num_parents = 1,
976 .flags = CLK_SET_RATE_PARENT,
977 .ops = &clk_branch2_ops,
978 },
979 },
980};
981
982static struct clk_branch disp_cc_mdss_mdp_clk = {
983 .halt_reg = 0x200c,
984 .halt_check = BRANCH_HALT,
985 .clkr = {
986 .enable_reg = 0x200c,
987 .enable_mask = BIT(0),
988 .hw.init = &(const struct clk_init_data) {
989 .name = "disp_cc_mdss_mdp_clk",
990 .parent_hws = (const struct clk_hw*[]){
991 &disp_cc_mdss_mdp_clk_src.clkr.hw,
992 },
993 .num_parents = 1,
994 .flags = CLK_SET_RATE_PARENT,
995 .ops = &clk_branch2_ops,
996 },
997 },
998};
999
1000static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
1001 .halt_reg = 0x201c,
1002 .halt_check = BRANCH_VOTED,
1003 .clkr = {
1004 .enable_reg = 0x201c,
1005 .enable_mask = BIT(0),
1006 .hw.init = &(const struct clk_init_data) {
1007 .name = "disp_cc_mdss_mdp_lut_clk",
1008 .parent_hws = (const struct clk_hw*[]){
1009 &disp_cc_mdss_mdp_clk_src.clkr.hw,
1010 },
1011 .num_parents = 1,
1012 .ops = &clk_branch2_ops,
1013 },
1014 },
1015};
1016
1017static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1018 .halt_reg = 0x4004,
1019 .halt_check = BRANCH_VOTED,
1020 .clkr = {
1021 .enable_reg = 0x4004,
1022 .enable_mask = BIT(0),
1023 .hw.init = &(const struct clk_init_data) {
1024 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1025 .parent_hws = (const struct clk_hw*[]){
1026 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1027 },
1028 .num_parents = 1,
1029 .flags = CLK_SET_RATE_PARENT,
1030 .ops = &clk_branch2_ops,
1031 },
1032 },
1033};
1034
1035static struct clk_branch disp_cc_mdss_pclk0_clk = {
1036 .halt_reg = 0x2004,
1037 .halt_check = BRANCH_HALT,
1038 .clkr = {
1039 .enable_reg = 0x2004,
1040 .enable_mask = BIT(0),
1041 .hw.init = &(const struct clk_init_data) {
1042 .name = "disp_cc_mdss_pclk0_clk",
1043 .parent_hws = (const struct clk_hw*[]){
1044 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1045 },
1046 .num_parents = 1,
1047 .flags = CLK_SET_RATE_PARENT,
1048 .ops = &clk_branch2_ops,
1049 },
1050 },
1051};
1052
1053static struct clk_branch disp_cc_mdss_pclk1_clk = {
1054 .halt_reg = 0x2008,
1055 .halt_check = BRANCH_HALT,
1056 .clkr = {
1057 .enable_reg = 0x2008,
1058 .enable_mask = BIT(0),
1059 .hw.init = &(const struct clk_init_data) {
1060 .name = "disp_cc_mdss_pclk1_clk",
1061 .parent_hws = (const struct clk_hw*[]){
1062 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1063 },
1064 .num_parents = 1,
1065 .flags = CLK_SET_RATE_PARENT,
1066 .ops = &clk_branch2_ops,
1067 },
1068 },
1069};
1070
1071static struct clk_branch disp_cc_mdss_rot_clk = {
1072 .halt_reg = 0x2014,
1073 .halt_check = BRANCH_HALT,
1074 .clkr = {
1075 .enable_reg = 0x2014,
1076 .enable_mask = BIT(0),
1077 .hw.init = &(const struct clk_init_data) {
1078 .name = "disp_cc_mdss_rot_clk",
1079 .parent_hws = (const struct clk_hw*[]){
1080 &disp_cc_mdss_rot_clk_src.clkr.hw,
1081 },
1082 .num_parents = 1,
1083 .flags = CLK_SET_RATE_PARENT,
1084 .ops = &clk_branch2_ops,
1085 },
1086 },
1087};
1088
1089static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1090 .halt_reg = 0x400c,
1091 .halt_check = BRANCH_HALT,
1092 .clkr = {
1093 .enable_reg = 0x400c,
1094 .enable_mask = BIT(0),
1095 .hw.init = &(const struct clk_init_data) {
1096 .name = "disp_cc_mdss_rscc_ahb_clk",
1097 .parent_hws = (const struct clk_hw*[]){
1098 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1099 },
1100 .num_parents = 1,
1101 .flags = CLK_SET_RATE_PARENT,
1102 .ops = &clk_branch2_ops,
1103 },
1104 },
1105};
1106
1107static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1108 .halt_reg = 0x4008,
1109 .halt_check = BRANCH_HALT,
1110 .clkr = {
1111 .enable_reg = 0x4008,
1112 .enable_mask = BIT(0),
1113 .hw.init = &(const struct clk_init_data) {
1114 .name = "disp_cc_mdss_rscc_vsync_clk",
1115 .parent_hws = (const struct clk_hw*[]){
1116 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 .ops = &clk_branch2_ops,
1121 },
1122 },
1123};
1124
1125static struct clk_branch disp_cc_mdss_vsync_clk = {
1126 .halt_reg = 0x2024,
1127 .halt_check = BRANCH_HALT,
1128 .clkr = {
1129 .enable_reg = 0x2024,
1130 .enable_mask = BIT(0),
1131 .hw.init = &(const struct clk_init_data) {
1132 .name = "disp_cc_mdss_vsync_clk",
1133 .parent_hws = (const struct clk_hw*[]){
1134 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1135 },
1136 .num_parents = 1,
1137 .flags = CLK_SET_RATE_PARENT,
1138 .ops = &clk_branch2_ops,
1139 },
1140 },
1141};
1142
1143static struct gdsc mdss_gdsc = {
1144 .gdscr = 0x3000,
1145 .en_rest_wait_val = 0x2,
1146 .en_few_wait_val = 0x2,
1147 .clk_dis_wait_val = 0xf,
1148 .pd = {
1149 .name = "mdss_gdsc",
1150 },
1151 .pwrsts = PWRSTS_OFF_ON,
1152 .flags = HW_CTRL | RETAIN_FF_ENABLE,
1153};
1154
1155static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1156 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1157 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1158 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1159 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1160 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1161 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1162 [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1163 [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1164 [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1165 [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1166 [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1167 [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1168 [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1169 [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1170 [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1171 [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1172 [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1173 [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1174 [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1175 [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1176 [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1177 [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1178 [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1179 [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1180 [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1181 [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1182 [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1183 [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1184 [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1185 [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1186 [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1187 [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1188 [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1189 [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1190 [DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_edp_link_div_clk_src.clkr,
1191 [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1192 [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1193 [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1194 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1195 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1196 [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1197 [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1198 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1199 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1200 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1201 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1202 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1203 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1204 [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1205 [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1206 [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1207 [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1208 [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1209 [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1210 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1211 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1212 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1213 [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1214};
1215
1216static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1217 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1218 [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1219};
1220
1221static struct gdsc *disp_cc_sm8250_gdscs[] = {
1222 [MDSS_GDSC] = &mdss_gdsc,
1223};
1224
1225static const struct regmap_config disp_cc_sm8250_regmap_config = {
1226 .reg_bits = 32,
1227 .reg_stride = 4,
1228 .val_bits = 32,
1229 .max_register = 0x10000,
1230 .fast_io = true,
1231};
1232
1233static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1234 .config = &disp_cc_sm8250_regmap_config,
1235 .clks = disp_cc_sm8250_clocks,
1236 .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1237 .resets = disp_cc_sm8250_resets,
1238 .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1239 .gdscs = disp_cc_sm8250_gdscs,
1240 .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1241};
1242
1243static const struct of_device_id disp_cc_sm8250_match_table[] = {
1244 { .compatible = "qcom,sc8180x-dispcc" },
1245 { .compatible = "qcom,sm8150-dispcc" },
1246 { .compatible = "qcom,sm8250-dispcc" },
1247 { .compatible = "qcom,sm8350-dispcc" },
1248 { }
1249};
1250MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1251
1252static int disp_cc_sm8250_probe(struct platform_device *pdev)
1253{
1254 struct regmap *regmap;
1255 int ret;
1256
1257 ret = devm_pm_runtime_enable(dev: &pdev->dev);
1258 if (ret)
1259 return ret;
1260
1261 ret = pm_runtime_resume_and_get(dev: &pdev->dev);
1262 if (ret)
1263 return ret;
1264
1265 regmap = qcom_cc_map(pdev, desc: &disp_cc_sm8250_desc);
1266 if (IS_ERR(ptr: regmap)) {
1267 pm_runtime_put(dev: &pdev->dev);
1268 return PTR_ERR(ptr: regmap);
1269 }
1270
1271 /* Apply differences for SM8150 and SM8350 */
1272 BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1273 if (of_device_is_compatible(device: pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1274 of_device_is_compatible(device: pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1275 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1276 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1277 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1278 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1279 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1280 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1281 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1282 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1283
1284 disp_cc_mdss_dp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1285 &disp_cc_mdss_dp_link_clk_src.clkr.hw;
1286 disp_cc_mdss_dp_link1_intf_clk.clkr.hw.init->parent_hws[0] =
1287 &disp_cc_mdss_dp_link1_clk_src.clkr.hw;
1288 disp_cc_mdss_edp_link_intf_clk.clkr.hw.init->parent_hws[0] =
1289 &disp_cc_mdss_edp_link_clk_src.clkr.hw;
1290
1291 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = NULL;
1292 disp_cc_sm8250_clocks[DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = NULL;
1293 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC] = NULL;
1294 } else if (of_device_is_compatible(device: pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1295 static struct clk_rcg2 * const rcgs[] = {
1296 &disp_cc_mdss_byte0_clk_src,
1297 &disp_cc_mdss_byte1_clk_src,
1298 &disp_cc_mdss_dp_aux1_clk_src,
1299 &disp_cc_mdss_dp_aux_clk_src,
1300 &disp_cc_mdss_dp_link1_clk_src,
1301 &disp_cc_mdss_dp_link_clk_src,
1302 &disp_cc_mdss_dp_pixel1_clk_src,
1303 &disp_cc_mdss_dp_pixel2_clk_src,
1304 &disp_cc_mdss_dp_pixel_clk_src,
1305 &disp_cc_mdss_edp_aux_clk_src,
1306 &disp_cc_mdss_edp_link_clk_src,
1307 &disp_cc_mdss_edp_pixel_clk_src,
1308 &disp_cc_mdss_esc0_clk_src,
1309 &disp_cc_mdss_esc1_clk_src,
1310 &disp_cc_mdss_mdp_clk_src,
1311 &disp_cc_mdss_pclk0_clk_src,
1312 &disp_cc_mdss_pclk1_clk_src,
1313 &disp_cc_mdss_rot_clk_src,
1314 &disp_cc_mdss_vsync_clk_src,
1315 };
1316 static struct clk_regmap_div * const divs[] = {
1317 &disp_cc_mdss_byte0_div_clk_src,
1318 &disp_cc_mdss_byte1_div_clk_src,
1319 &disp_cc_mdss_dp_link1_div_clk_src,
1320 &disp_cc_mdss_dp_link_div_clk_src,
1321 &disp_cc_mdss_edp_link_div_clk_src,
1322 };
1323 unsigned int i;
1324 static bool offset_applied;
1325
1326 /*
1327 * note: trion == lucid, except for the prepare() op
1328 * only apply the offsets once (in case of deferred probe)
1329 */
1330 if (!offset_applied) {
1331 for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1332 rcgs[i]->cmd_rcgr -= 4;
1333
1334 for (i = 0; i < ARRAY_SIZE(divs); i++) {
1335 divs[i]->reg -= 4;
1336 divs[i]->width = 4;
1337 }
1338
1339 disp_cc_mdss_ahb_clk.halt_reg -= 4;
1340 disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1341
1342 offset_applied = true;
1343 }
1344
1345 disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1346
1347 disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1348 disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1349 disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1350 disp_cc_pll0.vco_table = lucid_5lpe_vco;
1351 disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1352 disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1353 disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1354 disp_cc_pll1.vco_table = lucid_5lpe_vco;
1355
1356 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK] = NULL;
1357 disp_cc_sm8250_clocks[DISP_CC_MDSS_EDP_GTC_CLK_SRC] = NULL;
1358 }
1359
1360 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1361 clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1362
1363 /* Enable clock gating for MDP clocks */
1364 regmap_update_bits(map: regmap, reg: 0x8000, mask: 0x10, val: 0x10);
1365
1366 /* Keep some clocks always-on */
1367 qcom_branch_set_clk_en(regmap, cbcr: 0x605c); /* DISP_CC_XO_CLK */
1368
1369 ret = qcom_cc_really_probe(pdev, desc: &disp_cc_sm8250_desc, regmap);
1370
1371 pm_runtime_put(dev: &pdev->dev);
1372
1373 return ret;
1374}
1375
1376static struct platform_driver disp_cc_sm8250_driver = {
1377 .probe = disp_cc_sm8250_probe,
1378 .driver = {
1379 .name = "disp_cc-sm8250",
1380 .of_match_table = disp_cc_sm8250_match_table,
1381 },
1382};
1383
1384module_platform_driver(disp_cc_sm8250_driver);
1385
1386MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1387MODULE_LICENSE("GPL v2");
1388

source code of linux/drivers/clk/qcom/dispcc-sm8250.c