1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/mod_devicetable.h>
8#include <linux/module.h>
9#include <linux/platform_device.h>
10#include <linux/regmap.h>
11
12#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
13
14#include "clk-alpha-pll.h"
15#include "clk-branch.h"
16#include "clk-rcg.h"
17#include "clk-regmap.h"
18#include "clk-regmap-divider.h"
19#include "clk-regmap-mux.h"
20#include "clk-regmap-phy-mux.h"
21#include "reset.h"
22
23enum {
24 DT_XO,
25 DT_SLEEP_CLK,
26 DT_PCIE_2LANE_PHY_PIPE_CLK,
27 DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
28 DT_USB_PCIE_WRAPPER_PIPE_CLK,
29};
30
31enum {
32 P_PCIE3X2_PIPE,
33 P_PCIE3X1_0_PIPE,
34 P_PCIE3X1_1_PIPE,
35 P_USB3PHY_0_PIPE,
36 P_CORE_BI_PLL_TEST_SE,
37 P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
38 P_GPLL0_OUT_AUX,
39 P_GPLL0_OUT_MAIN,
40 P_GPLL2_OUT_AUX,
41 P_GPLL2_OUT_MAIN,
42 P_GPLL4_OUT_AUX,
43 P_GPLL4_OUT_MAIN,
44 P_SLEEP_CLK,
45 P_XO,
46};
47
48static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
49
50static struct clk_alpha_pll gpll0_main = {
51 .offset = 0x20000,
52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
53 .clkr = {
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
56 .hw.init = &(const struct clk_init_data) {
57 .name = "gpll0_main",
58 .parent_data = &gcc_parent_data_xo,
59 .num_parents = 1,
60 .ops = &clk_alpha_pll_stromer_ops,
61 },
62 },
63};
64
65static struct clk_fixed_factor gpll0_div2 = {
66 .mult = 1,
67 .div = 2,
68 .hw.init = &(struct clk_init_data) {
69 .name = "gpll0_div2",
70 .parent_hws = (const struct clk_hw *[]) {
71 &gpll0_main.clkr.hw },
72 .num_parents = 1,
73 .ops = &clk_fixed_factor_ops,
74 },
75};
76
77static struct clk_alpha_pll_postdiv gpll0 = {
78 .offset = 0x20000,
79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
80 .width = 4,
81 .clkr.hw.init = &(struct clk_init_data) {
82 .name = "gpll0",
83 .parent_hws = (const struct clk_hw *[]) {
84 &gpll0_main.clkr.hw },
85 .num_parents = 1,
86 .ops = &clk_alpha_pll_postdiv_ro_ops,
87 },
88};
89
90static struct clk_alpha_pll gpll2_main = {
91 .offset = 0x21000,
92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
93 .clkr = {
94 .enable_reg = 0xb000,
95 .enable_mask = BIT(1),
96 .hw.init = &(const struct clk_init_data) {
97 .name = "gpll2",
98 .parent_data = &gcc_parent_data_xo,
99 .num_parents = 1,
100 .ops = &clk_alpha_pll_stromer_ops,
101 },
102 },
103};
104
105static struct clk_alpha_pll_postdiv gpll2 = {
106 .offset = 0x21000,
107 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
108 .width = 4,
109 .clkr.hw.init = &(struct clk_init_data) {
110 .name = "gpll2_main",
111 .parent_hws = (const struct clk_hw *[]) {
112 &gpll2_main.clkr.hw },
113 .num_parents = 1,
114 .ops = &clk_alpha_pll_postdiv_ro_ops,
115 },
116};
117
118static struct clk_alpha_pll gpll4_main = {
119 .offset = 0x22000,
120 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
121 .clkr = {
122 .enable_reg = 0xb000,
123 .enable_mask = BIT(2),
124 .hw.init = &(const struct clk_init_data) {
125 .name = "gpll4_main",
126 .parent_data = &gcc_parent_data_xo,
127 .num_parents = 1,
128 .ops = &clk_alpha_pll_stromer_ops,
129 /*
130 * There are no consumers for this GPLL in kernel yet,
131 * (will be added soon), so the clock framework
132 * disables this source. But some of the clocks
133 * initialized by boot loaders uses this source. So we
134 * need to keep this clock ON. Add the
135 * CLK_IGNORE_UNUSED flag so the clock will not be
136 * disabled. Once the consumer in kernel is added, we
137 * can get rid of this flag.
138 */
139 .flags = CLK_IGNORE_UNUSED,
140 },
141 },
142};
143
144static struct clk_alpha_pll_postdiv gpll4 = {
145 .offset = 0x22000,
146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
147 .width = 4,
148 .clkr.hw.init = &(struct clk_init_data) {
149 .name = "gpll4",
150 .parent_hws = (const struct clk_hw *[]) {
151 &gpll4_main.clkr.hw },
152 .num_parents = 1,
153 .ops = &clk_alpha_pll_postdiv_ro_ops,
154 },
155};
156
157static const struct parent_map gcc_parent_map_xo[] = {
158 { P_XO, 0 },
159};
160
161static const struct parent_map gcc_parent_map_0[] = {
162 { P_XO, 0 },
163 { P_GPLL0_OUT_MAIN, 1 },
164 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
165};
166
167static const struct clk_parent_data gcc_parent_data_0[] = {
168 { .index = DT_XO },
169 { .hw = &gpll0.clkr.hw },
170 { .hw = &gpll0_div2.hw },
171};
172
173static const struct parent_map gcc_parent_map_1[] = {
174 { P_XO, 0 },
175 { P_GPLL0_OUT_MAIN, 1 },
176};
177
178static const struct clk_parent_data gcc_parent_data_1[] = {
179 { .index = DT_XO },
180 { .hw = &gpll0.clkr.hw },
181};
182
183static const struct parent_map gcc_parent_map_2[] = {
184 { P_XO, 0 },
185 { P_GPLL0_OUT_MAIN, 1 },
186 { P_GPLL4_OUT_MAIN, 2 },
187};
188
189static const struct clk_parent_data gcc_parent_data_2[] = {
190 { .index = DT_XO },
191 { .hw = &gpll0.clkr.hw },
192 { .hw = &gpll4.clkr.hw },
193};
194
195static const struct parent_map gcc_parent_map_3[] = {
196 { P_XO, 0 },
197 { P_GPLL0_OUT_MAIN, 1 },
198 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
199 { P_SLEEP_CLK, 6 },
200};
201
202static const struct clk_parent_data gcc_parent_data_3[] = {
203 { .index = DT_XO },
204 { .hw = &gpll0.clkr.hw },
205 { .hw = &gpll0_div2.hw },
206 { .index = DT_SLEEP_CLK },
207};
208
209static const struct parent_map gcc_parent_map_4[] = {
210 { P_XO, 0 },
211 { P_GPLL4_OUT_MAIN, 1 },
212 { P_GPLL0_OUT_AUX, 2 },
213 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
214};
215
216static const struct clk_parent_data gcc_parent_data_4[] = {
217 { .index = DT_XO },
218 { .hw = &gpll4.clkr.hw },
219 { .hw = &gpll0.clkr.hw },
220 { .hw = &gpll0_div2.hw },
221};
222
223static const struct parent_map gcc_parent_map_5[] = {
224 { P_XO, 0 },
225 { P_GPLL0_OUT_MAIN, 1 },
226 { P_GPLL0_OUT_AUX, 2 },
227 { P_SLEEP_CLK, 6 },
228};
229
230static const struct clk_parent_data gcc_parent_data_5[] = {
231 { .index = DT_XO },
232 { .hw = &gpll0.clkr.hw },
233 { .hw = &gpll0.clkr.hw },
234 { .index = DT_SLEEP_CLK },
235};
236
237static const struct parent_map gcc_parent_map_6[] = {
238 { P_XO, 0 },
239 { P_GPLL0_OUT_MAIN, 1 },
240 { P_GPLL2_OUT_AUX, 2 },
241 { P_GPLL4_OUT_AUX, 3 },
242 { P_SLEEP_CLK, 6 },
243};
244
245static const struct clk_parent_data gcc_parent_data_6[] = {
246 { .index = DT_XO },
247 { .hw = &gpll0.clkr.hw },
248 { .hw = &gpll2.clkr.hw },
249 { .hw = &gpll4.clkr.hw },
250 { .index = DT_SLEEP_CLK },
251};
252
253static const struct parent_map gcc_parent_map_7[] = {
254 { P_XO, 0 },
255 { P_GPLL0_OUT_MAIN, 1 },
256 { P_GPLL2_OUT_AUX, 2 },
257};
258
259static const struct clk_parent_data gcc_parent_data_7[] = {
260 { .index = DT_XO },
261 { .hw = &gpll0.clkr.hw },
262 { .hw = &gpll2.clkr.hw },
263};
264
265static const struct parent_map gcc_parent_map_8[] = {
266 { P_XO, 0 },
267 { P_GPLL0_OUT_MAIN, 1 },
268 { P_GPLL2_OUT_MAIN, 2 },
269 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
270};
271
272static const struct clk_parent_data gcc_parent_data_8[] = {
273 { .index = DT_XO },
274 { .hw = &gpll0.clkr.hw },
275 { .hw = &gpll2.clkr.hw },
276 { .hw = &gpll0_div2.hw },
277};
278
279static const struct parent_map gcc_parent_map_9[] = {
280 { P_SLEEP_CLK, 6 },
281};
282
283static const struct clk_parent_data gcc_parent_data_9[] = {
284 { .index = DT_SLEEP_CLK },
285};
286
287static const struct parent_map gcc_parent_map_10[] = {
288 { P_XO, 0 },
289 { P_GPLL0_OUT_MAIN, 1 },
290 { P_GPLL4_OUT_MAIN, 2 },
291 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
292};
293
294static const struct clk_parent_data gcc_parent_data_10[] = {
295 { .index = DT_XO },
296 { .hw = &gpll0.clkr.hw },
297 { .hw = &gpll4.clkr.hw },
298 { .hw = &gpll0_div2.hw },
299};
300
301static const struct parent_map gcc_parent_map_11[] = {
302 { P_XO, 0 },
303 { P_GPLL0_OUT_AUX, 2 },
304 { P_SLEEP_CLK, 6 },
305};
306
307static const struct clk_parent_data gcc_parent_data_11[] = {
308 { .index = DT_XO },
309 { .hw = &gpll0.clkr.hw },
310 { .index = DT_SLEEP_CLK },
311};
312
313static const struct parent_map gcc_parent_map_12[] = {
314 { P_XO, 0 },
315 { P_GPLL4_OUT_AUX, 1 },
316 { P_GPLL0_OUT_MAIN, 3 },
317 { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
318};
319
320static const struct clk_parent_data gcc_parent_data_12[] = {
321 { .index = DT_XO },
322 { .hw = &gpll4.clkr.hw },
323 { .hw = &gpll0.clkr.hw },
324 { .hw = &gpll0_div2.hw },
325};
326
327static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
328 F(24000000, P_XO, 1, 0, 0),
329 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
330 { }
331};
332
333static struct clk_rcg2 gcc_adss_pwm_clk_src = {
334 .cmd_rcgr = 0x1c004,
335 .mnd_width = 0,
336 .hid_width = 5,
337 .parent_map = gcc_parent_map_1,
338 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
339 .clkr.hw.init = &(const struct clk_init_data) {
340 .name = "gcc_adss_pwm_clk_src",
341 .parent_data = gcc_parent_data_1,
342 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
343 .ops = &clk_rcg2_ops,
344 },
345};
346
347static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
348 F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
349 F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
350 { }
351};
352
353static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
354 F(960000, P_XO, 1, 1, 25),
355 F(4800000, P_XO, 5, 0, 0),
356 F(9600000, P_XO, 2.5, 0, 0),
357 F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
358 F(24000000, P_XO, 1, 0, 0),
359 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
360 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
361 { }
362};
363
364static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
365 .cmd_rcgr = 0x2004,
366 .mnd_width = 8,
367 .hid_width = 5,
368 .parent_map = gcc_parent_map_0,
369 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
370 .clkr.hw.init = &(const struct clk_init_data) {
371 .name = "gcc_blsp1_qup1_spi_apps_clk_src",
372 .parent_data = gcc_parent_data_0,
373 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
374 .ops = &clk_rcg2_ops,
375 },
376};
377
378static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
379 .cmd_rcgr = 0x3004,
380 .mnd_width = 8,
381 .hid_width = 5,
382 .parent_map = gcc_parent_map_0,
383 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
384 .clkr.hw.init = &(const struct clk_init_data) {
385 .name = "gcc_blsp1_qup2_spi_apps_clk_src",
386 .parent_data = gcc_parent_data_0,
387 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
388 .ops = &clk_rcg2_ops,
389 },
390};
391
392static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
393 .cmd_rcgr = 0x4004,
394 .mnd_width = 8,
395 .hid_width = 5,
396 .parent_map = gcc_parent_map_0,
397 .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
398 .clkr.hw.init = &(const struct clk_init_data) {
399 .name = "gcc_blsp1_qup3_spi_apps_clk_src",
400 .parent_data = gcc_parent_data_0,
401 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
402 .ops = &clk_rcg2_ops,
403 },
404};
405
406static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
407 F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
408 F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
409 F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
410 F(24000000, P_XO, 1, 0, 0),
411 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
412 F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
413 F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
414 F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
415 F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
416 F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
417 F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
418 F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
419 F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
420 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
421 { }
422};
423
424static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
425 .cmd_rcgr = 0x202c,
426 .mnd_width = 16,
427 .hid_width = 5,
428 .parent_map = gcc_parent_map_0,
429 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
430 .clkr.hw.init = &(const struct clk_init_data) {
431 .name = "gcc_blsp1_uart1_apps_clk_src",
432 .parent_data = gcc_parent_data_0,
433 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
434 .ops = &clk_rcg2_ops,
435 },
436};
437
438static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
439 .cmd_rcgr = 0x302c,
440 .mnd_width = 16,
441 .hid_width = 5,
442 .parent_map = gcc_parent_map_0,
443 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
444 .clkr.hw.init = &(const struct clk_init_data) {
445 .name = "gcc_blsp1_uart2_apps_clk_src",
446 .parent_data = gcc_parent_data_0,
447 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
448 .ops = &clk_rcg2_ops,
449 },
450};
451
452static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
453 .cmd_rcgr = 0x402c,
454 .mnd_width = 16,
455 .hid_width = 5,
456 .parent_map = gcc_parent_map_0,
457 .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
458 .clkr.hw.init = &(const struct clk_init_data) {
459 .name = "gcc_blsp1_uart3_apps_clk_src",
460 .parent_data = gcc_parent_data_0,
461 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
462 .ops = &clk_rcg2_ops,
463 },
464};
465
466static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
467 F(24000000, P_XO, 1, 0, 0),
468 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
469 { }
470};
471
472static struct clk_rcg2 gcc_gp1_clk_src = {
473 .cmd_rcgr = 0x8004,
474 .mnd_width = 8,
475 .hid_width = 5,
476 .parent_map = gcc_parent_map_3,
477 .freq_tbl = ftbl_gcc_gp1_clk_src,
478 .clkr.hw.init = &(const struct clk_init_data) {
479 .name = "gcc_gp1_clk_src",
480 .parent_data = gcc_parent_data_3,
481 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
482 .ops = &clk_rcg2_ops,
483 },
484};
485
486static struct clk_rcg2 gcc_gp2_clk_src = {
487 .cmd_rcgr = 0x9004,
488 .mnd_width = 8,
489 .hid_width = 5,
490 .parent_map = gcc_parent_map_3,
491 .freq_tbl = ftbl_gcc_gp1_clk_src,
492 .clkr.hw.init = &(const struct clk_init_data) {
493 .name = "gcc_gp2_clk_src",
494 .parent_data = gcc_parent_data_3,
495 .num_parents = ARRAY_SIZE(gcc_parent_data_3),
496 .ops = &clk_rcg2_ops,
497 },
498};
499
500static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
501 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
502 { }
503};
504
505static struct clk_rcg2 gcc_lpass_sway_clk_src = {
506 .cmd_rcgr = 0x27004,
507 .mnd_width = 0,
508 .hid_width = 5,
509 .parent_map = gcc_parent_map_1,
510 .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
511 .clkr.hw.init = &(const struct clk_init_data) {
512 .name = "gcc_lpass_sway_clk_src",
513 .parent_data = gcc_parent_data_1,
514 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
515 .ops = &clk_rcg2_ops,
516 },
517};
518
519static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
520 F(24000000, P_XO, 1, 0, 0),
521 { }
522};
523
524static struct clk_rcg2 gcc_nss_ts_clk_src = {
525 .cmd_rcgr = 0x17088,
526 .mnd_width = 0,
527 .hid_width = 5,
528 .parent_map = gcc_parent_map_xo,
529 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
530 .clkr.hw.init = &(const struct clk_init_data) {
531 .name = "gcc_nss_ts_clk_src",
532 .parent_data = &gcc_parent_data_xo,
533 .num_parents = 1,
534 .ops = &clk_rcg2_ops,
535 },
536};
537
538static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
539 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
540 { }
541};
542
543static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
544 .cmd_rcgr = 0x29018,
545 .mnd_width = 0,
546 .hid_width = 5,
547 .parent_map = gcc_parent_map_2,
548 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
549 .clkr.hw.init = &(const struct clk_init_data) {
550 .name = "gcc_pcie3x1_0_axi_clk_src",
551 .parent_data = gcc_parent_data_2,
552 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
553 .ops = &clk_rcg2_ops,
554 },
555};
556
557static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
558 .cmd_rcgr = 0x2907c,
559 .hid_width = 5,
560 .parent_map = gcc_parent_map_0,
561 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
562 .clkr.hw.init = &(const struct clk_init_data) {
563 .name = "gcc_pcie3x1_0_rchg_clk_src",
564 .parent_data = gcc_parent_data_0,
565 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
566 .ops = &clk_rcg2_ops,
567 },
568};
569
570static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
571 .halt_reg = 0x2907c,
572 .clkr = {
573 .enable_reg = 0x2907c,
574 .enable_mask = BIT(1),
575 .hw.init = &(struct clk_init_data) {
576 .name = "gcc_pcie3x1_0_rchg_clk",
577 .parent_hws = (const struct clk_hw *[]) {
578 &gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
579 .num_parents = 1,
580 .flags = CLK_SET_RATE_PARENT,
581 .ops = &clk_branch2_ops,
582 },
583 },
584};
585
586static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
587 .cmd_rcgr = 0x2a004,
588 .mnd_width = 0,
589 .hid_width = 5,
590 .parent_map = gcc_parent_map_2,
591 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
592 .clkr.hw.init = &(const struct clk_init_data) {
593 .name = "gcc_pcie3x1_1_axi_clk_src",
594 .parent_data = gcc_parent_data_2,
595 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
596 .ops = &clk_rcg2_ops,
597 },
598};
599
600static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
601 .cmd_rcgr = 0x2a078,
602 .hid_width = 5,
603 .parent_map = gcc_parent_map_0,
604 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
605 .clkr.hw.init = &(const struct clk_init_data) {
606 .name = "gcc_pcie3x1_1_rchg_clk_src",
607 .parent_data = gcc_parent_data_0,
608 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
609 .ops = &clk_rcg2_ops,
610 },
611};
612
613static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
614 .halt_reg = 0x2a078,
615 .clkr = {
616 .enable_reg = 0x2a078,
617 .enable_mask = BIT(1),
618 .hw.init = &(struct clk_init_data) {
619 .name = "gcc_pcie3x1_1_rchg_clk",
620 .parent_hws = (const struct clk_hw *[]) {
621 &gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
622 .num_parents = 1,
623 .flags = CLK_SET_RATE_PARENT,
624 .ops = &clk_branch2_ops,
625 },
626 },
627};
628
629static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
630 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
631 { }
632};
633
634static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
635 .cmd_rcgr = 0x28018,
636 .mnd_width = 0,
637 .hid_width = 5,
638 .parent_map = gcc_parent_map_2,
639 .freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
640 .clkr.hw.init = &(const struct clk_init_data) {
641 .name = "gcc_pcie3x2_axi_m_clk_src",
642 .parent_data = gcc_parent_data_2,
643 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
644 .ops = &clk_rcg2_ops,
645 },
646};
647
648static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
649 .cmd_rcgr = 0x28084,
650 .mnd_width = 0,
651 .hid_width = 5,
652 .parent_map = gcc_parent_map_2,
653 .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
654 .clkr.hw.init = &(const struct clk_init_data) {
655 .name = "gcc_pcie3x2_axi_s_clk_src",
656 .parent_data = gcc_parent_data_2,
657 .num_parents = ARRAY_SIZE(gcc_parent_data_2),
658 .ops = &clk_rcg2_ops,
659 },
660};
661
662static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
663 .cmd_rcgr = 0x28078,
664 .mnd_width = 0,
665 .hid_width = 5,
666 .parent_map = gcc_parent_map_0,
667 .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
668 .clkr.hw.init = &(const struct clk_init_data) {
669 .name = "gcc_pcie3x2_rchg_clk_src",
670 .parent_data = gcc_parent_data_0,
671 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
672 .ops = &clk_rcg2_ops,
673 },
674};
675
676static struct clk_branch gcc_pcie3x2_rchg_clk = {
677 .halt_reg = 0x28078,
678 .clkr = {
679 .enable_reg = 0x28078,
680 .enable_mask = BIT(1),
681 .hw.init = &(struct clk_init_data) {
682 .name = "gcc_pcie3x2_rchg_clk",
683 .parent_hws = (const struct clk_hw *[]) {
684 &gcc_pcie3x2_rchg_clk_src.clkr.hw },
685 .num_parents = 1,
686 .flags = CLK_SET_RATE_PARENT,
687 .ops = &clk_branch2_ops,
688 },
689 },
690};
691
692static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
693 F(2000000, P_XO, 12, 0, 0),
694 { }
695};
696
697static struct clk_rcg2 gcc_pcie_aux_clk_src = {
698 .cmd_rcgr = 0x28004,
699 .mnd_width = 16,
700 .hid_width = 5,
701 .parent_map = gcc_parent_map_5,
702 .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
703 .clkr.hw.init = &(const struct clk_init_data) {
704 .name = "gcc_pcie_aux_clk_src",
705 .parent_data = gcc_parent_data_5,
706 .num_parents = ARRAY_SIZE(gcc_parent_data_5),
707 .ops = &clk_rcg2_ops,
708 },
709};
710
711static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {
712 .reg = 0x28064,
713 .clkr = {
714 .hw.init = &(struct clk_init_data) {
715 .name = "gcc_pcie3x2_pipe_clk_src",
716 .parent_data = &(const struct clk_parent_data) {
717 .index = DT_PCIE_2LANE_PHY_PIPE_CLK,
718 },
719 .num_parents = 1,
720 .ops = &clk_regmap_phy_mux_ops,
721 },
722 },
723};
724
725static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {
726 .reg = 0x29064,
727 .clkr = {
728 .hw.init = &(struct clk_init_data) {
729 .name = "gcc_pcie3x1_0_pipe_clk_src",
730 .parent_data = &(const struct clk_parent_data) {
731 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
732 },
733 .num_parents = 1,
734 .ops = &clk_regmap_phy_mux_ops,
735 },
736 },
737};
738
739static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {
740 .reg = 0x2a064,
741 .clkr = {
742 .hw.init = &(struct clk_init_data) {
743 .name = "gcc_pcie3x1_1_pipe_clk_src",
744 .parent_data = &(const struct clk_parent_data) {
745 .index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,
746 },
747 .num_parents = 1,
748 .ops = &clk_regmap_phy_mux_ops,
749 },
750 },
751};
752
753static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
754 F(24000000, P_XO, 1, 0, 0),
755 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
756 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
757 { }
758};
759
760static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
761 .cmd_rcgr = 0x31004,
762 .mnd_width = 0,
763 .hid_width = 5,
764 .parent_map = gcc_parent_map_0,
765 .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
766 .clkr.hw.init = &(const struct clk_init_data) {
767 .name = "gcc_pcnoc_bfdcd_clk_src",
768 .parent_data = gcc_parent_data_0,
769 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
770 .ops = &clk_rcg2_ops,
771 },
772};
773
774static struct clk_rcg2 gcc_q6_axim_clk_src = {
775 .cmd_rcgr = 0x25004,
776 .mnd_width = 0,
777 .hid_width = 5,
778 .parent_map = gcc_parent_map_6,
779 .freq_tbl = ftbl_gcc_apss_axi_clk_src,
780 .clkr.hw.init = &(const struct clk_init_data) {
781 .name = "gcc_q6_axim_clk_src",
782 .parent_data = gcc_parent_data_6,
783 .num_parents = ARRAY_SIZE(gcc_parent_data_6),
784 .ops = &clk_rcg2_ops,
785 },
786};
787
788static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
789 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
790 { }
791};
792
793static struct clk_rcg2 gcc_qdss_at_clk_src = {
794 .cmd_rcgr = 0x2d004,
795 .mnd_width = 0,
796 .hid_width = 5,
797 .parent_map = gcc_parent_map_4,
798 .freq_tbl = ftbl_gcc_qdss_at_clk_src,
799 .clkr.hw.init = &(const struct clk_init_data) {
800 .name = "gcc_qdss_at_clk_src",
801 .parent_data = gcc_parent_data_4,
802 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
803 .ops = &clk_rcg2_ops,
804 },
805};
806
807static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
808 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
809 { }
810};
811
812static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
813 .cmd_rcgr = 0x2d01c,
814 .mnd_width = 0,
815 .hid_width = 5,
816 .parent_map = gcc_parent_map_4,
817 .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
818 .clkr.hw.init = &(const struct clk_init_data) {
819 .name = "gcc_qdss_tsctr_clk_src",
820 .parent_data = gcc_parent_data_4,
821 .num_parents = ARRAY_SIZE(gcc_parent_data_4),
822 .ops = &clk_rcg2_ops,
823 },
824};
825
826static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
827 .mult = 1,
828 .div = 2,
829 .hw.init = &(struct clk_init_data) {
830 .name = "gcc_qdss_tsctr_div2_clk_src",
831 .parent_hws = (const struct clk_hw *[]) {
832 &gcc_qdss_tsctr_clk_src.clkr.hw },
833 .num_parents = 1,
834 .flags = CLK_SET_RATE_PARENT,
835 .ops = &clk_fixed_factor_ops,
836 },
837};
838
839static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
840 .mult = 1,
841 .div = 3,
842 .hw.init = &(struct clk_init_data) {
843 .name = "gcc_qdss_tsctr_div3_clk_src",
844 .parent_hws = (const struct clk_hw *[]) {
845 &gcc_qdss_tsctr_clk_src.clkr.hw },
846 .num_parents = 1,
847 .ops = &clk_fixed_factor_ops,
848 },
849};
850
851static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
852 .mult = 1,
853 .div = 4,
854 .hw.init = &(struct clk_init_data) {
855 .name = "gcc_qdss_tsctr_div4_clk_src",
856 .parent_hws = (const struct clk_hw *[]) {
857 &gcc_qdss_tsctr_clk_src.clkr.hw },
858 .num_parents = 1,
859 .ops = &clk_fixed_factor_ops,
860 },
861};
862
863static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
864 .mult = 1,
865 .div = 8,
866 .hw.init = &(struct clk_init_data) {
867 .name = "gcc_qdss_tsctr_div8_clk_src",
868 .parent_hws = (const struct clk_hw *[]) {
869 &gcc_qdss_tsctr_clk_src.clkr.hw },
870 .num_parents = 1,
871 .ops = &clk_fixed_factor_ops,
872 },
873};
874
875static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
876 .mult = 1,
877 .div = 16,
878 .hw.init = &(struct clk_init_data) {
879 .name = "gcc_qdss_tsctr_div16_clk_src",
880 .parent_hws = (const struct clk_hw *[]) {
881 &gcc_qdss_tsctr_clk_src.clkr.hw },
882 .num_parents = 1,
883 .ops = &clk_fixed_factor_ops,
884 },
885};
886
887static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
888 F(24000000, P_XO, 1, 0, 0),
889 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
890 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
891 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
892 { }
893};
894
895static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
896 .cmd_rcgr = 0x32004,
897 .mnd_width = 0,
898 .hid_width = 5,
899 .parent_map = gcc_parent_map_7,
900 .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
901 .clkr.hw.init = &(const struct clk_init_data) {
902 .name = "gcc_qpic_io_macro_clk_src",
903 .parent_data = gcc_parent_data_7,
904 .num_parents = ARRAY_SIZE(gcc_parent_data_7),
905 .ops = &clk_rcg2_ops,
906 },
907};
908
909static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
910 F(143713, P_XO, 1, 1, 167),
911 F(400000, P_XO, 1, 1, 60),
912 F(24000000, P_XO, 1, 0, 0),
913 F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
914 F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
915 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
916 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
917 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
918 { }
919};
920
921static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
922 .cmd_rcgr = 0x33004,
923 .mnd_width = 8,
924 .hid_width = 5,
925 .parent_map = gcc_parent_map_8,
926 .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
927 .clkr.hw.init = &(const struct clk_init_data) {
928 .name = "gcc_sdcc1_apps_clk_src",
929 .parent_data = gcc_parent_data_8,
930 .num_parents = ARRAY_SIZE(gcc_parent_data_8),
931 .ops = &clk_rcg2_floor_ops,
932 },
933};
934
935static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
936 F(32000, P_SLEEP_CLK, 1, 0, 0),
937 { }
938};
939
940static struct clk_rcg2 gcc_sleep_clk_src = {
941 .cmd_rcgr = 0x3400c,
942 .mnd_width = 0,
943 .hid_width = 5,
944 .parent_map = gcc_parent_map_9,
945 .freq_tbl = ftbl_gcc_sleep_clk_src,
946 .clkr.hw.init = &(const struct clk_init_data) {
947 .name = "gcc_sleep_clk_src",
948 .parent_data = gcc_parent_data_9,
949 .num_parents = ARRAY_SIZE(gcc_parent_data_9),
950 .ops = &clk_rcg2_ops,
951 },
952};
953
954static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
955 F(24000000, P_XO, 1, 0, 0),
956 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
957 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
958 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
959 { }
960};
961
962static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
963 .cmd_rcgr = 0x2e004,
964 .mnd_width = 0,
965 .hid_width = 5,
966 .parent_map = gcc_parent_map_10,
967 .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
968 .clkr.hw.init = &(const struct clk_init_data) {
969 .name = "gcc_system_noc_bfdcd_clk_src",
970 .parent_data = gcc_parent_data_10,
971 .num_parents = ARRAY_SIZE(gcc_parent_data_10),
972 .ops = &clk_rcg2_ops,
973 },
974};
975
976static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
977 .mult = 1,
978 .div = 2,
979 .hw.init = &(struct clk_init_data) {
980 .name = "gcc_system_noc_bfdcd_div2_clk_src",
981 .parent_hws = (const struct clk_hw *[]) {
982 &gcc_system_noc_bfdcd_clk_src.clkr.hw },
983 .num_parents = 1,
984 .ops = &clk_fixed_factor_ops,
985 .flags = CLK_SET_RATE_PARENT,
986 },
987};
988
989static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
990 .cmd_rcgr = 0x16004,
991 .mnd_width = 0,
992 .hid_width = 5,
993 .parent_map = gcc_parent_map_xo,
994 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
995 .clkr.hw.init = &(const struct clk_init_data) {
996 .name = "gcc_uniphy_sys_clk_src",
997 .parent_data = &gcc_parent_data_xo,
998 .num_parents = 1,
999 .ops = &clk_rcg2_ops,
1000 },
1001};
1002
1003static struct clk_rcg2 gcc_usb0_aux_clk_src = {
1004 .cmd_rcgr = 0x2c018,
1005 .mnd_width = 16,
1006 .hid_width = 5,
1007 .parent_map = gcc_parent_map_11,
1008 .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
1009 .clkr.hw.init = &(const struct clk_init_data) {
1010 .name = "gcc_usb0_aux_clk_src",
1011 .parent_data = gcc_parent_data_11,
1012 .num_parents = ARRAY_SIZE(gcc_parent_data_11),
1013 .ops = &clk_rcg2_ops,
1014 },
1015};
1016
1017static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
1018 F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1019 { }
1020};
1021
1022static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
1023 .cmd_rcgr = 0x2c07c,
1024 .mnd_width = 8,
1025 .hid_width = 5,
1026 .parent_map = gcc_parent_map_1,
1027 .freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
1028 .clkr.hw.init = &(const struct clk_init_data) {
1029 .name = "gcc_usb0_lfps_clk_src",
1030 .parent_data = gcc_parent_data_1,
1031 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1032 .ops = &clk_rcg2_ops,
1033 },
1034};
1035
1036static struct clk_rcg2 gcc_usb0_master_clk_src = {
1037 .cmd_rcgr = 0x2c004,
1038 .mnd_width = 8,
1039 .hid_width = 5,
1040 .parent_map = gcc_parent_map_0,
1041 .freq_tbl = ftbl_gcc_gp1_clk_src,
1042 .clkr.hw.init = &(const struct clk_init_data) {
1043 .name = "gcc_usb0_master_clk_src",
1044 .parent_data = gcc_parent_data_0,
1045 .num_parents = ARRAY_SIZE(gcc_parent_data_0),
1046 .ops = &clk_rcg2_ops,
1047 },
1048};
1049
1050static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
1051 F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
1052 { }
1053};
1054
1055static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
1056 .cmd_rcgr = 0x2c02c,
1057 .mnd_width = 8,
1058 .hid_width = 5,
1059 .parent_map = gcc_parent_map_12,
1060 .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
1061 .clkr.hw.init = &(const struct clk_init_data) {
1062 .name = "gcc_usb0_mock_utmi_clk_src",
1063 .parent_data = gcc_parent_data_12,
1064 .num_parents = ARRAY_SIZE(gcc_parent_data_12),
1065 .ops = &clk_rcg2_ops,
1066 },
1067};
1068
1069static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {
1070 .reg = 0x2c074,
1071 .clkr = {
1072 .hw.init = &(struct clk_init_data) {
1073 .name = "gcc_usb0_pipe_clk_src",
1074 .parent_data = &(const struct clk_parent_data) {
1075 .index = DT_USB_PCIE_WRAPPER_PIPE_CLK,
1076 },
1077 .num_parents = 1,
1078 .ops = &clk_regmap_phy_mux_ops,
1079 },
1080 },
1081};
1082
1083static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
1084 .cmd_rcgr = 0x25030,
1085 .mnd_width = 0,
1086 .hid_width = 5,
1087 .parent_map = gcc_parent_map_1,
1088 .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
1089 .clkr.hw.init = &(const struct clk_init_data) {
1090 .name = "gcc_wcss_ahb_clk_src",
1091 .parent_data = gcc_parent_data_1,
1092 .num_parents = ARRAY_SIZE(gcc_parent_data_1),
1093 .ops = &clk_rcg2_ops,
1094 },
1095};
1096
1097static struct clk_rcg2 gcc_xo_clk_src = {
1098 .cmd_rcgr = 0x34004,
1099 .mnd_width = 0,
1100 .hid_width = 5,
1101 .parent_map = gcc_parent_map_xo,
1102 .freq_tbl = ftbl_gcc_nss_ts_clk_src,
1103 .clkr.hw.init = &(const struct clk_init_data) {
1104 .name = "gcc_xo_clk_src",
1105 .parent_data = &gcc_parent_data_xo,
1106 .num_parents = 1,
1107 .ops = &clk_rcg2_ops,
1108 },
1109};
1110
1111static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1112 .mult = 1,
1113 .div = 4,
1114 .hw.init = &(struct clk_init_data) {
1115 .name = "gcc_xo_div4_clk_src",
1116 .parent_hws = (const struct clk_hw *[]) {
1117 &gcc_xo_clk_src.clkr.hw },
1118 .num_parents = 1,
1119 .ops = &clk_fixed_factor_ops,
1120 .flags = CLK_SET_RATE_PARENT,
1121 },
1122};
1123
1124static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
1125 .reg = 0x2d028,
1126 .shift = 0,
1127 .width = 4,
1128 .clkr.hw.init = &(const struct clk_init_data) {
1129 .name = "gcc_qdss_dap_div_clk_src",
1130 .parent_hws = (const struct clk_hw*[]) {
1131 &gcc_qdss_tsctr_clk_src.clkr.hw,
1132 },
1133 .num_parents = 1,
1134 .ops = &clk_regmap_div_ro_ops,
1135 },
1136};
1137
1138static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
1139 .reg = 0x2c040,
1140 .shift = 0,
1141 .width = 2,
1142 .clkr.hw.init = &(const struct clk_init_data) {
1143 .name = "gcc_usb0_mock_utmi_div_clk_src",
1144 .parent_hws = (const struct clk_hw*[]) {
1145 &gcc_usb0_mock_utmi_clk_src.clkr.hw,
1146 },
1147 .num_parents = 1,
1148 .flags = CLK_SET_RATE_PARENT,
1149 .ops = &clk_regmap_div_ro_ops,
1150 },
1151};
1152
1153static struct clk_branch gcc_adss_pwm_clk = {
1154 .halt_reg = 0x1c00c,
1155 .halt_check = BRANCH_HALT,
1156 .clkr = {
1157 .enable_reg = 0x1c00c,
1158 .enable_mask = BIT(0),
1159 .hw.init = &(const struct clk_init_data) {
1160 .name = "gcc_adss_pwm_clk",
1161 .parent_hws = (const struct clk_hw*[]) {
1162 &gcc_adss_pwm_clk_src.clkr.hw,
1163 },
1164 .num_parents = 1,
1165 .flags = CLK_SET_RATE_PARENT,
1166 .ops = &clk_branch2_ops,
1167 },
1168 },
1169};
1170
1171static struct clk_branch gcc_ahb_clk = {
1172 .halt_reg = 0x34024,
1173 .halt_check = BRANCH_HALT_VOTED,
1174 .clkr = {
1175 .enable_reg = 0x34024,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(const struct clk_init_data) {
1178 .name = "gcc_ahb_clk",
1179 .parent_hws = (const struct clk_hw*[]) {
1180 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1181 },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_blsp1_ahb_clk = {
1190 .halt_reg = 0x1008,
1191 .halt_check = BRANCH_HALT_VOTED,
1192 .clkr = {
1193 .enable_reg = 0xb004,
1194 .enable_mask = BIT(4),
1195 .hw.init = &(const struct clk_init_data) {
1196 .name = "gcc_blsp1_ahb_clk",
1197 .parent_hws = (const struct clk_hw*[]) {
1198 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1199 },
1200 .num_parents = 1,
1201 .flags = CLK_SET_RATE_PARENT,
1202 .ops = &clk_branch2_ops,
1203 },
1204 },
1205};
1206
1207static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1208 .halt_reg = 0x2024,
1209 .halt_check = BRANCH_HALT,
1210 .clkr = {
1211 .enable_reg = 0x2024,
1212 .enable_mask = BIT(0),
1213 .hw.init = &(const struct clk_init_data) {
1214 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1215 .parent_hws = (const struct clk_hw*[]) {
1216 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1217 },
1218 .num_parents = 1,
1219 .flags = CLK_SET_RATE_PARENT,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223};
1224
1225static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1226 .halt_reg = 0x2020,
1227 .halt_check = BRANCH_HALT,
1228 .clkr = {
1229 .enable_reg = 0x2020,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(const struct clk_init_data) {
1232 .name = "gcc_blsp1_qup1_spi_apps_clk",
1233 .parent_hws = (const struct clk_hw*[]) {
1234 &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
1235 },
1236 .num_parents = 1,
1237 .flags = CLK_SET_RATE_PARENT,
1238 .ops = &clk_branch2_ops,
1239 },
1240 },
1241};
1242
1243static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1244 .halt_reg = 0x3024,
1245 .halt_check = BRANCH_HALT,
1246 .clkr = {
1247 .enable_reg = 0x3024,
1248 .enable_mask = BIT(0),
1249 .hw.init = &(const struct clk_init_data) {
1250 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1251 .parent_hws = (const struct clk_hw*[]) {
1252 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1253 },
1254 .num_parents = 1,
1255 .flags = CLK_SET_RATE_PARENT,
1256 .ops = &clk_branch2_ops,
1257 },
1258 },
1259};
1260
1261static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1262 .halt_reg = 0x3020,
1263 .halt_check = BRANCH_HALT,
1264 .clkr = {
1265 .enable_reg = 0x3020,
1266 .enable_mask = BIT(0),
1267 .hw.init = &(const struct clk_init_data) {
1268 .name = "gcc_blsp1_qup2_spi_apps_clk",
1269 .parent_hws = (const struct clk_hw*[]) {
1270 &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
1271 },
1272 .num_parents = 1,
1273 .flags = CLK_SET_RATE_PARENT,
1274 .ops = &clk_branch2_ops,
1275 },
1276 },
1277};
1278
1279static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1280 .halt_reg = 0x4024,
1281 .halt_check = BRANCH_HALT,
1282 .clkr = {
1283 .enable_reg = 0x4024,
1284 .enable_mask = BIT(0),
1285 .hw.init = &(const struct clk_init_data) {
1286 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1287 .parent_hws = (const struct clk_hw*[]) {
1288 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1289 },
1290 .num_parents = 1,
1291 .flags = CLK_SET_RATE_PARENT,
1292 .ops = &clk_branch2_ops,
1293 },
1294 },
1295};
1296
1297static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1298 .halt_reg = 0x4020,
1299 .halt_check = BRANCH_HALT,
1300 .clkr = {
1301 .enable_reg = 0x4020,
1302 .enable_mask = BIT(0),
1303 .hw.init = &(const struct clk_init_data) {
1304 .name = "gcc_blsp1_qup3_spi_apps_clk",
1305 .parent_hws = (const struct clk_hw*[]) {
1306 &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
1307 },
1308 .num_parents = 1,
1309 .flags = CLK_SET_RATE_PARENT,
1310 .ops = &clk_branch2_ops,
1311 },
1312 },
1313};
1314
1315static struct clk_branch gcc_blsp1_sleep_clk = {
1316 .halt_reg = 0x1010,
1317 .halt_check = BRANCH_HALT_VOTED,
1318 .clkr = {
1319 .enable_reg = 0xb004,
1320 .enable_mask = BIT(5),
1321 .hw.init = &(const struct clk_init_data) {
1322 .name = "gcc_blsp1_sleep_clk",
1323 .parent_hws = (const struct clk_hw*[]) {
1324 &gcc_sleep_clk_src.clkr.hw,
1325 },
1326 .num_parents = 1,
1327 .flags = CLK_SET_RATE_PARENT,
1328 .ops = &clk_branch2_ops,
1329 },
1330 },
1331};
1332
1333static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1334 .halt_reg = 0x2040,
1335 .halt_check = BRANCH_HALT,
1336 .clkr = {
1337 .enable_reg = 0x2040,
1338 .enable_mask = BIT(0),
1339 .hw.init = &(const struct clk_init_data) {
1340 .name = "gcc_blsp1_uart1_apps_clk",
1341 .parent_hws = (const struct clk_hw*[]) {
1342 &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
1343 },
1344 .num_parents = 1,
1345 .flags = CLK_SET_RATE_PARENT,
1346 .ops = &clk_branch2_ops,
1347 },
1348 },
1349};
1350
1351static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1352 .halt_reg = 0x3040,
1353 .halt_check = BRANCH_HALT,
1354 .clkr = {
1355 .enable_reg = 0x3040,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(const struct clk_init_data) {
1358 .name = "gcc_blsp1_uart2_apps_clk",
1359 .parent_hws = (const struct clk_hw*[]) {
1360 &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
1361 },
1362 .num_parents = 1,
1363 .flags = CLK_SET_RATE_PARENT,
1364 .ops = &clk_branch2_ops,
1365 },
1366 },
1367};
1368
1369static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1370 .halt_reg = 0x4054,
1371 .halt_check = BRANCH_HALT,
1372 .clkr = {
1373 .enable_reg = 0x4054,
1374 .enable_mask = BIT(0),
1375 .hw.init = &(const struct clk_init_data) {
1376 .name = "gcc_blsp1_uart3_apps_clk",
1377 .parent_hws = (const struct clk_hw*[]) {
1378 &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
1379 },
1380 .num_parents = 1,
1381 .flags = CLK_SET_RATE_PARENT,
1382 .ops = &clk_branch2_ops,
1383 },
1384 },
1385};
1386
1387static struct clk_branch gcc_ce_ahb_clk = {
1388 .halt_reg = 0x25074,
1389 .halt_check = BRANCH_HALT,
1390 .clkr = {
1391 .enable_reg = 0x25074,
1392 .enable_mask = BIT(0),
1393 .hw.init = &(const struct clk_init_data) {
1394 .name = "gcc_ce_ahb_clk",
1395 .parent_hws = (const struct clk_hw*[]) {
1396 &gcc_system_noc_bfdcd_div2_clk_src.hw,
1397 },
1398 .num_parents = 1,
1399 .flags = CLK_SET_RATE_PARENT,
1400 .ops = &clk_branch2_ops,
1401 },
1402 },
1403};
1404
1405static struct clk_branch gcc_ce_axi_clk = {
1406 .halt_reg = 0x25068,
1407 .halt_check = BRANCH_HALT,
1408 .clkr = {
1409 .enable_reg = 0x25068,
1410 .enable_mask = BIT(0),
1411 .hw.init = &(const struct clk_init_data) {
1412 .name = "gcc_ce_axi_clk",
1413 .parent_hws = (const struct clk_hw*[]) {
1414 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1415 },
1416 .num_parents = 1,
1417 .flags = CLK_SET_RATE_PARENT,
1418 .ops = &clk_branch2_ops,
1419 },
1420 },
1421};
1422
1423static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
1424 .halt_reg = 0x25070,
1425 .halt_check = BRANCH_HALT,
1426 .clkr = {
1427 .enable_reg = 0x25070,
1428 .enable_mask = BIT(0),
1429 .hw.init = &(const struct clk_init_data) {
1430 .name = "gcc_ce_pcnoc_ahb_clk",
1431 .parent_hws = (const struct clk_hw*[]) {
1432 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1433 },
1434 .num_parents = 1,
1435 .flags = CLK_SET_RATE_PARENT,
1436 .ops = &clk_branch2_ops,
1437 },
1438 },
1439};
1440
1441static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
1442 .halt_reg = 0x3a004,
1443 .halt_check = BRANCH_HALT,
1444 .clkr = {
1445 .enable_reg = 0x3a004,
1446 .enable_mask = BIT(0),
1447 .hw.init = &(const struct clk_init_data) {
1448 .name = "gcc_cmn_12gpll_ahb_clk",
1449 .parent_hws = (const struct clk_hw*[]) {
1450 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1451 },
1452 .num_parents = 1,
1453 .flags = CLK_SET_RATE_PARENT,
1454 .ops = &clk_branch2_ops,
1455 },
1456 },
1457};
1458
1459static struct clk_branch gcc_cmn_12gpll_apu_clk = {
1460 .halt_reg = 0x3a00c,
1461 .halt_check = BRANCH_HALT,
1462 .clkr = {
1463 .enable_reg = 0x3a00c,
1464 .enable_mask = BIT(0),
1465 .hw.init = &(const struct clk_init_data) {
1466 .name = "gcc_cmn_12gpll_apu_clk",
1467 .parent_hws = (const struct clk_hw*[]) {
1468 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1469 },
1470 .num_parents = 1,
1471 .flags = CLK_SET_RATE_PARENT,
1472 .ops = &clk_branch2_ops,
1473 },
1474 },
1475};
1476
1477static struct clk_branch gcc_cmn_12gpll_sys_clk = {
1478 .halt_reg = 0x3a008,
1479 .halt_check = BRANCH_HALT,
1480 .clkr = {
1481 .enable_reg = 0x3a008,
1482 .enable_mask = BIT(0),
1483 .hw.init = &(const struct clk_init_data) {
1484 .name = "gcc_cmn_12gpll_sys_clk",
1485 .parent_hws = (const struct clk_hw*[]) {
1486 &gcc_uniphy_sys_clk_src.clkr.hw,
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 .ops = &clk_branch2_ops,
1491 },
1492 },
1493};
1494
1495static struct clk_branch gcc_gp1_clk = {
1496 .halt_reg = 0x8018,
1497 .halt_check = BRANCH_HALT,
1498 .clkr = {
1499 .enable_reg = 0x8018,
1500 .enable_mask = BIT(0),
1501 .hw.init = &(const struct clk_init_data) {
1502 .name = "gcc_gp1_clk",
1503 .parent_hws = (const struct clk_hw*[]) {
1504 &gcc_gp1_clk_src.clkr.hw,
1505 },
1506 .num_parents = 1,
1507 .flags = CLK_SET_RATE_PARENT,
1508 .ops = &clk_branch2_ops,
1509 },
1510 },
1511};
1512
1513static struct clk_branch gcc_gp2_clk = {
1514 .halt_reg = 0x9018,
1515 .halt_check = BRANCH_HALT,
1516 .clkr = {
1517 .enable_reg = 0x9018,
1518 .enable_mask = BIT(0),
1519 .hw.init = &(const struct clk_init_data) {
1520 .name = "gcc_gp2_clk",
1521 .parent_hws = (const struct clk_hw*[]) {
1522 &gcc_gp2_clk_src.clkr.hw,
1523 },
1524 .num_parents = 1,
1525 .flags = CLK_SET_RATE_PARENT,
1526 .ops = &clk_branch2_ops,
1527 },
1528 },
1529};
1530
1531static struct clk_branch gcc_lpass_core_axim_clk = {
1532 .halt_reg = 0x27018,
1533 .halt_check = BRANCH_HALT_VOTED,
1534 .clkr = {
1535 .enable_reg = 0x27018,
1536 .enable_mask = BIT(0),
1537 .hw.init = &(const struct clk_init_data) {
1538 .name = "gcc_lpass_core_axim_clk",
1539 .parent_hws = (const struct clk_hw*[]) {
1540 &gcc_lpass_sway_clk_src.clkr.hw,
1541 },
1542 .num_parents = 1,
1543 .flags = CLK_SET_RATE_PARENT,
1544 .ops = &clk_branch2_ops,
1545 },
1546 },
1547};
1548
1549static struct clk_branch gcc_lpass_sway_clk = {
1550 .halt_reg = 0x27014,
1551 .halt_check = BRANCH_HALT,
1552 .clkr = {
1553 .enable_reg = 0x27014,
1554 .enable_mask = BIT(0),
1555 .hw.init = &(const struct clk_init_data) {
1556 .name = "gcc_lpass_sway_clk",
1557 .parent_hws = (const struct clk_hw*[]) {
1558 &gcc_lpass_sway_clk_src.clkr.hw,
1559 },
1560 .num_parents = 1,
1561 .flags = CLK_SET_RATE_PARENT,
1562 .ops = &clk_branch2_ops,
1563 },
1564 },
1565};
1566
1567static struct clk_branch gcc_mdio_ahb_clk = {
1568 .halt_reg = 0x12004,
1569 .halt_check = BRANCH_HALT,
1570 .clkr = {
1571 .enable_reg = 0x12004,
1572 .enable_mask = BIT(0),
1573 .hw.init = &(const struct clk_init_data) {
1574 .name = "gcc_mdio_ahb_clk",
1575 .parent_hws = (const struct clk_hw*[]) {
1576 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1577 },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583};
1584
1585static struct clk_branch gcc_mdio_slave_ahb_clk = {
1586 .halt_reg = 0x1200c,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x1200c,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(const struct clk_init_data) {
1592 .name = "gcc_mdio_slave_ahb_clk",
1593 .parent_hws = (const struct clk_hw*[]) {
1594 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1595 },
1596 .num_parents = 1,
1597 .flags = CLK_SET_RATE_PARENT,
1598 .ops = &clk_branch2_ops,
1599 },
1600 },
1601};
1602
1603static struct clk_branch gcc_nss_ts_clk = {
1604 .halt_reg = 0x17018,
1605 .halt_check = BRANCH_HALT_VOTED,
1606 .clkr = {
1607 .enable_reg = 0x17018,
1608 .enable_mask = BIT(0),
1609 .hw.init = &(const struct clk_init_data) {
1610 .name = "gcc_nss_ts_clk",
1611 .parent_hws = (const struct clk_hw*[]) {
1612 &gcc_nss_ts_clk_src.clkr.hw,
1613 },
1614 .num_parents = 1,
1615 .flags = CLK_SET_RATE_PARENT,
1616 .ops = &clk_branch2_ops,
1617 },
1618 },
1619};
1620
1621static struct clk_branch gcc_nsscc_clk = {
1622 .halt_reg = 0x17034,
1623 .halt_check = BRANCH_HALT,
1624 .clkr = {
1625 .enable_reg = 0x17034,
1626 .enable_mask = BIT(0),
1627 .hw.init = &(const struct clk_init_data) {
1628 .name = "gcc_nsscc_clk",
1629 .parent_hws = (const struct clk_hw*[]) {
1630 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1631 },
1632 .num_parents = 1,
1633 .flags = CLK_SET_RATE_PARENT,
1634 .ops = &clk_branch2_ops,
1635 },
1636 },
1637};
1638
1639static struct clk_branch gcc_nsscfg_clk = {
1640 .halt_reg = 0x1702c,
1641 .halt_check = BRANCH_HALT,
1642 .clkr = {
1643 .enable_reg = 0x1702c,
1644 .enable_mask = BIT(0),
1645 .hw.init = &(const struct clk_init_data) {
1646 .name = "gcc_nsscfg_clk",
1647 .parent_hws = (const struct clk_hw*[]) {
1648 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1649 },
1650 .num_parents = 1,
1651 .flags = CLK_SET_RATE_PARENT,
1652 .ops = &clk_branch2_ops,
1653 },
1654 },
1655};
1656
1657static struct clk_branch gcc_nssnoc_atb_clk = {
1658 .halt_reg = 0x17014,
1659 .halt_check = BRANCH_HALT,
1660 .clkr = {
1661 .enable_reg = 0x17014,
1662 .enable_mask = BIT(0),
1663 .hw.init = &(const struct clk_init_data) {
1664 .name = "gcc_nssnoc_atb_clk",
1665 .parent_hws = (const struct clk_hw*[]) {
1666 &gcc_qdss_at_clk_src.clkr.hw,
1667 },
1668 .num_parents = 1,
1669 .flags = CLK_SET_RATE_PARENT,
1670 .ops = &clk_branch2_ops,
1671 },
1672 },
1673};
1674
1675static struct clk_branch gcc_nssnoc_nsscc_clk = {
1676 .halt_reg = 0x17030,
1677 .halt_check = BRANCH_HALT,
1678 .clkr = {
1679 .enable_reg = 0x17030,
1680 .enable_mask = BIT(0),
1681 .hw.init = &(const struct clk_init_data) {
1682 .name = "gcc_nssnoc_nsscc_clk",
1683 .parent_hws = (const struct clk_hw*[]) {
1684 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1685 },
1686 .num_parents = 1,
1687 .flags = CLK_SET_RATE_PARENT,
1688 .ops = &clk_branch2_ops,
1689 },
1690 },
1691};
1692
1693static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
1694 .halt_reg = 0x1701c,
1695 .halt_check = BRANCH_HALT,
1696 .clkr = {
1697 .enable_reg = 0x1701c,
1698 .enable_mask = BIT(0),
1699 .hw.init = &(const struct clk_init_data) {
1700 .name = "gcc_nssnoc_qosgen_ref_clk",
1701 .parent_hws = (const struct clk_hw*[]) {
1702 &gcc_xo_div4_clk_src.hw,
1703 },
1704 .num_parents = 1,
1705 .flags = CLK_SET_RATE_PARENT,
1706 .ops = &clk_branch2_ops,
1707 },
1708 },
1709};
1710
1711static struct clk_branch gcc_nssnoc_snoc_1_clk = {
1712 .halt_reg = 0x1707c,
1713 .halt_check = BRANCH_HALT,
1714 .clkr = {
1715 .enable_reg = 0x1707c,
1716 .enable_mask = BIT(0),
1717 .hw.init = &(const struct clk_init_data) {
1718 .name = "gcc_nssnoc_snoc_1_clk",
1719 .parent_hws = (const struct clk_hw*[]) {
1720 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1721 },
1722 .num_parents = 1,
1723 .flags = CLK_SET_RATE_PARENT,
1724 .ops = &clk_branch2_ops,
1725 },
1726 },
1727};
1728
1729static struct clk_branch gcc_nssnoc_snoc_clk = {
1730 .halt_reg = 0x17028,
1731 .halt_check = BRANCH_HALT,
1732 .clkr = {
1733 .enable_reg = 0x17028,
1734 .enable_mask = BIT(0),
1735 .hw.init = &(const struct clk_init_data) {
1736 .name = "gcc_nssnoc_snoc_clk",
1737 .parent_hws = (const struct clk_hw*[]) {
1738 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
1739 },
1740 .num_parents = 1,
1741 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops,
1743 },
1744 },
1745};
1746
1747static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
1748 .halt_reg = 0x17020,
1749 .halt_check = BRANCH_HALT,
1750 .clkr = {
1751 .enable_reg = 0x17020,
1752 .enable_mask = BIT(0),
1753 .hw.init = &(const struct clk_init_data) {
1754 .name = "gcc_nssnoc_timeout_ref_clk",
1755 .parent_hws = (const struct clk_hw*[]) {
1756 &gcc_xo_div4_clk_src.hw,
1757 },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
1766 .halt_reg = 0x17074,
1767 .halt_check = BRANCH_HALT,
1768 .clkr = {
1769 .enable_reg = 0x17074,
1770 .enable_mask = BIT(0),
1771 .hw.init = &(const struct clk_init_data) {
1772 .name = "gcc_nssnoc_xo_dcd_clk",
1773 .parent_hws = (const struct clk_hw*[]) {
1774 &gcc_xo_clk_src.clkr.hw,
1775 },
1776 .num_parents = 1,
1777 .flags = CLK_SET_RATE_PARENT,
1778 .ops = &clk_branch2_ops,
1779 },
1780 },
1781};
1782
1783static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
1784 .halt_reg = 0x29030,
1785 .halt_check = BRANCH_HALT,
1786 .clkr = {
1787 .enable_reg = 0x29030,
1788 .enable_mask = BIT(0),
1789 .hw.init = &(const struct clk_init_data) {
1790 .name = "gcc_pcie3x1_0_ahb_clk",
1791 .parent_hws = (const struct clk_hw*[]) {
1792 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1793 },
1794 .num_parents = 1,
1795 .flags = CLK_SET_RATE_PARENT,
1796 .ops = &clk_branch2_ops,
1797 },
1798 },
1799};
1800
1801static struct clk_branch gcc_pcie3x1_0_aux_clk = {
1802 .halt_reg = 0x29070,
1803 .halt_check = BRANCH_HALT,
1804 .clkr = {
1805 .enable_reg = 0x29070,
1806 .enable_mask = BIT(0),
1807 .hw.init = &(const struct clk_init_data) {
1808 .name = "gcc_pcie3x1_0_aux_clk",
1809 .parent_hws = (const struct clk_hw*[]) {
1810 &gcc_pcie_aux_clk_src.clkr.hw,
1811 },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 .ops = &clk_branch2_ops,
1815 },
1816 },
1817};
1818
1819static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
1820 .halt_reg = 0x29038,
1821 .halt_check = BRANCH_HALT,
1822 .clkr = {
1823 .enable_reg = 0x29038,
1824 .enable_mask = BIT(0),
1825 .hw.init = &(const struct clk_init_data) {
1826 .name = "gcc_pcie3x1_0_axi_m_clk",
1827 .parent_hws = (const struct clk_hw*[]) {
1828 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1829 },
1830 .num_parents = 1,
1831 .flags = CLK_SET_RATE_PARENT,
1832 .ops = &clk_branch2_ops,
1833 },
1834 },
1835};
1836
1837static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
1838 .halt_reg = 0x29048,
1839 .halt_check = BRANCH_HALT,
1840 .clkr = {
1841 .enable_reg = 0x29048,
1842 .enable_mask = BIT(0),
1843 .hw.init = &(const struct clk_init_data) {
1844 .name = "gcc_pcie3x1_0_axi_s_bridge_clk",
1845 .parent_hws = (const struct clk_hw*[]) {
1846 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1847 },
1848 .num_parents = 1,
1849 .flags = CLK_SET_RATE_PARENT,
1850 .ops = &clk_branch2_ops,
1851 },
1852 },
1853};
1854
1855static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
1856 .halt_reg = 0x29040,
1857 .halt_check = BRANCH_HALT,
1858 .clkr = {
1859 .enable_reg = 0x29040,
1860 .enable_mask = BIT(0),
1861 .hw.init = &(const struct clk_init_data) {
1862 .name = "gcc_pcie3x1_0_axi_s_clk",
1863 .parent_hws = (const struct clk_hw*[]) {
1864 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
1865 },
1866 .num_parents = 1,
1867 .flags = CLK_SET_RATE_PARENT,
1868 .ops = &clk_branch2_ops,
1869 },
1870 },
1871};
1872
1873static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
1874 .halt_reg = 0x29068,
1875 .halt_check = BRANCH_HALT_DELAY,
1876 .clkr = {
1877 .enable_reg = 0x29068,
1878 .enable_mask = BIT(0),
1879 .hw.init = &(const struct clk_init_data) {
1880 .name = "gcc_pcie3x1_0_pipe_clk",
1881 .parent_hws = (const struct clk_hw*[]) {
1882 &gcc_pcie3x1_0_pipe_clk_src.clkr.hw,
1883 },
1884 .num_parents = 1,
1885 .flags = CLK_SET_RATE_PARENT,
1886 .ops = &clk_branch2_ops,
1887 },
1888 },
1889};
1890
1891static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
1892 .halt_reg = 0x2a00c,
1893 .halt_check = BRANCH_HALT,
1894 .clkr = {
1895 .enable_reg = 0x2a00c,
1896 .enable_mask = BIT(0),
1897 .hw.init = &(const struct clk_init_data) {
1898 .name = "gcc_pcie3x1_1_ahb_clk",
1899 .parent_hws = (const struct clk_hw*[]) {
1900 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
1901 },
1902 .num_parents = 1,
1903 .flags = CLK_SET_RATE_PARENT,
1904 .ops = &clk_branch2_ops,
1905 },
1906 },
1907};
1908
1909static struct clk_branch gcc_pcie3x1_1_aux_clk = {
1910 .halt_reg = 0x2a070,
1911 .halt_check = BRANCH_HALT,
1912 .clkr = {
1913 .enable_reg = 0x2a070,
1914 .enable_mask = BIT(0),
1915 .hw.init = &(const struct clk_init_data) {
1916 .name = "gcc_pcie3x1_1_aux_clk",
1917 .parent_hws = (const struct clk_hw*[]) {
1918 &gcc_pcie_aux_clk_src.clkr.hw,
1919 },
1920 .num_parents = 1,
1921 .flags = CLK_SET_RATE_PARENT,
1922 .ops = &clk_branch2_ops,
1923 },
1924 },
1925};
1926
1927static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
1928 .halt_reg = 0x2a014,
1929 .halt_check = BRANCH_HALT,
1930 .clkr = {
1931 .enable_reg = 0x2a014,
1932 .enable_mask = BIT(0),
1933 .hw.init = &(const struct clk_init_data) {
1934 .name = "gcc_pcie3x1_1_axi_m_clk",
1935 .parent_hws = (const struct clk_hw*[]) {
1936 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1937 },
1938 .num_parents = 1,
1939 .flags = CLK_SET_RATE_PARENT,
1940 .ops = &clk_branch2_ops,
1941 },
1942 },
1943};
1944
1945static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
1946 .halt_reg = 0x2a024,
1947 .halt_check = BRANCH_HALT,
1948 .clkr = {
1949 .enable_reg = 0x2a024,
1950 .enable_mask = BIT(0),
1951 .hw.init = &(const struct clk_init_data) {
1952 .name = "gcc_pcie3x1_1_axi_s_bridge_clk",
1953 .parent_hws = (const struct clk_hw*[]) {
1954 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1955 },
1956 .num_parents = 1,
1957 .flags = CLK_SET_RATE_PARENT,
1958 .ops = &clk_branch2_ops,
1959 },
1960 },
1961};
1962
1963static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
1964 .halt_reg = 0x2a01c,
1965 .halt_check = BRANCH_HALT,
1966 .clkr = {
1967 .enable_reg = 0x2a01c,
1968 .enable_mask = BIT(0),
1969 .hw.init = &(const struct clk_init_data) {
1970 .name = "gcc_pcie3x1_1_axi_s_clk",
1971 .parent_hws = (const struct clk_hw*[]) {
1972 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
1973 },
1974 .num_parents = 1,
1975 .flags = CLK_SET_RATE_PARENT,
1976 .ops = &clk_branch2_ops,
1977 },
1978 },
1979};
1980
1981static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
1982 .halt_reg = 0x2a068,
1983 .halt_check = BRANCH_HALT_DELAY,
1984 .clkr = {
1985 .enable_reg = 0x2a068,
1986 .enable_mask = BIT(0),
1987 .hw.init = &(const struct clk_init_data) {
1988 .name = "gcc_pcie3x1_1_pipe_clk",
1989 .parent_hws = (const struct clk_hw*[]) {
1990 &gcc_pcie3x1_1_pipe_clk_src.clkr.hw,
1991 },
1992 .num_parents = 1,
1993 .flags = CLK_SET_RATE_PARENT,
1994 .ops = &clk_branch2_ops,
1995 },
1996 },
1997};
1998
1999static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
2000 .halt_reg = 0x29078,
2001 .halt_check = BRANCH_HALT,
2002 .clkr = {
2003 .enable_reg = 0x29078,
2004 .enable_mask = BIT(0),
2005 .hw.init = &(const struct clk_init_data) {
2006 .name = "gcc_pcie3x1_phy_ahb_clk",
2007 .parent_hws = (const struct clk_hw*[]) {
2008 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2009 },
2010 .num_parents = 1,
2011 .flags = CLK_SET_RATE_PARENT,
2012 .ops = &clk_branch2_ops,
2013 },
2014 },
2015};
2016
2017static struct clk_branch gcc_pcie3x2_ahb_clk = {
2018 .halt_reg = 0x28030,
2019 .halt_check = BRANCH_HALT,
2020 .clkr = {
2021 .enable_reg = 0x28030,
2022 .enable_mask = BIT(0),
2023 .hw.init = &(const struct clk_init_data) {
2024 .name = "gcc_pcie3x2_ahb_clk",
2025 .parent_hws = (const struct clk_hw*[]) {
2026 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2027 },
2028 .num_parents = 1,
2029 .flags = CLK_SET_RATE_PARENT,
2030 .ops = &clk_branch2_ops,
2031 },
2032 },
2033};
2034
2035static struct clk_branch gcc_pcie3x2_aux_clk = {
2036 .halt_reg = 0x28070,
2037 .halt_check = BRANCH_HALT,
2038 .clkr = {
2039 .enable_reg = 0x28070,
2040 .enable_mask = BIT(0),
2041 .hw.init = &(const struct clk_init_data) {
2042 .name = "gcc_pcie3x2_aux_clk",
2043 .parent_hws = (const struct clk_hw*[]) {
2044 &gcc_pcie_aux_clk_src.clkr.hw,
2045 },
2046 .num_parents = 1,
2047 .flags = CLK_SET_RATE_PARENT,
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_pcie3x2_axi_m_clk = {
2054 .halt_reg = 0x28038,
2055 .halt_check = BRANCH_HALT,
2056 .clkr = {
2057 .enable_reg = 0x28038,
2058 .enable_mask = BIT(0),
2059 .hw.init = &(const struct clk_init_data) {
2060 .name = "gcc_pcie3x2_axi_m_clk",
2061 .parent_hws = (const struct clk_hw*[]) {
2062 &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2063 },
2064 .num_parents = 1,
2065 .flags = CLK_SET_RATE_PARENT,
2066 .ops = &clk_branch2_ops,
2067 },
2068 },
2069};
2070
2071static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
2072 .halt_reg = 0x28048,
2073 .halt_check = BRANCH_HALT,
2074 .clkr = {
2075 .enable_reg = 0x28048,
2076 .enable_mask = BIT(0),
2077 .hw.init = &(const struct clk_init_data) {
2078 .name = "gcc_pcie3x2_axi_s_bridge_clk",
2079 .parent_hws = (const struct clk_hw*[]) {
2080 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2081 },
2082 .num_parents = 1,
2083 .flags = CLK_SET_RATE_PARENT,
2084 .ops = &clk_branch2_ops,
2085 },
2086 },
2087};
2088
2089static struct clk_branch gcc_pcie3x2_axi_s_clk = {
2090 .halt_reg = 0x28040,
2091 .halt_check = BRANCH_HALT,
2092 .clkr = {
2093 .enable_reg = 0x28040,
2094 .enable_mask = BIT(0),
2095 .hw.init = &(const struct clk_init_data) {
2096 .name = "gcc_pcie3x2_axi_s_clk",
2097 .parent_hws = (const struct clk_hw*[]) {
2098 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2099 },
2100 .num_parents = 1,
2101 .flags = CLK_SET_RATE_PARENT,
2102 .ops = &clk_branch2_ops,
2103 },
2104 },
2105};
2106
2107static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
2108 .halt_reg = 0x28080,
2109 .halt_check = BRANCH_HALT,
2110 .clkr = {
2111 .enable_reg = 0x28080,
2112 .enable_mask = BIT(0),
2113 .hw.init = &(const struct clk_init_data) {
2114 .name = "gcc_pcie3x2_phy_ahb_clk",
2115 .parent_hws = (const struct clk_hw*[]) {
2116 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2117 },
2118 .num_parents = 1,
2119 .flags = CLK_SET_RATE_PARENT,
2120 .ops = &clk_branch2_ops,
2121 },
2122 },
2123};
2124
2125static struct clk_branch gcc_pcie3x2_pipe_clk = {
2126 .halt_reg = 0x28068,
2127 .halt_check = BRANCH_HALT_DELAY,
2128 .clkr = {
2129 .enable_reg = 0x28068,
2130 .enable_mask = BIT(0),
2131 .hw.init = &(const struct clk_init_data) {
2132 .name = "gcc_pcie3x2_pipe_clk",
2133 .parent_hws = (const struct clk_hw*[]) {
2134 &gcc_pcie3x2_pipe_clk_src.clkr.hw,
2135 },
2136 .num_parents = 1,
2137 .flags = CLK_SET_RATE_PARENT,
2138 .ops = &clk_branch2_ops,
2139 },
2140 },
2141};
2142
2143static struct clk_branch gcc_pcnoc_at_clk = {
2144 .halt_reg = 0x31024,
2145 .halt_check = BRANCH_HALT_VOTED,
2146 .clkr = {
2147 .enable_reg = 0x31024,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(const struct clk_init_data) {
2150 .name = "gcc_pcnoc_at_clk",
2151 .parent_hws = (const struct clk_hw*[]) {
2152 &gcc_qdss_at_clk_src.clkr.hw,
2153 },
2154 .num_parents = 1,
2155 .flags = CLK_SET_RATE_PARENT,
2156 .ops = &clk_branch2_ops,
2157 },
2158 },
2159};
2160
2161static struct clk_branch gcc_pcnoc_lpass_clk = {
2162 .halt_reg = 0x31020,
2163 .halt_check = BRANCH_HALT,
2164 .clkr = {
2165 .enable_reg = 0x31020,
2166 .enable_mask = BIT(0),
2167 .hw.init = &(const struct clk_init_data) {
2168 .name = "gcc_pcnoc_lpass_clk",
2169 .parent_hws = (const struct clk_hw*[]) {
2170 &gcc_lpass_sway_clk_src.clkr.hw,
2171 },
2172 .num_parents = 1,
2173 .flags = CLK_SET_RATE_PARENT,
2174 .ops = &clk_branch2_ops,
2175 },
2176 },
2177};
2178
2179static struct clk_branch gcc_prng_ahb_clk = {
2180 .halt_reg = 0x13024,
2181 .halt_check = BRANCH_HALT_VOTED,
2182 .clkr = {
2183 .enable_reg = 0xb004,
2184 .enable_mask = BIT(10),
2185 .hw.init = &(const struct clk_init_data) {
2186 .name = "gcc_prng_ahb_clk",
2187 .parent_hws = (const struct clk_hw*[]) {
2188 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2189 },
2190 .num_parents = 1,
2191 .flags = CLK_SET_RATE_PARENT,
2192 .ops = &clk_branch2_ops,
2193 },
2194 },
2195};
2196
2197static struct clk_branch gcc_q6_ahb_clk = {
2198 .halt_reg = 0x25014,
2199 .halt_check = BRANCH_HALT_VOTED,
2200 .clkr = {
2201 .enable_reg = 0x25014,
2202 .enable_mask = BIT(0),
2203 .hw.init = &(const struct clk_init_data) {
2204 .name = "gcc_q6_ahb_clk",
2205 .parent_hws = (const struct clk_hw*[]) {
2206 &gcc_wcss_ahb_clk_src.clkr.hw,
2207 },
2208 .num_parents = 1,
2209 .flags = CLK_SET_RATE_PARENT,
2210 .ops = &clk_branch2_ops,
2211 },
2212 },
2213};
2214
2215static struct clk_branch gcc_q6_ahb_s_clk = {
2216 .halt_reg = 0x25018,
2217 .halt_check = BRANCH_HALT_VOTED,
2218 .clkr = {
2219 .enable_reg = 0x25018,
2220 .enable_mask = BIT(0),
2221 .hw.init = &(const struct clk_init_data) {
2222 .name = "gcc_q6_ahb_s_clk",
2223 .parent_hws = (const struct clk_hw*[]) {
2224 &gcc_wcss_ahb_clk_src.clkr.hw,
2225 },
2226 .num_parents = 1,
2227 .flags = CLK_SET_RATE_PARENT,
2228 .ops = &clk_branch2_ops,
2229 },
2230 },
2231};
2232
2233static struct clk_branch gcc_q6_axim_clk = {
2234 .halt_reg = 0x2500c,
2235 .halt_check = BRANCH_HALT_VOTED,
2236 .clkr = {
2237 .enable_reg = 0x2500c,
2238 .enable_mask = BIT(0),
2239 .hw.init = &(const struct clk_init_data) {
2240 .name = "gcc_q6_axim_clk",
2241 .parent_hws = (const struct clk_hw*[]) {
2242 &gcc_q6_axim_clk_src.clkr.hw,
2243 },
2244 .num_parents = 1,
2245 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops,
2247 },
2248 },
2249};
2250
2251static struct clk_branch gcc_q6_axis_clk = {
2252 .halt_reg = 0x25010,
2253 .halt_check = BRANCH_HALT_VOTED,
2254 .clkr = {
2255 .enable_reg = 0x25010,
2256 .enable_mask = BIT(0),
2257 .hw.init = &(const struct clk_init_data) {
2258 .name = "gcc_q6_axis_clk",
2259 .parent_hws = (const struct clk_hw*[]) {
2260 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2261 },
2262 .num_parents = 1,
2263 .flags = CLK_SET_RATE_PARENT,
2264 .ops = &clk_branch2_ops,
2265 },
2266 },
2267};
2268
2269static struct clk_branch gcc_q6_tsctr_1to2_clk = {
2270 .halt_reg = 0x25020,
2271 .halt_check = BRANCH_HALT_VOTED,
2272 .clkr = {
2273 .enable_reg = 0x25020,
2274 .enable_mask = BIT(0),
2275 .hw.init = &(const struct clk_init_data) {
2276 .name = "gcc_q6_tsctr_1to2_clk",
2277 .parent_hws = (const struct clk_hw*[]) {
2278 &gcc_qdss_tsctr_div2_clk_src.hw,
2279 },
2280 .num_parents = 1,
2281 .flags = CLK_SET_RATE_PARENT,
2282 .ops = &clk_branch2_ops,
2283 },
2284 },
2285};
2286
2287static struct clk_branch gcc_q6ss_atbm_clk = {
2288 .halt_reg = 0x2501c,
2289 .halt_check = BRANCH_HALT_VOTED,
2290 .clkr = {
2291 .enable_reg = 0x2501c,
2292 .enable_mask = BIT(0),
2293 .hw.init = &(const struct clk_init_data) {
2294 .name = "gcc_q6ss_atbm_clk",
2295 .parent_hws = (const struct clk_hw*[]) {
2296 &gcc_qdss_at_clk_src.clkr.hw,
2297 },
2298 .num_parents = 1,
2299 .flags = CLK_SET_RATE_PARENT,
2300 .ops = &clk_branch2_ops,
2301 },
2302 },
2303};
2304
2305static struct clk_branch gcc_q6ss_pclkdbg_clk = {
2306 .halt_reg = 0x25024,
2307 .halt_check = BRANCH_HALT_VOTED,
2308 .clkr = {
2309 .enable_reg = 0x25024,
2310 .enable_mask = BIT(0),
2311 .hw.init = &(const struct clk_init_data) {
2312 .name = "gcc_q6ss_pclkdbg_clk",
2313 .parent_hws = (const struct clk_hw*[]) {
2314 &gcc_qdss_dap_div_clk_src.clkr.hw,
2315 },
2316 .num_parents = 1,
2317 .flags = CLK_SET_RATE_PARENT,
2318 .ops = &clk_branch2_ops,
2319 },
2320 },
2321};
2322
2323static struct clk_branch gcc_q6ss_trig_clk = {
2324 .halt_reg = 0x250a0,
2325 .halt_check = BRANCH_HALT_VOTED,
2326 .clkr = {
2327 .enable_reg = 0x250a0,
2328 .enable_mask = BIT(0),
2329 .hw.init = &(const struct clk_init_data) {
2330 .name = "gcc_q6ss_trig_clk",
2331 .parent_hws = (const struct clk_hw*[]) {
2332 &gcc_qdss_dap_div_clk_src.clkr.hw,
2333 },
2334 .num_parents = 1,
2335 .flags = CLK_SET_RATE_PARENT,
2336 .ops = &clk_branch2_ops,
2337 },
2338 },
2339};
2340
2341static struct clk_branch gcc_qdss_at_clk = {
2342 .halt_reg = 0x2d038,
2343 .halt_check = BRANCH_HALT_VOTED,
2344 .clkr = {
2345 .enable_reg = 0x2d038,
2346 .enable_mask = BIT(0),
2347 .hw.init = &(const struct clk_init_data) {
2348 .name = "gcc_qdss_at_clk",
2349 .parent_hws = (const struct clk_hw*[]) {
2350 &gcc_qdss_at_clk_src.clkr.hw,
2351 },
2352 .num_parents = 1,
2353 .flags = CLK_SET_RATE_PARENT,
2354 .ops = &clk_branch2_ops,
2355 },
2356 },
2357};
2358
2359static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2360 .halt_reg = 0x2d06c,
2361 .halt_check = BRANCH_HALT_VOTED,
2362 .clkr = {
2363 .enable_reg = 0x2d06c,
2364 .enable_mask = BIT(0),
2365 .hw.init = &(const struct clk_init_data) {
2366 .name = "gcc_qdss_cfg_ahb_clk",
2367 .parent_hws = (const struct clk_hw*[]) {
2368 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2369 },
2370 .num_parents = 1,
2371 .flags = CLK_SET_RATE_PARENT,
2372 .ops = &clk_branch2_ops,
2373 },
2374 },
2375};
2376
2377static struct clk_branch gcc_qdss_dap_ahb_clk = {
2378 .halt_reg = 0x2d068,
2379 .halt_check = BRANCH_HALT_VOTED,
2380 .clkr = {
2381 .enable_reg = 0x2d068,
2382 .enable_mask = BIT(0),
2383 .hw.init = &(const struct clk_init_data) {
2384 .name = "gcc_qdss_dap_ahb_clk",
2385 .parent_hws = (const struct clk_hw*[]) {
2386 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2387 },
2388 .num_parents = 1,
2389 .flags = CLK_SET_RATE_PARENT,
2390 .ops = &clk_branch2_ops,
2391 },
2392 },
2393};
2394
2395static struct clk_branch gcc_qdss_dap_clk = {
2396 .halt_reg = 0x2d05c,
2397 .halt_check = BRANCH_HALT_VOTED,
2398 .clkr = {
2399 .enable_reg = 0xb004,
2400 .enable_mask = BIT(2),
2401 .hw.init = &(const struct clk_init_data) {
2402 .name = "gcc_qdss_dap_clk",
2403 .parent_hws = (const struct clk_hw*[]) {
2404 &gcc_qdss_dap_div_clk_src.clkr.hw,
2405 },
2406 .num_parents = 1,
2407 .flags = CLK_SET_RATE_PARENT,
2408 .ops = &clk_branch2_ops,
2409 },
2410 },
2411};
2412
2413static struct clk_branch gcc_qdss_etr_usb_clk = {
2414 .halt_reg = 0x2d064,
2415 .halt_check = BRANCH_HALT_VOTED,
2416 .clkr = {
2417 .enable_reg = 0x2d064,
2418 .enable_mask = BIT(0),
2419 .hw.init = &(const struct clk_init_data) {
2420 .name = "gcc_qdss_etr_usb_clk",
2421 .parent_hws = (const struct clk_hw*[]) {
2422 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2423 },
2424 .num_parents = 1,
2425 .flags = CLK_SET_RATE_PARENT,
2426 .ops = &clk_branch2_ops,
2427 },
2428 },
2429};
2430
2431static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2432 .mult = 1,
2433 .div = 6,
2434 .hw.init = &(struct clk_init_data) {
2435 .name = "gcc_eud_at_div_clk_src",
2436 .parent_hws = (const struct clk_hw *[]) {
2437 &gcc_qdss_at_clk_src.clkr.hw },
2438 .num_parents = 1,
2439 .flags = CLK_SET_RATE_PARENT,
2440 .ops = &clk_fixed_factor_ops,
2441 },
2442};
2443
2444static struct clk_branch gcc_qdss_eud_at_clk = {
2445 .halt_reg = 0x2d070,
2446 .halt_check = BRANCH_HALT_VOTED,
2447 .clkr = {
2448 .enable_reg = 0x2d070,
2449 .enable_mask = BIT(0),
2450 .hw.init = &(const struct clk_init_data) {
2451 .name = "gcc_qdss_eud_at_clk",
2452 .parent_hws = (const struct clk_hw*[]) {
2453 &gcc_eud_at_div_clk_src.hw,
2454 },
2455 .num_parents = 1,
2456 .flags = CLK_SET_RATE_PARENT,
2457 .ops = &clk_branch2_ops,
2458 },
2459 },
2460};
2461
2462static struct clk_branch gcc_qpic_ahb_clk = {
2463 .halt_reg = 0x32010,
2464 .halt_check = BRANCH_HALT,
2465 .clkr = {
2466 .enable_reg = 0x32010,
2467 .enable_mask = BIT(0),
2468 .hw.init = &(const struct clk_init_data) {
2469 .name = "gcc_qpic_ahb_clk",
2470 .parent_hws = (const struct clk_hw*[]) {
2471 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2472 },
2473 .num_parents = 1,
2474 .flags = CLK_SET_RATE_PARENT,
2475 .ops = &clk_branch2_ops,
2476 },
2477 },
2478};
2479
2480static struct clk_branch gcc_qpic_clk = {
2481 .halt_reg = 0x32014,
2482 .halt_check = BRANCH_HALT,
2483 .clkr = {
2484 .enable_reg = 0x32014,
2485 .enable_mask = BIT(0),
2486 .hw.init = &(const struct clk_init_data) {
2487 .name = "gcc_qpic_clk",
2488 .parent_hws = (const struct clk_hw*[]) {
2489 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2490 },
2491 .num_parents = 1,
2492 .flags = CLK_SET_RATE_PARENT,
2493 .ops = &clk_branch2_ops,
2494 },
2495 },
2496};
2497
2498static struct clk_branch gcc_qpic_io_macro_clk = {
2499 .halt_reg = 0x3200c,
2500 .halt_check = BRANCH_HALT,
2501 .clkr = {
2502 .enable_reg = 0x3200c,
2503 .enable_mask = BIT(0),
2504 .hw.init = &(const struct clk_init_data) {
2505 .name = "gcc_qpic_io_macro_clk",
2506 .parent_hws = (const struct clk_hw*[]) {
2507 &gcc_qpic_io_macro_clk_src.clkr.hw,
2508 },
2509 .num_parents = 1,
2510 .flags = CLK_SET_RATE_PARENT,
2511 .ops = &clk_branch2_ops,
2512 },
2513 },
2514};
2515
2516static struct clk_branch gcc_qpic_sleep_clk = {
2517 .halt_reg = 0x3201c,
2518 .halt_check = BRANCH_HALT,
2519 .clkr = {
2520 .enable_reg = 0x3201c,
2521 .enable_mask = BIT(0),
2522 .hw.init = &(const struct clk_init_data) {
2523 .name = "gcc_qpic_sleep_clk",
2524 .parent_hws = (const struct clk_hw*[]) {
2525 &gcc_sleep_clk_src.clkr.hw,
2526 },
2527 .num_parents = 1,
2528 .flags = CLK_SET_RATE_PARENT,
2529 .ops = &clk_branch2_ops,
2530 },
2531 },
2532};
2533
2534static struct clk_branch gcc_sdcc1_ahb_clk = {
2535 .halt_reg = 0x33034,
2536 .halt_check = BRANCH_HALT,
2537 .clkr = {
2538 .enable_reg = 0x33034,
2539 .enable_mask = BIT(0),
2540 .hw.init = &(const struct clk_init_data) {
2541 .name = "gcc_sdcc1_ahb_clk",
2542 .parent_hws = (const struct clk_hw*[]) {
2543 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2544 },
2545 .num_parents = 1,
2546 .flags = CLK_SET_RATE_PARENT,
2547 .ops = &clk_branch2_ops,
2548 },
2549 },
2550};
2551
2552static struct clk_branch gcc_sdcc1_apps_clk = {
2553 .halt_reg = 0x3302c,
2554 .halt_check = BRANCH_HALT,
2555 .clkr = {
2556 .enable_reg = 0x3302c,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(const struct clk_init_data) {
2559 .name = "gcc_sdcc1_apps_clk",
2560 .parent_hws = (const struct clk_hw*[]) {
2561 &gcc_sdcc1_apps_clk_src.clkr.hw,
2562 },
2563 .num_parents = 1,
2564 .flags = CLK_SET_RATE_PARENT,
2565 .ops = &clk_branch2_ops,
2566 },
2567 },
2568};
2569
2570static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2571 .halt_reg = 0x2e028,
2572 .halt_check = BRANCH_HALT,
2573 .clkr = {
2574 .enable_reg = 0x2e028,
2575 .enable_mask = BIT(0),
2576 .hw.init = &(const struct clk_init_data) {
2577 .name = "gcc_snoc_lpass_cfg_clk",
2578 .parent_hws = (const struct clk_hw*[]) {
2579 &gcc_lpass_sway_clk_src.clkr.hw,
2580 },
2581 .num_parents = 1,
2582 .flags = CLK_SET_RATE_PARENT,
2583 .ops = &clk_branch2_ops,
2584 },
2585 },
2586};
2587
2588static struct clk_branch gcc_snoc_nssnoc_1_clk = {
2589 .halt_reg = 0x17090,
2590 .halt_check = BRANCH_HALT,
2591 .clkr = {
2592 .enable_reg = 0x17090,
2593 .enable_mask = BIT(0),
2594 .hw.init = &(const struct clk_init_data) {
2595 .name = "gcc_snoc_nssnoc_1_clk",
2596 .parent_hws = (const struct clk_hw*[]) {
2597 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2598 },
2599 .num_parents = 1,
2600 .flags = CLK_SET_RATE_PARENT,
2601 .ops = &clk_branch2_ops,
2602 },
2603 },
2604};
2605
2606static struct clk_branch gcc_snoc_nssnoc_clk = {
2607 .halt_reg = 0x17084,
2608 .halt_check = BRANCH_HALT,
2609 .clkr = {
2610 .enable_reg = 0x17084,
2611 .enable_mask = BIT(0),
2612 .hw.init = &(const struct clk_init_data) {
2613 .name = "gcc_snoc_nssnoc_clk",
2614 .parent_hws = (const struct clk_hw*[]) {
2615 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
2616 },
2617 .num_parents = 1,
2618 .flags = CLK_SET_RATE_PARENT,
2619 .ops = &clk_branch2_ops,
2620 },
2621 },
2622};
2623
2624static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
2625 .halt_reg = 0x2e050,
2626 .halt_check = BRANCH_HALT,
2627 .clkr = {
2628 .enable_reg = 0x2e050,
2629 .enable_mask = BIT(0),
2630 .hw.init = &(const struct clk_init_data) {
2631 .name = "gcc_snoc_pcie3_1lane_1_m_clk",
2632 .parent_hws = (const struct clk_hw*[]) {
2633 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2634 },
2635 .num_parents = 1,
2636 .flags = CLK_SET_RATE_PARENT,
2637 .ops = &clk_branch2_ops,
2638 },
2639 },
2640};
2641
2642static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
2643 .halt_reg = 0x2e0ac,
2644 .halt_check = BRANCH_HALT,
2645 .clkr = {
2646 .enable_reg = 0x2e0ac,
2647 .enable_mask = BIT(0),
2648 .hw.init = &(const struct clk_init_data) {
2649 .name = "gcc_snoc_pcie3_1lane_1_s_clk",
2650 .parent_hws = (const struct clk_hw*[]) {
2651 &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
2652 },
2653 .num_parents = 1,
2654 .flags = CLK_SET_RATE_PARENT,
2655 .ops = &clk_branch2_ops,
2656 },
2657 },
2658};
2659
2660static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
2661 .halt_reg = 0x2e080,
2662 .halt_check = BRANCH_HALT,
2663 .clkr = {
2664 .enable_reg = 0x2e080,
2665 .enable_mask = BIT(0),
2666 .hw.init = &(const struct clk_init_data) {
2667 .name = "gcc_snoc_pcie3_1lane_m_clk",
2668 .parent_hws = (const struct clk_hw*[]) {
2669 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2670 },
2671 .num_parents = 1,
2672 .flags = CLK_SET_RATE_PARENT,
2673 .ops = &clk_branch2_ops,
2674 },
2675 },
2676};
2677
2678static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
2679 .halt_reg = 0x2e04c,
2680 .halt_check = BRANCH_HALT,
2681 .clkr = {
2682 .enable_reg = 0x2e04c,
2683 .enable_mask = BIT(0),
2684 .hw.init = &(const struct clk_init_data) {
2685 .name = "gcc_snoc_pcie3_1lane_s_clk",
2686 .parent_hws = (const struct clk_hw*[]) {
2687 &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
2688 },
2689 .num_parents = 1,
2690 .flags = CLK_SET_RATE_PARENT,
2691 .ops = &clk_branch2_ops,
2692 },
2693 },
2694};
2695
2696static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
2697 .halt_reg = 0x2e07c,
2698 .halt_check = BRANCH_HALT,
2699 .clkr = {
2700 .enable_reg = 0x2e07c,
2701 .enable_mask = BIT(0),
2702 .hw.init = &(const struct clk_init_data) {
2703 .name = "gcc_snoc_pcie3_2lane_m_clk",
2704 .parent_hws = (const struct clk_hw*[]) {
2705 &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
2706 },
2707 .num_parents = 1,
2708 .flags = CLK_SET_RATE_PARENT,
2709 .ops = &clk_branch2_ops,
2710 },
2711 },
2712};
2713
2714static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
2715 .halt_reg = 0x2e048,
2716 .halt_check = BRANCH_HALT,
2717 .clkr = {
2718 .enable_reg = 0x2e048,
2719 .enable_mask = BIT(0),
2720 .hw.init = &(const struct clk_init_data) {
2721 .name = "gcc_snoc_pcie3_2lane_s_clk",
2722 .parent_hws = (const struct clk_hw*[]) {
2723 &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
2724 },
2725 .num_parents = 1,
2726 .flags = CLK_SET_RATE_PARENT,
2727 .ops = &clk_branch2_ops,
2728 },
2729 },
2730};
2731
2732static struct clk_branch gcc_snoc_usb_clk = {
2733 .halt_reg = 0x2e058,
2734 .halt_check = BRANCH_HALT_VOTED,
2735 .clkr = {
2736 .enable_reg = 0x2e058,
2737 .enable_mask = BIT(0),
2738 .hw.init = &(const struct clk_init_data) {
2739 .name = "gcc_snoc_usb_clk",
2740 .parent_hws = (const struct clk_hw*[]) {
2741 &gcc_usb0_master_clk_src.clkr.hw,
2742 },
2743 .num_parents = 1,
2744 .flags = CLK_SET_RATE_PARENT,
2745 .ops = &clk_branch2_ops,
2746 },
2747 },
2748};
2749
2750static struct clk_branch gcc_sys_noc_at_clk = {
2751 .halt_reg = 0x2e038,
2752 .halt_check = BRANCH_HALT_VOTED,
2753 .clkr = {
2754 .enable_reg = 0x2e038,
2755 .enable_mask = BIT(0),
2756 .hw.init = &(const struct clk_init_data) {
2757 .name = "gcc_sys_noc_at_clk",
2758 .parent_hws = (const struct clk_hw*[]) {
2759 &gcc_qdss_at_clk_src.clkr.hw,
2760 },
2761 .num_parents = 1,
2762 .flags = CLK_SET_RATE_PARENT,
2763 .ops = &clk_branch2_ops,
2764 },
2765 },
2766};
2767
2768static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2769 .halt_reg = 0x2e030,
2770 .halt_check = BRANCH_HALT,
2771 .clkr = {
2772 .enable_reg = 0x2e030,
2773 .enable_mask = BIT(0),
2774 .hw.init = &(const struct clk_init_data) {
2775 .name = "gcc_sys_noc_wcss_ahb_clk",
2776 .parent_hws = (const struct clk_hw*[]) {
2777 &gcc_wcss_ahb_clk_src.clkr.hw,
2778 },
2779 .num_parents = 1,
2780 .flags = CLK_SET_RATE_PARENT,
2781 .ops = &clk_branch2_ops,
2782 },
2783 },
2784};
2785
2786static struct clk_branch gcc_uniphy0_ahb_clk = {
2787 .halt_reg = 0x16010,
2788 .halt_check = BRANCH_HALT,
2789 .clkr = {
2790 .enable_reg = 0x16010,
2791 .enable_mask = BIT(0),
2792 .hw.init = &(const struct clk_init_data) {
2793 .name = "gcc_uniphy0_ahb_clk",
2794 .parent_hws = (const struct clk_hw*[]) {
2795 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2796 },
2797 .num_parents = 1,
2798 .flags = CLK_SET_RATE_PARENT,
2799 .ops = &clk_branch2_ops,
2800 },
2801 },
2802};
2803
2804static struct clk_branch gcc_uniphy0_sys_clk = {
2805 .halt_reg = 0x1600c,
2806 .halt_check = BRANCH_HALT,
2807 .clkr = {
2808 .enable_reg = 0x1600c,
2809 .enable_mask = BIT(0),
2810 .hw.init = &(const struct clk_init_data) {
2811 .name = "gcc_uniphy0_sys_clk",
2812 .parent_hws = (const struct clk_hw*[]) {
2813 &gcc_uniphy_sys_clk_src.clkr.hw,
2814 },
2815 .num_parents = 1,
2816 .flags = CLK_SET_RATE_PARENT,
2817 .ops = &clk_branch2_ops,
2818 },
2819 },
2820};
2821
2822static struct clk_branch gcc_uniphy1_ahb_clk = {
2823 .halt_reg = 0x1601c,
2824 .halt_check = BRANCH_HALT,
2825 .clkr = {
2826 .enable_reg = 0x1601c,
2827 .enable_mask = BIT(0),
2828 .hw.init = &(const struct clk_init_data) {
2829 .name = "gcc_uniphy1_ahb_clk",
2830 .parent_hws = (const struct clk_hw*[]) {
2831 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2832 },
2833 .num_parents = 1,
2834 .flags = CLK_SET_RATE_PARENT,
2835 .ops = &clk_branch2_ops,
2836 },
2837 },
2838};
2839
2840static struct clk_branch gcc_uniphy1_sys_clk = {
2841 .halt_reg = 0x16018,
2842 .halt_check = BRANCH_HALT,
2843 .clkr = {
2844 .enable_reg = 0x16018,
2845 .enable_mask = BIT(0),
2846 .hw.init = &(const struct clk_init_data) {
2847 .name = "gcc_uniphy1_sys_clk",
2848 .parent_hws = (const struct clk_hw*[]) {
2849 &gcc_uniphy_sys_clk_src.clkr.hw,
2850 },
2851 .num_parents = 1,
2852 .flags = CLK_SET_RATE_PARENT,
2853 .ops = &clk_branch2_ops,
2854 },
2855 },
2856};
2857
2858static struct clk_branch gcc_usb0_aux_clk = {
2859 .halt_reg = 0x2c050,
2860 .halt_check = BRANCH_HALT_VOTED,
2861 .clkr = {
2862 .enable_reg = 0x2c050,
2863 .enable_mask = BIT(0),
2864 .hw.init = &(const struct clk_init_data) {
2865 .name = "gcc_usb0_aux_clk",
2866 .parent_hws = (const struct clk_hw*[]) {
2867 &gcc_usb0_aux_clk_src.clkr.hw,
2868 },
2869 .num_parents = 1,
2870 .flags = CLK_SET_RATE_PARENT,
2871 .ops = &clk_branch2_ops,
2872 },
2873 },
2874};
2875
2876static struct clk_branch gcc_usb0_eud_at_clk = {
2877 .halt_reg = 0x30004,
2878 .halt_check = BRANCH_HALT_VOTED,
2879 .clkr = {
2880 .enable_reg = 0x30004,
2881 .enable_mask = BIT(0),
2882 .hw.init = &(const struct clk_init_data) {
2883 .name = "gcc_usb0_eud_at_clk",
2884 .parent_hws = (const struct clk_hw*[]) {
2885 &gcc_eud_at_div_clk_src.hw,
2886 },
2887 .num_parents = 1,
2888 .flags = CLK_SET_RATE_PARENT,
2889 .ops = &clk_branch2_ops,
2890 },
2891 },
2892};
2893
2894static struct clk_branch gcc_usb0_lfps_clk = {
2895 .halt_reg = 0x2c090,
2896 .halt_check = BRANCH_HALT_VOTED,
2897 .clkr = {
2898 .enable_reg = 0x2c090,
2899 .enable_mask = BIT(0),
2900 .hw.init = &(const struct clk_init_data) {
2901 .name = "gcc_usb0_lfps_clk",
2902 .parent_hws = (const struct clk_hw*[]) {
2903 &gcc_usb0_lfps_clk_src.clkr.hw,
2904 },
2905 .num_parents = 1,
2906 .flags = CLK_SET_RATE_PARENT,
2907 .ops = &clk_branch2_ops,
2908 },
2909 },
2910};
2911
2912static struct clk_branch gcc_usb0_master_clk = {
2913 .halt_reg = 0x2c048,
2914 .halt_check = BRANCH_HALT_VOTED,
2915 .clkr = {
2916 .enable_reg = 0x2c048,
2917 .enable_mask = BIT(0),
2918 .hw.init = &(const struct clk_init_data) {
2919 .name = "gcc_usb0_master_clk",
2920 .parent_hws = (const struct clk_hw*[]) {
2921 &gcc_usb0_master_clk_src.clkr.hw,
2922 },
2923 .num_parents = 1,
2924 .flags = CLK_SET_RATE_PARENT,
2925 .ops = &clk_branch2_ops,
2926 },
2927 },
2928};
2929
2930static struct clk_branch gcc_usb0_mock_utmi_clk = {
2931 .halt_reg = 0x2c054,
2932 .clkr = {
2933 .enable_reg = 0x2c054,
2934 .enable_mask = BIT(0),
2935 .hw.init = &(const struct clk_init_data) {
2936 .name = "gcc_usb0_mock_utmi_clk",
2937 .parent_hws = (const struct clk_hw*[]) {
2938 &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
2939 },
2940 .num_parents = 1,
2941 .flags = CLK_SET_RATE_PARENT,
2942 .ops = &clk_branch2_ops,
2943 },
2944 },
2945};
2946
2947static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2948 .halt_reg = 0x2c05c,
2949 .halt_check = BRANCH_HALT_VOTED,
2950 .clkr = {
2951 .enable_reg = 0x2c05c,
2952 .enable_mask = BIT(0),
2953 .hw.init = &(const struct clk_init_data) {
2954 .name = "gcc_usb0_phy_cfg_ahb_clk",
2955 .parent_hws = (const struct clk_hw*[]) {
2956 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
2957 },
2958 .num_parents = 1,
2959 .flags = CLK_SET_RATE_PARENT,
2960 .ops = &clk_branch2_ops,
2961 },
2962 },
2963};
2964
2965static struct clk_branch gcc_usb0_pipe_clk = {
2966 .halt_reg = 0x2c078,
2967 .halt_check = BRANCH_HALT_DELAY,
2968 .clkr = {
2969 .enable_reg = 0x2c078,
2970 .enable_mask = BIT(0),
2971 .hw.init = &(const struct clk_init_data) {
2972 .name = "gcc_usb0_pipe_clk",
2973 .parent_hws = (const struct clk_hw*[]) {
2974 &gcc_usb0_pipe_clk_src.clkr.hw,
2975 },
2976 .num_parents = 1,
2977 .flags = CLK_SET_RATE_PARENT,
2978 .ops = &clk_branch2_ops,
2979 },
2980 },
2981};
2982
2983static struct clk_branch gcc_usb0_sleep_clk = {
2984 .halt_reg = 0x2c058,
2985 .halt_check = BRANCH_HALT_VOTED,
2986 .clkr = {
2987 .enable_reg = 0x2c058,
2988 .enable_mask = BIT(0),
2989 .hw.init = &(const struct clk_init_data) {
2990 .name = "gcc_usb0_sleep_clk",
2991 .parent_hws = (const struct clk_hw*[]) {
2992 &gcc_sleep_clk_src.clkr.hw,
2993 },
2994 .num_parents = 1,
2995 .flags = CLK_SET_RATE_PARENT,
2996 .ops = &clk_branch2_ops,
2997 },
2998 },
2999};
3000
3001static struct clk_branch gcc_wcss_axim_clk = {
3002 .halt_reg = 0x2505c,
3003 .halt_check = BRANCH_HALT,
3004 .clkr = {
3005 .enable_reg = 0x2505c,
3006 .enable_mask = BIT(0),
3007 .hw.init = &(const struct clk_init_data) {
3008 .name = "gcc_wcss_axim_clk",
3009 .parent_hws = (const struct clk_hw*[]) {
3010 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
3011 },
3012 .num_parents = 1,
3013 .flags = CLK_SET_RATE_PARENT,
3014 .ops = &clk_branch2_ops,
3015 },
3016 },
3017};
3018
3019static struct clk_branch gcc_wcss_axis_clk = {
3020 .halt_reg = 0x25060,
3021 .halt_check = BRANCH_HALT,
3022 .clkr = {
3023 .enable_reg = 0x25060,
3024 .enable_mask = BIT(0),
3025 .hw.init = &(const struct clk_init_data) {
3026 .name = "gcc_wcss_axis_clk",
3027 .parent_hws = (const struct clk_hw*[]) {
3028 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
3029 },
3030 .num_parents = 1,
3031 .flags = CLK_SET_RATE_PARENT,
3032 .ops = &clk_branch2_ops,
3033 },
3034 },
3035};
3036
3037static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
3038 .halt_reg = 0x25048,
3039 .halt_check = BRANCH_HALT,
3040 .clkr = {
3041 .enable_reg = 0x25048,
3042 .enable_mask = BIT(0),
3043 .hw.init = &(const struct clk_init_data) {
3044 .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
3045 .parent_hws = (const struct clk_hw*[]) {
3046 &gcc_qdss_dap_div_clk_src.clkr.hw,
3047 },
3048 .num_parents = 1,
3049 .flags = CLK_SET_RATE_PARENT,
3050 .ops = &clk_branch2_ops,
3051 },
3052 },
3053};
3054
3055static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3056 .halt_reg = 0x25038,
3057 .halt_check = BRANCH_HALT,
3058 .clkr = {
3059 .enable_reg = 0x25038,
3060 .enable_mask = BIT(0),
3061 .hw.init = &(const struct clk_init_data) {
3062 .name = "gcc_wcss_dbg_ifc_apb_clk",
3063 .parent_hws = (const struct clk_hw*[]) {
3064 &gcc_qdss_dap_div_clk_src.clkr.hw,
3065 },
3066 .num_parents = 1,
3067 .flags = CLK_SET_RATE_PARENT,
3068 .ops = &clk_branch2_ops,
3069 },
3070 },
3071};
3072
3073static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
3074 .halt_reg = 0x2504c,
3075 .halt_check = BRANCH_HALT,
3076 .clkr = {
3077 .enable_reg = 0x2504c,
3078 .enable_mask = BIT(0),
3079 .hw.init = &(const struct clk_init_data) {
3080 .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
3081 .parent_hws = (const struct clk_hw*[]) {
3082 &gcc_qdss_at_clk_src.clkr.hw,
3083 },
3084 .num_parents = 1,
3085 .flags = CLK_SET_RATE_PARENT,
3086 .ops = &clk_branch2_ops,
3087 },
3088 },
3089};
3090
3091static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
3092 .halt_reg = 0x2503c,
3093 .halt_check = BRANCH_HALT,
3094 .clkr = {
3095 .enable_reg = 0x2503c,
3096 .enable_mask = BIT(0),
3097 .hw.init = &(const struct clk_init_data) {
3098 .name = "gcc_wcss_dbg_ifc_atb_clk",
3099 .parent_hws = (const struct clk_hw*[]) {
3100 &gcc_qdss_at_clk_src.clkr.hw,
3101 },
3102 .num_parents = 1,
3103 .flags = CLK_SET_RATE_PARENT,
3104 .ops = &clk_branch2_ops,
3105 },
3106 },
3107};
3108
3109static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
3110 .halt_reg = 0x25050,
3111 .halt_check = BRANCH_HALT,
3112 .clkr = {
3113 .enable_reg = 0x25050,
3114 .enable_mask = BIT(0),
3115 .hw.init = &(const struct clk_init_data) {
3116 .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
3117 .parent_hws = (const struct clk_hw*[]) {
3118 &gcc_qdss_tsctr_div2_clk_src.hw,
3119 },
3120 .num_parents = 1,
3121 .flags = CLK_SET_RATE_PARENT,
3122 .ops = &clk_branch2_ops,
3123 },
3124 },
3125};
3126
3127static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3128 .halt_reg = 0x25040,
3129 .halt_check = BRANCH_HALT,
3130 .clkr = {
3131 .enable_reg = 0x25040,
3132 .enable_mask = BIT(0),
3133 .hw.init = &(const struct clk_init_data) {
3134 .name = "gcc_wcss_dbg_ifc_nts_clk",
3135 .parent_hws = (const struct clk_hw*[]) {
3136 &gcc_qdss_tsctr_div2_clk_src.hw,
3137 },
3138 .num_parents = 1,
3139 .flags = CLK_SET_RATE_PARENT,
3140 .ops = &clk_branch2_ops,
3141 },
3142 },
3143};
3144
3145static struct clk_branch gcc_wcss_ecahb_clk = {
3146 .halt_reg = 0x25058,
3147 .halt_check = BRANCH_HALT,
3148 .clkr = {
3149 .enable_reg = 0x25058,
3150 .enable_mask = BIT(0),
3151 .hw.init = &(const struct clk_init_data) {
3152 .name = "gcc_wcss_ecahb_clk",
3153 .parent_hws = (const struct clk_hw*[]) {
3154 &gcc_wcss_ahb_clk_src.clkr.hw,
3155 },
3156 .num_parents = 1,
3157 .flags = CLK_SET_RATE_PARENT,
3158 .ops = &clk_branch2_ops,
3159 },
3160 },
3161};
3162
3163static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
3164 .halt_reg = 0x2e0b0,
3165 .halt_check = BRANCH_HALT,
3166 .clkr = {
3167 .enable_reg = 0x2e0b0,
3168 .enable_mask = BIT(0),
3169 .hw.init = &(const struct clk_init_data) {
3170 .name = "gcc_wcss_mst_async_bdg_clk",
3171 .parent_hws = (const struct clk_hw*[]) {
3172 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
3173 },
3174 .num_parents = 1,
3175 .flags = CLK_SET_RATE_PARENT,
3176 .ops = &clk_branch2_ops,
3177 },
3178 },
3179};
3180
3181static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
3182 .halt_reg = 0x2e0b4,
3183 .halt_check = BRANCH_HALT,
3184 .clkr = {
3185 .enable_reg = 0x2e0b4,
3186 .enable_mask = BIT(0),
3187 .hw.init = &(const struct clk_init_data) {
3188 .name = "gcc_wcss_slv_async_bdg_clk",
3189 .parent_hws = (const struct clk_hw*[]) {
3190 &gcc_system_noc_bfdcd_clk_src.clkr.hw,
3191 },
3192 .num_parents = 1,
3193 .flags = CLK_SET_RATE_PARENT,
3194 .ops = &clk_branch2_ops,
3195 },
3196 },
3197};
3198
3199static struct clk_branch gcc_xo_clk = {
3200 .halt_reg = 0x34018,
3201 .halt_check = BRANCH_HALT,
3202 .clkr = {
3203 .enable_reg = 0x34018,
3204 .enable_mask = BIT(0),
3205 .hw.init = &(const struct clk_init_data) {
3206 .name = "gcc_xo_clk",
3207 .parent_hws = (const struct clk_hw*[]) {
3208 &gcc_xo_clk_src.clkr.hw,
3209 },
3210 .num_parents = 1,
3211 .flags = CLK_SET_RATE_PARENT,
3212 .ops = &clk_branch2_ops,
3213 },
3214 },
3215};
3216
3217static struct clk_branch gcc_xo_div4_clk = {
3218 .halt_reg = 0x3401c,
3219 .halt_check = BRANCH_HALT,
3220 .clkr = {
3221 .enable_reg = 0x3401c,
3222 .enable_mask = BIT(0),
3223 .hw.init = &(const struct clk_init_data) {
3224 .name = "gcc_xo_div4_clk",
3225 .parent_hws = (const struct clk_hw*[]) {
3226 &gcc_xo_div4_clk_src.hw,
3227 },
3228 .num_parents = 1,
3229 .flags = CLK_SET_RATE_PARENT,
3230 .ops = &clk_branch2_ops,
3231 },
3232 },
3233};
3234
3235static struct clk_branch gcc_im_sleep_clk = {
3236 .halt_reg = 0x34020,
3237 .halt_check = BRANCH_HALT,
3238 .clkr = {
3239 .enable_reg = 0x34020,
3240 .enable_mask = BIT(0),
3241 .hw.init = &(const struct clk_init_data) {
3242 .name = "gcc_im_sleep_clk",
3243 .parent_hws = (const struct clk_hw*[]) {
3244 &gcc_sleep_clk_src.clkr.hw,
3245 },
3246 .num_parents = 1,
3247 .flags = CLK_SET_RATE_PARENT,
3248 .ops = &clk_branch2_ops,
3249 },
3250 },
3251};
3252
3253static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
3254 .halt_reg = 0x17080,
3255 .halt_check = BRANCH_HALT,
3256 .clkr = {
3257 .enable_reg = 0x17080,
3258 .enable_mask = BIT(0),
3259 .hw.init = &(const struct clk_init_data) {
3260 .name = "gcc_nssnoc_pcnoc_1_clk",
3261 .parent_hws = (const struct clk_hw*[]) {
3262 &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
3263 },
3264 .num_parents = 1,
3265 .flags = CLK_SET_RATE_PARENT,
3266 .ops = &clk_branch2_ops,
3267 },
3268 },
3269};
3270
3271static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
3272 .reg = 0x2e010,
3273 .shift = 0,
3274 .width = 2,
3275 .clkr.hw.init = &(const struct clk_init_data) {
3276 .name = "gcc_snoc_qosgen_extref_div_clk_src",
3277 .parent_hws = (const struct clk_hw*[]) {
3278 &gcc_xo_clk_src.clkr.hw,
3279 },
3280 .num_parents = 1,
3281 .flags = CLK_SET_RATE_PARENT,
3282 .ops = &clk_regmap_div_ro_ops,
3283 },
3284};
3285
3286static struct clk_regmap *gcc_ipq5332_clocks[] = {
3287 [GPLL0_MAIN] = &gpll0_main.clkr,
3288 [GPLL0] = &gpll0.clkr,
3289 [GPLL2_MAIN] = &gpll2_main.clkr,
3290 [GPLL2] = &gpll2.clkr,
3291 [GPLL4_MAIN] = &gpll4_main.clkr,
3292 [GPLL4] = &gpll4.clkr,
3293 [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
3294 [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
3295 [GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
3296 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
3297 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3298 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3299 [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
3300 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3301 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3302 [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
3303 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3304 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3305 [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
3306 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
3307 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3308 [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
3309 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3310 [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
3311 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3312 [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
3313 [GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
3314 [GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
3315 [GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
3316 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
3317 [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
3318 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
3319 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3320 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3321 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3322 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3323 [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
3324 [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
3325 [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
3326 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
3327 [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
3328 [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
3329 [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
3330 [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
3331 [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
3332 [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
3333 [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
3334 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
3335 [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
3336 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
3337 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
3338 [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
3339 [GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
3340 [GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
3341 [GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
3342 [GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
3343 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
3344 [GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
3345 [GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
3346 [GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
3347 [GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
3348 [GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
3349 [GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
3350 [GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
3351 [GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
3352 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
3353 [GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
3354 [GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
3355 [GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
3356 [GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
3357 [GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
3358 [GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
3359 [GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
3360 [GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
3361 [GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
3362 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
3363 [GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
3364 [GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
3365 [GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
3366 [GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
3367 [GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
3368 [GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
3369 [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
3370 [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
3371 [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
3372 [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
3373 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3374 [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
3375 [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
3376 [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
3377 [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
3378 [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
3379 [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
3380 [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
3381 [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
3382 [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
3383 [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
3384 [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
3385 [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
3386 [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
3387 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
3388 [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
3389 [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
3390 [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
3391 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3392 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3393 [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
3394 [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
3395 [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
3396 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3397 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3398 [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
3399 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3400 [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
3401 [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
3402 [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
3403 [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
3404 [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
3405 [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
3406 [GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
3407 [GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
3408 [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
3409 [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
3410 [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
3411 [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
3412 [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
3413 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
3414 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
3415 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
3416 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
3417 [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
3418 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3419 [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
3420 [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
3421 [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
3422 [GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
3423 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3424 [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
3425 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3426 [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
3427 [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
3428 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3429 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3430 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3431 [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
3432 [GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
3433 [GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
3434 [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
3435 [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
3436 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
3437 [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
3438 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
3439 [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
3440 [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
3441 [GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
3442 [GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
3443 [GCC_XO_CLK] = &gcc_xo_clk.clkr,
3444 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
3445 [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
3446 [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
3447 [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
3448 [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
3449 [GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,
3450 [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,
3451 [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,
3452 [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,
3453};
3454
3455static const struct qcom_reset_map gcc_ipq5332_resets[] = {
3456 [GCC_ADSS_BCR] = { 0x1c000 },
3457 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
3458 [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
3459 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
3460 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
3461 [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
3462 [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
3463 [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
3464 [GCC_BLSP1_BCR] = { 0x1000 },
3465 [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
3466 [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
3467 [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
3468 [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
3469 [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
3470 [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
3471 [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
3472 [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
3473 [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
3474 [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
3475 [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
3476 [GCC_BLSP1_UART1_BCR] = { 0x2028 },
3477 [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
3478 [GCC_BLSP1_UART2_BCR] = { 0x3028 },
3479 [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
3480 [GCC_BLSP1_UART3_BCR] = { 0x4028 },
3481 [GCC_CE_BCR] = { 0x18008 },
3482 [GCC_CMN_BLK_BCR] = { 0x3a000 },
3483 [GCC_CMN_LDO0_BCR] = { 0x1d000 },
3484 [GCC_CMN_LDO1_BCR] = { 0x1d008 },
3485 [GCC_DCC_BCR] = { 0x35000 },
3486 [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
3487 [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
3488 [GCC_LPASS_BCR] = { 0x27000 },
3489 [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
3490 [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
3491 [GCC_MDIOM_BCR] = { 0x12000 },
3492 [GCC_MDIOS_BCR] = { 0x12008 },
3493 [GCC_NSS_BCR] = { 0x17000 },
3494 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
3495 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
3496 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
3497 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
3498 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
3499 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
3500 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
3501 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
3502 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
3503 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
3504 [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
3505 [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
3506 [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
3507 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
3508 [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
3509 [GCC_PCIE3X1_0_BCR] = { 0x29000 },
3510 [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
3511 [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
3512 [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
3513 [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
3514 [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
3515 [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
3516 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
3517 [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
3518 [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
3519 [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
3520 [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
3521 [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
3522 [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
3523 [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
3524 [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
3525 [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
3526 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
3527 [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
3528 [GCC_PCIE3X2_BCR] = { 0x28000 },
3529 [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
3530 [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
3531 [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
3532 [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
3533 [GCC_PCNOC_BCR] = { 0x31000 },
3534 [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
3535 [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
3536 [GCC_PRNG_BCR] = { 0x13020 },
3537 [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
3538 [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
3539 [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
3540 [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
3541 [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
3542 [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
3543 [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
3544 [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
3545 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
3546 [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
3547 [GCC_QDSS_BCR] = { 0x2d000 },
3548 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
3549 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
3550 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
3551 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
3552 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
3553 [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
3554 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
3555 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
3556 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
3557 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
3558 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
3559 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
3560 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
3561 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
3562 [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
3563 [GCC_QPIC_BCR] = { 0x32000 },
3564 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
3565 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
3566 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
3567 [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
3568 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
3569 [GCC_SDCC_BCR] = { 0x33000 },
3570 [GCC_SNOC_BCR] = { 0x2e000 },
3571 [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
3572 [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
3573 [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
3574 [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
3575 [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
3576 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
3577 [GCC_UNIPHY0_BCR] = { 0x16000 },
3578 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
3579 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
3580 [GCC_UNIPHY1_BCR] = { 0x16014 },
3581 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
3582 [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
3583 [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
3584 [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
3585 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
3586 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
3587 [GCC_USB0_PHY_BCR] = { 0x2c06c },
3588 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
3589 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
3590 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
3591 [GCC_USB_BCR] = { 0x2c000 },
3592 [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
3593 [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
3594 [GCC_WCSS_BCR] = { 0x18004 },
3595 [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
3596 [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
3597 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
3598 [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
3599 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
3600 [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
3601 [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
3602 [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
3603 [GCC_WCSS_Q6_BCR] = { 0x18000 },
3604 [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
3605 [GCC_XO_CLK_ARES] = { 0x34018, 2 },
3606 [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
3607 [GCC_Q6SS_DBG_ARES] = { 0x25094 },
3608 [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
3609 [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
3610 [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
3611 [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
3612 [GCC_WCSSAON_ARES] = { 0x2509C },
3613 [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
3614 [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
3615 [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3616 [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
3617 [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
3618 [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
3619 [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3620 [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
3621 [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
3622 [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
3623 [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3624 [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
3625 [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
3626 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
3627 [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
3628 [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
3629};
3630
3631static const struct regmap_config gcc_ipq5332_regmap_config = {
3632 .reg_bits = 32,
3633 .reg_stride = 4,
3634 .val_bits = 32,
3635 .max_register = 0x3f024,
3636 .fast_io = true,
3637};
3638
3639static struct clk_hw *gcc_ipq5332_hws[] = {
3640 &gpll0_div2.hw,
3641 &gcc_xo_div4_clk_src.hw,
3642 &gcc_system_noc_bfdcd_div2_clk_src.hw,
3643 &gcc_qdss_tsctr_div2_clk_src.hw,
3644 &gcc_qdss_tsctr_div3_clk_src.hw,
3645 &gcc_qdss_tsctr_div4_clk_src.hw,
3646 &gcc_qdss_tsctr_div8_clk_src.hw,
3647 &gcc_qdss_tsctr_div16_clk_src.hw,
3648 &gcc_eud_at_div_clk_src.hw,
3649};
3650
3651static const struct qcom_cc_desc gcc_ipq5332_desc = {
3652 .config = &gcc_ipq5332_regmap_config,
3653 .clks = gcc_ipq5332_clocks,
3654 .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
3655 .resets = gcc_ipq5332_resets,
3656 .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
3657 .clk_hws = gcc_ipq5332_hws,
3658 .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
3659};
3660
3661static int gcc_ipq5332_probe(struct platform_device *pdev)
3662{
3663 return qcom_cc_probe(pdev, desc: &gcc_ipq5332_desc);
3664}
3665
3666static const struct of_device_id gcc_ipq5332_match_table[] = {
3667 { .compatible = "qcom,ipq5332-gcc" },
3668 { }
3669};
3670MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
3671
3672static struct platform_driver gcc_ipq5332_driver = {
3673 .probe = gcc_ipq5332_probe,
3674 .driver = {
3675 .name = "gcc-ipq5332",
3676 .of_match_table = gcc_ipq5332_match_table,
3677 },
3678};
3679
3680static int __init gcc_ipq5332_init(void)
3681{
3682 return platform_driver_register(&gcc_ipq5332_driver);
3683}
3684core_initcall(gcc_ipq5332_init);
3685
3686static void __exit gcc_ipq5332_exit(void)
3687{
3688 platform_driver_unregister(&gcc_ipq5332_driver);
3689}
3690module_exit(gcc_ipq5332_exit);
3691
3692MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
3693MODULE_LICENSE("GPL");
3694

source code of linux/drivers/clk/qcom/gcc-ipq5332.c