1	// SPDX-License-Identifier: GPL-2.0
2	/*
3	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/kernel.h>
7	#include <linux/err.h>
8	#include <linux/platform_device.h>
9	#include <linux/module.h>
10	#include <linux/of.h>
11	#include <linux/clk-provider.h>
12	#include <linux/regmap.h>
13
14	#include <linux/reset-controller.h>
15	#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
16	#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
17
18	#include "common.h"
19	#include "clk-regmap.h"
20	#include "clk-pll.h"
21	#include "clk-rcg.h"
22	#include "clk-branch.h"
23	#include "clk-alpha-pll.h"
24	#include "clk-regmap-divider.h"
25	#include "clk-regmap-mux.h"
26	#include "reset.h"
27
28	enum {
29	P_XO,
30	P_BIAS_PLL,
31	P_UNIPHY0_RX,
32	P_UNIPHY0_TX,
33	P_UNIPHY1_RX,
34	P_BIAS_PLL_NSS_NOC,
35	P_UNIPHY1_TX,
36	P_PCIE20_PHY0_PIPE,
37	P_USB3PHY_0_PIPE,
38	P_GPLL0,
39	P_GPLL0_DIV2,
40	P_GPLL2,
41	P_GPLL4,
42	P_GPLL6,
43	P_SLEEP_CLK,
44	P_UBI32_PLL,
45	P_NSS_CRYPTO_PLL,
46	P_PI_SLEEP,
47	};
48
49	static struct clk_alpha_pll gpll0_main = {
50	.offset = 0x21000,
51	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
52	.clkr = {
53	.enable_reg = 0x0b000,
54	.enable_mask = BIT(0),
55	.hw.init = &(struct clk_init_data){
56	.name = "gpll0_main",
57	.parent_data = &(const struct clk_parent_data){
58	.fw_name = "xo",
59	},
60	.num_parents = 1,
61	.ops = &clk_alpha_pll_ops,
62	},
63	},
64	};
65
66	static struct clk_fixed_factor gpll0_out_main_div2 = {
67	.mult = 1,
68	.div = 2,
69	.hw.init = &(struct clk_init_data){
70	.name = "gpll0_out_main_div2",
71	.parent_hws = (const struct clk_hw *[]){
72	&gpll0_main.clkr.hw },
73	.num_parents = 1,
74	.ops = &clk_fixed_factor_ops,
75	},
76	};
77
78	static struct clk_alpha_pll_postdiv gpll0 = {
79	.offset = 0x21000,
80	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
81	.width = 4,
82	.clkr.hw.init = &(struct clk_init_data){
83	.name = "gpll0",
84	.parent_hws = (const struct clk_hw *[]){
85	&gpll0_main.clkr.hw },
86	.num_parents = 1,
87	.ops = &clk_alpha_pll_postdiv_ro_ops,
88	},
89	};
90
91	static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
92	{ .fw_name = "xo" },
93	{ .hw = &gpll0.clkr.hw},
94	{ .hw = &gpll0_out_main_div2.hw},
95	};
96
97	static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
98	{ P_XO, 0 },
99	{ P_GPLL0, 1 },
100	{ P_GPLL0_DIV2, 4 },
101	};
102
103	static struct clk_alpha_pll ubi32_pll_main = {
104	.offset = 0x25000,
105	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
106	.flags = SUPPORTS_DYNAMIC_UPDATE,
107	.clkr = {
108	.enable_reg = 0x0b000,
109	.enable_mask = BIT(6),
110	.hw.init = &(struct clk_init_data){
111	.name = "ubi32_pll_main",
112	.parent_data = &(const struct clk_parent_data){
113	.fw_name = "xo",
114	},
115	.num_parents = 1,
116	.ops = &clk_alpha_pll_huayra_ops,
117	},
118	},
119	};
120
121	static struct clk_alpha_pll_postdiv ubi32_pll = {
122	.offset = 0x25000,
123	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
124	.width = 2,
125	.clkr.hw.init = &(struct clk_init_data){
126	.name = "ubi32_pll",
127	.parent_hws = (const struct clk_hw *[]){
128	&ubi32_pll_main.clkr.hw },
129	.num_parents = 1,
130	.ops = &clk_alpha_pll_postdiv_ro_ops,
131	.flags = CLK_SET_RATE_PARENT,
132	},
133	};
134
135	static struct clk_alpha_pll gpll6_main = {
136	.offset = 0x37000,
137	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
138	.clkr = {
139	.enable_reg = 0x0b000,
140	.enable_mask = BIT(7),
141	.hw.init = &(struct clk_init_data){
142	.name = "gpll6_main",
143	.parent_data = &(const struct clk_parent_data){
144	.fw_name = "xo",
145	},
146	.num_parents = 1,
147	.ops = &clk_alpha_pll_ops,
148	},
149	},
150	};
151
152	static struct clk_alpha_pll_postdiv gpll6 = {
153	.offset = 0x37000,
154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
155	.width = 2,
156	.clkr.hw.init = &(struct clk_init_data){
157	.name = "gpll6",
158	.parent_hws = (const struct clk_hw *[]){
159	&gpll6_main.clkr.hw },
160	.num_parents = 1,
161	.ops = &clk_alpha_pll_postdiv_ro_ops,
162	},
163	};
164
165	static struct clk_alpha_pll gpll4_main = {
166	.offset = 0x24000,
167	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
168	.clkr = {
169	.enable_reg = 0x0b000,
170	.enable_mask = BIT(5),
171	.hw.init = &(struct clk_init_data){
172	.name = "gpll4_main",
173	.parent_data = &(const struct clk_parent_data){
174	.fw_name = "xo",
175	},
176	.num_parents = 1,
177	.ops = &clk_alpha_pll_ops,
178	},
179	},
180	};
181
182	static struct clk_alpha_pll_postdiv gpll4 = {
183	.offset = 0x24000,
184	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
185	.width = 4,
186	.clkr.hw.init = &(struct clk_init_data){
187	.name = "gpll4",
188	.parent_hws = (const struct clk_hw *[]){
189	&gpll4_main.clkr.hw },
190	.num_parents = 1,
191	.ops = &clk_alpha_pll_postdiv_ro_ops,
192	},
193	};
194
195	static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
196	F(24000000, P_XO, 1, 0, 0),
197	F(50000000, P_GPLL0, 16, 0, 0),
198	F(100000000, P_GPLL0, 8, 0, 0),
199	{ }
200	};
201
202	static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
203	.cmd_rcgr = 0x27000,
204	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
205	.hid_width = 5,
206	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
207	.clkr.hw.init = &(struct clk_init_data){
208	.name = "pcnoc_bfdcd_clk_src",
209	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
210	.num_parents = 3,
211	.ops = &clk_rcg2_ops,
212	},
213	};
214
215	static struct clk_alpha_pll gpll2_main = {
216	.offset = 0x4a000,
217	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
218	.clkr = {
219	.enable_reg = 0x0b000,
220	.enable_mask = BIT(2),
221	.hw.init = &(struct clk_init_data){
222	.name = "gpll2_main",
223	.parent_data = &(const struct clk_parent_data){
224	.fw_name = "xo",
225	},
226	.num_parents = 1,
227	.ops = &clk_alpha_pll_ops,
228	},
229	},
230	};
231
232	static struct clk_alpha_pll_postdiv gpll2 = {
233	.offset = 0x4a000,
234	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
235	.width = 4,
236	.clkr.hw.init = &(struct clk_init_data){
237	.name = "gpll2",
238	.parent_hws = (const struct clk_hw *[]){
239	&gpll2_main.clkr.hw },
240	.num_parents = 1,
241	.ops = &clk_alpha_pll_postdiv_ro_ops,
242	},
243	};
244
245	static struct clk_alpha_pll nss_crypto_pll_main = {
246	.offset = 0x22000,
247	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
248	.clkr = {
249	.enable_reg = 0x0b000,
250	.enable_mask = BIT(4),
251	.hw.init = &(struct clk_init_data){
252	.name = "nss_crypto_pll_main",
253	.parent_data = &(const struct clk_parent_data){
254	.fw_name = "xo",
255	},
256	.num_parents = 1,
257	.ops = &clk_alpha_pll_ops,
258	},
259	},
260	};
261
262	static struct clk_alpha_pll_postdiv nss_crypto_pll = {
263	.offset = 0x22000,
264	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
265	.width = 4,
266	.clkr.hw.init = &(struct clk_init_data){
267	.name = "nss_crypto_pll",
268	.parent_hws = (const struct clk_hw *[]){
269	&nss_crypto_pll_main.clkr.hw },
270	.num_parents = 1,
271	.ops = &clk_alpha_pll_postdiv_ro_ops,
272	},
273	};
274
275	static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
276	F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
277	F(320000000, P_GPLL0, 2.5, 0, 0),
278	F(600000000, P_GPLL4, 2, 0, 0),
279	{ }
280	};
281
282	static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
283	{ .fw_name = "xo" },
284	{ .hw = &gpll4.clkr.hw },
285	{ .hw = &gpll0.clkr.hw },
286	{ .hw = &gpll6.clkr.hw },
287	{ .hw = &gpll0_out_main_div2.hw },
288	};
289
290	static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
291	{ P_XO, 0 },
292	{ P_GPLL4, 1 },
293	{ P_GPLL0, 2 },
294	{ P_GPLL6, 3 },
295	{ P_GPLL0_DIV2, 4 },
296	};
297
298	static struct clk_rcg2 qdss_tsctr_clk_src = {
299	.cmd_rcgr = 0x29064,
300	.freq_tbl = ftbl_qdss_tsctr_clk_src,
301	.hid_width = 5,
302	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
303	.clkr.hw.init = &(struct clk_init_data){
304	.name = "qdss_tsctr_clk_src",
305	.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
306	.num_parents = 5,
307	.ops = &clk_rcg2_ops,
308	},
309	};
310
311	static struct clk_fixed_factor qdss_dap_sync_clk_src = {
312	.mult = 1,
313	.div = 4,
314	.hw.init = &(struct clk_init_data){
315	.name = "qdss_dap_sync_clk_src",
316	.parent_hws = (const struct clk_hw *[]){
317	&qdss_tsctr_clk_src.clkr.hw },
318	.num_parents = 1,
319	.ops = &clk_fixed_factor_ops,
320	},
321	};
322
323	static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
324	F(66670000, P_GPLL0_DIV2, 6, 0, 0),
325	F(240000000, P_GPLL4, 5, 0, 0),
326	{ }
327	};
328
329	static struct clk_rcg2 qdss_at_clk_src = {
330	.cmd_rcgr = 0x2900c,
331	.freq_tbl = ftbl_qdss_at_clk_src,
332	.hid_width = 5,
333	.parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
334	.clkr.hw.init = &(struct clk_init_data){
335	.name = "qdss_at_clk_src",
336	.parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
337	.num_parents = 5,
338	.ops = &clk_rcg2_ops,
339	},
340	};
341
342	static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
343	.mult = 1,
344	.div = 2,
345	.hw.init = &(struct clk_init_data){
346	.name = "qdss_tsctr_div2_clk_src",
347	.parent_hws = (const struct clk_hw *[]){
348	&qdss_tsctr_clk_src.clkr.hw },
349	.num_parents = 1,
350	.flags = CLK_SET_RATE_PARENT,
351	.ops = &clk_fixed_factor_ops,
352	},
353	};
354
355	static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
356	F(24000000, P_XO, 1, 0, 0),
357	F(300000000, P_BIAS_PLL, 1, 0, 0),
358	{ }
359	};
360
361	static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
362	{ .fw_name = "xo" },
363	{ .fw_name = "bias_pll_cc_clk" },
364	{ .hw = &gpll0.clkr.hw },
365	{ .hw = &gpll4.clkr.hw },
366	{ .hw = &nss_crypto_pll.clkr.hw },
367	{ .hw = &ubi32_pll.clkr.hw },
368	};
369
370	static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
371	{ P_XO, 0 },
372	{ P_BIAS_PLL, 1 },
373	{ P_GPLL0, 2 },
374	{ P_GPLL4, 3 },
375	{ P_NSS_CRYPTO_PLL, 4 },
376	{ P_UBI32_PLL, 5 },
377	};
378
379	static struct clk_rcg2 nss_ppe_clk_src = {
380	.cmd_rcgr = 0x68080,
381	.freq_tbl = ftbl_nss_ppe_clk_src,
382	.hid_width = 5,
383	.parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
384	.clkr.hw.init = &(struct clk_init_data){
385	.name = "nss_ppe_clk_src",
386	.parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
387	.num_parents = 6,
388	.ops = &clk_rcg2_ops,
389	},
390	};
391
392	static struct clk_branch gcc_xo_clk_src = {
393	.halt_reg = 0x30018,
394	.clkr = {
395	.enable_reg = 0x30018,
396	.enable_mask = BIT(1),
397	.hw.init = &(struct clk_init_data){
398	.name = "gcc_xo_clk_src",
399	.parent_data = &(const struct clk_parent_data){
400	.fw_name = "xo",
401	},
402	.num_parents = 1,
403	.flags = CLK_SET_RATE_PARENT,
404	.ops = &clk_branch2_ops,
405	},
406	},
407	};
408
409	static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
410	F(24000000, P_XO, 1, 0, 0),
411	F(200000000, P_GPLL0, 4, 0, 0),
412	{ }
413	};
414
415	static const struct clk_parent_data gcc_xo_gpll0[] = {
416	{ .fw_name = "xo" },
417	{ .hw = &gpll0.clkr.hw },
418	};
419
420	static const struct parent_map gcc_xo_gpll0_map[] = {
421	{ P_XO, 0 },
422	{ P_GPLL0, 1 },
423	};
424
425	static struct clk_rcg2 nss_ce_clk_src = {
426	.cmd_rcgr = 0x68098,
427	.freq_tbl = ftbl_nss_ce_clk_src,
428	.hid_width = 5,
429	.parent_map = gcc_xo_gpll0_map,
430	.clkr.hw.init = &(struct clk_init_data){
431	.name = "nss_ce_clk_src",
432	.parent_data = gcc_xo_gpll0,
433	.num_parents = 2,
434	.ops = &clk_rcg2_ops,
435	},
436	};
437
438	static struct clk_branch gcc_sleep_clk_src = {
439	.halt_reg = 0x30000,
440	.clkr = {
441	.enable_reg = 0x30000,
442	.enable_mask = BIT(1),
443	.hw.init = &(struct clk_init_data){
444	.name = "gcc_sleep_clk_src",
445	.parent_data = &(const struct clk_parent_data){
446	.fw_name = "sleep_clk",
447	},
448	.num_parents = 1,
449	.ops = &clk_branch2_ops,
450	},
451	},
452	};
453
454	static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = {
455	F(24000000, P_XO, 1, 0, 0),
456	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
457	F(100000000, P_GPLL0, 8, 0, 0),
458	F(133333333, P_GPLL0, 6, 0, 0),
459	F(160000000, P_GPLL0, 5, 0, 0),
460	F(200000000, P_GPLL0, 4, 0, 0),
461	F(266666667, P_GPLL0, 3, 0, 0),
462	{ }
463	};
464
465	static const struct clk_parent_data
466	gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
467	{ .fw_name = "xo" },
468	{ .hw = &gpll0.clkr.hw },
469	{ .hw = &gpll6.clkr.hw },
470	{ .hw = &gpll0_out_main_div2.hw },
471	};
472
473	static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
474	{ P_XO, 0 },
475	{ P_GPLL0, 1 },
476	{ P_GPLL6, 2 },
477	{ P_GPLL0_DIV2, 3 },
478	};
479
480	static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = {
481	.cmd_rcgr = 0x76054,
482	.freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src,
483	.hid_width = 5,
484	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
485	.clkr.hw.init = &(struct clk_init_data){
486	.name = "snoc_nssnoc_bfdcd_clk_src",
487	.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
488	.num_parents = 4,
489	.ops = &clk_rcg2_ops,
490	},
491	};
492
493	static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
494	F(24000000, P_XO, 1, 0, 0),
495	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
496	F(50000000, P_GPLL0, 16, 0, 0),
497	F(100000000, P_GPLL0, 8, 0, 0),
498	{ }
499	};
500
501	static struct clk_rcg2 apss_ahb_clk_src = {
502	.cmd_rcgr = 0x46000,
503	.freq_tbl = ftbl_apss_ahb_clk_src,
504	.hid_width = 5,
505	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
506	.clkr.hw.init = &(struct clk_init_data){
507	.name = "apss_ahb_clk_src",
508	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
509	.num_parents = 3,
510	.ops = &clk_rcg2_ops,
511	},
512	};
513
514	static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
515	F(24000000, P_XO, 1, 0, 0),
516	F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
517	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
518	F(78125000, P_UNIPHY1_RX, 4, 0, 0),
519	F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
520	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
521	F(156250000, P_UNIPHY1_RX, 2, 0, 0),
522	F(312500000, P_UNIPHY1_RX, 1, 0, 0),
523	{ }
524	};
525
526	static const struct clk_parent_data
527	gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
528	{ .fw_name = "xo" },
529	{ .fw_name = "uniphy0_gcc_rx_clk" },
530	{ .fw_name = "uniphy0_gcc_tx_clk" },
531	{ .fw_name = "uniphy1_gcc_rx_clk" },
532	{ .fw_name = "uniphy1_gcc_tx_clk" },
533	{ .hw = &ubi32_pll.clkr.hw },
534	{ .fw_name = "bias_pll_cc_clk" },
535	};
536
537	static const struct parent_map
538	gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
539	{ P_XO, 0 },
540	{ P_UNIPHY0_RX, 1 },
541	{ P_UNIPHY0_TX, 2 },
542	{ P_UNIPHY1_RX, 3 },
543	{ P_UNIPHY1_TX, 4 },
544	{ P_UBI32_PLL, 5 },
545	{ P_BIAS_PLL, 6 },
546	};
547
548	static struct clk_rcg2 nss_port5_rx_clk_src = {
549	.cmd_rcgr = 0x68060,
550	.freq_tbl = ftbl_nss_port5_rx_clk_src,
551	.hid_width = 5,
552	.parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
553	.clkr.hw.init = &(struct clk_init_data){
554	.name = "nss_port5_rx_clk_src",
555	.parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
556	.num_parents = 7,
557	.ops = &clk_rcg2_ops,
558	},
559	};
560
561	static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
562	F(24000000, P_XO, 1, 0, 0),
563	F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
564	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
565	F(78125000, P_UNIPHY1_TX, 4, 0, 0),
566	F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
567	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
568	F(156250000, P_UNIPHY1_TX, 2, 0, 0),
569	F(312500000, P_UNIPHY1_TX, 1, 0, 0),
570	{ }
571	};
572
573	static const struct clk_parent_data
574	gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
575	{ .fw_name = "xo" },
576	{ .fw_name = "uniphy0_gcc_tx_clk" },
577	{ .fw_name = "uniphy0_gcc_rx_clk" },
578	{ .fw_name = "uniphy1_gcc_tx_clk" },
579	{ .fw_name = "uniphy1_gcc_rx_clk" },
580	{ .hw = &ubi32_pll.clkr.hw },
581	{ .fw_name = "bias_pll_cc_clk" },
582	};
583
584	static const struct parent_map
585	gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
586	{ P_XO, 0 },
587	{ P_UNIPHY0_TX, 1 },
588	{ P_UNIPHY0_RX, 2 },
589	{ P_UNIPHY1_TX, 3 },
590	{ P_UNIPHY1_RX, 4 },
591	{ P_UBI32_PLL, 5 },
592	{ P_BIAS_PLL, 6 },
593	};
594
595	static struct clk_rcg2 nss_port5_tx_clk_src = {
596	.cmd_rcgr = 0x68068,
597	.freq_tbl = ftbl_nss_port5_tx_clk_src,
598	.hid_width = 5,
599	.parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
600	.clkr.hw.init = &(struct clk_init_data){
601	.name = "nss_port5_tx_clk_src",
602	.parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
603	.num_parents = 7,
604	.ops = &clk_rcg2_ops,
605	},
606	};
607
608	static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
609	F(24000000, P_XO, 1, 0, 0),
610	F(200000000, P_GPLL0, 4, 0, 0),
611	F(240000000, P_GPLL4, 5, 0, 0),
612	{ }
613	};
614
615	static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
616	F(24000000, P_XO, 1, 0, 0),
617	F(100000000, P_GPLL0, 8, 0, 0),
618	{ }
619	};
620
621	static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
622	{ .fw_name = "xo" },
623	{ .hw = &gpll0.clkr.hw },
624	{ .hw = &gpll4.clkr.hw },
625	};
626
627	static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
628	{ P_XO, 0 },
629	{ P_GPLL0, 1 },
630	{ P_GPLL4, 2 },
631	};
632
633	static struct clk_rcg2 pcie0_axi_clk_src = {
634	.cmd_rcgr = 0x75054,
635	.freq_tbl = ftbl_pcie_axi_clk_src,
636	.hid_width = 5,
637	.parent_map = gcc_xo_gpll0_gpll4_map,
638	.clkr.hw.init = &(struct clk_init_data){
639	.name = "pcie0_axi_clk_src",
640	.parent_data = gcc_xo_gpll0_gpll4,
641	.num_parents = 3,
642	.ops = &clk_rcg2_ops,
643	},
644	};
645
646	static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
647	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
648	F(100000000, P_GPLL0, 8, 0, 0),
649	F(133330000, P_GPLL0, 6, 0, 0),
650	F(200000000, P_GPLL0, 4, 0, 0),
651	{ }
652	};
653
654	static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
655	{ .fw_name = "xo" },
656	{ .hw = &gpll0_out_main_div2.hw },
657	{ .hw = &gpll0.clkr.hw },
658	};
659
660	static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
661	{ P_XO, 0 },
662	{ P_GPLL0_DIV2, 2 },
663	{ P_GPLL0, 1 },
664	};
665
666	static struct clk_rcg2 usb0_master_clk_src = {
667	.cmd_rcgr = 0x3e00c,
668	.freq_tbl = ftbl_usb0_master_clk_src,
669	.mnd_width = 8,
670	.hid_width = 5,
671	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
672	.clkr.hw.init = &(struct clk_init_data){
673	.name = "usb0_master_clk_src",
674	.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
675	.num_parents = 3,
676	.ops = &clk_rcg2_ops,
677	},
678	};
679
680	static struct clk_regmap_div apss_ahb_postdiv_clk_src = {
681	.reg = 0x46018,
682	.shift = 4,
683	.width = 4,
684	.clkr = {
685	.hw.init = &(struct clk_init_data){
686	.name = "apss_ahb_postdiv_clk_src",
687	.parent_hws = (const struct clk_hw *[]){
688	&apss_ahb_clk_src.clkr.hw },
689	.num_parents = 1,
690	.ops = &clk_regmap_div_ops,
691	},
692	},
693	};
694
695	static struct clk_fixed_factor gcc_xo_div4_clk_src = {
696	.mult = 1,
697	.div = 4,
698	.hw.init = &(struct clk_init_data){
699	.name = "gcc_xo_div4_clk_src",
700	.parent_hws = (const struct clk_hw *[]){
701	&gcc_xo_clk_src.clkr.hw },
702	.num_parents = 1,
703	.ops = &clk_fixed_factor_ops,
704	.flags = CLK_SET_RATE_PARENT,
705	},
706	};
707
708	static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
709	F(24000000, P_XO, 1, 0, 0),
710	F(25000000, P_UNIPHY0_RX, 5, 0, 0),
711	F(125000000, P_UNIPHY0_RX, 1, 0, 0),
712	{ }
713	};
714
715	static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
716	{ .fw_name = "xo" },
717	{ .fw_name = "uniphy0_gcc_rx_clk" },
718	{ .fw_name = "uniphy0_gcc_tx_clk" },
719	{ .hw = &ubi32_pll.clkr.hw },
720	{ .fw_name = "bias_pll_cc_clk" },
721	};
722
723	static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
724	{ P_XO, 0 },
725	{ P_UNIPHY0_RX, 1 },
726	{ P_UNIPHY0_TX, 2 },
727	{ P_UBI32_PLL, 5 },
728	{ P_BIAS_PLL, 6 },
729	};
730
731	static struct clk_rcg2 nss_port1_rx_clk_src = {
732	.cmd_rcgr = 0x68020,
733	.freq_tbl = ftbl_nss_port1_rx_clk_src,
734	.hid_width = 5,
735	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
736	.clkr.hw.init = &(struct clk_init_data){
737	.name = "nss_port1_rx_clk_src",
738	.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
739	.num_parents = 5,
740	.ops = &clk_rcg2_ops,
741	},
742	};
743
744	static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
745	F(24000000, P_XO, 1, 0, 0),
746	F(25000000, P_UNIPHY0_TX, 5, 0, 0),
747	F(125000000, P_UNIPHY0_TX, 1, 0, 0),
748	{ }
749	};
750
751	static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
752	{ .fw_name = "xo" },
753	{ .fw_name = "uniphy0_gcc_tx_clk" },
754	{ .fw_name = "uniphy0_gcc_rx_clk" },
755	{ .hw = &ubi32_pll.clkr.hw },
756	{ .fw_name = "bias_pll_cc_clk" },
757	};
758
759	static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
760	{ P_XO, 0 },
761	{ P_UNIPHY0_TX, 1 },
762	{ P_UNIPHY0_RX, 2 },
763	{ P_UBI32_PLL, 5 },
764	{ P_BIAS_PLL, 6 },
765	};
766
767	static struct clk_rcg2 nss_port1_tx_clk_src = {
768	.cmd_rcgr = 0x68028,
769	.freq_tbl = ftbl_nss_port1_tx_clk_src,
770	.hid_width = 5,
771	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
772	.clkr.hw.init = &(struct clk_init_data){
773	.name = "nss_port1_tx_clk_src",
774	.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
775	.num_parents = 5,
776	.ops = &clk_rcg2_ops,
777	},
778	};
779
780	static struct clk_rcg2 nss_port2_rx_clk_src = {
781	.cmd_rcgr = 0x68030,
782	.freq_tbl = ftbl_nss_port1_rx_clk_src,
783	.hid_width = 5,
784	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
785	.clkr.hw.init = &(struct clk_init_data){
786	.name = "nss_port2_rx_clk_src",
787	.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
788	.num_parents = 5,
789	.ops = &clk_rcg2_ops,
790	},
791	};
792
793	static struct clk_rcg2 nss_port2_tx_clk_src = {
794	.cmd_rcgr = 0x68038,
795	.freq_tbl = ftbl_nss_port1_tx_clk_src,
796	.hid_width = 5,
797	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
798	.clkr.hw.init = &(struct clk_init_data){
799	.name = "nss_port2_tx_clk_src",
800	.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
801	.num_parents = 5,
802	.ops = &clk_rcg2_ops,
803	},
804	};
805
806	static struct clk_rcg2 nss_port3_rx_clk_src = {
807	.cmd_rcgr = 0x68040,
808	.freq_tbl = ftbl_nss_port1_rx_clk_src,
809	.hid_width = 5,
810	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
811	.clkr.hw.init = &(struct clk_init_data){
812	.name = "nss_port3_rx_clk_src",
813	.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
814	.num_parents = 5,
815	.ops = &clk_rcg2_ops,
816	},
817	};
818
819	static struct clk_rcg2 nss_port3_tx_clk_src = {
820	.cmd_rcgr = 0x68048,
821	.freq_tbl = ftbl_nss_port1_tx_clk_src,
822	.hid_width = 5,
823	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
824	.clkr.hw.init = &(struct clk_init_data){
825	.name = "nss_port3_tx_clk_src",
826	.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
827	.num_parents = 5,
828	.ops = &clk_rcg2_ops,
829	},
830	};
831
832	static struct clk_rcg2 nss_port4_rx_clk_src = {
833	.cmd_rcgr = 0x68050,
834	.freq_tbl = ftbl_nss_port1_rx_clk_src,
835	.hid_width = 5,
836	.parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
837	.clkr.hw.init = &(struct clk_init_data){
838	.name = "nss_port4_rx_clk_src",
839	.parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
840	.num_parents = 5,
841	.ops = &clk_rcg2_ops,
842	},
843	};
844
845	static struct clk_rcg2 nss_port4_tx_clk_src = {
846	.cmd_rcgr = 0x68058,
847	.freq_tbl = ftbl_nss_port1_tx_clk_src,
848	.hid_width = 5,
849	.parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
850	.clkr.hw.init = &(struct clk_init_data){
851	.name = "nss_port4_tx_clk_src",
852	.parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
853	.num_parents = 5,
854	.ops = &clk_rcg2_ops,
855	},
856	};
857
858	static struct clk_regmap_div nss_port5_rx_div_clk_src = {
859	.reg = 0x68440,
860	.shift = 0,
861	.width = 4,
862	.clkr = {
863	.hw.init = &(struct clk_init_data){
864	.name = "nss_port5_rx_div_clk_src",
865	.parent_hws = (const struct clk_hw *[]){
866	&nss_port5_rx_clk_src.clkr.hw },
867	.num_parents = 1,
868	.ops = &clk_regmap_div_ops,
869	.flags = CLK_SET_RATE_PARENT,
870	},
871	},
872	};
873
874	static struct clk_regmap_div nss_port5_tx_div_clk_src = {
875	.reg = 0x68444,
876	.shift = 0,
877	.width = 4,
878	.clkr = {
879	.hw.init = &(struct clk_init_data){
880	.name = "nss_port5_tx_div_clk_src",
881	.parent_hws = (const struct clk_hw *[]){
882	&nss_port5_tx_clk_src.clkr.hw },
883	.num_parents = 1,
884	.ops = &clk_regmap_div_ops,
885	.flags = CLK_SET_RATE_PARENT,
886	},
887	},
888	};
889
890	static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
891	F(24000000, P_XO, 1, 0, 0),
892	F(100000000, P_GPLL0_DIV2, 4, 0, 0),
893	F(200000000, P_GPLL0, 4, 0, 0),
894	F(308570000, P_GPLL6, 3.5, 0, 0),
895	F(400000000, P_GPLL0, 2, 0, 0),
896	F(533000000, P_GPLL0, 1.5, 0, 0),
897	{ }
898	};
899
900	static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = {
901	{ .fw_name = "xo" },
902	{ .hw = &gpll0.clkr.hw },
903	{ .hw = &gpll6.clkr.hw },
904	{ .hw = &ubi32_pll.clkr.hw },
905	{ .hw = &gpll0_out_main_div2.hw },
906	};
907
908	static const struct parent_map
909	gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = {
910	{ P_XO, 0 },
911	{ P_GPLL0, 1 },
912	{ P_GPLL6, 2 },
913	{ P_UBI32_PLL, 3 },
914	{ P_GPLL0_DIV2, 6 },
915	};
916
917	static struct clk_rcg2 apss_axi_clk_src = {
918	.cmd_rcgr = 0x38048,
919	.freq_tbl = ftbl_apss_axi_clk_src,
920	.hid_width = 5,
921	.parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map,
922	.clkr.hw.init = &(struct clk_init_data){
923	.name = "apss_axi_clk_src",
924	.parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2,
925	.num_parents = 5,
926	.ops = &clk_rcg2_ops,
927	},
928	};
929
930	static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
931	F(24000000, P_XO, 1, 0, 0),
932	F(300000000, P_NSS_CRYPTO_PLL, 2, 0, 0),
933	{ }
934	};
935
936	static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
937	{ .fw_name = "xo" },
938	{ .hw = &nss_crypto_pll.clkr.hw },
939	{ .hw = &gpll0.clkr.hw },
940	};
941
942	static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
943	{ P_XO, 0 },
944	{ P_NSS_CRYPTO_PLL, 1 },
945	{ P_GPLL0, 2 },
946	};
947
948	static struct clk_rcg2 nss_crypto_clk_src = {
949	.cmd_rcgr = 0x68144,
950	.freq_tbl = ftbl_nss_crypto_clk_src,
951	.mnd_width = 16,
952	.hid_width = 5,
953	.parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
954	.clkr.hw.init = &(struct clk_init_data){
955	.name = "nss_crypto_clk_src",
956	.parent_data = gcc_xo_nss_crypto_pll_gpll0,
957	.num_parents = 3,
958	.ops = &clk_rcg2_ops,
959	},
960	};
961
962	static struct clk_regmap_div nss_port1_rx_div_clk_src = {
963	.reg = 0x68400,
964	.shift = 0,
965	.width = 4,
966	.clkr = {
967	.hw.init = &(struct clk_init_data){
968	.name = "nss_port1_rx_div_clk_src",
969	.parent_hws = (const struct clk_hw *[]){
970	&nss_port1_rx_clk_src.clkr.hw },
971	.num_parents = 1,
972	.ops = &clk_regmap_div_ops,
973	.flags = CLK_SET_RATE_PARENT,
974	},
975	},
976	};
977
978	static struct clk_regmap_div nss_port1_tx_div_clk_src = {
979	.reg = 0x68404,
980	.shift = 0,
981	.width = 4,
982	.clkr = {
983	.hw.init = &(struct clk_init_data){
984	.name = "nss_port1_tx_div_clk_src",
985	.parent_hws = (const struct clk_hw *[]){
986	&nss_port1_tx_clk_src.clkr.hw },
987	.num_parents = 1,
988	.ops = &clk_regmap_div_ops,
989	.flags = CLK_SET_RATE_PARENT,
990	},
991	},
992	};
993
994	static struct clk_regmap_div nss_port2_rx_div_clk_src = {
995	.reg = 0x68410,
996	.shift = 0,
997	.width = 4,
998	.clkr = {
999	.hw.init = &(struct clk_init_data){
1000	.name = "nss_port2_rx_div_clk_src",
1001	.parent_hws = (const struct clk_hw *[]){
1002	&nss_port2_rx_clk_src.clkr.hw },
1003	.num_parents = 1,
1004	.ops = &clk_regmap_div_ops,
1005	.flags = CLK_SET_RATE_PARENT,
1006	},
1007	},
1008	};
1009
1010	static struct clk_regmap_div nss_port2_tx_div_clk_src = {
1011	.reg = 0x68414,
1012	.shift = 0,
1013	.width = 4,
1014	.clkr = {
1015	.hw.init = &(struct clk_init_data){
1016	.name = "nss_port2_tx_div_clk_src",
1017	.parent_hws = (const struct clk_hw *[]){
1018	&nss_port2_tx_clk_src.clkr.hw },
1019	.num_parents = 1,
1020	.ops = &clk_regmap_div_ops,
1021	.flags = CLK_SET_RATE_PARENT,
1022	},
1023	},
1024	};
1025
1026	static struct clk_regmap_div nss_port3_rx_div_clk_src = {
1027	.reg = 0x68420,
1028	.shift = 0,
1029	.width = 4,
1030	.clkr = {
1031	.hw.init = &(struct clk_init_data){
1032	.name = "nss_port3_rx_div_clk_src",
1033	.parent_hws = (const struct clk_hw *[]){
1034	&nss_port3_rx_clk_src.clkr.hw },
1035	.num_parents = 1,
1036	.ops = &clk_regmap_div_ops,
1037	.flags = CLK_SET_RATE_PARENT,
1038	},
1039	},
1040	};
1041
1042	static struct clk_regmap_div nss_port3_tx_div_clk_src = {
1043	.reg = 0x68424,
1044	.shift = 0,
1045	.width = 4,
1046	.clkr = {
1047	.hw.init = &(struct clk_init_data){
1048	.name = "nss_port3_tx_div_clk_src",
1049	.parent_hws = (const struct clk_hw *[]){
1050	&nss_port3_tx_clk_src.clkr.hw },
1051	.num_parents = 1,
1052	.ops = &clk_regmap_div_ops,
1053	.flags = CLK_SET_RATE_PARENT,
1054	},
1055	},
1056	};
1057
1058	static struct clk_regmap_div nss_port4_rx_div_clk_src = {
1059	.reg = 0x68430,
1060	.shift = 0,
1061	.width = 4,
1062	.clkr = {
1063	.hw.init = &(struct clk_init_data){
1064	.name = "nss_port4_rx_div_clk_src",
1065	.parent_hws = (const struct clk_hw *[]){
1066	&nss_port4_rx_clk_src.clkr.hw },
1067	.num_parents = 1,
1068	.ops = &clk_regmap_div_ops,
1069	.flags = CLK_SET_RATE_PARENT,
1070	},
1071	},
1072	};
1073
1074	static struct clk_regmap_div nss_port4_tx_div_clk_src = {
1075	.reg = 0x68434,
1076	.shift = 0,
1077	.width = 4,
1078	.clkr = {
1079	.hw.init = &(struct clk_init_data){
1080	.name = "nss_port4_tx_div_clk_src",
1081	.parent_hws = (const struct clk_hw *[]){
1082	&nss_port4_tx_clk_src.clkr.hw },
1083	.num_parents = 1,
1084	.ops = &clk_regmap_div_ops,
1085	.flags = CLK_SET_RATE_PARENT,
1086	},
1087	},
1088	};
1089
1090	static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1091	F(24000000, P_XO, 1, 0, 0),
1092	F(149760000, P_UBI32_PLL, 10, 0, 0),
1093	F(187200000, P_UBI32_PLL, 8, 0, 0),
1094	F(249600000, P_UBI32_PLL, 6, 0, 0),
1095	F(374400000, P_UBI32_PLL, 4, 0, 0),
1096	F(748800000, P_UBI32_PLL, 2, 0, 0),
1097	F(1497600000, P_UBI32_PLL, 1, 0, 0),
1098	{ }
1099	};
1100
1101	static const struct clk_parent_data
1102	gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
1103	{ .fw_name = "xo" },
1104	{ .hw = &ubi32_pll.clkr.hw },
1105	{ .hw = &gpll0.clkr.hw },
1106	{ .hw = &gpll2.clkr.hw },
1107	{ .hw = &gpll4.clkr.hw },
1108	{ .hw = &gpll6.clkr.hw },
1109	};
1110
1111	static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
1112	{ P_XO, 0 },
1113	{ P_UBI32_PLL, 1 },
1114	{ P_GPLL0, 2 },
1115	{ P_GPLL2, 3 },
1116	{ P_GPLL4, 4 },
1117	{ P_GPLL6, 5 },
1118	};
1119
1120	static struct clk_rcg2 nss_ubi0_clk_src = {
1121	.cmd_rcgr = 0x68104,
1122	.freq_tbl = ftbl_nss_ubi_clk_src,
1123	.hid_width = 5,
1124	.parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1125	.clkr.hw.init = &(struct clk_init_data){
1126	.name = "nss_ubi0_clk_src",
1127	.parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1128	.num_parents = 6,
1129	.ops = &clk_rcg2_ops,
1130	.flags = CLK_SET_RATE_PARENT,
1131	},
1132	};
1133
1134	static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
1135	F(24000000, P_XO, 1, 0, 0),
1136	F(100000000, P_GPLL0, 8, 0, 0),
1137	{ }
1138	};
1139
1140	static struct clk_rcg2 adss_pwm_clk_src = {
1141	.cmd_rcgr = 0x1c008,
1142	.freq_tbl = ftbl_adss_pwm_clk_src,
1143	.hid_width = 5,
1144	.parent_map = gcc_xo_gpll0_map,
1145	.clkr.hw.init = &(struct clk_init_data){
1146	.name = "adss_pwm_clk_src",
1147	.parent_data = gcc_xo_gpll0,
1148	.num_parents = 2,
1149	.ops = &clk_rcg2_ops,
1150	},
1151	};
1152
1153	static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
1154	F(24000000, P_XO, 1, 0, 0),
1155	F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1156	F(50000000, P_GPLL0, 16, 0, 0),
1157	{ }
1158	};
1159
1160	static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
1161	.cmd_rcgr = 0x0200c,
1162	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1163	.hid_width = 5,
1164	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1165	.clkr.hw.init = &(struct clk_init_data){
1166	.name = "blsp1_qup1_i2c_apps_clk_src",
1167	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1168	.num_parents = 3,
1169	.ops = &clk_rcg2_ops,
1170	},
1171	};
1172
1173	static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
1174	F(960000, P_XO, 10, 2, 5),
1175	F(4800000, P_XO, 5, 0, 0),
1176	F(9600000, P_XO, 2, 4, 5),
1177	F(12500000, P_GPLL0_DIV2, 16, 1, 2),
1178	F(16000000, P_GPLL0, 10, 1, 5),
1179	F(24000000, P_XO, 1, 0, 0),
1180	F(25000000, P_GPLL0, 16, 1, 2),
1181	F(50000000, P_GPLL0, 16, 0, 0),
1182	{ }
1183	};
1184
1185	static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
1186	.cmd_rcgr = 0x02024,
1187	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1188	.mnd_width = 8,
1189	.hid_width = 5,
1190	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1191	.clkr.hw.init = &(struct clk_init_data){
1192	.name = "blsp1_qup1_spi_apps_clk_src",
1193	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1194	.num_parents = 3,
1195	.ops = &clk_rcg2_ops,
1196	},
1197	};
1198
1199	static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
1200	.cmd_rcgr = 0x03000,
1201	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1202	.hid_width = 5,
1203	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1204	.clkr.hw.init = &(struct clk_init_data){
1205	.name = "blsp1_qup2_i2c_apps_clk_src",
1206	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1207	.num_parents = 3,
1208	.ops = &clk_rcg2_ops,
1209	},
1210	};
1211
1212	static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
1213	.cmd_rcgr = 0x03014,
1214	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1215	.mnd_width = 8,
1216	.hid_width = 5,
1217	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1218	.clkr.hw.init = &(struct clk_init_data){
1219	.name = "blsp1_qup2_spi_apps_clk_src",
1220	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1221	.num_parents = 3,
1222	.ops = &clk_rcg2_ops,
1223	},
1224	};
1225
1226	static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
1227	.cmd_rcgr = 0x04000,
1228	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1229	.hid_width = 5,
1230	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1231	.clkr.hw.init = &(struct clk_init_data){
1232	.name = "blsp1_qup3_i2c_apps_clk_src",
1233	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1234	.num_parents = 3,
1235	.ops = &clk_rcg2_ops,
1236	},
1237	};
1238
1239	static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
1240	.cmd_rcgr = 0x04014,
1241	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1242	.mnd_width = 8,
1243	.hid_width = 5,
1244	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1245	.clkr.hw.init = &(struct clk_init_data){
1246	.name = "blsp1_qup3_spi_apps_clk_src",
1247	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1248	.num_parents = 3,
1249	.ops = &clk_rcg2_ops,
1250	},
1251	};
1252
1253	static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
1254	.cmd_rcgr = 0x05000,
1255	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1256	.hid_width = 5,
1257	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1258	.clkr.hw.init = &(struct clk_init_data){
1259	.name = "blsp1_qup4_i2c_apps_clk_src",
1260	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1261	.num_parents = 3,
1262	.ops = &clk_rcg2_ops,
1263	},
1264	};
1265
1266	static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
1267	.cmd_rcgr = 0x05014,
1268	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1269	.mnd_width = 8,
1270	.hid_width = 5,
1271	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1272	.clkr.hw.init = &(struct clk_init_data){
1273	.name = "blsp1_qup4_spi_apps_clk_src",
1274	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1275	.num_parents = 3,
1276	.ops = &clk_rcg2_ops,
1277	},
1278	};
1279
1280	static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
1281	.cmd_rcgr = 0x06000,
1282	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1283	.hid_width = 5,
1284	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1285	.clkr.hw.init = &(struct clk_init_data){
1286	.name = "blsp1_qup5_i2c_apps_clk_src",
1287	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1288	.num_parents = 3,
1289	.ops = &clk_rcg2_ops,
1290	},
1291	};
1292
1293	static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
1294	.cmd_rcgr = 0x06014,
1295	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1296	.mnd_width = 8,
1297	.hid_width = 5,
1298	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1299	.clkr.hw.init = &(struct clk_init_data){
1300	.name = "blsp1_qup5_spi_apps_clk_src",
1301	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1302	.num_parents = 3,
1303	.ops = &clk_rcg2_ops,
1304	},
1305	};
1306
1307	static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
1308	.cmd_rcgr = 0x07000,
1309	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
1310	.hid_width = 5,
1311	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1312	.clkr.hw.init = &(struct clk_init_data){
1313	.name = "blsp1_qup6_i2c_apps_clk_src",
1314	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1315	.num_parents = 3,
1316	.ops = &clk_rcg2_ops,
1317	},
1318	};
1319
1320	static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
1321	.cmd_rcgr = 0x07014,
1322	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
1323	.mnd_width = 8,
1324	.hid_width = 5,
1325	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1326	.clkr.hw.init = &(struct clk_init_data){
1327	.name = "blsp1_qup6_spi_apps_clk_src",
1328	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1329	.num_parents = 3,
1330	.ops = &clk_rcg2_ops,
1331	},
1332	};
1333
1334	static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
1335	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
1336	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
1337	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
1338	F(16000000, P_GPLL0_DIV2, 5, 1, 5),
1339	F(24000000, P_XO, 1, 0, 0),
1340	F(24000000, P_GPLL0, 1, 3, 100),
1341	F(25000000, P_GPLL0, 16, 1, 2),
1342	F(32000000, P_GPLL0, 1, 1, 25),
1343	F(40000000, P_GPLL0, 1, 1, 20),
1344	F(46400000, P_GPLL0, 1, 29, 500),
1345	F(48000000, P_GPLL0, 1, 3, 50),
1346	F(51200000, P_GPLL0, 1, 8, 125),
1347	F(56000000, P_GPLL0, 1, 7, 100),
1348	F(58982400, P_GPLL0, 1, 1152, 15625),
1349	F(60000000, P_GPLL0, 1, 3, 40),
1350	F(64000000, P_GPLL0, 12.5, 1, 1),
1351	{ }
1352	};
1353
1354	static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
1355	.cmd_rcgr = 0x02044,
1356	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1357	.mnd_width = 16,
1358	.hid_width = 5,
1359	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1360	.clkr.hw.init = &(struct clk_init_data){
1361	.name = "blsp1_uart1_apps_clk_src",
1362	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1363	.num_parents = 3,
1364	.ops = &clk_rcg2_ops,
1365	},
1366	};
1367
1368	static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
1369	.cmd_rcgr = 0x03034,
1370	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1371	.mnd_width = 16,
1372	.hid_width = 5,
1373	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1374	.clkr.hw.init = &(struct clk_init_data){
1375	.name = "blsp1_uart2_apps_clk_src",
1376	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1377	.num_parents = 3,
1378	.ops = &clk_rcg2_ops,
1379	},
1380	};
1381
1382	static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
1383	.cmd_rcgr = 0x04034,
1384	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1385	.mnd_width = 16,
1386	.hid_width = 5,
1387	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1388	.clkr.hw.init = &(struct clk_init_data){
1389	.name = "blsp1_uart3_apps_clk_src",
1390	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1391	.num_parents = 3,
1392	.ops = &clk_rcg2_ops,
1393	},
1394	};
1395
1396	static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
1397	.cmd_rcgr = 0x05034,
1398	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1399	.mnd_width = 16,
1400	.hid_width = 5,
1401	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1402	.clkr.hw.init = &(struct clk_init_data){
1403	.name = "blsp1_uart4_apps_clk_src",
1404	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1405	.num_parents = 3,
1406	.ops = &clk_rcg2_ops,
1407	},
1408	};
1409
1410	static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
1411	.cmd_rcgr = 0x06034,
1412	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1413	.mnd_width = 16,
1414	.hid_width = 5,
1415	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1416	.clkr.hw.init = &(struct clk_init_data){
1417	.name = "blsp1_uart5_apps_clk_src",
1418	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1419	.num_parents = 3,
1420	.ops = &clk_rcg2_ops,
1421	},
1422	};
1423
1424	static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
1425	.cmd_rcgr = 0x07034,
1426	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
1427	.mnd_width = 16,
1428	.hid_width = 5,
1429	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1430	.clkr.hw.init = &(struct clk_init_data){
1431	.name = "blsp1_uart6_apps_clk_src",
1432	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1433	.num_parents = 3,
1434	.ops = &clk_rcg2_ops,
1435	},
1436	};
1437
1438	static const struct freq_tbl ftbl_crypto_clk_src[] = {
1439	F(40000000, P_GPLL0_DIV2, 10, 0, 0),
1440	F(80000000, P_GPLL0, 10, 0, 0),
1441	F(100000000, P_GPLL0, 8, 0, 0),
1442	F(160000000, P_GPLL0, 5, 0, 0),
1443	{ }
1444	};
1445
1446	static struct clk_rcg2 crypto_clk_src = {
1447	.cmd_rcgr = 0x16004,
1448	.freq_tbl = ftbl_crypto_clk_src,
1449	.hid_width = 5,
1450	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1451	.clkr.hw.init = &(struct clk_init_data){
1452	.name = "crypto_clk_src",
1453	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1454	.num_parents = 3,
1455	.ops = &clk_rcg2_ops,
1456	},
1457	};
1458
1459	static const struct freq_tbl ftbl_gp_clk_src[] = {
1460	F(24000000, P_XO, 1, 0, 0),
1461	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1462	F(100000000, P_GPLL0, 8, 0, 0),
1463	F(200000000, P_GPLL0, 4, 0, 0),
1464	F(266666666, P_GPLL0, 3, 0, 0),
1465	{ }
1466	};
1467
1468	static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
1469	{ .fw_name = "xo" },
1470	{ .hw = &gpll0.clkr.hw },
1471	{ .hw = &gpll6.clkr.hw },
1472	{ .hw = &gpll0_out_main_div2.hw },
1473	{ .fw_name = "sleep_clk" },
1474	};
1475
1476	static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
1477	{ P_XO, 0 },
1478	{ P_GPLL0, 1 },
1479	{ P_GPLL6, 2 },
1480	{ P_GPLL0_DIV2, 4 },
1481	{ P_SLEEP_CLK, 6 },
1482	};
1483
1484	static struct clk_rcg2 gp1_clk_src = {
1485	.cmd_rcgr = 0x08004,
1486	.freq_tbl = ftbl_gp_clk_src,
1487	.mnd_width = 8,
1488	.hid_width = 5,
1489	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1490	.clkr.hw.init = &(struct clk_init_data){
1491	.name = "gp1_clk_src",
1492	.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1493	.num_parents = 5,
1494	.ops = &clk_rcg2_ops,
1495	},
1496	};
1497
1498	static struct clk_rcg2 gp2_clk_src = {
1499	.cmd_rcgr = 0x09004,
1500	.freq_tbl = ftbl_gp_clk_src,
1501	.mnd_width = 8,
1502	.hid_width = 5,
1503	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1504	.clkr.hw.init = &(struct clk_init_data){
1505	.name = "gp2_clk_src",
1506	.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1507	.num_parents = 5,
1508	.ops = &clk_rcg2_ops,
1509	},
1510	};
1511
1512	static struct clk_rcg2 gp3_clk_src = {
1513	.cmd_rcgr = 0x0a004,
1514	.freq_tbl = ftbl_gp_clk_src,
1515	.mnd_width = 8,
1516	.hid_width = 5,
1517	.parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
1518	.clkr.hw.init = &(struct clk_init_data){
1519	.name = "gp3_clk_src",
1520	.parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
1521	.num_parents = 5,
1522	.ops = &clk_rcg2_ops,
1523	},
1524	};
1525
1526	static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1527	.mult = 1,
1528	.div = 4,
1529	.hw.init = &(struct clk_init_data){
1530	.name = "nss_ppe_cdiv_clk_src",
1531	.parent_hws = (const struct clk_hw *[]){
1532	&nss_ppe_clk_src.clkr.hw },
1533	.num_parents = 1,
1534	.ops = &clk_fixed_factor_ops,
1535	.flags = CLK_SET_RATE_PARENT,
1536	},
1537	};
1538
1539	static struct clk_regmap_div nss_ubi0_div_clk_src = {
1540	.reg = 0x68118,
1541	.shift = 0,
1542	.width = 4,
1543	.clkr = {
1544	.hw.init = &(struct clk_init_data){
1545	.name = "nss_ubi0_div_clk_src",
1546	.parent_hws = (const struct clk_hw *[]){
1547	&nss_ubi0_clk_src.clkr.hw },
1548	.num_parents = 1,
1549	.ops = &clk_regmap_div_ro_ops,
1550	.flags = CLK_SET_RATE_PARENT,
1551	},
1552	},
1553	};
1554
1555	static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1556	F(24000000, P_XO, 1, 0, 0),
1557	{ }
1558	};
1559
1560	static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
1561	{ .fw_name = "xo" },
1562	{ .hw = &gpll0.clkr.hw },
1563	{ .fw_name = "sleep_clk" },
1564	};
1565
1566	static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
1567	{ P_XO, 0 },
1568	{ P_GPLL0, 2 },
1569	{ P_PI_SLEEP, 6 },
1570	};
1571
1572	static struct clk_rcg2 pcie0_aux_clk_src = {
1573	.cmd_rcgr = 0x75024,
1574	.freq_tbl = ftbl_pcie_aux_clk_src,
1575	.mnd_width = 16,
1576	.hid_width = 5,
1577	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1578	.clkr.hw.init = &(struct clk_init_data){
1579	.name = "pcie0_aux_clk_src",
1580	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1581	.num_parents = 3,
1582	.ops = &clk_rcg2_ops,
1583	},
1584	};
1585
1586	static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
1587	{ .fw_name = "pcie20_phy0_pipe_clk" },
1588	{ .fw_name = "xo" },
1589	};
1590
1591	static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
1592	{ P_PCIE20_PHY0_PIPE, 0 },
1593	{ P_XO, 2 },
1594	};
1595
1596	static struct clk_regmap_mux pcie0_pipe_clk_src = {
1597	.reg = 0x7501c,
1598	.shift = 8,
1599	.width = 2,
1600	.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
1601	.clkr = {
1602	.hw.init = &(struct clk_init_data){
1603	.name = "pcie0_pipe_clk_src",
1604	.parent_data = gcc_pcie20_phy0_pipe_clk_xo,
1605	.num_parents = 2,
1606	.ops = &clk_regmap_mux_closest_ops,
1607	.flags = CLK_SET_RATE_PARENT,
1608	},
1609	},
1610	};
1611
1612	static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
1613	F(144000, P_XO, 16, 12, 125),
1614	F(400000, P_XO, 12, 1, 5),
1615	F(24000000, P_GPLL2, 12, 1, 4),
1616	F(48000000, P_GPLL2, 12, 1, 2),
1617	F(96000000, P_GPLL2, 12, 0, 0),
1618	F(177777778, P_GPLL0, 4.5, 0, 0),
1619	F(192000000, P_GPLL2, 6, 0, 0),
1620	F(384000000, P_GPLL2, 3, 0, 0),
1621	{ }
1622	};
1623
1624	static const struct clk_parent_data
1625	gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
1626	{ .fw_name = "xo" },
1627	{ .hw = &gpll0.clkr.hw },
1628	{ .hw = &gpll2.clkr.hw },
1629	{ .hw = &gpll0_out_main_div2.hw },
1630	};
1631
1632	static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
1633	{ P_XO, 0 },
1634	{ P_GPLL0, 1 },
1635	{ P_GPLL2, 2 },
1636	{ P_GPLL0_DIV2, 4 },
1637	};
1638
1639	static struct clk_rcg2 sdcc1_apps_clk_src = {
1640	.cmd_rcgr = 0x42004,
1641	.freq_tbl = ftbl_sdcc_apps_clk_src,
1642	.mnd_width = 8,
1643	.hid_width = 5,
1644	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
1645	.clkr.hw.init = &(struct clk_init_data){
1646	.name = "sdcc1_apps_clk_src",
1647	.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1648	.num_parents = 4,
1649	.ops = &clk_rcg2_floor_ops,
1650	},
1651	};
1652
1653	static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1654	F(24000000, P_XO, 1, 0, 0),
1655	{ }
1656	};
1657
1658	static struct clk_rcg2 usb0_aux_clk_src = {
1659	.cmd_rcgr = 0x3e05c,
1660	.freq_tbl = ftbl_usb_aux_clk_src,
1661	.mnd_width = 16,
1662	.hid_width = 5,
1663	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1664	.clkr.hw.init = &(struct clk_init_data){
1665	.name = "usb0_aux_clk_src",
1666	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1667	.num_parents = 3,
1668	.ops = &clk_rcg2_ops,
1669	},
1670	};
1671
1672	static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1673	F(24000000, P_XO, 1, 0, 0),
1674	F(60000000, P_GPLL6, 6, 1, 3),
1675	{ }
1676	};
1677
1678	static const struct clk_parent_data
1679	gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
1680	{ .fw_name = "xo" },
1681	{ .hw = &gpll6.clkr.hw },
1682	{ .hw = &gpll0.clkr.hw },
1683	{ .hw = &gpll0_out_main_div2.hw },
1684	};
1685
1686	static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
1687	{ P_XO, 0 },
1688	{ P_GPLL6, 1 },
1689	{ P_GPLL0, 3 },
1690	{ P_GPLL0_DIV2, 4 },
1691	};
1692
1693	static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1694	.cmd_rcgr = 0x3e020,
1695	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1696	.mnd_width = 8,
1697	.hid_width = 5,
1698	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1699	.clkr.hw.init = &(struct clk_init_data){
1700	.name = "usb0_mock_utmi_clk_src",
1701	.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1702	.num_parents = 4,
1703	.ops = &clk_rcg2_ops,
1704	},
1705	};
1706
1707	static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
1708	{ .fw_name = "usb3phy_0_cc_pipe_clk" },
1709	{ .fw_name = "xo" },
1710	};
1711
1712	static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
1713	{ P_USB3PHY_0_PIPE, 0 },
1714	{ P_XO, 2 },
1715	};
1716
1717	static struct clk_regmap_mux usb0_pipe_clk_src = {
1718	.reg = 0x3e048,
1719	.shift = 8,
1720	.width = 2,
1721	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1722	.clkr = {
1723	.hw.init = &(struct clk_init_data){
1724	.name = "usb0_pipe_clk_src",
1725	.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1726	.num_parents = 2,
1727	.ops = &clk_regmap_mux_closest_ops,
1728	.flags = CLK_SET_RATE_PARENT,
1729	},
1730	},
1731	};
1732
1733	static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
1734	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1735	F(160000000, P_GPLL0, 5, 0, 0),
1736	F(216000000, P_GPLL6, 5, 0, 0),
1737	F(308570000, P_GPLL6, 3.5, 0, 0),
1738	{ }
1739	};
1740
1741	static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
1742	{ .fw_name = "xo"},
1743	{ .hw = &gpll0.clkr.hw },
1744	{ .hw = &gpll6.clkr.hw },
1745	{ .hw = &gpll0_out_main_div2.hw },
1746	};
1747
1748	static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
1749	{ P_XO, 0 },
1750	{ P_GPLL0, 1 },
1751	{ P_GPLL6, 2 },
1752	{ P_GPLL0_DIV2, 4 },
1753	};
1754
1755	static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1756	.cmd_rcgr = 0x5d000,
1757	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
1758	.mnd_width = 8,
1759	.hid_width = 5,
1760	.parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
1761	.clkr.hw.init = &(struct clk_init_data){
1762	.name = "sdcc1_ice_core_clk_src",
1763	.parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
1764	.num_parents = 4,
1765	.ops = &clk_rcg2_ops,
1766	},
1767	};
1768
1769	static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
1770	F(24000000, P_XO, 1, 0, 0),
1771	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1772	F(100000000, P_GPLL0, 8, 0, 0),
1773	F(200000000, P_GPLL0, 4, 0, 0),
1774	{ }
1775	};
1776
1777	static struct clk_rcg2 qdss_stm_clk_src = {
1778	.cmd_rcgr = 0x2902C,
1779	.freq_tbl = ftbl_qdss_stm_clk_src,
1780	.hid_width = 5,
1781	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
1782	.clkr.hw.init = &(struct clk_init_data){
1783	.name = "qdss_stm_clk_src",
1784	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
1785	.num_parents = 3,
1786	.ops = &clk_rcg2_ops,
1787	},
1788	};
1789
1790	static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
1791	F(80000000, P_GPLL0_DIV2, 5, 0, 0),
1792	F(160000000, P_GPLL0, 5, 0, 0),
1793	F(300000000, P_GPLL4, 4, 0, 0),
1794	{ }
1795	};
1796
1797	static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
1798	{ .fw_name = "xo" },
1799	{ .hw = &gpll4.clkr.hw },
1800	{ .hw = &gpll0.clkr.hw },
1801	{ .hw = &gpll0_out_main_div2.hw },
1802	};
1803
1804	static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
1805	{ P_XO, 0 },
1806	{ P_GPLL4, 1 },
1807	{ P_GPLL0, 2 },
1808	{ P_GPLL0_DIV2, 4 },
1809	};
1810
1811	static struct clk_rcg2 qdss_traceclkin_clk_src = {
1812	.cmd_rcgr = 0x29048,
1813	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
1814	.hid_width = 5,
1815	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
1816	.clkr.hw.init = &(struct clk_init_data){
1817	.name = "qdss_traceclkin_clk_src",
1818	.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
1819	.num_parents = 4,
1820	.ops = &clk_rcg2_ops,
1821	},
1822	};
1823
1824	static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1825	.cmd_rcgr = 0x3f020,
1826	.freq_tbl = ftbl_usb_mock_utmi_clk_src,
1827	.mnd_width = 8,
1828	.hid_width = 5,
1829	.parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1830	.clkr.hw.init = &(struct clk_init_data){
1831	.name = "usb1_mock_utmi_clk_src",
1832	.parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1833	.num_parents = 4,
1834	.ops = &clk_rcg2_ops,
1835	},
1836	};
1837
1838	static struct clk_branch gcc_adss_pwm_clk = {
1839	.halt_reg = 0x1c020,
1840	.clkr = {
1841	.enable_reg = 0x1c020,
1842	.enable_mask = BIT(0),
1843	.hw.init = &(struct clk_init_data){
1844	.name = "gcc_adss_pwm_clk",
1845	.parent_hws = (const struct clk_hw *[]){
1846	&adss_pwm_clk_src.clkr.hw },
1847	.num_parents = 1,
1848	.flags = CLK_SET_RATE_PARENT,
1849	.ops = &clk_branch2_ops,
1850	},
1851	},
1852	};
1853
1854	static struct clk_branch gcc_apss_ahb_clk = {
1855	.halt_reg = 0x4601c,
1856	.halt_check = BRANCH_HALT_VOTED,
1857	.clkr = {
1858	.enable_reg = 0x0b004,
1859	.enable_mask = BIT(14),
1860	.hw.init = &(struct clk_init_data){
1861	.name = "gcc_apss_ahb_clk",
1862	.parent_hws = (const struct clk_hw *[]){
1863	&apss_ahb_postdiv_clk_src.clkr.hw },
1864	.num_parents = 1,
1865	.flags = CLK_SET_RATE_PARENT,
1866	.ops = &clk_branch2_ops,
1867	},
1868	},
1869	};
1870
1871	static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1872	F(24000000, P_XO, 1, 0, 0),
1873	F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1874	F(100000000, P_GPLL0, 8, 0, 0),
1875	F(133333333, P_GPLL0, 6, 0, 0),
1876	F(160000000, P_GPLL0, 5, 0, 0),
1877	F(200000000, P_GPLL0, 4, 0, 0),
1878	F(266666667, P_GPLL0, 3, 0, 0),
1879	{ }
1880	};
1881
1882	static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1883	.cmd_rcgr = 0x26004,
1884	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1885	.hid_width = 5,
1886	.parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1887	.clkr.hw.init = &(struct clk_init_data){
1888	.name = "system_noc_bfdcd_clk_src",
1889	.parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1890	.num_parents = 4,
1891	.ops = &clk_rcg2_ops,
1892	},
1893	};
1894
1895	static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = {
1896	F(24000000, P_XO, 1, 0, 0),
1897	F(307670000, P_BIAS_PLL_NSS_NOC, 1.5, 0, 0),
1898	F(533333333, P_GPLL0, 1.5, 0, 0),
1899	{ }
1900	};
1901
1902	static const struct clk_parent_data
1903	gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
1904	{ .fw_name = "xo" },
1905	{ .hw = &gpll0.clkr.hw },
1906	{ .hw = &gpll2.clkr.hw },
1907	{ .fw_name = "bias_pll_nss_noc_clk" },
1908	};
1909
1910	static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
1911	{ P_XO, 0 },
1912	{ P_GPLL0, 1 },
1913	{ P_GPLL2, 3 },
1914	{ P_BIAS_PLL_NSS_NOC, 4 },
1915	};
1916
1917	static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = {
1918	.cmd_rcgr = 0x68088,
1919	.freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src,
1920	.hid_width = 5,
1921	.parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map,
1922	.clkr.hw.init = &(struct clk_init_data){
1923	.name = "ubi32_mem_noc_bfdcd_clk_src",
1924	.parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk,
1925	.num_parents = 4,
1926	.ops = &clk_rcg2_ops,
1927	},
1928	};
1929
1930	static struct clk_branch gcc_apss_axi_clk = {
1931	.halt_reg = 0x46020,
1932	.halt_check = BRANCH_HALT_VOTED,
1933	.clkr = {
1934	.enable_reg = 0x0b004,
1935	.enable_mask = BIT(13),
1936	.hw.init = &(struct clk_init_data){
1937	.name = "gcc_apss_axi_clk",
1938	.parent_hws = (const struct clk_hw *[]){
1939	&apss_axi_clk_src.clkr.hw },
1940	.num_parents = 1,
1941	.flags = CLK_SET_RATE_PARENT,
1942	.ops = &clk_branch2_ops,
1943	},
1944	},
1945	};
1946
1947	static struct clk_branch gcc_blsp1_ahb_clk = {
1948	.halt_reg = 0x01008,
1949	.halt_check = BRANCH_HALT_VOTED,
1950	.clkr = {
1951	.enable_reg = 0x0b004,
1952	.enable_mask = BIT(10),
1953	.hw.init = &(struct clk_init_data){
1954	.name = "gcc_blsp1_ahb_clk",
1955	.parent_hws = (const struct clk_hw *[]){
1956	&pcnoc_bfdcd_clk_src.clkr.hw },
1957	.num_parents = 1,
1958	.flags = CLK_SET_RATE_PARENT,
1959	.ops = &clk_branch2_ops,
1960	},
1961	},
1962	};
1963
1964	static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1965	.halt_reg = 0x02008,
1966	.clkr = {
1967	.enable_reg = 0x02008,
1968	.enable_mask = BIT(0),
1969	.hw.init = &(struct clk_init_data){
1970	.name = "gcc_blsp1_qup1_i2c_apps_clk",
1971	.parent_hws = (const struct clk_hw *[]){
1972	&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1973	.num_parents = 1,
1974	.flags = CLK_SET_RATE_PARENT,
1975	.ops = &clk_branch2_ops,
1976	},
1977	},
1978	};
1979
1980	static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1981	.halt_reg = 0x02004,
1982	.clkr = {
1983	.enable_reg = 0x02004,
1984	.enable_mask = BIT(0),
1985	.hw.init = &(struct clk_init_data){
1986	.name = "gcc_blsp1_qup1_spi_apps_clk",
1987	.parent_hws = (const struct clk_hw *[]){
1988	&blsp1_qup1_spi_apps_clk_src.clkr.hw },
1989	.num_parents = 1,
1990	.flags = CLK_SET_RATE_PARENT,
1991	.ops = &clk_branch2_ops,
1992	},
1993	},
1994	};
1995
1996	static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1997	.halt_reg = 0x03010,
1998	.clkr = {
1999	.enable_reg = 0x03010,
2000	.enable_mask = BIT(0),
2001	.hw.init = &(struct clk_init_data){
2002	.name = "gcc_blsp1_qup2_i2c_apps_clk",
2003	.parent_hws = (const struct clk_hw *[]){
2004	&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
2005	.num_parents = 1,
2006	.flags = CLK_SET_RATE_PARENT,
2007	.ops = &clk_branch2_ops,
2008	},
2009	},
2010	};
2011
2012	static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
2013	.halt_reg = 0x0300c,
2014	.clkr = {
2015	.enable_reg = 0x0300c,
2016	.enable_mask = BIT(0),
2017	.hw.init = &(struct clk_init_data){
2018	.name = "gcc_blsp1_qup2_spi_apps_clk",
2019	.parent_hws = (const struct clk_hw *[]){
2020	&blsp1_qup2_spi_apps_clk_src.clkr.hw },
2021	.num_parents = 1,
2022	.flags = CLK_SET_RATE_PARENT,
2023	.ops = &clk_branch2_ops,
2024	},
2025	},
2026	};
2027
2028	static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
2029	.halt_reg = 0x04010,
2030	.clkr = {
2031	.enable_reg = 0x04010,
2032	.enable_mask = BIT(0),
2033	.hw.init = &(struct clk_init_data){
2034	.name = "gcc_blsp1_qup3_i2c_apps_clk",
2035	.parent_hws = (const struct clk_hw *[]){
2036	&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
2037	.num_parents = 1,
2038	.flags = CLK_SET_RATE_PARENT,
2039	.ops = &clk_branch2_ops,
2040	},
2041	},
2042	};
2043
2044	static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
2045	.halt_reg = 0x0400c,
2046	.clkr = {
2047	.enable_reg = 0x0400c,
2048	.enable_mask = BIT(0),
2049	.hw.init = &(struct clk_init_data){
2050	.name = "gcc_blsp1_qup3_spi_apps_clk",
2051	.parent_hws = (const struct clk_hw *[]){
2052	&blsp1_qup3_spi_apps_clk_src.clkr.hw },
2053	.num_parents = 1,
2054	.flags = CLK_SET_RATE_PARENT,
2055	.ops = &clk_branch2_ops,
2056	},
2057	},
2058	};
2059
2060	static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
2061	.halt_reg = 0x05010,
2062	.clkr = {
2063	.enable_reg = 0x05010,
2064	.enable_mask = BIT(0),
2065	.hw.init = &(struct clk_init_data){
2066	.name = "gcc_blsp1_qup4_i2c_apps_clk",
2067	.parent_hws = (const struct clk_hw *[]){
2068	&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
2069	.num_parents = 1,
2070	.flags = CLK_SET_RATE_PARENT,
2071	.ops = &clk_branch2_ops,
2072	},
2073	},
2074	};
2075
2076	static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
2077	.halt_reg = 0x0500c,
2078	.clkr = {
2079	.enable_reg = 0x0500c,
2080	.enable_mask = BIT(0),
2081	.hw.init = &(struct clk_init_data){
2082	.name = "gcc_blsp1_qup4_spi_apps_clk",
2083	.parent_hws = (const struct clk_hw *[]){
2084	&blsp1_qup4_spi_apps_clk_src.clkr.hw },
2085	.num_parents = 1,
2086	.flags = CLK_SET_RATE_PARENT,
2087	.ops = &clk_branch2_ops,
2088	},
2089	},
2090	};
2091
2092	static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
2093	.halt_reg = 0x06010,
2094	.clkr = {
2095	.enable_reg = 0x06010,
2096	.enable_mask = BIT(0),
2097	.hw.init = &(struct clk_init_data){
2098	.name = "gcc_blsp1_qup5_i2c_apps_clk",
2099	.parent_hws = (const struct clk_hw *[]){
2100	&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
2101	.num_parents = 1,
2102	.flags = CLK_SET_RATE_PARENT,
2103	.ops = &clk_branch2_ops,
2104	},
2105	},
2106	};
2107
2108	static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
2109	.halt_reg = 0x0600c,
2110	.clkr = {
2111	.enable_reg = 0x0600c,
2112	.enable_mask = BIT(0),
2113	.hw.init = &(struct clk_init_data){
2114	.name = "gcc_blsp1_qup5_spi_apps_clk",
2115	.parent_hws = (const struct clk_hw *[]){
2116	&blsp1_qup5_spi_apps_clk_src.clkr.hw },
2117	.num_parents = 1,
2118	.flags = CLK_SET_RATE_PARENT,
2119	.ops = &clk_branch2_ops,
2120	},
2121	},
2122	};
2123
2124	static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
2125	.halt_reg = 0x07010,
2126	.clkr = {
2127	.enable_reg = 0x07010,
2128	.enable_mask = BIT(0),
2129	.hw.init = &(struct clk_init_data){
2130	.name = "gcc_blsp1_qup6_i2c_apps_clk",
2131	.parent_hws = (const struct clk_hw *[]){
2132	&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
2133	.num_parents = 1,
2134	/*
2135	* RPM uses QUP6 I2C to communicate with the external
2136	* PMIC so it must not be disabled.
2137	*/
2138	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2139	.ops = &clk_branch2_ops,
2140	},
2141	},
2142	};
2143
2144	static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
2145	.halt_reg = 0x0700c,
2146	.clkr = {
2147	.enable_reg = 0x0700c,
2148	.enable_mask = BIT(0),
2149	.hw.init = &(struct clk_init_data){
2150	.name = "gcc_blsp1_qup6_spi_apps_clk",
2151	.parent_hws = (const struct clk_hw *[]){
2152	&blsp1_qup6_spi_apps_clk_src.clkr.hw },
2153	.num_parents = 1,
2154	.flags = CLK_SET_RATE_PARENT,
2155	.ops = &clk_branch2_ops,
2156	},
2157	},
2158	};
2159
2160	static struct clk_branch gcc_blsp1_uart1_apps_clk = {
2161	.halt_reg = 0x0203c,
2162	.clkr = {
2163	.enable_reg = 0x0203c,
2164	.enable_mask = BIT(0),
2165	.hw.init = &(struct clk_init_data){
2166	.name = "gcc_blsp1_uart1_apps_clk",
2167	.parent_hws = (const struct clk_hw *[]){
2168	&blsp1_uart1_apps_clk_src.clkr.hw },
2169	.num_parents = 1,
2170	.flags = CLK_SET_RATE_PARENT,
2171	.ops = &clk_branch2_ops,
2172	},
2173	},
2174	};
2175
2176	static struct clk_branch gcc_blsp1_uart2_apps_clk = {
2177	.halt_reg = 0x0302c,
2178	.clkr = {
2179	.enable_reg = 0x0302c,
2180	.enable_mask = BIT(0),
2181	.hw.init = &(struct clk_init_data){
2182	.name = "gcc_blsp1_uart2_apps_clk",
2183	.parent_hws = (const struct clk_hw *[]){
2184	&blsp1_uart2_apps_clk_src.clkr.hw },
2185	.num_parents = 1,
2186	.flags = CLK_SET_RATE_PARENT,
2187	.ops = &clk_branch2_ops,
2188	},
2189	},
2190	};
2191
2192	static struct clk_branch gcc_blsp1_uart3_apps_clk = {
2193	.halt_reg = 0x0402c,
2194	.clkr = {
2195	.enable_reg = 0x0402c,
2196	.enable_mask = BIT(0),
2197	.hw.init = &(struct clk_init_data){
2198	.name = "gcc_blsp1_uart3_apps_clk",
2199	.parent_hws = (const struct clk_hw *[]){
2200	&blsp1_uart3_apps_clk_src.clkr.hw },
2201	.num_parents = 1,
2202	.flags = CLK_SET_RATE_PARENT,
2203	.ops = &clk_branch2_ops,
2204	},
2205	},
2206	};
2207
2208	static struct clk_branch gcc_blsp1_uart4_apps_clk = {
2209	.halt_reg = 0x0502c,
2210	.clkr = {
2211	.enable_reg = 0x0502c,
2212	.enable_mask = BIT(0),
2213	.hw.init = &(struct clk_init_data){
2214	.name = "gcc_blsp1_uart4_apps_clk",
2215	.parent_hws = (const struct clk_hw *[]){
2216	&blsp1_uart4_apps_clk_src.clkr.hw },
2217	.num_parents = 1,
2218	.flags = CLK_SET_RATE_PARENT,
2219	.ops = &clk_branch2_ops,
2220	},
2221	},
2222	};
2223
2224	static struct clk_branch gcc_blsp1_uart5_apps_clk = {
2225	.halt_reg = 0x0602c,
2226	.clkr = {
2227	.enable_reg = 0x0602c,
2228	.enable_mask = BIT(0),
2229	.hw.init = &(struct clk_init_data){
2230	.name = "gcc_blsp1_uart5_apps_clk",
2231	.parent_hws = (const struct clk_hw *[]){
2232	&blsp1_uart5_apps_clk_src.clkr.hw },
2233	.num_parents = 1,
2234	.flags = CLK_SET_RATE_PARENT,
2235	.ops = &clk_branch2_ops,
2236	},
2237	},
2238	};
2239
2240	static struct clk_branch gcc_blsp1_uart6_apps_clk = {
2241	.halt_reg = 0x0702c,
2242	.clkr = {
2243	.enable_reg = 0x0702c,
2244	.enable_mask = BIT(0),
2245	.hw.init = &(struct clk_init_data){
2246	.name = "gcc_blsp1_uart6_apps_clk",
2247	.parent_hws = (const struct clk_hw *[]){
2248	&blsp1_uart6_apps_clk_src.clkr.hw },
2249	.num_parents = 1,
2250	.flags = CLK_SET_RATE_PARENT,
2251	.ops = &clk_branch2_ops,
2252	},
2253	},
2254	};
2255
2256	static struct clk_branch gcc_crypto_ahb_clk = {
2257	.halt_reg = 0x16024,
2258	.halt_check = BRANCH_HALT_VOTED,
2259	.clkr = {
2260	.enable_reg = 0x0b004,
2261	.enable_mask = BIT(0),
2262	.hw.init = &(struct clk_init_data){
2263	.name = "gcc_crypto_ahb_clk",
2264	.parent_hws = (const struct clk_hw *[]){
2265	&pcnoc_bfdcd_clk_src.clkr.hw },
2266	.num_parents = 1,
2267	.flags = CLK_SET_RATE_PARENT,
2268	.ops = &clk_branch2_ops,
2269	},
2270	},
2271	};
2272
2273	static struct clk_branch gcc_crypto_axi_clk = {
2274	.halt_reg = 0x16020,
2275	.halt_check = BRANCH_HALT_VOTED,
2276	.clkr = {
2277	.enable_reg = 0x0b004,
2278	.enable_mask = BIT(1),
2279	.hw.init = &(struct clk_init_data){
2280	.name = "gcc_crypto_axi_clk",
2281	.parent_hws = (const struct clk_hw *[]){
2282	&pcnoc_bfdcd_clk_src.clkr.hw },
2283	.num_parents = 1,
2284	.flags = CLK_SET_RATE_PARENT,
2285	.ops = &clk_branch2_ops,
2286	},
2287	},
2288	};
2289
2290	static struct clk_branch gcc_crypto_clk = {
2291	.halt_reg = 0x1601c,
2292	.halt_check = BRANCH_HALT_VOTED,
2293	.clkr = {
2294	.enable_reg = 0x0b004,
2295	.enable_mask = BIT(2),
2296	.hw.init = &(struct clk_init_data){
2297	.name = "gcc_crypto_clk",
2298	.parent_hws = (const struct clk_hw *[]){
2299	&crypto_clk_src.clkr.hw },
2300	.num_parents = 1,
2301	.flags = CLK_SET_RATE_PARENT,
2302	.ops = &clk_branch2_ops,
2303	},
2304	},
2305	};
2306
2307	static struct clk_fixed_factor gpll6_out_main_div2 = {
2308	.mult = 1,
2309	.div = 2,
2310	.hw.init = &(struct clk_init_data){
2311	.name = "gpll6_out_main_div2",
2312	.parent_hws = (const struct clk_hw *[]){
2313	&gpll6_main.clkr.hw },
2314	.num_parents = 1,
2315	.ops = &clk_fixed_factor_ops,
2316	.flags = CLK_SET_RATE_PARENT,
2317	},
2318	};
2319
2320	static struct clk_branch gcc_xo_clk = {
2321	.halt_reg = 0x30030,
2322	.clkr = {
2323	.enable_reg = 0x30030,
2324	.enable_mask = BIT(0),
2325	.hw.init = &(struct clk_init_data){
2326	.name = "gcc_xo_clk",
2327	.parent_hws = (const struct clk_hw *[]){
2328	&gcc_xo_clk_src.clkr.hw },
2329	.num_parents = 1,
2330	.flags = CLK_SET_RATE_PARENT,
2331	.ops = &clk_branch2_ops,
2332	},
2333	},
2334	};
2335
2336	static struct clk_branch gcc_gp1_clk = {
2337	.halt_reg = 0x08000,
2338	.clkr = {
2339	.enable_reg = 0x08000,
2340	.enable_mask = BIT(0),
2341	.hw.init = &(struct clk_init_data){
2342	.name = "gcc_gp1_clk",
2343	.parent_hws = (const struct clk_hw *[]){
2344	&gp1_clk_src.clkr.hw },
2345	.num_parents = 1,
2346	.flags = CLK_SET_RATE_PARENT,
2347	.ops = &clk_branch2_ops,
2348	},
2349	},
2350	};
2351
2352	static struct clk_branch gcc_gp2_clk = {
2353	.halt_reg = 0x09000,
2354	.clkr = {
2355	.enable_reg = 0x09000,
2356	.enable_mask = BIT(0),
2357	.hw.init = &(struct clk_init_data){
2358	.name = "gcc_gp2_clk",
2359	.parent_hws = (const struct clk_hw *[]){
2360	&gp2_clk_src.clkr.hw },
2361	.num_parents = 1,
2362	.flags = CLK_SET_RATE_PARENT,
2363	.ops = &clk_branch2_ops,
2364	},
2365	},
2366	};
2367
2368	static struct clk_branch gcc_gp3_clk = {
2369	.halt_reg = 0x0a000,
2370	.clkr = {
2371	.enable_reg = 0x0a000,
2372	.enable_mask = BIT(0),
2373	.hw.init = &(struct clk_init_data){
2374	.name = "gcc_gp3_clk",
2375	.parent_hws = (const struct clk_hw *[]){
2376	&gp3_clk_src.clkr.hw },
2377	.num_parents = 1,
2378	.flags = CLK_SET_RATE_PARENT,
2379	.ops = &clk_branch2_ops,
2380	},
2381	},
2382	};
2383
2384	static struct clk_branch gcc_mdio_ahb_clk = {
2385	.halt_reg = 0x58004,
2386	.clkr = {
2387	.enable_reg = 0x58004,
2388	.enable_mask = BIT(0),
2389	.hw.init = &(struct clk_init_data){
2390	.name = "gcc_mdio_ahb_clk",
2391	.parent_hws = (const struct clk_hw *[]){
2392	&pcnoc_bfdcd_clk_src.clkr.hw },
2393	.num_parents = 1,
2394	.flags = CLK_SET_RATE_PARENT,
2395	.ops = &clk_branch2_ops,
2396	},
2397	},
2398	};
2399
2400	static struct clk_branch gcc_crypto_ppe_clk = {
2401	.halt_reg = 0x68310,
2402	.clkr = {
2403	.enable_reg = 0x68310,
2404	.enable_mask = BIT(0),
2405	.hw.init = &(struct clk_init_data){
2406	.name = "gcc_crypto_ppe_clk",
2407	.parent_hws = (const struct clk_hw *[]){
2408	&nss_ppe_clk_src.clkr.hw },
2409	.num_parents = 1,
2410	.flags = CLK_SET_RATE_PARENT,
2411	.ops = &clk_branch2_ops,
2412	},
2413	},
2414	};
2415
2416	static struct clk_branch gcc_nss_ce_apb_clk = {
2417	.halt_reg = 0x68174,
2418	.clkr = {
2419	.enable_reg = 0x68174,
2420	.enable_mask = BIT(0),
2421	.hw.init = &(struct clk_init_data){
2422	.name = "gcc_nss_ce_apb_clk",
2423	.parent_hws = (const struct clk_hw *[]){
2424	&nss_ce_clk_src.clkr.hw },
2425	.num_parents = 1,
2426	.flags = CLK_SET_RATE_PARENT,
2427	.ops = &clk_branch2_ops,
2428	},
2429	},
2430	};
2431
2432	static struct clk_branch gcc_nss_ce_axi_clk = {
2433	.halt_reg = 0x68170,
2434	.clkr = {
2435	.enable_reg = 0x68170,
2436	.enable_mask = BIT(0),
2437	.hw.init = &(struct clk_init_data){
2438	.name = "gcc_nss_ce_axi_clk",
2439	.parent_hws = (const struct clk_hw *[]){
2440	&nss_ce_clk_src.clkr.hw },
2441	.num_parents = 1,
2442	.flags = CLK_SET_RATE_PARENT,
2443	.ops = &clk_branch2_ops,
2444	},
2445	},
2446	};
2447
2448	static struct clk_branch gcc_nss_cfg_clk = {
2449	.halt_reg = 0x68160,
2450	.clkr = {
2451	.enable_reg = 0x68160,
2452	.enable_mask = BIT(0),
2453	.hw.init = &(struct clk_init_data){
2454	.name = "gcc_nss_cfg_clk",
2455	.parent_hws = (const struct clk_hw *[]){
2456	&pcnoc_bfdcd_clk_src.clkr.hw },
2457	.num_parents = 1,
2458	.flags = CLK_SET_RATE_PARENT,
2459	.ops = &clk_branch2_ops,
2460	},
2461	},
2462	};
2463
2464	static struct clk_branch gcc_nss_crypto_clk = {
2465	.halt_reg = 0x68164,
2466	.clkr = {
2467	.enable_reg = 0x68164,
2468	.enable_mask = BIT(0),
2469	.hw.init = &(struct clk_init_data){
2470	.name = "gcc_nss_crypto_clk",
2471	.parent_hws = (const struct clk_hw *[]){
2472	&nss_crypto_clk_src.clkr.hw },
2473	.num_parents = 1,
2474	.flags = CLK_SET_RATE_PARENT,
2475	.ops = &clk_branch2_ops,
2476	},
2477	},
2478	};
2479
2480	static struct clk_branch gcc_nss_csr_clk = {
2481	.halt_reg = 0x68318,
2482	.clkr = {
2483	.enable_reg = 0x68318,
2484	.enable_mask = BIT(0),
2485	.hw.init = &(struct clk_init_data){
2486	.name = "gcc_nss_csr_clk",
2487	.parent_hws = (const struct clk_hw *[]){
2488	&nss_ce_clk_src.clkr.hw },
2489	.num_parents = 1,
2490	.flags = CLK_SET_RATE_PARENT,
2491	.ops = &clk_branch2_ops,
2492	},
2493	},
2494	};
2495
2496	static struct clk_branch gcc_nss_edma_cfg_clk = {
2497	.halt_reg = 0x6819C,
2498	.clkr = {
2499	.enable_reg = 0x6819C,
2500	.enable_mask = BIT(0),
2501	.hw.init = &(struct clk_init_data){
2502	.name = "gcc_nss_edma_cfg_clk",
2503	.parent_hws = (const struct clk_hw *[]){
2504	&nss_ppe_clk_src.clkr.hw },
2505	.num_parents = 1,
2506	.flags = CLK_SET_RATE_PARENT,
2507	.ops = &clk_branch2_ops,
2508	},
2509	},
2510	};
2511
2512	static struct clk_branch gcc_nss_edma_clk = {
2513	.halt_reg = 0x68198,
2514	.clkr = {
2515	.enable_reg = 0x68198,
2516	.enable_mask = BIT(0),
2517	.hw.init = &(struct clk_init_data){
2518	.name = "gcc_nss_edma_clk",
2519	.parent_hws = (const struct clk_hw *[]){
2520	&nss_ppe_clk_src.clkr.hw },
2521	.num_parents = 1,
2522	.flags = CLK_SET_RATE_PARENT,
2523	.ops = &clk_branch2_ops,
2524	},
2525	},
2526	};
2527
2528	static struct clk_branch gcc_nss_noc_clk = {
2529	.halt_reg = 0x68168,
2530	.clkr = {
2531	.enable_reg = 0x68168,
2532	.enable_mask = BIT(0),
2533	.hw.init = &(struct clk_init_data){
2534	.name = "gcc_nss_noc_clk",
2535	.parent_hws = (const struct clk_hw *[]){
2536	&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2537	.num_parents = 1,
2538	.flags = CLK_SET_RATE_PARENT,
2539	.ops = &clk_branch2_ops,
2540	},
2541	},
2542	};
2543
2544	static struct clk_branch gcc_ubi0_utcm_clk = {
2545	.halt_reg = 0x2606c,
2546	.clkr = {
2547	.enable_reg = 0x2606c,
2548	.enable_mask = BIT(0),
2549	.hw.init = &(struct clk_init_data){
2550	.name = "gcc_ubi0_utcm_clk",
2551	.parent_hws = (const struct clk_hw *[]){
2552	&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2553	.num_parents = 1,
2554	.flags = CLK_SET_RATE_PARENT,
2555	.ops = &clk_branch2_ops,
2556	},
2557	},
2558	};
2559
2560	static struct clk_branch gcc_snoc_nssnoc_clk = {
2561	.halt_reg = 0x26070,
2562	.clkr = {
2563	.enable_reg = 0x26070,
2564	.enable_mask = BIT(0),
2565	.hw.init = &(struct clk_init_data){
2566	.name = "gcc_snoc_nssnoc_clk",
2567	.parent_hws = (const struct clk_hw *[]){
2568	&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
2569	.num_parents = 1,
2570	.flags = CLK_SET_RATE_PARENT,
2571	.ops = &clk_branch2_ops,
2572	},
2573	},
2574	};
2575
2576	static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2577	F(24000000, P_XO, 1, 0, 0),
2578	F(133333333, P_GPLL0, 6, 0, 0),
2579	{ }
2580	};
2581
2582	static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
2583	F(24000000, P_XO, 1, 0, 0),
2584	F(400000000, P_GPLL0, 2, 0, 0),
2585	{ }
2586	};
2587
2588	static struct clk_rcg2 wcss_ahb_clk_src = {
2589	.cmd_rcgr = 0x59020,
2590	.freq_tbl = ftbl_wcss_ahb_clk_src,
2591	.hid_width = 5,
2592	.parent_map = gcc_xo_gpll0_map,
2593	.clkr.hw.init = &(struct clk_init_data){
2594	.name = "wcss_ahb_clk_src",
2595	.parent_data = gcc_xo_gpll0,
2596	.num_parents = 2,
2597	.ops = &clk_rcg2_ops,
2598	},
2599	};
2600
2601	static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = {
2602	{ .fw_name = "xo" },
2603	{ .hw = &gpll0.clkr.hw },
2604	{ .hw = &gpll2.clkr.hw },
2605	{ .hw = &gpll4.clkr.hw },
2606	{ .hw = &gpll6.clkr.hw },
2607	};
2608
2609	static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = {
2610	{ P_XO, 0 },
2611	{ P_GPLL0, 1 },
2612	{ P_GPLL2, 2 },
2613	{ P_GPLL4, 3 },
2614	{ P_GPLL6, 4 },
2615	};
2616
2617	static struct clk_rcg2 q6_axi_clk_src = {
2618	.cmd_rcgr = 0x59120,
2619	.freq_tbl = ftbl_q6_axi_clk_src,
2620	.hid_width = 5,
2621	.parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map,
2622	.clkr.hw.init = &(struct clk_init_data){
2623	.name = "q6_axi_clk_src",
2624	.parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6,
2625	.num_parents = 5,
2626	.ops = &clk_rcg2_ops,
2627	},
2628	};
2629
2630	static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = {
2631	F(24000000, P_XO, 1, 0, 0),
2632	F(100000000, P_GPLL0, 8, 0, 0),
2633	{ }
2634	};
2635
2636	static struct clk_rcg2 lpass_core_axim_clk_src = {
2637	.cmd_rcgr = 0x1F020,
2638	.freq_tbl = ftbl_lpass_core_axim_clk_src,
2639	.hid_width = 5,
2640	.parent_map = gcc_xo_gpll0_map,
2641	.clkr.hw.init = &(struct clk_init_data){
2642	.name = "lpass_core_axim_clk_src",
2643	.parent_data = gcc_xo_gpll0,
2644	.num_parents = 2,
2645	.ops = &clk_rcg2_ops,
2646	},
2647	};
2648
2649	static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = {
2650	F(24000000, P_XO, 1, 0, 0),
2651	F(266666667, P_GPLL0, 3, 0, 0),
2652	{ }
2653	};
2654
2655	static struct clk_rcg2 lpass_snoc_cfg_clk_src = {
2656	.cmd_rcgr = 0x1F040,
2657	.freq_tbl = ftbl_lpass_snoc_cfg_clk_src,
2658	.hid_width = 5,
2659	.parent_map = gcc_xo_gpll0_map,
2660	.clkr.hw.init = &(struct clk_init_data){
2661	.name = "lpass_snoc_cfg_clk_src",
2662	.parent_data = gcc_xo_gpll0,
2663	.num_parents = 2,
2664	.ops = &clk_rcg2_ops,
2665	},
2666	};
2667
2668	static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = {
2669	F(24000000, P_XO, 1, 0, 0),
2670	F(400000000, P_GPLL0, 2, 0, 0),
2671	{ }
2672	};
2673
2674	static struct clk_rcg2 lpass_q6_axim_clk_src = {
2675	.cmd_rcgr = 0x1F008,
2676	.freq_tbl = ftbl_lpass_q6_axim_clk_src,
2677	.hid_width = 5,
2678	.parent_map = gcc_xo_gpll0_map,
2679	.clkr.hw.init = &(struct clk_init_data){
2680	.name = "lpass_q6_axim_clk_src",
2681	.parent_data = gcc_xo_gpll0,
2682	.num_parents = 2,
2683	.ops = &clk_rcg2_ops,
2684	},
2685	};
2686
2687	static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = {
2688	F(24000000, P_XO, 1, 0, 0),
2689	F(50000000, P_GPLL0, 16, 0, 0),
2690	{ }
2691	};
2692
2693	static struct clk_rcg2 rbcpr_wcss_clk_src = {
2694	.cmd_rcgr = 0x3a00c,
2695	.freq_tbl = ftbl_rbcpr_wcss_clk_src,
2696	.hid_width = 5,
2697	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
2698	.clkr.hw.init = &(struct clk_init_data){
2699	.name = "rbcpr_wcss_clk_src",
2700	.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
2701	.num_parents = 3,
2702	.ops = &clk_rcg2_ops,
2703	},
2704	};
2705
2706	static struct clk_branch gcc_lpass_core_axim_clk = {
2707	.halt_reg = 0x1F028,
2708	.clkr = {
2709	.enable_reg = 0x1F028,
2710	.enable_mask = BIT(0),
2711	.hw.init = &(struct clk_init_data){
2712	.name = "gcc_lpass_core_axim_clk",
2713	.parent_hws = (const struct clk_hw *[]){
2714	&lpass_core_axim_clk_src.clkr.hw },
2715	.num_parents = 1,
2716	.flags = CLK_SET_RATE_PARENT,
2717	.ops = &clk_branch2_ops,
2718	},
2719	},
2720	};
2721
2722	static struct clk_branch gcc_lpass_snoc_cfg_clk = {
2723	.halt_reg = 0x1F048,
2724	.clkr = {
2725	.enable_reg = 0x1F048,
2726	.enable_mask = BIT(0),
2727	.hw.init = &(struct clk_init_data){
2728	.name = "gcc_lpass_snoc_cfg_clk",
2729	.parent_hws = (const struct clk_hw *[]){
2730	&lpass_snoc_cfg_clk_src.clkr.hw },
2731	.num_parents = 1,
2732	.flags = CLK_SET_RATE_PARENT,
2733	.ops = &clk_branch2_ops,
2734	},
2735	},
2736	};
2737
2738	static struct clk_branch gcc_lpass_q6_axim_clk = {
2739	.halt_reg = 0x1F010,
2740	.clkr = {
2741	.enable_reg = 0x1F010,
2742	.enable_mask = BIT(0),
2743	.hw.init = &(struct clk_init_data){
2744	.name = "gcc_lpass_q6_axim_clk",
2745	.parent_hws = (const struct clk_hw *[]){
2746	&lpass_q6_axim_clk_src.clkr.hw },
2747	.num_parents = 1,
2748	.flags = CLK_SET_RATE_PARENT,
2749	.ops = &clk_branch2_ops,
2750	},
2751	},
2752	};
2753
2754	static struct clk_branch gcc_lpass_q6_atbm_at_clk = {
2755	.halt_reg = 0x1F018,
2756	.clkr = {
2757	.enable_reg = 0x1F018,
2758	.enable_mask = BIT(0),
2759	.hw.init = &(struct clk_init_data){
2760	.name = "gcc_lpass_q6_atbm_at_clk",
2761	.parent_hws = (const struct clk_hw *[]){
2762	&qdss_at_clk_src.clkr.hw },
2763	.num_parents = 1,
2764	.flags = CLK_SET_RATE_PARENT,
2765	.ops = &clk_branch2_ops,
2766	},
2767	},
2768	};
2769
2770	static struct clk_branch gcc_lpass_q6_pclkdbg_clk = {
2771	.halt_reg = 0x1F01C,
2772	.clkr = {
2773	.enable_reg = 0x1F01C,
2774	.enable_mask = BIT(0),
2775	.hw.init = &(struct clk_init_data){
2776	.name = "gcc_lpass_q6_pclkdbg_clk",
2777	.parent_hws = (const struct clk_hw *[]){
2778	&qdss_dap_sync_clk_src.hw },
2779	.num_parents = 1,
2780	.flags = CLK_SET_RATE_PARENT,
2781	.ops = &clk_branch2_ops,
2782	},
2783	},
2784	};
2785
2786	static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = {
2787	.halt_reg = 0x1F014,
2788	.clkr = {
2789	.enable_reg = 0x1F014,
2790	.enable_mask = BIT(0),
2791	.hw.init = &(struct clk_init_data){
2792	.name = "gcc_lpass_q6ss_tsctr_1to2_clk",
2793	.parent_hws = (const struct clk_hw *[]){
2794	&qdss_tsctr_div2_clk_src.hw },
2795	.num_parents = 1,
2796	.flags = CLK_SET_RATE_PARENT,
2797	.ops = &clk_branch2_ops,
2798	},
2799	},
2800	};
2801
2802	static struct clk_branch gcc_lpass_q6ss_trig_clk = {
2803	.halt_reg = 0x1F038,
2804	.clkr = {
2805	.enable_reg = 0x1F038,
2806	.enable_mask = BIT(0),
2807	.hw.init = &(struct clk_init_data){
2808	.name = "gcc_lpass_q6ss_trig_clk",
2809	.parent_hws = (const struct clk_hw *[]){
2810	&qdss_dap_sync_clk_src.hw },
2811	.num_parents = 1,
2812	.flags = CLK_SET_RATE_PARENT,
2813	.ops = &clk_branch2_ops,
2814	},
2815	},
2816	};
2817
2818	static struct clk_branch gcc_lpass_tbu_clk = {
2819	.halt_reg = 0x12094,
2820	.clkr = {
2821	.enable_reg = 0xb00c,
2822	.enable_mask = BIT(10),
2823	.hw.init = &(struct clk_init_data){
2824	.name = "gcc_lpass_tbu_clk",
2825	.parent_hws = (const struct clk_hw *[]){
2826	&lpass_q6_axim_clk_src.clkr.hw },
2827	.num_parents = 1,
2828	.flags = CLK_SET_RATE_PARENT,
2829	.ops = &clk_branch2_ops,
2830	},
2831	},
2832	};
2833
2834	static struct clk_branch gcc_pcnoc_lpass_clk = {
2835	.halt_reg = 0x27020,
2836	.clkr = {
2837	.enable_reg = 0x27020,
2838	.enable_mask = BIT(0),
2839	.hw.init = &(struct clk_init_data){
2840	.name = "gcc_pcnoc_lpass_clk",
2841	.parent_hws = (const struct clk_hw *[]){
2842	&lpass_core_axim_clk_src.clkr.hw },
2843	.num_parents = 1,
2844	.flags = CLK_SET_RATE_PARENT,
2845	.ops = &clk_branch2_ops,
2846	},
2847	},
2848	};
2849
2850	static struct clk_branch gcc_mem_noc_lpass_clk = {
2851	.halt_reg = 0x1D044,
2852	.clkr = {
2853	.enable_reg = 0x1D044,
2854	.enable_mask = BIT(0),
2855	.hw.init = &(struct clk_init_data){
2856	.name = "gcc_mem_noc_lpass_clk",
2857	.parent_hws = (const struct clk_hw *[]){
2858	&lpass_q6_axim_clk_src.clkr.hw },
2859	.num_parents = 1,
2860	.flags = CLK_SET_RATE_PARENT,
2861	.ops = &clk_branch2_ops,
2862	},
2863	},
2864	};
2865
2866	static struct clk_branch gcc_snoc_lpass_cfg_clk = {
2867	.halt_reg = 0x26074,
2868	.clkr = {
2869	.enable_reg = 0x26074,
2870	.enable_mask = BIT(0),
2871	.hw.init = &(struct clk_init_data){
2872	.name = "gcc_snoc_lpass_cfg_clk",
2873	.parent_hws = (const struct clk_hw *[]){
2874	&lpass_snoc_cfg_clk_src.clkr.hw },
2875	.num_parents = 1,
2876	.flags = CLK_SET_RATE_PARENT,
2877	.ops = &clk_branch2_ops,
2878	},
2879	},
2880	};
2881
2882	static struct clk_branch gcc_mem_noc_ubi32_clk = {
2883	.halt_reg = 0x1D03C,
2884	.clkr = {
2885	.enable_reg = 0x1D03C,
2886	.enable_mask = BIT(0),
2887	.hw.init = &(struct clk_init_data){
2888	.name = "gcc_mem_noc_ubi32_clk",
2889	.parent_hws = (const struct clk_hw *[]){
2890	&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
2891	.num_parents = 1,
2892	.flags = CLK_SET_RATE_PARENT,
2893	.ops = &clk_branch2_ops,
2894	},
2895	},
2896	};
2897
2898	static struct clk_branch gcc_nss_port1_rx_clk = {
2899	.halt_reg = 0x68240,
2900	.clkr = {
2901	.enable_reg = 0x68240,
2902	.enable_mask = BIT(0),
2903	.hw.init = &(struct clk_init_data){
2904	.name = "gcc_nss_port1_rx_clk",
2905	.parent_hws = (const struct clk_hw *[]){
2906	&nss_port1_rx_div_clk_src.clkr.hw },
2907	.num_parents = 1,
2908	.flags = CLK_SET_RATE_PARENT,
2909	.ops = &clk_branch2_ops,
2910	},
2911	},
2912	};
2913
2914	static struct clk_branch gcc_nss_port1_tx_clk = {
2915	.halt_reg = 0x68244,
2916	.clkr = {
2917	.enable_reg = 0x68244,
2918	.enable_mask = BIT(0),
2919	.hw.init = &(struct clk_init_data){
2920	.name = "gcc_nss_port1_tx_clk",
2921	.parent_hws = (const struct clk_hw *[]){
2922	&nss_port1_tx_div_clk_src.clkr.hw },
2923	.num_parents = 1,
2924	.flags = CLK_SET_RATE_PARENT,
2925	.ops = &clk_branch2_ops,
2926	},
2927	},
2928	};
2929
2930	static struct clk_branch gcc_nss_port2_rx_clk = {
2931	.halt_reg = 0x68248,
2932	.clkr = {
2933	.enable_reg = 0x68248,
2934	.enable_mask = BIT(0),
2935	.hw.init = &(struct clk_init_data){
2936	.name = "gcc_nss_port2_rx_clk",
2937	.parent_hws = (const struct clk_hw *[]){
2938	&nss_port2_rx_div_clk_src.clkr.hw },
2939	.num_parents = 1,
2940	.flags = CLK_SET_RATE_PARENT,
2941	.ops = &clk_branch2_ops,
2942	},
2943	},
2944	};
2945
2946	static struct clk_branch gcc_nss_port2_tx_clk = {
2947	.halt_reg = 0x6824c,
2948	.clkr = {
2949	.enable_reg = 0x6824c,
2950	.enable_mask = BIT(0),
2951	.hw.init = &(struct clk_init_data){
2952	.name = "gcc_nss_port2_tx_clk",
2953	.parent_hws = (const struct clk_hw *[]){
2954	&nss_port2_tx_div_clk_src.clkr.hw },
2955	.num_parents = 1,
2956	.flags = CLK_SET_RATE_PARENT,
2957	.ops = &clk_branch2_ops,
2958	},
2959	},
2960	};
2961
2962	static struct clk_branch gcc_nss_port3_rx_clk = {
2963	.halt_reg = 0x68250,
2964	.clkr = {
2965	.enable_reg = 0x68250,
2966	.enable_mask = BIT(0),
2967	.hw.init = &(struct clk_init_data){
2968	.name = "gcc_nss_port3_rx_clk",
2969	.parent_hws = (const struct clk_hw *[]){
2970	&nss_port3_rx_div_clk_src.clkr.hw },
2971	.num_parents = 1,
2972	.flags = CLK_SET_RATE_PARENT,
2973	.ops = &clk_branch2_ops,
2974	},
2975	},
2976	};
2977
2978	static struct clk_branch gcc_nss_port3_tx_clk = {
2979	.halt_reg = 0x68254,
2980	.clkr = {
2981	.enable_reg = 0x68254,
2982	.enable_mask = BIT(0),
2983	.hw.init = &(struct clk_init_data){
2984	.name = "gcc_nss_port3_tx_clk",
2985	.parent_hws = (const struct clk_hw *[]){
2986	&nss_port3_tx_div_clk_src.clkr.hw },
2987	.num_parents = 1,
2988	.flags = CLK_SET_RATE_PARENT,
2989	.ops = &clk_branch2_ops,
2990	},
2991	},
2992	};
2993
2994	static struct clk_branch gcc_nss_port4_rx_clk = {
2995	.halt_reg = 0x68258,
2996	.clkr = {
2997	.enable_reg = 0x68258,
2998	.enable_mask = BIT(0),
2999	.hw.init = &(struct clk_init_data){
3000	.name = "gcc_nss_port4_rx_clk",
3001	.parent_hws = (const struct clk_hw *[]){
3002	&nss_port4_rx_div_clk_src.clkr.hw },
3003	.num_parents = 1,
3004	.flags = CLK_SET_RATE_PARENT,
3005	.ops = &clk_branch2_ops,
3006	},
3007	},
3008	};
3009
3010	static struct clk_branch gcc_nss_port4_tx_clk = {
3011	.halt_reg = 0x6825c,
3012	.clkr = {
3013	.enable_reg = 0x6825c,
3014	.enable_mask = BIT(0),
3015	.hw.init = &(struct clk_init_data){
3016	.name = "gcc_nss_port4_tx_clk",
3017	.parent_hws = (const struct clk_hw *[]){
3018	&nss_port4_tx_div_clk_src.clkr.hw },
3019	.num_parents = 1,
3020	.flags = CLK_SET_RATE_PARENT,
3021	.ops = &clk_branch2_ops,
3022	},
3023	},
3024	};
3025
3026	static struct clk_branch gcc_nss_port5_rx_clk = {
3027	.halt_reg = 0x68260,
3028	.clkr = {
3029	.enable_reg = 0x68260,
3030	.enable_mask = BIT(0),
3031	.hw.init = &(struct clk_init_data){
3032	.name = "gcc_nss_port5_rx_clk",
3033	.parent_hws = (const struct clk_hw *[]){
3034	&nss_port5_rx_div_clk_src.clkr.hw },
3035	.num_parents = 1,
3036	.flags = CLK_SET_RATE_PARENT,
3037	.ops = &clk_branch2_ops,
3038	},
3039	},
3040	};
3041
3042	static struct clk_branch gcc_nss_port5_tx_clk = {
3043	.halt_reg = 0x68264,
3044	.clkr = {
3045	.enable_reg = 0x68264,
3046	.enable_mask = BIT(0),
3047	.hw.init = &(struct clk_init_data){
3048	.name = "gcc_nss_port5_tx_clk",
3049	.parent_hws = (const struct clk_hw *[]){
3050	&nss_port5_tx_div_clk_src.clkr.hw },
3051	.num_parents = 1,
3052	.flags = CLK_SET_RATE_PARENT,
3053	.ops = &clk_branch2_ops,
3054	},
3055	},
3056	};
3057
3058	static struct clk_branch gcc_nss_ppe_cfg_clk = {
3059	.halt_reg = 0x68194,
3060	.clkr = {
3061	.enable_reg = 0x68194,
3062	.enable_mask = BIT(0),
3063	.hw.init = &(struct clk_init_data){
3064	.name = "gcc_nss_ppe_cfg_clk",
3065	.parent_hws = (const struct clk_hw *[]){
3066	&nss_ppe_clk_src.clkr.hw },
3067	.num_parents = 1,
3068	.flags = CLK_SET_RATE_PARENT,
3069	.ops = &clk_branch2_ops,
3070	},
3071	},
3072	};
3073
3074	static struct clk_branch gcc_nss_ppe_clk = {
3075	.halt_reg = 0x68190,
3076	.clkr = {
3077	.enable_reg = 0x68190,
3078	.enable_mask = BIT(0),
3079	.hw.init = &(struct clk_init_data){
3080	.name = "gcc_nss_ppe_clk",
3081	.parent_hws = (const struct clk_hw *[]){
3082	&nss_ppe_clk_src.clkr.hw },
3083	.num_parents = 1,
3084	.flags = CLK_SET_RATE_PARENT,
3085	.ops = &clk_branch2_ops,
3086	},
3087	},
3088	};
3089
3090	static struct clk_branch gcc_nss_ppe_ipe_clk = {
3091	.halt_reg = 0x68338,
3092	.clkr = {
3093	.enable_reg = 0x68338,
3094	.enable_mask = BIT(0),
3095	.hw.init = &(struct clk_init_data){
3096	.name = "gcc_nss_ppe_ipe_clk",
3097	.parent_hws = (const struct clk_hw *[]){
3098	&nss_ppe_clk_src.clkr.hw },
3099	.num_parents = 1,
3100	.flags = CLK_SET_RATE_PARENT,
3101	.ops = &clk_branch2_ops,
3102	},
3103	},
3104	};
3105
3106	static struct clk_branch gcc_nss_ptp_ref_clk = {
3107	.halt_reg = 0x6816C,
3108	.clkr = {
3109	.enable_reg = 0x6816C,
3110	.enable_mask = BIT(0),
3111	.hw.init = &(struct clk_init_data){
3112	.name = "gcc_nss_ptp_ref_clk",
3113	.parent_hws = (const struct clk_hw *[]){
3114	&nss_ppe_cdiv_clk_src.hw },
3115	.num_parents = 1,
3116	.flags = CLK_SET_RATE_PARENT,
3117	.ops = &clk_branch2_ops,
3118	},
3119	},
3120	};
3121
3122	static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3123	.halt_reg = 0x6830C,
3124	.clkr = {
3125	.enable_reg = 0x6830C,
3126	.enable_mask = BIT(0),
3127	.hw.init = &(struct clk_init_data){
3128	.name = "gcc_nssnoc_ce_apb_clk",
3129	.parent_hws = (const struct clk_hw *[]){
3130	&nss_ce_clk_src.clkr.hw },
3131	.num_parents = 1,
3132	.flags = CLK_SET_RATE_PARENT,
3133	.ops = &clk_branch2_ops,
3134	},
3135	},
3136	};
3137
3138	static struct clk_branch gcc_nssnoc_ce_axi_clk = {
3139	.halt_reg = 0x68308,
3140	.clkr = {
3141	.enable_reg = 0x68308,
3142	.enable_mask = BIT(0),
3143	.hw.init = &(struct clk_init_data){
3144	.name = "gcc_nssnoc_ce_axi_clk",
3145	.parent_hws = (const struct clk_hw *[]){
3146	&nss_ce_clk_src.clkr.hw },
3147	.num_parents = 1,
3148	.flags = CLK_SET_RATE_PARENT,
3149	.ops = &clk_branch2_ops,
3150	},
3151	},
3152	};
3153
3154	static struct clk_branch gcc_nssnoc_crypto_clk = {
3155	.halt_reg = 0x68314,
3156	.clkr = {
3157	.enable_reg = 0x68314,
3158	.enable_mask = BIT(0),
3159	.hw.init = &(struct clk_init_data){
3160	.name = "gcc_nssnoc_crypto_clk",
3161	.parent_hws = (const struct clk_hw *[]){
3162	&nss_crypto_clk_src.clkr.hw },
3163	.num_parents = 1,
3164	.flags = CLK_SET_RATE_PARENT,
3165	.ops = &clk_branch2_ops,
3166	},
3167	},
3168	};
3169
3170	static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
3171	.halt_reg = 0x68304,
3172	.clkr = {
3173	.enable_reg = 0x68304,
3174	.enable_mask = BIT(0),
3175	.hw.init = &(struct clk_init_data){
3176	.name = "gcc_nssnoc_ppe_cfg_clk",
3177	.parent_hws = (const struct clk_hw *[]){
3178	&nss_ppe_clk_src.clkr.hw },
3179	.flags = CLK_SET_RATE_PARENT,
3180	.ops = &clk_branch2_ops,
3181	},
3182	},
3183	};
3184
3185	static struct clk_branch gcc_nssnoc_ppe_clk = {
3186	.halt_reg = 0x68300,
3187	.clkr = {
3188	.enable_reg = 0x68300,
3189	.enable_mask = BIT(0),
3190	.hw.init = &(struct clk_init_data){
3191	.name = "gcc_nssnoc_ppe_clk",
3192	.parent_hws = (const struct clk_hw *[]){
3193	&nss_ppe_clk_src.clkr.hw },
3194	.num_parents = 1,
3195	.flags = CLK_SET_RATE_PARENT,
3196	.ops = &clk_branch2_ops,
3197	},
3198	},
3199	};
3200
3201	static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3202	.halt_reg = 0x68180,
3203	.clkr = {
3204	.enable_reg = 0x68180,
3205	.enable_mask = BIT(0),
3206	.hw.init = &(struct clk_init_data){
3207	.name = "gcc_nssnoc_qosgen_ref_clk",
3208	.parent_hws = (const struct clk_hw *[]){
3209	&gcc_xo_clk_src.clkr.hw },
3210	.num_parents = 1,
3211	.flags = CLK_SET_RATE_PARENT,
3212	.ops = &clk_branch2_ops,
3213	},
3214	},
3215	};
3216
3217	static struct clk_branch gcc_nssnoc_snoc_clk = {
3218	.halt_reg = 0x68188,
3219	.clkr = {
3220	.enable_reg = 0x68188,
3221	.enable_mask = BIT(0),
3222	.hw.init = &(struct clk_init_data){
3223	.name = "gcc_nssnoc_snoc_clk",
3224	.parent_hws = (const struct clk_hw *[]){
3225	&system_noc_bfdcd_clk_src.clkr.hw },
3226	.num_parents = 1,
3227	.flags = CLK_SET_RATE_PARENT,
3228	.ops = &clk_branch2_ops,
3229	},
3230	},
3231	};
3232
3233	static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3234	.halt_reg = 0x68184,
3235	.clkr = {
3236	.enable_reg = 0x68184,
3237	.enable_mask = BIT(0),
3238	.hw.init = &(struct clk_init_data){
3239	.name = "gcc_nssnoc_timeout_ref_clk",
3240	.parent_hws = (const struct clk_hw *[]){
3241	&gcc_xo_div4_clk_src.hw },
3242	.num_parents = 1,
3243	.flags = CLK_SET_RATE_PARENT,
3244	.ops = &clk_branch2_ops,
3245	},
3246	},
3247	};
3248
3249	static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
3250	.halt_reg = 0x68270,
3251	.clkr = {
3252	.enable_reg = 0x68270,
3253	.enable_mask = BIT(0),
3254	.hw.init = &(struct clk_init_data){
3255	.name = "gcc_nssnoc_ubi0_ahb_clk",
3256	.parent_hws = (const struct clk_hw *[]){
3257	&nss_ce_clk_src.clkr.hw },
3258	.num_parents = 1,
3259	.flags = CLK_SET_RATE_PARENT,
3260	.ops = &clk_branch2_ops,
3261	},
3262	},
3263	};
3264
3265	static struct clk_branch gcc_port1_mac_clk = {
3266	.halt_reg = 0x68320,
3267	.clkr = {
3268	.enable_reg = 0x68320,
3269	.enable_mask = BIT(0),
3270	.hw.init = &(struct clk_init_data){
3271	.name = "gcc_port1_mac_clk",
3272	.parent_hws = (const struct clk_hw *[]){
3273	&nss_ppe_clk_src.clkr.hw },
3274	.num_parents = 1,
3275	.flags = CLK_SET_RATE_PARENT,
3276	.ops = &clk_branch2_ops,
3277	},
3278	},
3279	};
3280
3281	static struct clk_branch gcc_port2_mac_clk = {
3282	.halt_reg = 0x68324,
3283	.clkr = {
3284	.enable_reg = 0x68324,
3285	.enable_mask = BIT(0),
3286	.hw.init = &(struct clk_init_data){
3287	.name = "gcc_port2_mac_clk",
3288	.parent_hws = (const struct clk_hw *[]){
3289	&nss_ppe_clk_src.clkr.hw },
3290	.num_parents = 1,
3291	.flags = CLK_SET_RATE_PARENT,
3292	.ops = &clk_branch2_ops,
3293	},
3294	},
3295	};
3296
3297	static struct clk_branch gcc_port3_mac_clk = {
3298	.halt_reg = 0x68328,
3299	.clkr = {
3300	.enable_reg = 0x68328,
3301	.enable_mask = BIT(0),
3302	.hw.init = &(struct clk_init_data){
3303	.name = "gcc_port3_mac_clk",
3304	.parent_hws = (const struct clk_hw *[]){
3305	&nss_ppe_clk_src.clkr.hw },
3306	.num_parents = 1,
3307	.flags = CLK_SET_RATE_PARENT,
3308	.ops = &clk_branch2_ops,
3309	},
3310	},
3311	};
3312
3313	static struct clk_branch gcc_port4_mac_clk = {
3314	.halt_reg = 0x6832c,
3315	.clkr = {
3316	.enable_reg = 0x6832c,
3317	.enable_mask = BIT(0),
3318	.hw.init = &(struct clk_init_data){
3319	.name = "gcc_port4_mac_clk",
3320	.parent_hws = (const struct clk_hw *[]){
3321	&nss_ppe_clk_src.clkr.hw },
3322	.num_parents = 1,
3323	.flags = CLK_SET_RATE_PARENT,
3324	.ops = &clk_branch2_ops,
3325	},
3326	},
3327	};
3328
3329	static struct clk_branch gcc_port5_mac_clk = {
3330	.halt_reg = 0x68330,
3331	.clkr = {
3332	.enable_reg = 0x68330,
3333	.enable_mask = BIT(0),
3334	.hw.init = &(struct clk_init_data){
3335	.name = "gcc_port5_mac_clk",
3336	.parent_hws = (const struct clk_hw *[]){
3337	&nss_ppe_clk_src.clkr.hw },
3338	.num_parents = 1,
3339	.flags = CLK_SET_RATE_PARENT,
3340	.ops = &clk_branch2_ops,
3341	},
3342	},
3343	};
3344
3345	static struct clk_branch gcc_ubi0_ahb_clk = {
3346	.halt_reg = 0x6820C,
3347	.halt_check = BRANCH_HALT_DELAY,
3348	.clkr = {
3349	.enable_reg = 0x6820C,
3350	.enable_mask = BIT(0),
3351	.hw.init = &(struct clk_init_data){
3352	.name = "gcc_ubi0_ahb_clk",
3353	.parent_hws = (const struct clk_hw *[]){
3354	&nss_ce_clk_src.clkr.hw },
3355	.num_parents = 1,
3356	.flags = CLK_SET_RATE_PARENT,
3357	.ops = &clk_branch2_ops,
3358	},
3359	},
3360	};
3361
3362	static struct clk_branch gcc_ubi0_axi_clk = {
3363	.halt_reg = 0x68200,
3364	.halt_check = BRANCH_HALT_DELAY,
3365	.clkr = {
3366	.enable_reg = 0x68200,
3367	.enable_mask = BIT(0),
3368	.hw.init = &(struct clk_init_data){
3369	.name = "gcc_ubi0_axi_clk",
3370	.parent_hws = (const struct clk_hw *[]){
3371	&ubi32_mem_noc_bfdcd_clk_src.clkr.hw },
3372	.num_parents = 1,
3373	.flags = CLK_SET_RATE_PARENT,
3374	.ops = &clk_branch2_ops,
3375	},
3376	},
3377	};
3378
3379	static struct clk_branch gcc_ubi0_nc_axi_clk = {
3380	.halt_reg = 0x68204,
3381	.halt_check = BRANCH_HALT_DELAY,
3382	.clkr = {
3383	.enable_reg = 0x68204,
3384	.enable_mask = BIT(0),
3385	.hw.init = &(struct clk_init_data){
3386	.name = "gcc_ubi0_nc_axi_clk",
3387	.parent_hws = (const struct clk_hw *[]){
3388	&snoc_nssnoc_bfdcd_clk_src.clkr.hw },
3389	.num_parents = 1,
3390	.flags = CLK_SET_RATE_PARENT,
3391	.ops = &clk_branch2_ops,
3392	},
3393	},
3394	};
3395
3396	static struct clk_branch gcc_ubi0_core_clk = {
3397	.halt_reg = 0x68210,
3398	.halt_check = BRANCH_HALT_DELAY,
3399	.clkr = {
3400	.enable_reg = 0x68210,
3401	.enable_mask = BIT(0),
3402	.hw.init = &(struct clk_init_data){
3403	.name = "gcc_ubi0_core_clk",
3404	.parent_hws = (const struct clk_hw *[]){
3405	&nss_ubi0_div_clk_src.clkr.hw },
3406	.num_parents = 1,
3407	.flags = CLK_SET_RATE_PARENT,
3408	.ops = &clk_branch2_ops,
3409	},
3410	},
3411	};
3412
3413	static struct clk_branch gcc_pcie0_ahb_clk = {
3414	.halt_reg = 0x75010,
3415	.clkr = {
3416	.enable_reg = 0x75010,
3417	.enable_mask = BIT(0),
3418	.hw.init = &(struct clk_init_data){
3419	.name = "gcc_pcie0_ahb_clk",
3420	.parent_hws = (const struct clk_hw *[]){
3421	&pcnoc_bfdcd_clk_src.clkr.hw },
3422	.num_parents = 1,
3423	.flags = CLK_SET_RATE_PARENT,
3424	.ops = &clk_branch2_ops,
3425	},
3426	},
3427	};
3428
3429	static struct clk_branch gcc_pcie0_aux_clk = {
3430	.halt_reg = 0x75014,
3431	.clkr = {
3432	.enable_reg = 0x75014,
3433	.enable_mask = BIT(0),
3434	.hw.init = &(struct clk_init_data){
3435	.name = "gcc_pcie0_aux_clk",
3436	.parent_hws = (const struct clk_hw *[]){
3437	&pcie0_aux_clk_src.clkr.hw },
3438	.num_parents = 1,
3439	.flags = CLK_SET_RATE_PARENT,
3440	.ops = &clk_branch2_ops,
3441	},
3442	},
3443	};
3444
3445	static struct clk_branch gcc_pcie0_axi_m_clk = {
3446	.halt_reg = 0x75008,
3447	.clkr = {
3448	.enable_reg = 0x75008,
3449	.enable_mask = BIT(0),
3450	.hw.init = &(struct clk_init_data){
3451	.name = "gcc_pcie0_axi_m_clk",
3452	.parent_hws = (const struct clk_hw *[]){
3453	&pcie0_axi_clk_src.clkr.hw },
3454	.num_parents = 1,
3455	.flags = CLK_SET_RATE_PARENT,
3456	.ops = &clk_branch2_ops,
3457	},
3458	},
3459	};
3460
3461	static struct clk_branch gcc_pcie0_axi_s_clk = {
3462	.halt_reg = 0x7500c,
3463	.clkr = {
3464	.enable_reg = 0x7500c,
3465	.enable_mask = BIT(0),
3466	.hw.init = &(struct clk_init_data){
3467	.name = "gcc_pcie0_axi_s_clk",
3468	.parent_hws = (const struct clk_hw *[]){
3469	&pcie0_axi_clk_src.clkr.hw },
3470	.num_parents = 1,
3471	.flags = CLK_SET_RATE_PARENT,
3472	.ops = &clk_branch2_ops,
3473	},
3474	},
3475	};
3476
3477	static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
3478	.halt_reg = 0x26048,
3479	.clkr = {
3480	.enable_reg = 0x26048,
3481	.enable_mask = BIT(0),
3482	.hw.init = &(struct clk_init_data){
3483	.name = "gcc_sys_noc_pcie0_axi_clk",
3484	.parent_hws = (const struct clk_hw *[]){
3485	&pcie0_axi_clk_src.clkr.hw },
3486	.num_parents = 1,
3487	.flags = CLK_SET_RATE_PARENT,
3488	.ops = &clk_branch2_ops,
3489	},
3490	},
3491	};
3492
3493	static struct clk_branch gcc_pcie0_pipe_clk = {
3494	.halt_reg = 0x75018,
3495	.halt_check = BRANCH_HALT_DELAY,
3496	.clkr = {
3497	.enable_reg = 0x75018,
3498	.enable_mask = BIT(0),
3499	.hw.init = &(struct clk_init_data){
3500	.name = "gcc_pcie0_pipe_clk",
3501	.parent_hws = (const struct clk_hw *[]){
3502	&pcie0_pipe_clk_src.clkr.hw },
3503	.num_parents = 1,
3504	.flags = CLK_SET_RATE_PARENT,
3505	.ops = &clk_branch2_ops,
3506	},
3507	},
3508	};
3509
3510	static struct clk_branch gcc_prng_ahb_clk = {
3511	.halt_reg = 0x13004,
3512	.halt_check = BRANCH_HALT_VOTED,
3513	.clkr = {
3514	.enable_reg = 0x0b004,
3515	.enable_mask = BIT(8),
3516	.hw.init = &(struct clk_init_data){
3517	.name = "gcc_prng_ahb_clk",
3518	.parent_hws = (const struct clk_hw *[]){
3519	&pcnoc_bfdcd_clk_src.clkr.hw },
3520	.num_parents = 1,
3521	.flags = CLK_SET_RATE_PARENT,
3522	.ops = &clk_branch2_ops,
3523	},
3524	},
3525	};
3526
3527	static struct clk_branch gcc_qdss_at_clk = {
3528	.halt_reg = 0x29024,
3529	.clkr = {
3530	.enable_reg = 0x29024,
3531	.enable_mask = BIT(0),
3532	.hw.init = &(struct clk_init_data){
3533	.name = "gcc_qdss_at_clk",
3534	.parent_hws = (const struct clk_hw *[]){
3535	&qdss_at_clk_src.clkr.hw },
3536	.num_parents = 1,
3537	.flags = CLK_SET_RATE_PARENT,
3538	.ops = &clk_branch2_ops,
3539	},
3540	},
3541	};
3542
3543	static struct clk_branch gcc_qdss_dap_clk = {
3544	.halt_reg = 0x29084,
3545	.clkr = {
3546	.enable_reg = 0x29084,
3547	.enable_mask = BIT(0),
3548	.hw.init = &(struct clk_init_data){
3549	.name = "gcc_qdss_dap_clk",
3550	.parent_hws = (const struct clk_hw *[]){
3551	&qdss_dap_sync_clk_src.hw },
3552	.num_parents = 1,
3553	.flags = CLK_SET_RATE_PARENT,
3554	.ops = &clk_branch2_ops,
3555	},
3556	},
3557	};
3558
3559	static struct clk_branch gcc_qpic_ahb_clk = {
3560	.halt_reg = 0x57024,
3561	.clkr = {
3562	.enable_reg = 0x57024,
3563	.enable_mask = BIT(0),
3564	.hw.init = &(struct clk_init_data){
3565	.name = "gcc_qpic_ahb_clk",
3566	.parent_hws = (const struct clk_hw *[]){
3567	&pcnoc_bfdcd_clk_src.clkr.hw },
3568	.num_parents = 1,
3569	.flags = CLK_SET_RATE_PARENT,
3570	.ops = &clk_branch2_ops,
3571	},
3572	},
3573	};
3574
3575	static struct clk_branch gcc_qpic_clk = {
3576	.halt_reg = 0x57020,
3577	.clkr = {
3578	.enable_reg = 0x57020,
3579	.enable_mask = BIT(0),
3580	.hw.init = &(struct clk_init_data){
3581	.name = "gcc_qpic_clk",
3582	.parent_hws = (const struct clk_hw *[]){
3583	&pcnoc_bfdcd_clk_src.clkr.hw },
3584	.num_parents = 1,
3585	.flags = CLK_SET_RATE_PARENT,
3586	.ops = &clk_branch2_ops,
3587	},
3588	},
3589	};
3590
3591	static struct clk_branch gcc_sdcc1_ahb_clk = {
3592	.halt_reg = 0x4201c,
3593	.clkr = {
3594	.enable_reg = 0x4201c,
3595	.enable_mask = BIT(0),
3596	.hw.init = &(struct clk_init_data){
3597	.name = "gcc_sdcc1_ahb_clk",
3598	.parent_hws = (const struct clk_hw *[]){
3599	&pcnoc_bfdcd_clk_src.clkr.hw },
3600	.num_parents = 1,
3601	.flags = CLK_SET_RATE_PARENT,
3602	.ops = &clk_branch2_ops,
3603	},
3604	},
3605	};
3606
3607	static struct clk_branch gcc_sdcc1_apps_clk = {
3608	.halt_reg = 0x42018,
3609	.clkr = {
3610	.enable_reg = 0x42018,
3611	.enable_mask = BIT(0),
3612	.hw.init = &(struct clk_init_data){
3613	.name = "gcc_sdcc1_apps_clk",
3614	.parent_hws = (const struct clk_hw *[]){
3615	&sdcc1_apps_clk_src.clkr.hw },
3616	.num_parents = 1,
3617	.flags = CLK_SET_RATE_PARENT,
3618	.ops = &clk_branch2_ops,
3619	},
3620	},
3621	};
3622
3623	static struct clk_branch gcc_uniphy0_ahb_clk = {
3624	.halt_reg = 0x56008,
3625	.clkr = {
3626	.enable_reg = 0x56008,
3627	.enable_mask = BIT(0),
3628	.hw.init = &(struct clk_init_data){
3629	.name = "gcc_uniphy0_ahb_clk",
3630	.parent_hws = (const struct clk_hw *[]){
3631	&pcnoc_bfdcd_clk_src.clkr.hw },
3632	.num_parents = 1,
3633	.flags = CLK_SET_RATE_PARENT,
3634	.ops = &clk_branch2_ops,
3635	},
3636	},
3637	};
3638
3639	static struct clk_branch gcc_uniphy0_port1_rx_clk = {
3640	.halt_reg = 0x56010,
3641	.clkr = {
3642	.enable_reg = 0x56010,
3643	.enable_mask = BIT(0),
3644	.hw.init = &(struct clk_init_data){
3645	.name = "gcc_uniphy0_port1_rx_clk",
3646	.parent_hws = (const struct clk_hw *[]){
3647	&nss_port1_rx_div_clk_src.clkr.hw },
3648	.num_parents = 1,
3649	.flags = CLK_SET_RATE_PARENT,
3650	.ops = &clk_branch2_ops,
3651	},
3652	},
3653	};
3654
3655	static struct clk_branch gcc_uniphy0_port1_tx_clk = {
3656	.halt_reg = 0x56014,
3657	.clkr = {
3658	.enable_reg = 0x56014,
3659	.enable_mask = BIT(0),
3660	.hw.init = &(struct clk_init_data){
3661	.name = "gcc_uniphy0_port1_tx_clk",
3662	.parent_hws = (const struct clk_hw *[]){
3663	&nss_port1_tx_div_clk_src.clkr.hw },
3664	.num_parents = 1,
3665	.flags = CLK_SET_RATE_PARENT,
3666	.ops = &clk_branch2_ops,
3667	},
3668	},
3669	};
3670
3671	static struct clk_branch gcc_uniphy0_port2_rx_clk = {
3672	.halt_reg = 0x56018,
3673	.clkr = {
3674	.enable_reg = 0x56018,
3675	.enable_mask = BIT(0),
3676	.hw.init = &(struct clk_init_data){
3677	.name = "gcc_uniphy0_port2_rx_clk",
3678	.parent_hws = (const struct clk_hw *[]){
3679	&nss_port2_rx_div_clk_src.clkr.hw },
3680	.num_parents = 1,
3681	.flags = CLK_SET_RATE_PARENT,
3682	.ops = &clk_branch2_ops,
3683	},
3684	},
3685	};
3686
3687	static struct clk_branch gcc_uniphy0_port2_tx_clk = {
3688	.halt_reg = 0x5601c,
3689	.clkr = {
3690	.enable_reg = 0x5601c,
3691	.enable_mask = BIT(0),
3692	.hw.init = &(struct clk_init_data){
3693	.name = "gcc_uniphy0_port2_tx_clk",
3694	.parent_hws = (const struct clk_hw *[]){
3695	&nss_port2_tx_div_clk_src.clkr.hw },
3696	.num_parents = 1,
3697	.flags = CLK_SET_RATE_PARENT,
3698	.ops = &clk_branch2_ops,
3699	},
3700	},
3701	};
3702
3703	static struct clk_branch gcc_uniphy0_port3_rx_clk = {
3704	.halt_reg = 0x56020,
3705	.clkr = {
3706	.enable_reg = 0x56020,
3707	.enable_mask = BIT(0),
3708	.hw.init = &(struct clk_init_data){
3709	.name = "gcc_uniphy0_port3_rx_clk",
3710	.parent_hws = (const struct clk_hw *[]){
3711	&nss_port3_rx_div_clk_src.clkr.hw },
3712	.num_parents = 1,
3713	.flags = CLK_SET_RATE_PARENT,
3714	.ops = &clk_branch2_ops,
3715	},
3716	},
3717	};
3718
3719	static struct clk_branch gcc_uniphy0_port3_tx_clk = {
3720	.halt_reg = 0x56024,
3721	.clkr = {
3722	.enable_reg = 0x56024,
3723	.enable_mask = BIT(0),
3724	.hw.init = &(struct clk_init_data){
3725	.name = "gcc_uniphy0_port3_tx_clk",
3726	.parent_hws = (const struct clk_hw *[]){
3727	&nss_port3_tx_div_clk_src.clkr.hw },
3728	.num_parents = 1,
3729	.flags = CLK_SET_RATE_PARENT,
3730	.ops = &clk_branch2_ops,
3731	},
3732	},
3733	};
3734
3735	static struct clk_branch gcc_uniphy0_port4_rx_clk = {
3736	.halt_reg = 0x56028,
3737	.clkr = {
3738	.enable_reg = 0x56028,
3739	.enable_mask = BIT(0),
3740	.hw.init = &(struct clk_init_data){
3741	.name = "gcc_uniphy0_port4_rx_clk",
3742	.parent_hws = (const struct clk_hw *[]){
3743	&nss_port4_rx_div_clk_src.clkr.hw },
3744	.num_parents = 1,
3745	.flags = CLK_SET_RATE_PARENT,
3746	.ops = &clk_branch2_ops,
3747	},
3748	},
3749	};
3750
3751	static struct clk_branch gcc_uniphy0_port4_tx_clk = {
3752	.halt_reg = 0x5602c,
3753	.clkr = {
3754	.enable_reg = 0x5602c,
3755	.enable_mask = BIT(0),
3756	.hw.init = &(struct clk_init_data){
3757	.name = "gcc_uniphy0_port4_tx_clk",
3758	.parent_hws = (const struct clk_hw *[]){
3759	&nss_port4_tx_div_clk_src.clkr.hw },
3760	.num_parents = 1,
3761	.flags = CLK_SET_RATE_PARENT,
3762	.ops = &clk_branch2_ops,
3763	},
3764	},
3765	};
3766
3767	static struct clk_branch gcc_uniphy0_port5_rx_clk = {
3768	.halt_reg = 0x56030,
3769	.clkr = {
3770	.enable_reg = 0x56030,
3771	.enable_mask = BIT(0),
3772	.hw.init = &(struct clk_init_data){
3773	.name = "gcc_uniphy0_port5_rx_clk",
3774	.parent_hws = (const struct clk_hw *[]){
3775	&nss_port5_rx_div_clk_src.clkr.hw },
3776	.num_parents = 1,
3777	.flags = CLK_SET_RATE_PARENT,
3778	.ops = &clk_branch2_ops,
3779	},
3780	},
3781	};
3782
3783	static struct clk_branch gcc_uniphy0_port5_tx_clk = {
3784	.halt_reg = 0x56034,
3785	.clkr = {
3786	.enable_reg = 0x56034,
3787	.enable_mask = BIT(0),
3788	.hw.init = &(struct clk_init_data){
3789	.name = "gcc_uniphy0_port5_tx_clk",
3790	.parent_hws = (const struct clk_hw *[]){
3791	&nss_port5_tx_div_clk_src.clkr.hw },
3792	.num_parents = 1,
3793	.flags = CLK_SET_RATE_PARENT,
3794	.ops = &clk_branch2_ops,
3795	},
3796	},
3797	};
3798
3799	static struct clk_branch gcc_uniphy0_sys_clk = {
3800	.halt_reg = 0x5600C,
3801	.clkr = {
3802	.enable_reg = 0x5600C,
3803	.enable_mask = BIT(0),
3804	.hw.init = &(struct clk_init_data){
3805	.name = "gcc_uniphy0_sys_clk",
3806	.parent_hws = (const struct clk_hw *[]){
3807	&gcc_xo_clk_src.clkr.hw },
3808	.num_parents = 1,
3809	.flags = CLK_SET_RATE_PARENT,
3810	.ops = &clk_branch2_ops,
3811	},
3812	},
3813	};
3814
3815	static struct clk_branch gcc_uniphy1_ahb_clk = {
3816	.halt_reg = 0x56108,
3817	.clkr = {
3818	.enable_reg = 0x56108,
3819	.enable_mask = BIT(0),
3820	.hw.init = &(struct clk_init_data){
3821	.name = "gcc_uniphy1_ahb_clk",
3822	.parent_hws = (const struct clk_hw *[]){
3823	&pcnoc_bfdcd_clk_src.clkr.hw },
3824	.num_parents = 1,
3825	.flags = CLK_SET_RATE_PARENT,
3826	.ops = &clk_branch2_ops,
3827	},
3828	},
3829	};
3830
3831	static struct clk_branch gcc_uniphy1_port5_rx_clk = {
3832	.halt_reg = 0x56110,
3833	.clkr = {
3834	.enable_reg = 0x56110,
3835	.enable_mask = BIT(0),
3836	.hw.init = &(struct clk_init_data){
3837	.name = "gcc_uniphy1_port5_rx_clk",
3838	.parent_hws = (const struct clk_hw *[]){
3839	&nss_port5_rx_div_clk_src.clkr.hw },
3840	.num_parents = 1,
3841	.flags = CLK_SET_RATE_PARENT,
3842	.ops = &clk_branch2_ops,
3843	},
3844	},
3845	};
3846
3847	static struct clk_branch gcc_uniphy1_port5_tx_clk = {
3848	.halt_reg = 0x56114,
3849	.clkr = {
3850	.enable_reg = 0x56114,
3851	.enable_mask = BIT(0),
3852	.hw.init = &(struct clk_init_data){
3853	.name = "gcc_uniphy1_port5_tx_clk",
3854	.parent_hws = (const struct clk_hw *[]){
3855	&nss_port5_tx_div_clk_src.clkr.hw },
3856	.num_parents = 1,
3857	.flags = CLK_SET_RATE_PARENT,
3858	.ops = &clk_branch2_ops,
3859	},
3860	},
3861	};
3862
3863	static struct clk_branch gcc_uniphy1_sys_clk = {
3864	.halt_reg = 0x5610C,
3865	.clkr = {
3866	.enable_reg = 0x5610C,
3867	.enable_mask = BIT(0),
3868	.hw.init = &(struct clk_init_data){
3869	.name = "gcc_uniphy1_sys_clk",
3870	.parent_hws = (const struct clk_hw *[]){
3871	&gcc_xo_clk_src.clkr.hw },
3872	.num_parents = 1,
3873	.flags = CLK_SET_RATE_PARENT,
3874	.ops = &clk_branch2_ops,
3875	},
3876	},
3877	};
3878
3879	static struct clk_branch gcc_usb0_aux_clk = {
3880	.halt_reg = 0x3e044,
3881	.clkr = {
3882	.enable_reg = 0x3e044,
3883	.enable_mask = BIT(0),
3884	.hw.init = &(struct clk_init_data){
3885	.name = "gcc_usb0_aux_clk",
3886	.parent_hws = (const struct clk_hw *[]){
3887	&usb0_aux_clk_src.clkr.hw },
3888	.num_parents = 1,
3889	.flags = CLK_SET_RATE_PARENT,
3890	.ops = &clk_branch2_ops,
3891	},
3892	},
3893	};
3894
3895	static struct clk_branch gcc_usb0_master_clk = {
3896	.halt_reg = 0x3e000,
3897	.clkr = {
3898	.enable_reg = 0x3e000,
3899	.enable_mask = BIT(0),
3900	.hw.init = &(struct clk_init_data){
3901	.name = "gcc_usb0_master_clk",
3902	.parent_hws = (const struct clk_hw *[]){
3903	&usb0_master_clk_src.clkr.hw },
3904	.num_parents = 1,
3905	.flags = CLK_SET_RATE_PARENT,
3906	.ops = &clk_branch2_ops,
3907	},
3908	},
3909	};
3910
3911	static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
3912	.halt_reg = 0x47014,
3913	.clkr = {
3914	.enable_reg = 0x47014,
3915	.enable_mask = BIT(0),
3916	.hw.init = &(struct clk_init_data){
3917	.name = "gcc_snoc_bus_timeout2_ahb_clk",
3918	.parent_hws = (const struct clk_hw *[]){
3919	&usb0_master_clk_src.clkr.hw },
3920	.num_parents = 1,
3921	.flags = CLK_SET_RATE_PARENT,
3922	.ops = &clk_branch2_ops,
3923	},
3924	},
3925	};
3926
3927	static struct clk_rcg2 pcie0_rchng_clk_src = {
3928	.cmd_rcgr = 0x75070,
3929	.freq_tbl = ftbl_pcie_rchng_clk_src,
3930	.hid_width = 5,
3931	.parent_map = gcc_xo_gpll0_map,
3932	.clkr.hw.init = &(struct clk_init_data){
3933	.name = "pcie0_rchng_clk_src",
3934	.parent_data = gcc_xo_gpll0,
3935	.num_parents = 2,
3936	.ops = &clk_rcg2_ops,
3937	},
3938	};
3939
3940	static struct clk_branch gcc_pcie0_rchng_clk = {
3941	.halt_reg = 0x75070,
3942	.clkr = {
3943	.enable_reg = 0x75070,
3944	.enable_mask = BIT(1),
3945	.hw.init = &(struct clk_init_data){
3946	.name = "gcc_pcie0_rchng_clk",
3947	.parent_hws = (const struct clk_hw *[]){
3948	&pcie0_rchng_clk_src.clkr.hw },
3949	.num_parents = 1,
3950	.flags = CLK_SET_RATE_PARENT,
3951	.ops = &clk_branch2_ops,
3952	},
3953	},
3954	};
3955
3956	static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
3957	.halt_reg = 0x75048,
3958	.clkr = {
3959	.enable_reg = 0x75048,
3960	.enable_mask = BIT(0),
3961	.hw.init = &(struct clk_init_data){
3962	.name = "gcc_pcie0_axi_s_bridge_clk",
3963	.parent_hws = (const struct clk_hw *[]){
3964	&pcie0_axi_clk_src.clkr.hw },
3965	.num_parents = 1,
3966	.flags = CLK_SET_RATE_PARENT,
3967	.ops = &clk_branch2_ops,
3968	},
3969	},
3970	};
3971
3972	static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
3973	.halt_reg = 0x26040,
3974	.clkr = {
3975	.enable_reg = 0x26040,
3976	.enable_mask = BIT(0),
3977	.hw.init = &(struct clk_init_data){
3978	.name = "gcc_sys_noc_usb0_axi_clk",
3979	.parent_hws = (const struct clk_hw *[]){
3980	&usb0_master_clk_src.clkr.hw },
3981	.num_parents = 1,
3982	.flags = CLK_SET_RATE_PARENT,
3983	.ops = &clk_branch2_ops,
3984	},
3985	},
3986	};
3987
3988	static struct clk_branch gcc_usb0_mock_utmi_clk = {
3989	.halt_reg = 0x3e008,
3990	.clkr = {
3991	.enable_reg = 0x3e008,
3992	.enable_mask = BIT(0),
3993	.hw.init = &(struct clk_init_data){
3994	.name = "gcc_usb0_mock_utmi_clk",
3995	.parent_hws = (const struct clk_hw *[]){
3996	&usb0_mock_utmi_clk_src.clkr.hw },
3997	.num_parents = 1,
3998	.flags = CLK_SET_RATE_PARENT,
3999	.ops = &clk_branch2_ops,
4000	},
4001	},
4002	};
4003
4004	static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
4005	.halt_reg = 0x3e080,
4006	.clkr = {
4007	.enable_reg = 0x3e080,
4008	.enable_mask = BIT(0),
4009	.hw.init = &(struct clk_init_data){
4010	.name = "gcc_usb0_phy_cfg_ahb_clk",
4011	.parent_hws = (const struct clk_hw *[]){
4012	&pcnoc_bfdcd_clk_src.clkr.hw },
4013	.num_parents = 1,
4014	.flags = CLK_SET_RATE_PARENT,
4015	.ops = &clk_branch2_ops,
4016	},
4017	},
4018	};
4019
4020	static struct clk_branch gcc_usb0_pipe_clk = {
4021	.halt_reg = 0x3e040,
4022	.halt_check = BRANCH_HALT_DELAY,
4023	.clkr = {
4024	.enable_reg = 0x3e040,
4025	.enable_mask = BIT(0),
4026	.hw.init = &(struct clk_init_data){
4027	.name = "gcc_usb0_pipe_clk",
4028	.parent_hws = (const struct clk_hw *[]){
4029	&usb0_pipe_clk_src.clkr.hw },
4030	.num_parents = 1,
4031	.flags = CLK_SET_RATE_PARENT,
4032	.ops = &clk_branch2_ops,
4033	},
4034	},
4035	};
4036
4037	static struct clk_branch gcc_usb0_sleep_clk = {
4038	.halt_reg = 0x3e004,
4039	.clkr = {
4040	.enable_reg = 0x3e004,
4041	.enable_mask = BIT(0),
4042	.hw.init = &(struct clk_init_data){
4043	.name = "gcc_usb0_sleep_clk",
4044	.parent_hws = (const struct clk_hw *[]){
4045	&gcc_sleep_clk_src.clkr.hw },
4046	.num_parents = 1,
4047	.flags = CLK_SET_RATE_PARENT,
4048	.ops = &clk_branch2_ops,
4049	},
4050	},
4051	};
4052
4053	static struct clk_branch gcc_usb1_master_clk = {
4054	.halt_reg = 0x3f000,
4055	.clkr = {
4056	.enable_reg = 0x3f000,
4057	.enable_mask = BIT(0),
4058	.hw.init = &(struct clk_init_data){
4059	.name = "gcc_usb1_master_clk",
4060	.parent_hws = (const struct clk_hw *[]){
4061	&pcnoc_bfdcd_clk_src.clkr.hw },
4062	.num_parents = 1,
4063	.flags = CLK_SET_RATE_PARENT,
4064	.ops = &clk_branch2_ops,
4065	},
4066	},
4067	};
4068
4069	static struct clk_branch gcc_usb1_mock_utmi_clk = {
4070	.halt_reg = 0x3f008,
4071	.clkr = {
4072	.enable_reg = 0x3f008,
4073	.enable_mask = BIT(0),
4074	.hw.init = &(struct clk_init_data){
4075	.name = "gcc_usb1_mock_utmi_clk",
4076	.parent_hws = (const struct clk_hw *[]){
4077	&usb1_mock_utmi_clk_src.clkr.hw },
4078	.num_parents = 1,
4079	.flags = CLK_SET_RATE_PARENT,
4080	.ops = &clk_branch2_ops,
4081	},
4082	},
4083	};
4084
4085	static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
4086	.halt_reg = 0x3f080,
4087	.clkr = {
4088	.enable_reg = 0x3f080,
4089	.enable_mask = BIT(0),
4090	.hw.init = &(struct clk_init_data){
4091	.name = "gcc_usb1_phy_cfg_ahb_clk",
4092	.parent_hws = (const struct clk_hw *[]){
4093	&pcnoc_bfdcd_clk_src.clkr.hw },
4094	.num_parents = 1,
4095	.flags = CLK_SET_RATE_PARENT,
4096	.ops = &clk_branch2_ops,
4097	},
4098	},
4099	};
4100
4101	static struct clk_branch gcc_usb1_sleep_clk = {
4102	.halt_reg = 0x3f004,
4103	.clkr = {
4104	.enable_reg = 0x3f004,
4105	.enable_mask = BIT(0),
4106	.hw.init = &(struct clk_init_data){
4107	.name = "gcc_usb1_sleep_clk",
4108	.parent_hws = (const struct clk_hw *[]){
4109	&gcc_sleep_clk_src.clkr.hw },
4110	.num_parents = 1,
4111	.flags = CLK_SET_RATE_PARENT,
4112	.ops = &clk_branch2_ops,
4113	},
4114	},
4115	};
4116
4117	static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
4118	.halt_reg = 0x56308,
4119	.clkr = {
4120	.enable_reg = 0x56308,
4121	.enable_mask = BIT(0),
4122	.hw.init = &(struct clk_init_data){
4123	.name = "gcc_cmn_12gpll_ahb_clk",
4124	.parent_hws = (const struct clk_hw *[]){
4125	&pcnoc_bfdcd_clk_src.clkr.hw },
4126	.num_parents = 1,
4127	.flags = CLK_SET_RATE_PARENT,
4128	.ops = &clk_branch2_ops,
4129	},
4130	},
4131	};
4132
4133	static struct clk_branch gcc_cmn_12gpll_sys_clk = {
4134	.halt_reg = 0x5630c,
4135	.clkr = {
4136	.enable_reg = 0x5630c,
4137	.enable_mask = BIT(0),
4138	.hw.init = &(struct clk_init_data){
4139	.name = "gcc_cmn_12gpll_sys_clk",
4140	.parent_hws = (const struct clk_hw *[]){
4141	&gcc_xo_clk_src.clkr.hw },
4142	.num_parents = 1,
4143	.flags = CLK_SET_RATE_PARENT,
4144	.ops = &clk_branch2_ops,
4145	},
4146	},
4147	};
4148
4149	static struct clk_branch gcc_sdcc1_ice_core_clk = {
4150	.halt_reg = 0x5d014,
4151	.clkr = {
4152	.enable_reg = 0x5d014,
4153	.enable_mask = BIT(0),
4154	.hw.init = &(struct clk_init_data){
4155	.name = "gcc_sdcc1_ice_core_clk",
4156	.parent_hws = (const struct clk_hw *[]){
4157	&sdcc1_ice_core_clk_src.clkr.hw },
4158	.num_parents = 1,
4159	.flags = CLK_SET_RATE_PARENT,
4160	.ops = &clk_branch2_ops,
4161	},
4162	},
4163	};
4164
4165	static struct clk_branch gcc_dcc_clk = {
4166	.halt_reg = 0x77004,
4167	.clkr = {
4168	.enable_reg = 0x77004,
4169	.enable_mask = BIT(0),
4170	.hw.init = &(struct clk_init_data){
4171	.name = "gcc_dcc_clk",
4172	.parent_hws = (const struct clk_hw *[]){
4173	&pcnoc_bfdcd_clk_src.clkr.hw },
4174	.num_parents = 1,
4175	.flags = CLK_SET_RATE_PARENT,
4176	.ops = &clk_branch2_ops,
4177	},
4178	},
4179	};
4180
4181	static const struct alpha_pll_config ubi32_pll_config = {
4182	.l = 0x3e,
4183	.alpha = 0x6667,
4184	.config_ctl_val = 0x240d4828,
4185	.config_ctl_hi_val = 0x6,
4186	.main_output_mask = BIT(0),
4187	.aux_output_mask = BIT(1),
4188	.pre_div_val = 0x0,
4189	.pre_div_mask = BIT(12),
4190	.post_div_val = 0x0,
4191	.post_div_mask = GENMASK(9, 8),
4192	.alpha_en_mask = BIT(24),
4193	.test_ctl_val = 0x1C0000C0,
4194	.test_ctl_hi_val = 0x4000,
4195	};
4196
4197	static const struct alpha_pll_config nss_crypto_pll_config = {
4198	.l = 0x32,
4199	.alpha = 0x0,
4200	.alpha_hi = 0x0,
4201	.config_ctl_val = 0x4001055b,
4202	.main_output_mask = BIT(0),
4203	.pre_div_val = 0x0,
4204	.pre_div_mask = GENMASK(14, 12),
4205	.post_div_val = 0x1 << 8,
4206	.post_div_mask = GENMASK(11, 8),
4207	.vco_mask = GENMASK(21, 20),
4208	.vco_val = 0x0,
4209	.alpha_en_mask = BIT(24),
4210	};
4211
4212	static struct clk_hw *gcc_ipq6018_hws[] = {
4213	&gpll0_out_main_div2.hw,
4214	&gcc_xo_div4_clk_src.hw,
4215	&nss_ppe_cdiv_clk_src.hw,
4216	&gpll6_out_main_div2.hw,
4217	&qdss_dap_sync_clk_src.hw,
4218	&qdss_tsctr_div2_clk_src.hw,
4219	};
4220
4221	static struct clk_regmap *gcc_ipq6018_clks[] = {
4222	[GPLL0_MAIN] = &gpll0_main.clkr,
4223	[GPLL0] = &gpll0.clkr,
4224	[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4225	[UBI32_PLL] = &ubi32_pll.clkr,
4226	[GPLL6_MAIN] = &gpll6_main.clkr,
4227	[GPLL6] = &gpll6.clkr,
4228	[GPLL4_MAIN] = &gpll4_main.clkr,
4229	[GPLL4] = &gpll4.clkr,
4230	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4231	[GPLL2_MAIN] = &gpll2_main.clkr,
4232	[GPLL2] = &gpll2.clkr,
4233	[NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4234	[NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4235	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4236	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4237	[NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4238	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4239	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4240	[SNOC_NSSNOC_BFDCD_CLK_SRC] = &snoc_nssnoc_bfdcd_clk_src.clkr,
4241	[NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4242	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4243	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
4244	[NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4245	[NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4246	[UBI32_MEM_NOC_BFDCD_CLK_SRC] = &ubi32_mem_noc_bfdcd_clk_src.clkr,
4247	[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4248	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4249	[APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr,
4250	[NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4251	[NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4252	[NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4253	[NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4254	[NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4255	[NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4256	[NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4257	[NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4258	[NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4259	[NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4260	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
4261	[NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4262	[NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4263	[NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4264	[NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4265	[NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4266	[NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4267	[NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4268	[NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4269	[NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4270	[NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4271	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4272	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4273	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4274	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4275	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4276	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4277	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4278	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4279	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4280	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4281	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4282	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4283	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4284	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4285	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4286	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4287	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4288	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4289	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4290	[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4291	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4292	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4293	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4294	[NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4295	[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4296	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4297	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4298	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4299	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4300	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4301	[USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4302	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4303	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
4304	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
4305	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4306	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4307	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4308	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4309	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4310	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4311	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4312	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4313	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4314	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4315	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4316	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4317	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4318	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4319	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4320	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4321	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4322	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4323	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4324	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4325	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4326	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4327	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4328	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4329	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4330	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
4331	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4332	[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4333	[GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4334	[GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4335	[GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4336	[GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4337	[GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4338	[GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4339	[GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4340	[GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4341	[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,
4342	[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
4343	[GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4344	[GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4345	[GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4346	[GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4347	[GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4348	[GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4349	[GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4350	[GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4351	[GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4352	[GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4353	[GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4354	[GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4355	[GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4356	[GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4357	[GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4358	[GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4359	[GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4360	[GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4361	[GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4362	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4363	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4364	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4365	[GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4366	[GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4367	[GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4368	[GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4369	[GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4370	[GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4371	[GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4372	[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4373	[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4374	[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4375	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4376	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4377	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4378	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4379	[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4380	[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4381	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4382	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
4383	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4384	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4385	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4386	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4387	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4388	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4389	[GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4390	[GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4391	[GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4392	[GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4393	[GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4394	[GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4395	[GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4396	[GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4397	[GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4398	[GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4399	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4400	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4401	[GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4402	[GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4403	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4404	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4405	[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4406	[GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
4407	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4408	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4409	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4410	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4411	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4412	[GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4413	[GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4414	[GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4415	[GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4416	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4417	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4418	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4419	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4420	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
4421	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4422	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4423	[PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4424	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4425	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4426	[RBCPR_WCSS_CLK_SRC] = &rbcpr_wcss_clk_src.clkr,
4427	[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
4428	[LPASS_CORE_AXIM_CLK_SRC] = &lpass_core_axim_clk_src.clkr,
4429	[GCC_LPASS_SNOC_CFG_CLK] = &gcc_lpass_snoc_cfg_clk.clkr,
4430	[LPASS_SNOC_CFG_CLK_SRC] = &lpass_snoc_cfg_clk_src.clkr,
4431	[GCC_LPASS_Q6_AXIM_CLK] = &gcc_lpass_q6_axim_clk.clkr,
4432	[LPASS_Q6_AXIM_CLK_SRC] = &lpass_q6_axim_clk_src.clkr,
4433	[GCC_LPASS_Q6_ATBM_AT_CLK] = &gcc_lpass_q6_atbm_at_clk.clkr,
4434	[GCC_LPASS_Q6_PCLKDBG_CLK] = &gcc_lpass_q6_pclkdbg_clk.clkr,
4435	[GCC_LPASS_Q6SS_TSCTR_1TO2_CLK] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr,
4436	[GCC_LPASS_Q6SS_TRIG_CLK] = &gcc_lpass_q6ss_trig_clk.clkr,
4437	[GCC_LPASS_TBU_CLK] = &gcc_lpass_tbu_clk.clkr,
4438	[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
4439	[GCC_MEM_NOC_UBI32_CLK] = &gcc_mem_noc_ubi32_clk.clkr,
4440	[GCC_MEM_NOC_LPASS_CLK] = &gcc_mem_noc_lpass_clk.clkr,
4441	[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
4442	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4443	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4444	};
4445
4446	static const struct qcom_reset_map gcc_ipq6018_resets[] = {
4447	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4448	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4449	[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
4450	[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
4451	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4452	[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
4453	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4454	[GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
4455	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4456	[GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
4457	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4458	[GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
4459	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4460	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4461	[GCC_SMMU_BCR] = { 0x12000, 0 },
4462	[GCC_APSS_TCU_BCR] = { 0x12050, 0 },
4463	[GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
4464	[GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
4465	[GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
4466	[GCC_PRNG_BCR] = { 0x13000, 0 },
4467	[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
4468	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4469	[GCC_WCSS_BCR] = { 0x18000, 0 },
4470	[GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
4471	[GCC_NSS_BCR] = { 0x19000, 0 },
4472	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4473	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4474	[GCC_DDRSS_BCR] = { 0x1e000, 0 },
4475	[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
4476	[GCC_PCNOC_BCR] = { 0x27018, 0 },
4477	[GCC_TCSR_BCR] = { 0x28000, 0 },
4478	[GCC_QDSS_BCR] = { 0x29000, 0 },
4479	[GCC_DCD_BCR] = { 0x2a000, 0 },
4480	[GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
4481	[GCC_MPM_BCR] = { 0x2c000, 0 },
4482	[GCC_SPDM_BCR] = { 0x2f000, 0 },
4483	[GCC_RBCPR_BCR] = { 0x33000, 0 },
4484	[GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
4485	[GCC_TLMM_BCR] = { 0x34000, 0 },
4486	[GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
4487	[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
4488	[GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
4489	[GCC_USB0_BCR] = { 0x3e070, 0 },
4490	[GCC_USB1_BCR] = { 0x3f070, 0 },
4491	[GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
4492	[GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
4493	[GCC_SDCC1_BCR] = { 0x42000, 0 },
4494	[GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
4495	[GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x47008, 0 },
4496	[GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47010, 0 },
4497	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
4498	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
4499	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
4500	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
4501	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
4502	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
4503	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
4504	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
4505	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
4506	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
4507	[GCC_UNIPHY0_BCR] = { 0x56000, 0 },
4508	[GCC_UNIPHY1_BCR] = { 0x56100, 0 },
4509	[GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
4510	[GCC_QPIC_BCR] = { 0x57018, 0 },
4511	[GCC_MDIO_BCR] = { 0x58000, 0 },
4512	[GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
4513	[GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
4514	[GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
4515	[GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
4516	[GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
4517	[GCC_PCIE0_BCR] = { 0x75004, 0 },
4518	[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
4519	[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
4520	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
4521	[GCC_DCC_BCR] = { 0x77000, 0 },
4522	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
4523	[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
4524	[GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
4525	[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
4526	[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
4527	[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
4528	[GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
4529	[GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
4530	[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },
4531	[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },
4532	[GCC_NSS_CFG_ARES] = { 0x68010, 16 },
4533	[GCC_NSS_NOC_ARES] = { 0x68010, 18 },
4534	[GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
4535	[GCC_NSS_CSR_ARES] = { 0x68010, 20 },
4536	[GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
4537	[GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
4538	[GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
4539	[GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
4540	[GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
4541	[GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
4542	[GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
4543	[GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
4544	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
4545	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
4546	[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
4547	[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
4548	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
4549	[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
4550	[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
4551	[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
4552	[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
4553	[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
4554	[GCC_PPE_FULL_RESET] = { .reg = 0x68014, .bitmask = 0xf0000 },
4555	[GCC_UNIPHY0_SOFT_RESET] = { .reg = 0x56004, .bitmask = 0x3ff2 },
4556	[GCC_UNIPHY0_XPCS_RESET] = { 0x56004, 2 },
4557	[GCC_UNIPHY1_SOFT_RESET] = { .reg = 0x56104, .bitmask = 0x32 },
4558	[GCC_UNIPHY1_XPCS_RESET] = { 0x56104, 2 },
4559	[GCC_EDMA_HW_RESET] = { .reg = 0x68014, .bitmask = 0x300000 },
4560	[GCC_NSSPORT1_RESET] = { .reg = 0x68014, .bitmask = 0x1000003 },
4561	[GCC_NSSPORT2_RESET] = { .reg = 0x68014, .bitmask = 0x200000c },
4562	[GCC_NSSPORT3_RESET] = { .reg = 0x68014, .bitmask = 0x4000030 },
4563	[GCC_NSSPORT4_RESET] = { .reg = 0x68014, .bitmask = 0x8000300 },
4564	[GCC_NSSPORT5_RESET] = { .reg = 0x68014, .bitmask = 0x10000c00 },
4565	[GCC_UNIPHY0_PORT1_ARES] = { .reg = 0x56004, .bitmask = 0x30 },
4566	[GCC_UNIPHY0_PORT2_ARES] = { .reg = 0x56004, .bitmask = 0xc0 },
4567	[GCC_UNIPHY0_PORT3_ARES] = { .reg = 0x56004, .bitmask = 0x300 },
4568	[GCC_UNIPHY0_PORT4_ARES] = { .reg = 0x56004, .bitmask = 0xc00 },
4569	[GCC_UNIPHY0_PORT5_ARES] = { .reg = 0x56004, .bitmask = 0x3000 },
4570	[GCC_UNIPHY0_PORT_4_5_RESET] = { .reg = 0x56004, .bitmask = 0x3c02 },
4571	[GCC_UNIPHY0_PORT_4_RESET] = { .reg = 0x56004, .bitmask = 0xc02 },
4572	[GCC_LPASS_BCR] = {0x1F000, 0},
4573	[GCC_UBI32_TBU_BCR] = {0x65000, 0},
4574	[GCC_LPASS_TBU_BCR] = {0x6C000, 0},
4575	[GCC_WCSSAON_RESET] = {0x59010, 0},
4576	[GCC_LPASS_Q6_AXIM_ARES] = {0x1F004, 0},
4577	[GCC_LPASS_Q6SS_TSCTR_1TO2_ARES] = {0x1F004, 1},
4578	[GCC_LPASS_Q6SS_TRIG_ARES] = {0x1F004, 2},
4579	[GCC_LPASS_Q6_ATBM_AT_ARES] = {0x1F004, 3},
4580	[GCC_LPASS_Q6_PCLKDBG_ARES] = {0x1F004, 4},
4581	[GCC_LPASS_CORE_AXIM_ARES] = {0x1F004, 5},
4582	[GCC_LPASS_SNOC_CFG_ARES] = {0x1F004, 6},
4583	[GCC_WCSS_DBG_ARES] = {0x59008, 0},
4584	[GCC_WCSS_ECAHB_ARES] = {0x59008, 1},
4585	[GCC_WCSS_ACMT_ARES] = {0x59008, 2},
4586	[GCC_WCSS_DBG_BDG_ARES] = {0x59008, 3},
4587	[GCC_WCSS_AHB_S_ARES] = {0x59008, 4},
4588	[GCC_WCSS_AXI_M_ARES] = {0x59008, 5},
4589	[GCC_Q6SS_DBG_ARES] = {0x59110, 0},
4590	[GCC_Q6_AHB_S_ARES] = {0x59110, 1},
4591	[GCC_Q6_AHB_ARES] = {0x59110, 2},
4592	[GCC_Q6_AXIM2_ARES] = {0x59110, 3},
4593	[GCC_Q6_AXIM_ARES] = {0x59110, 4},
4594	};
4595
4596	static const struct of_device_id gcc_ipq6018_match_table[] = {
4597	{ .compatible = "qcom,gcc-ipq6018" },
4598	{ }
4599	};
4600	MODULE_DEVICE_TABLE(of, gcc_ipq6018_match_table);
4601
4602	static const struct regmap_config gcc_ipq6018_regmap_config = {
4603	.reg_bits = 32,
4604	.reg_stride = 4,
4605	.val_bits = 32,
4606	.max_register = 0x7fffc,
4607	.fast_io = true,
4608	};
4609
4610	static const struct qcom_cc_desc gcc_ipq6018_desc = {
4611	.config = &gcc_ipq6018_regmap_config,
4612	.clks = gcc_ipq6018_clks,
4613	.num_clks = ARRAY_SIZE(gcc_ipq6018_clks),
4614	.resets = gcc_ipq6018_resets,
4615	.num_resets = ARRAY_SIZE(gcc_ipq6018_resets),
4616	.clk_hws = gcc_ipq6018_hws,
4617	.num_clk_hws = ARRAY_SIZE(gcc_ipq6018_hws),
4618	};
4619
4620	static int gcc_ipq6018_probe(struct platform_device *pdev)
4621	{
4622	struct regmap *regmap;
4623
4624	regmap = qcom_cc_map(pdev, desc: &gcc_ipq6018_desc);
4625	if (IS_ERR(ptr: regmap))
4626	return PTR_ERR(ptr: regmap);
4627
4628	/* Disable SW_COLLAPSE for USB0 GDSCR */
4629	regmap_update_bits(map: regmap, reg: 0x3e078, BIT(0), val: 0x0);
4630	/* Enable SW_OVERRIDE for USB0 GDSCR */
4631	regmap_update_bits(map: regmap, reg: 0x3e078, BIT(2), BIT(2));
4632	/* Disable SW_COLLAPSE for USB1 GDSCR */
4633	regmap_update_bits(map: regmap, reg: 0x3f078, BIT(0), val: 0x0);
4634	/* Enable SW_OVERRIDE for USB1 GDSCR */
4635	regmap_update_bits(map: regmap, reg: 0x3f078, BIT(2), BIT(2));
4636
4637	/* SW Workaround for UBI Huyara PLL */
4638	regmap_update_bits(map: regmap, reg: 0x2501c, BIT(26), BIT(26));
4639
4640	clk_alpha_pll_configure(pll: &ubi32_pll_main, regmap, config: &ubi32_pll_config);
4641
4642	clk_alpha_pll_configure(pll: &nss_crypto_pll_main, regmap,
4643	config: &nss_crypto_pll_config);
4644
4645	return qcom_cc_really_probe(pdev, desc: &gcc_ipq6018_desc, regmap);
4646	}
4647
4648	static struct platform_driver gcc_ipq6018_driver = {
4649	.probe = gcc_ipq6018_probe,
4650	.driver = {
4651	.name = "qcom,gcc-ipq6018",
4652	.of_match_table = gcc_ipq6018_match_table,
4653	},
4654	};
4655
4656	static int __init gcc_ipq6018_init(void)
4657	{
4658	return platform_driver_register(&gcc_ipq6018_driver);
4659	}
4660	core_initcall(gcc_ipq6018_init);
4661
4662	static void __exit gcc_ipq6018_exit(void)
4663	{
4664	platform_driver_unregister(&gcc_ipq6018_driver);
4665	}
4666	module_exit(gcc_ipq6018_exit);
4667
4668	MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ6018 Driver");
4669	MODULE_LICENSE("GPL v2");
4670