1	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2	/*
3	* Copyright (c) 2023 The Linux Foundation. All rights reserved.
4	*/
5
6	#include <linux/clk-provider.h>
7	#include <linux/kernel.h>
8	#include <linux/module.h>
9	#include <linux/of.h>
10	#include <linux/platform_device.h>
11	#include <linux/regmap.h>
12
13	#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
14	#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
15
16	#include "clk-alpha-pll.h"
17	#include "clk-branch.h"
18	#include "clk-rcg.h"
19	#include "clk-regmap.h"
20	#include "clk-regmap-divider.h"
21	#include "clk-regmap-mux.h"
22	#include "clk-regmap-phy-mux.h"
23	#include "common.h"
24	#include "reset.h"
25
26	/* Need to match the order of clocks in DT binding */
27	enum {
28	DT_XO,
29	DT_SLEEP_CLK,
30	DT_BIAS_PLL_UBI_NC_CLK,
31	DT_PCIE30_PHY0_PIPE_CLK,
32	DT_PCIE30_PHY1_PIPE_CLK,
33	DT_PCIE30_PHY2_PIPE_CLK,
34	DT_PCIE30_PHY3_PIPE_CLK,
35	DT_USB3PHY_0_CC_PIPE_CLK,
36	};
37
38	enum {
39	P_XO,
40	P_PCIE30_PHY0_PIPE,
41	P_PCIE30_PHY1_PIPE,
42	P_PCIE30_PHY2_PIPE,
43	P_PCIE30_PHY3_PIPE,
44	P_USB3PHY_0_PIPE,
45	P_GPLL0,
46	P_GPLL0_DIV2,
47	P_GPLL0_OUT_AUX,
48	P_GPLL2,
49	P_GPLL4,
50	P_PI_SLEEP,
51	P_BIAS_PLL_UBI_NC_CLK,
52	};
53
54	static const struct parent_map gcc_xo_map[] = {
55	{ P_XO, 0 },
56	};
57
58	static const struct clk_parent_data gcc_xo_data[] = {
59	{ .index = DT_XO },
60	};
61
62	static const struct clk_parent_data gcc_sleep_clk_data[] = {
63	{ .index = DT_SLEEP_CLK },
64	};
65
66	static struct clk_alpha_pll gpll0_main = {
67	.offset = 0x20000,
68	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
69	.clkr = {
70	.enable_reg = 0x0b000,
71	.enable_mask = BIT(0),
72	.hw.init = &(const struct clk_init_data) {
73	.name = "gpll0_main",
74	.parent_data = gcc_xo_data,
75	.num_parents = ARRAY_SIZE(gcc_xo_data),
76	.ops = &clk_alpha_pll_ops,
77	},
78	},
79	};
80
81	static struct clk_fixed_factor gpll0_out_main_div2 = {
82	.mult = 1,
83	.div = 2,
84	.hw.init = &(const struct clk_init_data) {
85	.name = "gpll0_out_main_div2",
86	.parent_hws = (const struct clk_hw *[]) {
87	&gpll0_main.clkr.hw
88	},
89	.num_parents = 1,
90	.ops = &clk_fixed_factor_ops,
91	},
92	};
93
94	static struct clk_alpha_pll_postdiv gpll0 = {
95	.offset = 0x20000,
96	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
97	.width = 4,
98	.clkr.hw.init = &(const struct clk_init_data) {
99	.name = "gpll0",
100	.parent_hws = (const struct clk_hw *[]) {
101	&gpll0_main.clkr.hw
102	},
103	.num_parents = 1,
104	.ops = &clk_alpha_pll_postdiv_ro_ops,
105	},
106	};
107
108	static struct clk_alpha_pll gpll4_main = {
109	.offset = 0x22000,
110	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
111	.clkr = {
112	.enable_reg = 0x0b000,
113	.enable_mask = BIT(2),
114	.hw.init = &(const struct clk_init_data) {
115	.name = "gpll4_main",
116	.parent_data = gcc_xo_data,
117	.num_parents = ARRAY_SIZE(gcc_xo_data),
118	.ops = &clk_alpha_pll_ops,
119	},
120	},
121	};
122
123	static struct clk_alpha_pll_postdiv gpll4 = {
124	.offset = 0x22000,
125	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
126	.width = 4,
127	.clkr.hw.init = &(const struct clk_init_data) {
128	.name = "gpll4",
129	.parent_hws = (const struct clk_hw *[]) {
130	&gpll4_main.clkr.hw
131	},
132	.num_parents = 1,
133	.ops = &clk_alpha_pll_postdiv_ro_ops,
134	},
135	};
136
137	static struct clk_alpha_pll gpll2_main = {
138	.offset = 0x21000,
139	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
140	.clkr = {
141	.enable_reg = 0x0b000,
142	.enable_mask = BIT(1),
143	.hw.init = &(const struct clk_init_data) {
144	.name = "gpll2_main",
145	.parent_data = gcc_xo_data,
146	.num_parents = ARRAY_SIZE(gcc_xo_data),
147	.ops = &clk_alpha_pll_ops,
148	},
149	},
150	};
151
152	static struct clk_alpha_pll_postdiv gpll2 = {
153	.offset = 0x21000,
154	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
155	.width = 4,
156	.clkr.hw.init = &(const struct clk_init_data) {
157	.name = "gpll2",
158	.parent_hws = (const struct clk_hw *[]) {
159	&gpll2_main.clkr.hw
160	},
161	.num_parents = 1,
162	.ops = &clk_alpha_pll_postdiv_ro_ops,
163	},
164	};
165
166	static struct clk_branch gcc_sleep_clk_src = {
167	.halt_reg = 0x3400c,
168	.clkr = {
169	.enable_reg = 0x3400c,
170	.enable_mask = BIT(1),
171	.hw.init = &(const struct clk_init_data) {
172	.name = "gcc_sleep_clk_src",
173	.parent_data = gcc_sleep_clk_data,
174	.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
175	.flags = CLK_IS_CRITICAL,
176	.ops = &clk_branch2_ops,
177	},
178	},
179	};
180
181	static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
182	{ .index = DT_XO },
183	{ .hw = &gpll0.clkr.hw },
184	{ .hw = &gpll0_out_main_div2.hw },
185	};
186
187	static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
188	{ P_XO, 0 },
189	{ P_GPLL0, 1 },
190	{ P_GPLL0_DIV2, 4 },
191	};
192
193	static const struct clk_parent_data gcc_xo_gpll0[] = {
194	{ .index = DT_XO },
195	{ .hw = &gpll0.clkr.hw },
196	};
197
198	static const struct parent_map gcc_xo_gpll0_map[] = {
199	{ P_XO, 0 },
200	{ P_GPLL0, 1 },
201	};
202
203	static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
204	{ .index = DT_XO },
205	{ .hw = &gpll0.clkr.hw },
206	{ .hw = &gpll4.clkr.hw },
207	};
208
209	static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
210	{ P_XO, 0 },
211	{ P_GPLL0, 1 },
212	{ P_GPLL4, 2 },
213	};
214
215	static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
216	{ .index = DT_XO },
217	{ .hw = &gpll0.clkr.hw },
218	{ .hw = &gpll0_out_main_div2.hw },
219	{ .hw = &gpll0.clkr.hw },
220	};
221
222	static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
223	{ P_XO, 0 },
224	{ P_GPLL0, 1 },
225	{ P_GPLL0_DIV2, 4 },
226	{ P_GPLL0, 5 },
227	};
228
229	static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
230	{ .index = DT_XO },
231	{ .hw = &gpll0.clkr.hw },
232	{ .hw = &gpll0_out_main_div2.hw },
233	{ .index = DT_SLEEP_CLK },
234	};
235
236	static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
237	{ P_XO, 0 },
238	{ P_GPLL0, 1 },
239	{ P_GPLL0_DIV2, 4 },
240	{ P_PI_SLEEP, 6 },
241	};
242
243	static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
244	{ .index = DT_XO },
245	{ .hw = &gpll0.clkr.hw },
246	{ .index = DT_SLEEP_CLK },
247	};
248
249	static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
250	{ P_XO, 0 },
251	{ P_GPLL0, 2 },
252	{ P_PI_SLEEP, 6 },
253	};
254
255	static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
256	{ .index = DT_XO },
257	{ .hw = &gpll0.clkr.hw },
258	{ .hw = &gpll4.clkr.hw },
259	{ .index = DT_BIAS_PLL_UBI_NC_CLK },
260	};
261
262	static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
263	{ P_XO, 0 },
264	{ P_GPLL0, 1 },
265	{ P_GPLL4, 2 },
266	{ P_BIAS_PLL_UBI_NC_CLK, 3 },
267	};
268
269	static const struct clk_parent_data
270	gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
271	{ .index = DT_XO },
272	{ .hw = &gpll0.clkr.hw },
273	{ .hw = &gpll0.clkr.hw },
274	{ .index = DT_SLEEP_CLK },
275	};
276
277	static const struct parent_map
278	gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
279	{ P_XO, 0 },
280	{ P_GPLL0, 1 },
281	{ P_GPLL0_OUT_AUX, 2 },
282	{ P_PI_SLEEP, 6 },
283	};
284
285	static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
286	{ .index = DT_XO },
287	{ .hw = &gpll0.clkr.hw },
288	{ .hw = &gpll0_out_main_div2.hw },
289	};
290
291	static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
292	{ P_XO, 0 },
293	{ P_GPLL0, 1 },
294	{ P_GPLL0_DIV2, 4 },
295	};
296
297	static const struct clk_parent_data
298	gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
299	{ .index = DT_XO },
300	{ .hw = &gpll4.clkr.hw },
301	{ .hw = &gpll0.clkr.hw },
302	{ .hw = &gpll0_out_main_div2.hw },
303	};
304
305	static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
306	{ P_XO, 0 },
307	{ P_GPLL4, 1 },
308	{ P_GPLL0, 3 },
309	{ P_GPLL0_DIV2, 4 },
310	};
311
312	static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
313	{ .index = DT_USB3PHY_0_CC_PIPE_CLK },
314	{ .index = DT_XO },
315	};
316
317	static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
318	{ P_USB3PHY_0_PIPE, 0 },
319	{ P_XO, 2 },
320	};
321
322	static const struct clk_parent_data
323	gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
324	{ .index = DT_XO },
325	{ .hw = &gpll0.clkr.hw },
326	{ .hw = &gpll2.clkr.hw },
327	{ .hw = &gpll0_out_main_div2.hw },
328	};
329
330	static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
331	{ P_XO, 0 },
332	{ P_GPLL0, 1 },
333	{ P_GPLL2, 2 },
334	{ P_GPLL0_DIV2, 4 },
335	};
336
337	static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
338	{ .index = DT_XO},
339	{ .hw = &gpll0.clkr.hw },
340	{ .hw = &gpll4.clkr.hw },
341	{ .hw = &gpll0_out_main_div2.hw },
342	};
343
344	static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
345	{ P_XO, 0 },
346	{ P_GPLL0, 1 },
347	{ P_GPLL4, 2 },
348	{ P_GPLL0_DIV2, 4 },
349	};
350
351	static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
352	{ .index = DT_XO },
353	{ .hw = &gpll4.clkr.hw },
354	{ .hw = &gpll0.clkr.hw },
355	{ .hw = &gpll0_out_main_div2.hw },
356	};
357
358	static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
359	{ P_XO, 0 },
360	{ P_GPLL4, 1 },
361	{ P_GPLL0, 2 },
362	{ P_GPLL0_DIV2, 4 },
363	};
364
365	static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
366	{ .index = DT_XO },
367	{ .hw = &gpll0.clkr.hw },
368	{ .hw = &gpll2.clkr.hw },
369	};
370
371	static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
372	{ P_XO, 0 },
373	{ P_GPLL0, 1 },
374	{ P_GPLL2, 2 },
375	};
376
377	static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
378	{ .index = DT_XO },
379	{ .hw = &gpll0.clkr.hw },
380	{ .hw = &gpll2.clkr.hw },
381	{ .hw = &gpll4.clkr.hw },
382	{ .index = DT_SLEEP_CLK },
383	};
384
385	static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
386	{ P_XO, 0 },
387	{ P_GPLL0, 1 },
388	{ P_GPLL2, 2 },
389	{ P_GPLL4, 3 },
390	{ P_PI_SLEEP, 6 },
391	};
392
393	static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
394	{ .index = DT_XO },
395	{ .hw = &gpll0.clkr.hw },
396	{ .hw = &gpll0.clkr.hw },
397	{ .hw = &gpll2.clkr.hw },
398	};
399
400	static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
401	{ P_XO, 0 },
402	{ P_GPLL0, 1 },
403	{ P_GPLL0_OUT_AUX, 2 },
404	{ P_GPLL2, 3 },
405	};
406
407	static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
408	F(24000000, P_XO, 1, 0, 0),
409	F(50000000, P_GPLL0, 16, 0, 0),
410	F(100000000, P_GPLL0, 8, 0, 0),
411	{ }
412	};
413
414	static struct clk_rcg2 apss_ahb_clk_src = {
415	.cmd_rcgr = 0x2400c,
416	.freq_tbl = ftbl_apss_ahb_clk_src,
417	.hid_width = 5,
418	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
419	.clkr.hw.init = &(const struct clk_init_data) {
420	.name = "apss_ahb_clk_src",
421	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
422	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
423	.ops = &clk_rcg2_ops,
424	},
425	};
426
427	static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
428	F(533000000, P_GPLL0, 1.5, 0, 0),
429	{ }
430	};
431
432	static struct clk_rcg2 apss_axi_clk_src = {
433	.cmd_rcgr = 0x24004,
434	.freq_tbl = ftbl_apss_axi_clk_src,
435	.hid_width = 5,
436	.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
437	.clkr.hw.init = &(const struct clk_init_data) {
438	.name = "apss_axi_clk_src",
439	.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
440	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
441	.ops = &clk_rcg2_ops,
442	},
443	};
444
445	static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
446	F(9600000, P_XO, 2.5, 0, 0),
447	F(24000000, P_XO, 1, 0, 0),
448	F(50000000, P_GPLL0, 16, 0, 0),
449	{ }
450	};
451
452	static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
453	.cmd_rcgr = 0x02018,
454	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
455	.hid_width = 5,
456	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
457	.clkr.hw.init = &(const struct clk_init_data) {
458	.name = "blsp1_qup1_i2c_apps_clk_src",
459	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
460	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
461	.ops = &clk_rcg2_ops,
462	},
463	};
464
465	static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
466	F(960000, P_XO, 10, 2, 5),
467	F(4800000, P_XO, 5, 0, 0),
468	F(9600000, P_XO, 2, 4, 5),
469	F(16000000, P_GPLL0, 10, 1, 5),
470	F(24000000, P_XO, 1, 0, 0),
471	F(25000000, P_GPLL0, 16, 1, 2),
472	F(50000000, P_GPLL0, 16, 0, 0),
473	{ }
474	};
475
476	static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
477	.cmd_rcgr = 0x02004,
478	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
479	.mnd_width = 8,
480	.hid_width = 5,
481	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
482	.clkr.hw.init = &(const struct clk_init_data) {
483	.name = "blsp1_qup1_spi_apps_clk_src",
484	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
485	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
486	.ops = &clk_rcg2_ops,
487	},
488	};
489
490	static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
491	.cmd_rcgr = 0x03018,
492	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
493	.hid_width = 5,
494	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
495	.clkr.hw.init = &(const struct clk_init_data) {
496	.name = "blsp1_qup2_i2c_apps_clk_src",
497	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
498	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
499	.ops = &clk_rcg2_ops,
500	},
501	};
502
503	static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
504	.cmd_rcgr = 0x03004,
505	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
506	.mnd_width = 8,
507	.hid_width = 5,
508	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
509	.clkr.hw.init = &(const struct clk_init_data) {
510	.name = "blsp1_qup2_spi_apps_clk_src",
511	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
512	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
513	.ops = &clk_rcg2_ops,
514	},
515	};
516
517	static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
518	.cmd_rcgr = 0x04018,
519	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
520	.hid_width = 5,
521	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
522	.clkr.hw.init = &(const struct clk_init_data) {
523	.name = "blsp1_qup3_i2c_apps_clk_src",
524	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
525	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
526	.ops = &clk_rcg2_ops,
527	},
528	};
529
530	static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
531	.cmd_rcgr = 0x04004,
532	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
533	.mnd_width = 8,
534	.hid_width = 5,
535	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
536	.clkr.hw.init = &(const struct clk_init_data) {
537	.name = "blsp1_qup3_spi_apps_clk_src",
538	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
539	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
540	.ops = &clk_rcg2_ops,
541	},
542	};
543
544	static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
545	.cmd_rcgr = 0x05018,
546	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
547	.hid_width = 5,
548	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
549	.clkr.hw.init = &(const struct clk_init_data) {
550	.name = "blsp1_qup4_i2c_apps_clk_src",
551	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
552	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
553	.ops = &clk_rcg2_ops,
554	},
555	};
556
557	static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
558	.cmd_rcgr = 0x05004,
559	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
560	.mnd_width = 8,
561	.hid_width = 5,
562	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
563	.clkr.hw.init = &(const struct clk_init_data) {
564	.name = "blsp1_qup4_spi_apps_clk_src",
565	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
566	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
567	.ops = &clk_rcg2_ops,
568	},
569	};
570
571	static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
572	.cmd_rcgr = 0x06018,
573	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
574	.hid_width = 5,
575	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
576	.clkr.hw.init = &(const struct clk_init_data) {
577	.name = "blsp1_qup5_i2c_apps_clk_src",
578	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
579	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
580	.ops = &clk_rcg2_ops,
581	},
582	};
583
584	static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
585	.cmd_rcgr = 0x06004,
586	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
587	.mnd_width = 8,
588	.hid_width = 5,
589	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
590	.clkr.hw.init = &(const struct clk_init_data) {
591	.name = "blsp1_qup5_spi_apps_clk_src",
592	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
593	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
594	.ops = &clk_rcg2_ops,
595	},
596	};
597
598	static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
599	.cmd_rcgr = 0x07018,
600	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
601	.hid_width = 5,
602	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
603	.clkr.hw.init = &(const struct clk_init_data) {
604	.name = "blsp1_qup6_i2c_apps_clk_src",
605	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
606	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
607	.ops = &clk_rcg2_ops,
608	},
609	};
610
611	static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
612	.cmd_rcgr = 0x07004,
613	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
614	.mnd_width = 8,
615	.hid_width = 5,
616	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
617	.clkr.hw.init = &(const struct clk_init_data) {
618	.name = "blsp1_qup6_spi_apps_clk_src",
619	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
620	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
621	.ops = &clk_rcg2_ops,
622	},
623	};
624
625	static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
626	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
627	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
628	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
629	F(24000000, P_XO, 1, 0, 0),
630	F(25000000, P_GPLL0, 16, 1, 2),
631	F(32000000, P_GPLL0, 1, 1, 25),
632	F(40000000, P_GPLL0, 1, 1, 20),
633	F(46400000, P_GPLL0, 1, 29, 500),
634	F(48000000, P_GPLL0, 1, 3, 50),
635	F(51200000, P_GPLL0, 1, 8, 125),
636	F(56000000, P_GPLL0, 1, 7, 100),
637	F(58982400, P_GPLL0, 1, 1152, 15625),
638	F(60000000, P_GPLL0, 1, 3, 40),
639	F(64000000, P_GPLL0, 12.5, 0, 0),
640	{ }
641	};
642
643	static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
644	.cmd_rcgr = 0x0202c,
645	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
646	.mnd_width = 16,
647	.hid_width = 5,
648	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
649	.clkr.hw.init = &(const struct clk_init_data) {
650	.name = "blsp1_uart1_apps_clk_src",
651	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
652	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
653	.ops = &clk_rcg2_ops,
654	},
655	};
656
657	static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
658	.cmd_rcgr = 0x0302c,
659	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
660	.mnd_width = 16,
661	.hid_width = 5,
662	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
663	.clkr.hw.init = &(const struct clk_init_data) {
664	.name = "blsp1_uart2_apps_clk_src",
665	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
666	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
667	.ops = &clk_rcg2_ops,
668	},
669	};
670
671	static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
672	.cmd_rcgr = 0x0402c,
673	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
674	.mnd_width = 16,
675	.hid_width = 5,
676	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
677	.clkr.hw.init = &(const struct clk_init_data) {
678	.name = "blsp1_uart3_apps_clk_src",
679	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
680	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
681	.ops = &clk_rcg2_ops,
682	},
683	};
684
685	static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
686	.cmd_rcgr = 0x0502c,
687	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
688	.mnd_width = 16,
689	.hid_width = 5,
690	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
691	.clkr.hw.init = &(const struct clk_init_data) {
692	.name = "blsp1_uart4_apps_clk_src",
693	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
694	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
695	.ops = &clk_rcg2_ops,
696	},
697	};
698
699	static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
700	.cmd_rcgr = 0x0602c,
701	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
702	.mnd_width = 16,
703	.hid_width = 5,
704	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
705	.clkr.hw.init = &(const struct clk_init_data) {
706	.name = "blsp1_uart5_apps_clk_src",
707	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
708	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
709	.ops = &clk_rcg2_ops,
710	},
711	};
712
713	static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
714	.cmd_rcgr = 0x0702c,
715	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
716	.mnd_width = 16,
717	.hid_width = 5,
718	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
719	.clkr.hw.init = &(const struct clk_init_data) {
720	.name = "blsp1_uart6_apps_clk_src",
721	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
722	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
723	.ops = &clk_rcg2_ops,
724	},
725	};
726
727	static const struct freq_tbl ftbl_gcc_crypto_clk_src[] = {
728	F(160000000, P_GPLL0, 5, 0, 0),
729	{ }
730	};
731
732	static struct clk_rcg2 gcc_crypto_clk_src = {
733	.cmd_rcgr = 0x16004,
734	.freq_tbl = ftbl_gcc_crypto_clk_src,
735	.hid_width = 5,
736	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
737	.clkr.hw.init = &(const struct clk_init_data) {
738	.name = "gcc_crypto_clk_src",
739	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
740	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
741	.ops = &clk_rcg2_ops,
742	},
743	};
744
745	static struct clk_branch gcc_crypto_clk = {
746	.halt_reg = 0x1600c,
747	.halt_check = BRANCH_HALT_VOTED,
748	.clkr = {
749	.enable_reg = 0x0b004,
750	.enable_mask = BIT(14),
751	.hw.init = &(const struct clk_init_data) {
752	.name = "gcc_crypto_clk",
753	.parent_hws = (const struct clk_hw *[]) {
754	&gcc_crypto_clk_src.clkr.hw },
755	.num_parents = 1,
756	.flags = CLK_SET_RATE_PARENT,
757	.ops = &clk_branch2_ops,
758	},
759	},
760	};
761
762	static struct clk_branch gcc_apss_ahb_clk = {
763	.halt_reg = 0x24018,
764	.halt_check = BRANCH_HALT_VOTED,
765	.clkr = {
766	.enable_reg = 0x0b004,
767	.enable_mask = BIT(0),
768	.hw.init = &(const struct clk_init_data) {
769	.name = "gcc_apss_ahb_clk",
770	.parent_hws = (const struct clk_hw *[]) {
771	&apss_ahb_clk_src.clkr.hw
772	},
773	.num_parents = 1,
774	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
775	.ops = &clk_branch2_ops,
776	},
777	},
778	};
779
780	static struct clk_branch gcc_apss_axi_clk = {
781	.halt_reg = 0x2401c,
782	.halt_check = BRANCH_HALT_VOTED,
783	.clkr = {
784	.enable_reg = 0x0b004,
785	.enable_mask = BIT(1),
786	.hw.init = &(const struct clk_init_data) {
787	.name = "gcc_apss_axi_clk",
788	.parent_hws = (const struct clk_hw *[]) {
789	&apss_axi_clk_src.clkr.hw
790	},
791	.num_parents = 1,
792	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
793	.ops = &clk_branch2_ops,
794	},
795	},
796	};
797
798	static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
799	.halt_reg = 0x2024,
800	.clkr = {
801	.enable_reg = 0x2024,
802	.enable_mask = BIT(0),
803	.hw.init = &(const struct clk_init_data) {
804	.name = "gcc_blsp1_qup1_i2c_apps_clk",
805	.parent_hws = (const struct clk_hw *[]) {
806	&blsp1_qup1_i2c_apps_clk_src.clkr.hw
807	},
808	.num_parents = 1,
809	.flags = CLK_SET_RATE_PARENT,
810	.ops = &clk_branch2_ops,
811	},
812	},
813	};
814
815	static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
816	.halt_reg = 0x02020,
817	.clkr = {
818	.enable_reg = 0x02020,
819	.enable_mask = BIT(0),
820	.hw.init = &(const struct clk_init_data) {
821	.name = "gcc_blsp1_qup1_spi_apps_clk",
822	.parent_hws = (const struct clk_hw *[]) {
823	&blsp1_qup1_spi_apps_clk_src.clkr.hw
824	},
825	.num_parents = 1,
826	.flags = CLK_SET_RATE_PARENT,
827	.ops = &clk_branch2_ops,
828	},
829	},
830	};
831
832	static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
833	.halt_reg = 0x03024,
834	.clkr = {
835	.enable_reg = 0x03024,
836	.enable_mask = BIT(0),
837	.hw.init = &(const struct clk_init_data) {
838	.name = "gcc_blsp1_qup2_i2c_apps_clk",
839	.parent_hws = (const struct clk_hw *[]) {
840	&blsp1_qup2_i2c_apps_clk_src.clkr.hw
841	},
842	.num_parents = 1,
843	.flags = CLK_SET_RATE_PARENT,
844	.ops = &clk_branch2_ops,
845	},
846	},
847	};
848
849	static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
850	.halt_reg = 0x03020,
851	.clkr = {
852	.enable_reg = 0x03020,
853	.enable_mask = BIT(0),
854	.hw.init = &(const struct clk_init_data) {
855	.name = "gcc_blsp1_qup2_spi_apps_clk",
856	.parent_hws = (const struct clk_hw *[]) {
857	&blsp1_qup2_spi_apps_clk_src.clkr.hw
858	},
859	.num_parents = 1,
860	.flags = CLK_SET_RATE_PARENT,
861	.ops = &clk_branch2_ops,
862	},
863	},
864	};
865
866	static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
867	.halt_reg = 0x04024,
868	.clkr = {
869	.enable_reg = 0x04024,
870	.enable_mask = BIT(0),
871	.hw.init = &(const struct clk_init_data) {
872	.name = "gcc_blsp1_qup3_i2c_apps_clk",
873	.parent_hws = (const struct clk_hw *[]) {
874	&blsp1_qup3_i2c_apps_clk_src.clkr.hw
875	},
876	.num_parents = 1,
877	.flags = CLK_SET_RATE_PARENT,
878	.ops = &clk_branch2_ops,
879	},
880	},
881	};
882
883	static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
884	.halt_reg = 0x04020,
885	.clkr = {
886	.enable_reg = 0x04020,
887	.enable_mask = BIT(0),
888	.hw.init = &(const struct clk_init_data) {
889	.name = "gcc_blsp1_qup3_spi_apps_clk",
890	.parent_hws = (const struct clk_hw *[]) {
891	&blsp1_qup3_spi_apps_clk_src.clkr.hw
892	},
893	.num_parents = 1,
894	.flags = CLK_SET_RATE_PARENT,
895	.ops = &clk_branch2_ops,
896	},
897	},
898	};
899
900	static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
901	.halt_reg = 0x05024,
902	.clkr = {
903	.enable_reg = 0x05024,
904	.enable_mask = BIT(0),
905	.hw.init = &(const struct clk_init_data) {
906	.name = "gcc_blsp1_qup4_i2c_apps_clk",
907	.parent_hws = (const struct clk_hw *[]) {
908	&blsp1_qup4_i2c_apps_clk_src.clkr.hw
909	},
910	.num_parents = 1,
911	.flags = CLK_SET_RATE_PARENT,
912	.ops = &clk_branch2_ops,
913	},
914	},
915	};
916
917	static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
918	.halt_reg = 0x05020,
919	.clkr = {
920	.enable_reg = 0x05020,
921	.enable_mask = BIT(0),
922	.hw.init = &(const struct clk_init_data) {
923	.name = "gcc_blsp1_qup4_spi_apps_clk",
924	.parent_hws = (const struct clk_hw *[]) {
925	&blsp1_qup4_spi_apps_clk_src.clkr.hw
926	},
927	.num_parents = 1,
928	.flags = CLK_SET_RATE_PARENT,
929	.ops = &clk_branch2_ops,
930	},
931	},
932	};
933
934	static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
935	.halt_reg = 0x06024,
936	.clkr = {
937	.enable_reg = 0x06024,
938	.enable_mask = BIT(0),
939	.hw.init = &(const struct clk_init_data) {
940	.name = "gcc_blsp1_qup5_i2c_apps_clk",
941	.parent_hws = (const struct clk_hw *[]) {
942	&blsp1_qup5_i2c_apps_clk_src.clkr.hw
943	},
944	.num_parents = 1,
945	.flags = CLK_SET_RATE_PARENT,
946	.ops = &clk_branch2_ops,
947	},
948	},
949	};
950
951	static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
952	.halt_reg = 0x06020,
953	.clkr = {
954	.enable_reg = 0x06020,
955	.enable_mask = BIT(0),
956	.hw.init = &(const struct clk_init_data) {
957	.name = "gcc_blsp1_qup5_spi_apps_clk",
958	.parent_hws = (const struct clk_hw *[]) {
959	&blsp1_qup5_spi_apps_clk_src.clkr.hw
960	},
961	.num_parents = 1,
962	.flags = CLK_SET_RATE_PARENT,
963	.ops = &clk_branch2_ops,
964	},
965	},
966	};
967
968	static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
969	.halt_reg = 0x07024,
970	.clkr = {
971	.enable_reg = 0x07024,
972	.enable_mask = BIT(0),
973	.hw.init = &(const struct clk_init_data) {
974	.name = "gcc_blsp1_qup6_i2c_apps_clk",
975	.parent_hws = (const struct clk_hw *[]) {
976	&blsp1_qup6_i2c_apps_clk_src.clkr.hw
977	},
978	.num_parents = 1,
979	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
980	.ops = &clk_branch2_ops,
981	},
982	},
983	};
984
985	static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
986	.halt_reg = 0x07020,
987	.clkr = {
988	.enable_reg = 0x07020,
989	.enable_mask = BIT(0),
990	.hw.init = &(const struct clk_init_data) {
991	.name = "gcc_blsp1_qup6_spi_apps_clk",
992	.parent_hws = (const struct clk_hw *[]) {
993	&blsp1_qup6_spi_apps_clk_src.clkr.hw
994	},
995	.num_parents = 1,
996	.flags = CLK_SET_RATE_PARENT,
997	.ops = &clk_branch2_ops,
998	},
999	},
1000	};
1001
1002	static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1003	.halt_reg = 0x02040,
1004	.clkr = {
1005	.enable_reg = 0x02040,
1006	.enable_mask = BIT(0),
1007	.hw.init = &(const struct clk_init_data) {
1008	.name = "gcc_blsp1_uart1_apps_clk",
1009	.parent_hws = (const struct clk_hw *[]) {
1010	&blsp1_uart1_apps_clk_src.clkr.hw
1011	},
1012	.num_parents = 1,
1013	.flags = CLK_SET_RATE_PARENT,
1014	.ops = &clk_branch2_ops,
1015	},
1016	},
1017	};
1018
1019	static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1020	.halt_reg = 0x03040,
1021	.clkr = {
1022	.enable_reg = 0x03040,
1023	.enable_mask = BIT(0),
1024	.hw.init = &(const struct clk_init_data) {
1025	.name = "gcc_blsp1_uart2_apps_clk",
1026	.parent_hws = (const struct clk_hw *[]) {
1027	&blsp1_uart2_apps_clk_src.clkr.hw
1028	},
1029	.num_parents = 1,
1030	.flags = CLK_SET_RATE_PARENT,
1031	.ops = &clk_branch2_ops,
1032	},
1033	},
1034	};
1035
1036	static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1037	.halt_reg = 0x04054,
1038	.clkr = {
1039	.enable_reg = 0x04054,
1040	.enable_mask = BIT(0),
1041	.hw.init = &(const struct clk_init_data) {
1042	.name = "gcc_blsp1_uart3_apps_clk",
1043	.parent_hws = (const struct clk_hw *[]) {
1044	&blsp1_uart3_apps_clk_src.clkr.hw
1045	},
1046	.num_parents = 1,
1047	.flags = CLK_SET_RATE_PARENT,
1048	.ops = &clk_branch2_ops,
1049	},
1050	},
1051	};
1052
1053	static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1054	.halt_reg = 0x05040,
1055	.clkr = {
1056	.enable_reg = 0x05040,
1057	.enable_mask = BIT(0),
1058	.hw.init = &(const struct clk_init_data) {
1059	.name = "gcc_blsp1_uart4_apps_clk",
1060	.parent_hws = (const struct clk_hw *[]) {
1061	&blsp1_uart4_apps_clk_src.clkr.hw
1062	},
1063	.num_parents = 1,
1064	.flags = CLK_SET_RATE_PARENT,
1065	.ops = &clk_branch2_ops,
1066	},
1067	},
1068	};
1069
1070	static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1071	.halt_reg = 0x06040,
1072	.clkr = {
1073	.enable_reg = 0x06040,
1074	.enable_mask = BIT(0),
1075	.hw.init = &(const struct clk_init_data) {
1076	.name = "gcc_blsp1_uart5_apps_clk",
1077	.parent_hws = (const struct clk_hw *[]) {
1078	&blsp1_uart5_apps_clk_src.clkr.hw
1079	},
1080	.num_parents = 1,
1081	.flags = CLK_SET_RATE_PARENT,
1082	.ops = &clk_branch2_ops,
1083	},
1084	},
1085	};
1086
1087	static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1088	.halt_reg = 0x07040,
1089	.clkr = {
1090	.enable_reg = 0x07040,
1091	.enable_mask = BIT(0),
1092	.hw.init = &(const struct clk_init_data) {
1093	.name = "gcc_blsp1_uart6_apps_clk",
1094	.parent_hws = (const struct clk_hw *[]) {
1095	&blsp1_uart6_apps_clk_src.clkr.hw
1096	},
1097	.num_parents = 1,
1098	.flags = CLK_SET_RATE_PARENT,
1099	.ops = &clk_branch2_ops,
1100	},
1101	},
1102	};
1103
1104	static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
1105	F(240000000, P_GPLL4, 5, 0, 0),
1106	{ }
1107	};
1108
1109	static struct clk_rcg2 pcie0_axi_m_clk_src = {
1110	.cmd_rcgr = 0x28018,
1111	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1112	.hid_width = 5,
1113	.parent_map = gcc_xo_gpll0_gpll4_map,
1114	.clkr.hw.init = &(const struct clk_init_data) {
1115	.name = "pcie0_axi_m_clk_src",
1116	.parent_data = gcc_xo_gpll0_gpll4,
1117	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1118	.ops = &clk_rcg2_ops,
1119	},
1120	};
1121
1122	static struct clk_branch gcc_pcie0_axi_m_clk = {
1123	.halt_reg = 0x28038,
1124	.clkr = {
1125	.enable_reg = 0x28038,
1126	.enable_mask = BIT(0),
1127	.hw.init = &(const struct clk_init_data) {
1128	.name = "gcc_pcie0_axi_m_clk",
1129	.parent_hws = (const struct clk_hw *[]) {
1130	&pcie0_axi_m_clk_src.clkr.hw
1131	},
1132	.num_parents = 1,
1133	.flags = CLK_SET_RATE_PARENT,
1134	.ops = &clk_branch2_ops,
1135	},
1136	},
1137	};
1138
1139	static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
1140	.halt_reg = 0x2e07c,
1141	.clkr = {
1142	.enable_reg = 0x2e07c,
1143	.enable_mask = BIT(0),
1144	.hw.init = &(const struct clk_init_data) {
1145	.name = "gcc_anoc_pcie0_1lane_m_clk",
1146	.parent_hws = (const struct clk_hw *[]) {
1147	&pcie0_axi_m_clk_src.clkr.hw
1148	},
1149	.num_parents = 1,
1150	.flags = CLK_SET_RATE_PARENT,
1151	.ops = &clk_branch2_ops,
1152	},
1153	},
1154	};
1155
1156	static struct clk_rcg2 pcie1_axi_m_clk_src = {
1157	.cmd_rcgr = 0x29018,
1158	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1159	.hid_width = 5,
1160	.parent_map = gcc_xo_gpll0_gpll4_map,
1161	.clkr.hw.init = &(const struct clk_init_data) {
1162	.name = "pcie1_axi_m_clk_src",
1163	.parent_data = gcc_xo_gpll0_gpll4,
1164	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1165	.ops = &clk_rcg2_ops,
1166	},
1167	};
1168
1169	static struct clk_branch gcc_pcie1_axi_m_clk = {
1170	.halt_reg = 0x29038,
1171	.clkr = {
1172	.enable_reg = 0x29038,
1173	.enable_mask = BIT(0),
1174	.hw.init = &(const struct clk_init_data) {
1175	.name = "gcc_pcie1_axi_m_clk",
1176	.parent_hws = (const struct clk_hw *[]) {
1177	&pcie1_axi_m_clk_src.clkr.hw
1178	},
1179	.num_parents = 1,
1180	.flags = CLK_SET_RATE_PARENT,
1181	.ops = &clk_branch2_ops,
1182	},
1183	},
1184	};
1185
1186	static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
1187	.halt_reg = 0x2e08c,
1188	.clkr = {
1189	.enable_reg = 0x2e08c,
1190	.enable_mask = BIT(0),
1191	.hw.init = &(const struct clk_init_data) {
1192	.name = "gcc_anoc_pcie1_1lane_m_clk",
1193	.parent_hws = (const struct clk_hw *[]) {
1194	&pcie1_axi_m_clk_src.clkr.hw
1195	},
1196	.num_parents = 1,
1197	.flags = CLK_SET_RATE_PARENT,
1198	.ops = &clk_branch2_ops,
1199	},
1200	},
1201	};
1202
1203	static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
1204	F(342857143, P_GPLL4, 3.5, 0, 0),
1205	{ }
1206	};
1207
1208	static struct clk_rcg2 pcie2_axi_m_clk_src = {
1209	.cmd_rcgr = 0x2a018,
1210	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1211	.hid_width = 5,
1212	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1213	.clkr.hw.init = &(const struct clk_init_data) {
1214	.name = "pcie2_axi_m_clk_src",
1215	.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1216	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1217	.ops = &clk_rcg2_ops,
1218	},
1219	};
1220
1221	static struct clk_branch gcc_pcie2_axi_m_clk = {
1222	.halt_reg = 0x2a038,
1223	.clkr = {
1224	.enable_reg = 0x2a038,
1225	.enable_mask = BIT(0),
1226	.hw.init = &(const struct clk_init_data) {
1227	.name = "gcc_pcie2_axi_m_clk",
1228	.parent_hws = (const struct clk_hw *[]) {
1229	&pcie2_axi_m_clk_src.clkr.hw
1230	},
1231	.num_parents = 1,
1232	.flags = CLK_SET_RATE_PARENT,
1233	.ops = &clk_branch2_ops,
1234	},
1235	},
1236	};
1237
1238	static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
1239	.halt_reg = 0x2e080,
1240	.clkr = {
1241	.enable_reg = 0x2e080,
1242	.enable_mask = BIT(0),
1243	.hw.init = &(const struct clk_init_data) {
1244	.name = "gcc_anoc_pcie2_2lane_m_clk",
1245	.parent_hws = (const struct clk_hw *[]) {
1246	&pcie2_axi_m_clk_src.clkr.hw
1247	},
1248	.num_parents = 1,
1249	.flags = CLK_SET_RATE_PARENT,
1250	.ops = &clk_branch2_ops,
1251	},
1252	},
1253	};
1254
1255	static struct clk_rcg2 pcie3_axi_m_clk_src = {
1256	.cmd_rcgr = 0x2b018,
1257	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
1258	.hid_width = 5,
1259	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
1260	.clkr.hw.init = &(const struct clk_init_data) {
1261	.name = "pcie3_axi_m_clk_src",
1262	.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
1263	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
1264	.ops = &clk_rcg2_ops,
1265	},
1266	};
1267
1268	static struct clk_branch gcc_pcie3_axi_m_clk = {
1269	.halt_reg = 0x2b038,
1270	.clkr = {
1271	.enable_reg = 0x2b038,
1272	.enable_mask = BIT(0),
1273	.hw.init = &(const struct clk_init_data) {
1274	.name = "gcc_pcie3_axi_m_clk",
1275	.parent_hws = (const struct clk_hw *[]) {
1276	&pcie3_axi_m_clk_src.clkr.hw
1277	},
1278	.num_parents = 1,
1279	.flags = CLK_SET_RATE_PARENT,
1280	.ops = &clk_branch2_ops,
1281	},
1282	},
1283	};
1284
1285	static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
1286	.halt_reg = 0x2e090,
1287	.clkr = {
1288	.enable_reg = 0x2e090,
1289	.enable_mask = BIT(0),
1290	.hw.init = &(const struct clk_init_data) {
1291	.name = "gcc_anoc_pcie3_2lane_m_clk",
1292	.parent_hws = (const struct clk_hw *[]) {
1293	&pcie3_axi_m_clk_src.clkr.hw
1294	},
1295	.num_parents = 1,
1296	.flags = CLK_SET_RATE_PARENT,
1297	.ops = &clk_branch2_ops,
1298	},
1299	},
1300	};
1301
1302	static struct clk_rcg2 pcie0_axi_s_clk_src = {
1303	.cmd_rcgr = 0x28020,
1304	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1305	.hid_width = 5,
1306	.parent_map = gcc_xo_gpll0_gpll4_map,
1307	.clkr.hw.init = &(const struct clk_init_data) {
1308	.name = "pcie0_axi_s_clk_src",
1309	.parent_data = gcc_xo_gpll0_gpll4,
1310	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1311	.ops = &clk_rcg2_ops,
1312	},
1313	};
1314
1315	static struct clk_branch gcc_pcie0_axi_s_clk = {
1316	.halt_reg = 0x2803c,
1317	.clkr = {
1318	.enable_reg = 0x2803c,
1319	.enable_mask = BIT(0),
1320	.hw.init = &(const struct clk_init_data) {
1321	.name = "gcc_pcie0_axi_s_clk",
1322	.parent_hws = (const struct clk_hw *[]) {
1323	&pcie0_axi_s_clk_src.clkr.hw
1324	},
1325	.num_parents = 1,
1326	.flags = CLK_SET_RATE_PARENT,
1327	.ops = &clk_branch2_ops,
1328	},
1329	},
1330	};
1331
1332	static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
1333	.halt_reg = 0x28040,
1334	.clkr = {
1335	.enable_reg = 0x28040,
1336	.enable_mask = BIT(0),
1337	.hw.init = &(const struct clk_init_data) {
1338	.name = "gcc_pcie0_axi_s_bridge_clk",
1339	.parent_hws = (const struct clk_hw *[]) {
1340	&pcie0_axi_s_clk_src.clkr.hw
1341	},
1342	.num_parents = 1,
1343	.flags = CLK_SET_RATE_PARENT,
1344	.ops = &clk_branch2_ops,
1345	},
1346	},
1347	};
1348
1349	static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
1350	.halt_reg = 0x2e048,
1351	.clkr = {
1352	.enable_reg = 0x2e048,
1353	.enable_mask = BIT(0),
1354	.hw.init = &(const struct clk_init_data) {
1355	.name = "gcc_snoc_pcie0_1lane_s_clk",
1356	.parent_hws = (const struct clk_hw *[]) {
1357	&pcie0_axi_s_clk_src.clkr.hw
1358	},
1359	.num_parents = 1,
1360	.flags = CLK_SET_RATE_PARENT,
1361	.ops = &clk_branch2_ops,
1362	},
1363	},
1364	};
1365
1366	static struct clk_rcg2 pcie1_axi_s_clk_src = {
1367	.cmd_rcgr = 0x29020,
1368	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1369	.hid_width = 5,
1370	.parent_map = gcc_xo_gpll0_gpll4_map,
1371	.clkr.hw.init = &(const struct clk_init_data) {
1372	.name = "pcie1_axi_s_clk_src",
1373	.parent_data = gcc_xo_gpll0_gpll4,
1374	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1375	.ops = &clk_rcg2_ops,
1376	},
1377	};
1378
1379	static struct clk_branch gcc_pcie1_axi_s_clk = {
1380	.halt_reg = 0x2903c,
1381	.clkr = {
1382	.enable_reg = 0x2903c,
1383	.enable_mask = BIT(0),
1384	.hw.init = &(const struct clk_init_data) {
1385	.name = "gcc_pcie1_axi_s_clk",
1386	.parent_hws = (const struct clk_hw *[]) {
1387	&pcie1_axi_s_clk_src.clkr.hw
1388	},
1389	.num_parents = 1,
1390	.flags = CLK_SET_RATE_PARENT,
1391	.ops = &clk_branch2_ops,
1392	},
1393	},
1394	};
1395
1396	static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
1397	.halt_reg = 0x29040,
1398	.clkr = {
1399	.enable_reg = 0x29040,
1400	.enable_mask = BIT(0),
1401	.hw.init = &(const struct clk_init_data) {
1402	.name = "gcc_pcie1_axi_s_bridge_clk",
1403	.parent_hws = (const struct clk_hw *[]) {
1404	&pcie1_axi_s_clk_src.clkr.hw
1405	},
1406	.num_parents = 1,
1407	.flags = CLK_SET_RATE_PARENT,
1408	.ops = &clk_branch2_ops,
1409	},
1410	},
1411	};
1412
1413	static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
1414	.halt_reg = 0x2e04c,
1415	.clkr = {
1416	.enable_reg = 0x2e04c,
1417	.enable_mask = BIT(0),
1418	.hw.init = &(const struct clk_init_data) {
1419	.name = "gcc_snoc_pcie1_1lane_s_clk",
1420	.parent_hws = (const struct clk_hw *[]) {
1421	&pcie1_axi_s_clk_src.clkr.hw
1422	},
1423	.num_parents = 1,
1424	.flags = CLK_SET_RATE_PARENT,
1425	.ops = &clk_branch2_ops,
1426	},
1427	},
1428	};
1429
1430	static struct clk_rcg2 pcie2_axi_s_clk_src = {
1431	.cmd_rcgr = 0x2a020,
1432	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1433	.hid_width = 5,
1434	.parent_map = gcc_xo_gpll0_gpll4_map,
1435	.clkr.hw.init = &(const struct clk_init_data) {
1436	.name = "pcie2_axi_s_clk_src",
1437	.parent_data = gcc_xo_gpll0_gpll4,
1438	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1439	.ops = &clk_rcg2_ops,
1440	},
1441	};
1442
1443	static struct clk_branch gcc_pcie2_axi_s_clk = {
1444	.halt_reg = 0x2a03c,
1445	.clkr = {
1446	.enable_reg = 0x2a03c,
1447	.enable_mask = BIT(0),
1448	.hw.init = &(const struct clk_init_data) {
1449	.name = "gcc_pcie2_axi_s_clk",
1450	.parent_hws = (const struct clk_hw *[]) {
1451	&pcie2_axi_s_clk_src.clkr.hw
1452	},
1453	.num_parents = 1,
1454	.flags = CLK_SET_RATE_PARENT,
1455	.ops = &clk_branch2_ops,
1456	},
1457	},
1458	};
1459
1460	static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
1461	.halt_reg = 0x2a040,
1462	.clkr = {
1463	.enable_reg = 0x2a040,
1464	.enable_mask = BIT(0),
1465	.hw.init = &(const struct clk_init_data) {
1466	.name = "gcc_pcie2_axi_s_bridge_clk",
1467	.parent_hws = (const struct clk_hw *[]) {
1468	&pcie2_axi_s_clk_src.clkr.hw
1469	},
1470	.num_parents = 1,
1471	.flags = CLK_SET_RATE_PARENT,
1472	.ops = &clk_branch2_ops,
1473	},
1474	},
1475	};
1476
1477	static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
1478	.halt_reg = 0x2e050,
1479	.clkr = {
1480	.enable_reg = 0x2e050,
1481	.enable_mask = BIT(0),
1482	.hw.init = &(const struct clk_init_data) {
1483	.name = "gcc_snoc_pcie2_2lane_s_clk",
1484	.parent_hws = (const struct clk_hw *[]) {
1485	&pcie2_axi_s_clk_src.clkr.hw
1486	},
1487	.num_parents = 1,
1488	.flags = CLK_SET_RATE_PARENT,
1489	.ops = &clk_branch2_ops,
1490	},
1491	},
1492	};
1493
1494	static struct clk_rcg2 pcie3_axi_s_clk_src = {
1495	.cmd_rcgr = 0x2b020,
1496	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
1497	.hid_width = 5,
1498	.parent_map = gcc_xo_gpll0_gpll4_map,
1499	.clkr.hw.init = &(const struct clk_init_data) {
1500	.name = "pcie3_axi_s_clk_src",
1501	.parent_data = gcc_xo_gpll0_gpll4,
1502	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
1503	.ops = &clk_rcg2_ops,
1504	},
1505	};
1506
1507	static struct clk_branch gcc_pcie3_axi_s_clk = {
1508	.halt_reg = 0x2b03c,
1509	.clkr = {
1510	.enable_reg = 0x2b03c,
1511	.enable_mask = BIT(0),
1512	.hw.init = &(const struct clk_init_data) {
1513	.name = "gcc_pcie3_axi_s_clk",
1514	.parent_hws = (const struct clk_hw *[]) {
1515	&pcie3_axi_s_clk_src.clkr.hw
1516	},
1517	.num_parents = 1,
1518	.flags = CLK_SET_RATE_PARENT,
1519	.ops = &clk_branch2_ops,
1520	},
1521	},
1522	};
1523
1524	static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
1525	.halt_reg = 0x2b040,
1526	.clkr = {
1527	.enable_reg = 0x2b040,
1528	.enable_mask = BIT(0),
1529	.hw.init = &(const struct clk_init_data) {
1530	.name = "gcc_pcie3_axi_s_bridge_clk",
1531	.parent_hws = (const struct clk_hw *[]) {
1532	&pcie3_axi_s_clk_src.clkr.hw
1533	},
1534	.num_parents = 1,
1535	.flags = CLK_SET_RATE_PARENT,
1536	.ops = &clk_branch2_ops,
1537	},
1538	},
1539	};
1540
1541	static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
1542	.halt_reg = 0x2e054,
1543	.clkr = {
1544	.enable_reg = 0x2e054,
1545	.enable_mask = BIT(0),
1546	.hw.init = &(const struct clk_init_data) {
1547	.name = "gcc_snoc_pcie3_2lane_s_clk",
1548	.parent_hws = (const struct clk_hw *[]) {
1549	&pcie3_axi_s_clk_src.clkr.hw
1550	},
1551	.num_parents = 1,
1552	.flags = CLK_SET_RATE_PARENT,
1553	.ops = &clk_branch2_ops,
1554	},
1555	},
1556	};
1557
1558	static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
1559	.reg = 0x28064,
1560	.clkr = {
1561	.hw.init = &(const struct clk_init_data) {
1562	.name = "pcie0_pipe_clk_src",
1563	.parent_data = &(const struct clk_parent_data) {
1564	.index = DT_PCIE30_PHY0_PIPE_CLK,
1565	},
1566	.num_parents = 1,
1567	.ops = &clk_regmap_phy_mux_ops,
1568	},
1569	},
1570	};
1571
1572	static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
1573	.reg = 0x29064,
1574	.clkr = {
1575	.hw.init = &(const struct clk_init_data) {
1576	.name = "pcie1_pipe_clk_src",
1577	.parent_data = &(const struct clk_parent_data) {
1578	.index = DT_PCIE30_PHY1_PIPE_CLK,
1579	},
1580	.num_parents = 1,
1581	.ops = &clk_regmap_phy_mux_ops,
1582	},
1583	},
1584	};
1585
1586	static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {
1587	.reg = 0x2a064,
1588	.clkr = {
1589	.hw.init = &(const struct clk_init_data) {
1590	.name = "pcie2_pipe_clk_src",
1591	.parent_data = &(const struct clk_parent_data) {
1592	.index = DT_PCIE30_PHY2_PIPE_CLK,
1593	},
1594	.num_parents = 1,
1595	.ops = &clk_regmap_phy_mux_ops,
1596	},
1597	},
1598	};
1599
1600	static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {
1601	.reg = 0x2b064,
1602	.clkr = {
1603	.hw.init = &(const struct clk_init_data) {
1604	.name = "pcie3_pipe_clk_src",
1605	.parent_data = &(const struct clk_parent_data) {
1606	.index = DT_PCIE30_PHY3_PIPE_CLK,
1607	},
1608	.num_parents = 1,
1609	.ops = &clk_regmap_phy_mux_ops,
1610	},
1611	},
1612	};
1613
1614	static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
1615	F(24000000, P_XO, 1, 0, 0),
1616	F(100000000, P_GPLL0, 8, 0, 0),
1617	{ }
1618	};
1619
1620	static struct clk_rcg2 pcie0_rchng_clk_src = {
1621	.cmd_rcgr = 0x28028,
1622	.freq_tbl = ftbl_pcie_rchng_clk_src,
1623	.hid_width = 5,
1624	.parent_map = gcc_xo_gpll0_map,
1625	.clkr.hw.init = &(const struct clk_init_data) {
1626	.name = "pcie0_rchng_clk_src",
1627	.parent_data = gcc_xo_gpll0,
1628	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1629	.ops = &clk_rcg2_ops,
1630	},
1631	};
1632
1633	static struct clk_branch gcc_pcie0_rchng_clk = {
1634	.halt_reg = 0x28028,
1635	.clkr = {
1636	.enable_reg = 0x28028,
1637	.enable_mask = BIT(1),
1638	.hw.init = &(const struct clk_init_data) {
1639	.name = "gcc_pcie0_rchng_clk",
1640	.parent_hws = (const struct clk_hw *[]) {
1641	&pcie0_rchng_clk_src.clkr.hw
1642
1643	},
1644	.num_parents = 1,
1645	.flags = CLK_SET_RATE_PARENT,
1646	.ops = &clk_branch2_ops,
1647	},
1648	},
1649	};
1650
1651	static struct clk_rcg2 pcie1_rchng_clk_src = {
1652	.cmd_rcgr = 0x29028,
1653	.freq_tbl = ftbl_pcie_rchng_clk_src,
1654	.hid_width = 5,
1655	.parent_map = gcc_xo_gpll0_map,
1656	.clkr.hw.init = &(const struct clk_init_data) {
1657	.name = "pcie1_rchng_clk_src",
1658	.parent_data = gcc_xo_gpll0,
1659	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1660	.ops = &clk_rcg2_ops,
1661	},
1662	};
1663
1664	static struct clk_branch gcc_pcie1_rchng_clk = {
1665	.halt_reg = 0x29028,
1666	.clkr = {
1667	.enable_reg = 0x29028,
1668	.enable_mask = BIT(1),
1669	.hw.init = &(const struct clk_init_data) {
1670	.name = "gcc_pcie1_rchng_clk",
1671	.parent_hws = (const struct clk_hw *[]) {
1672	&pcie1_rchng_clk_src.clkr.hw
1673	},
1674	.num_parents = 1,
1675	.flags = CLK_SET_RATE_PARENT,
1676	.ops = &clk_branch2_ops,
1677	},
1678	},
1679	};
1680
1681	static struct clk_rcg2 pcie2_rchng_clk_src = {
1682	.cmd_rcgr = 0x2a028,
1683	.freq_tbl = ftbl_pcie_rchng_clk_src,
1684	.hid_width = 5,
1685	.parent_map = gcc_xo_gpll0_map,
1686	.clkr.hw.init = &(const struct clk_init_data) {
1687	.name = "pcie2_rchng_clk_src",
1688	.parent_data = gcc_xo_gpll0,
1689	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1690	.ops = &clk_rcg2_ops,
1691	},
1692	};
1693
1694	static struct clk_branch gcc_pcie2_rchng_clk = {
1695	.halt_reg = 0x2a028,
1696	.clkr = {
1697	.enable_reg = 0x2a028,
1698	.enable_mask = BIT(1),
1699	.hw.init = &(const struct clk_init_data) {
1700	.name = "gcc_pcie2_rchng_clk",
1701	.parent_hws = (const struct clk_hw *[]) {
1702	&pcie2_rchng_clk_src.clkr.hw
1703	},
1704	.num_parents = 1,
1705	.flags = CLK_SET_RATE_PARENT,
1706	.ops = &clk_branch2_ops,
1707	},
1708	},
1709	};
1710
1711	static struct clk_rcg2 pcie3_rchng_clk_src = {
1712	.cmd_rcgr = 0x2b028,
1713	.freq_tbl = ftbl_pcie_rchng_clk_src,
1714	.hid_width = 5,
1715	.parent_map = gcc_xo_gpll0_map,
1716	.clkr.hw.init = &(const struct clk_init_data) {
1717	.name = "pcie3_rchng_clk_src",
1718	.parent_data = gcc_xo_gpll0,
1719	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1720	.ops = &clk_rcg2_ops,
1721	},
1722	};
1723
1724	static struct clk_branch gcc_pcie3_rchng_clk = {
1725	.halt_reg = 0x2b028,
1726	.clkr = {
1727	.enable_reg = 0x2b028,
1728	.enable_mask = BIT(1),
1729	.hw.init = &(const struct clk_init_data) {
1730	.name = "gcc_pcie3_rchng_clk",
1731	.parent_hws = (const struct clk_hw *[]) {
1732	&pcie3_rchng_clk_src.clkr.hw
1733	},
1734	.num_parents = 1,
1735	.flags = CLK_SET_RATE_PARENT,
1736	.ops = &clk_branch2_ops,
1737	},
1738	},
1739	};
1740
1741	static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
1742	F(20000000, P_GPLL0, 10, 1, 4),
1743	{ }
1744	};
1745
1746	static struct clk_rcg2 pcie_aux_clk_src = {
1747	.cmd_rcgr = 0x28004,
1748	.freq_tbl = ftbl_pcie_aux_clk_src,
1749	.mnd_width = 16,
1750	.hid_width = 5,
1751	.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
1752	.clkr.hw.init = &(const struct clk_init_data) {
1753	.name = "pcie_aux_clk_src",
1754	.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
1755	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
1756	.ops = &clk_rcg2_ops,
1757	},
1758	};
1759
1760	static struct clk_branch gcc_pcie0_aux_clk = {
1761	.halt_reg = 0x28034,
1762	.clkr = {
1763	.enable_reg = 0x28034,
1764	.enable_mask = BIT(0),
1765	.hw.init = &(const struct clk_init_data) {
1766	.name = "gcc_pcie0_aux_clk",
1767	.parent_hws = (const struct clk_hw *[]) {
1768	&pcie_aux_clk_src.clkr.hw
1769	},
1770	.num_parents = 1,
1771	.flags = CLK_SET_RATE_PARENT,
1772	.ops = &clk_branch2_ops,
1773	},
1774	},
1775	};
1776
1777	static struct clk_branch gcc_pcie1_aux_clk = {
1778	.halt_reg = 0x29034,
1779	.clkr = {
1780	.enable_reg = 0x29034,
1781	.enable_mask = BIT(0),
1782	.hw.init = &(const struct clk_init_data) {
1783	.name = "gcc_pcie1_aux_clk",
1784	.parent_hws = (const struct clk_hw *[]) {
1785	&pcie_aux_clk_src.clkr.hw
1786	},
1787	.num_parents = 1,
1788	.flags = CLK_SET_RATE_PARENT,
1789	.ops = &clk_branch2_ops,
1790	},
1791	},
1792	};
1793
1794	static struct clk_branch gcc_pcie2_aux_clk = {
1795	.halt_reg = 0x2a034,
1796	.clkr = {
1797	.enable_reg = 0x2a034,
1798	.enable_mask = BIT(0),
1799	.hw.init = &(const struct clk_init_data) {
1800	.name = "gcc_pcie2_aux_clk",
1801	.parent_hws = (const struct clk_hw *[]) {
1802	&pcie_aux_clk_src.clkr.hw
1803	},
1804	.num_parents = 1,
1805	.flags = CLK_SET_RATE_PARENT,
1806	.ops = &clk_branch2_ops,
1807	},
1808	},
1809	};
1810
1811	static struct clk_branch gcc_pcie3_aux_clk = {
1812	.halt_reg = 0x2b034,
1813	.clkr = {
1814	.enable_reg = 0x2b034,
1815	.enable_mask = BIT(0),
1816	.hw.init = &(const struct clk_init_data) {
1817	.name = "gcc_pcie3_aux_clk",
1818	.parent_hws = (const struct clk_hw *[]) {
1819	&pcie_aux_clk_src.clkr.hw
1820	},
1821	.num_parents = 1,
1822	.flags = CLK_SET_RATE_PARENT,
1823	.ops = &clk_branch2_ops,
1824	},
1825	},
1826	};
1827
1828	static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1829	F(24000000, P_XO, 1, 0, 0),
1830	{ }
1831	};
1832
1833	static struct clk_rcg2 usb0_aux_clk_src = {
1834	.cmd_rcgr = 0x2c018,
1835	.freq_tbl = ftbl_usb_aux_clk_src,
1836	.mnd_width = 16,
1837	.hid_width = 5,
1838	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
1839	.clkr.hw.init = &(const struct clk_init_data) {
1840	.name = "usb0_aux_clk_src",
1841	.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
1842	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
1843	.ops = &clk_rcg2_ops,
1844	},
1845	};
1846
1847	static struct clk_branch gcc_usb0_aux_clk = {
1848	.halt_reg = 0x2c048,
1849	.clkr = {
1850	.enable_reg = 0x2c048,
1851	.enable_mask = BIT(0),
1852	.hw.init = &(const struct clk_init_data) {
1853	.name = "gcc_usb0_aux_clk",
1854	.parent_hws = (const struct clk_hw *[]) {
1855	&usb0_aux_clk_src.clkr.hw
1856	},
1857	.num_parents = 1,
1858	.flags = CLK_SET_RATE_PARENT,
1859	.ops = &clk_branch2_ops,
1860	},
1861	},
1862	};
1863
1864	static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
1865	F(100000000, P_GPLL0, 8, 0, 0),
1866	F(200000000, P_GPLL0, 4, 0, 0),
1867	{ }
1868	};
1869
1870	static struct clk_rcg2 usb0_master_clk_src = {
1871	.cmd_rcgr = 0x2c004,
1872	.freq_tbl = ftbl_usb0_master_clk_src,
1873	.mnd_width = 8,
1874	.hid_width = 5,
1875	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1876	.clkr.hw.init = &(const struct clk_init_data) {
1877	.name = "usb0_master_clk_src",
1878	.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
1879	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
1880	.ops = &clk_rcg2_ops,
1881	},
1882	};
1883
1884	static struct clk_branch gcc_usb0_master_clk = {
1885	.halt_reg = 0x2c044,
1886	.clkr = {
1887	.enable_reg = 0x2c044,
1888	.enable_mask = BIT(0),
1889	.hw.init = &(const struct clk_init_data) {
1890	.name = "gcc_usb0_master_clk",
1891	.parent_hws = (const struct clk_hw *[]) {
1892	&usb0_master_clk_src.clkr.hw
1893	},
1894	.num_parents = 1,
1895	.flags = CLK_SET_RATE_PARENT,
1896	.ops = &clk_branch2_ops,
1897	},
1898	},
1899	};
1900
1901	static struct clk_branch gcc_snoc_usb_clk = {
1902	.halt_reg = 0x2e058,
1903	.clkr = {
1904	.enable_reg = 0x2e058,
1905	.enable_mask = BIT(0),
1906	.hw.init = &(const struct clk_init_data) {
1907	.name = "gcc_snoc_usb_clk",
1908	.parent_hws = (const struct clk_hw *[]) {
1909	&usb0_master_clk_src.clkr.hw
1910	},
1911	.num_parents = 1,
1912	.flags = CLK_SET_RATE_PARENT,
1913	.ops = &clk_branch2_ops,
1914	},
1915	},
1916	};
1917
1918	static struct clk_branch gcc_anoc_usb_axi_clk = {
1919	.halt_reg = 0x2e084,
1920	.clkr = {
1921	.enable_reg = 0x2e084,
1922	.enable_mask = BIT(0),
1923	.hw.init = &(const struct clk_init_data) {
1924	.name = "gcc_anoc_usb_axi_clk",
1925	.parent_hws = (const struct clk_hw *[]) {
1926	&usb0_master_clk_src.clkr.hw
1927	},
1928	.num_parents = 1,
1929	.flags = CLK_SET_RATE_PARENT,
1930	.ops = &clk_branch2_ops,
1931	},
1932	},
1933	};
1934
1935	static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
1936	F(24000000, P_XO, 1, 0, 0),
1937	F(60000000, P_GPLL4, 10, 1, 2),
1938	{ }
1939	};
1940
1941	static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1942	.cmd_rcgr = 0x2c02c,
1943	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
1944	.mnd_width = 8,
1945	.hid_width = 5,
1946	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
1947	.clkr.hw.init = &(const struct clk_init_data) {
1948	.name = "usb0_mock_utmi_clk_src",
1949	.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
1950	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
1951	.ops = &clk_rcg2_ops,
1952	},
1953	};
1954
1955	static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
1956	.reg = 0x2c040,
1957	.shift = 0,
1958	.width = 2,
1959	.clkr.hw.init = &(const struct clk_init_data) {
1960	.name = "usb0_mock_utmi_div_clk_src",
1961	.parent_data = &(const struct clk_parent_data) {
1962	.hw = &usb0_mock_utmi_clk_src.clkr.hw,
1963	},
1964	.num_parents = 1,
1965	.flags = CLK_SET_RATE_PARENT,
1966	.ops = &clk_regmap_div_ro_ops,
1967	},
1968	};
1969
1970	static struct clk_branch gcc_usb0_mock_utmi_clk = {
1971	.halt_reg = 0x2c04c,
1972	.clkr = {
1973	.enable_reg = 0x2c04c,
1974	.enable_mask = BIT(0),
1975	.hw.init = &(const struct clk_init_data) {
1976	.name = "gcc_usb0_mock_utmi_clk",
1977	.parent_hws = (const struct clk_hw *[]) {
1978	&usb0_mock_utmi_div_clk_src.clkr.hw
1979	},
1980	.num_parents = 1,
1981	.flags = CLK_SET_RATE_PARENT,
1982	.ops = &clk_branch2_ops,
1983	},
1984	},
1985	};
1986
1987	static struct clk_regmap_mux usb0_pipe_clk_src = {
1988	.reg = 0x2C074,
1989	.shift = 8,
1990	.width = 2,
1991	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1992	.clkr = {
1993	.hw.init = &(const struct clk_init_data) {
1994	.name = "usb0_pipe_clk_src",
1995	.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
1996	.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
1997	.flags = CLK_SET_RATE_PARENT,
1998	.ops = &clk_regmap_mux_closest_ops,
1999	},
2000	},
2001	};
2002
2003	static struct clk_branch gcc_usb0_pipe_clk = {
2004	.halt_reg = 0x2c054,
2005	.halt_check = BRANCH_HALT_DELAY,
2006	.clkr = {
2007	.enable_reg = 0x2c054,
2008	.enable_mask = BIT(0),
2009	.hw.init = &(const struct clk_init_data){
2010	.name = "gcc_usb0_pipe_clk",
2011	.parent_hws = (const struct clk_hw *[]) {
2012	&usb0_pipe_clk_src.clkr.hw
2013	},
2014	.num_parents = 1,
2015	.flags = CLK_SET_RATE_PARENT,
2016	.ops = &clk_branch2_ops,
2017	},
2018	},
2019	};
2020
2021	static struct clk_branch gcc_usb0_sleep_clk = {
2022	.halt_reg = 0x2c058,
2023	.clkr = {
2024	.enable_reg = 0x2c058,
2025	.enable_mask = BIT(0),
2026	.hw.init = &(const struct clk_init_data){
2027	.name = "gcc_usb0_sleep_clk",
2028	.parent_hws = (const struct clk_hw *[]) {
2029	&gcc_sleep_clk_src.clkr.hw
2030	},
2031	.num_parents = 1,
2032	.flags = CLK_SET_RATE_PARENT,
2033	.ops = &clk_branch2_ops,
2034	},
2035	},
2036	};
2037
2038	static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
2039	F(144000, P_XO, 16, 12, 125),
2040	F(400000, P_XO, 12, 1, 5),
2041	F(24000000, P_GPLL2, 12, 1, 4),
2042	F(48000000, P_GPLL2, 12, 1, 2),
2043	F(96000000, P_GPLL2, 12, 0, 0),
2044	F(177777778, P_GPLL0, 4.5, 0, 0),
2045	F(192000000, P_GPLL2, 6, 0, 0),
2046	F(384000000, P_GPLL2, 3, 0, 0),
2047	F(400000000, P_GPLL0, 2, 0, 0),
2048	{ }
2049	};
2050
2051	static struct clk_rcg2 sdcc1_apps_clk_src = {
2052	.cmd_rcgr = 0x33004,
2053	.freq_tbl = ftbl_sdcc_apps_clk_src,
2054	.mnd_width = 8,
2055	.hid_width = 5,
2056	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
2057	.clkr.hw.init = &(const struct clk_init_data) {
2058	.name = "sdcc1_apps_clk_src",
2059	.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
2060	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
2061	.ops = &clk_rcg2_floor_ops,
2062	},
2063	};
2064
2065	static struct clk_branch gcc_sdcc1_apps_clk = {
2066	.halt_reg = 0x3302c,
2067	.clkr = {
2068	.enable_reg = 0x3302c,
2069	.enable_mask = BIT(0),
2070	.hw.init = &(const struct clk_init_data) {
2071	.name = "gcc_sdcc1_apps_clk",
2072	.parent_hws = (const struct clk_hw *[]) {
2073	&sdcc1_apps_clk_src.clkr.hw
2074	},
2075	.num_parents = 1,
2076	.flags = CLK_SET_RATE_PARENT,
2077	.ops = &clk_branch2_ops,
2078	},
2079	},
2080	};
2081
2082	static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
2083	F(150000000, P_GPLL4, 8, 0, 0),
2084	F(300000000, P_GPLL4, 4, 0, 0),
2085	{ }
2086	};
2087
2088	static struct clk_rcg2 sdcc1_ice_core_clk_src = {
2089	.cmd_rcgr = 0x33018,
2090	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
2091	.mnd_width = 8,
2092	.hid_width = 5,
2093	.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
2094	.clkr.hw.init = &(const struct clk_init_data) {
2095	.name = "sdcc1_ice_core_clk_src",
2096	.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
2097	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
2098	.ops = &clk_rcg2_ops,
2099	},
2100	};
2101
2102	static struct clk_branch gcc_sdcc1_ice_core_clk = {
2103	.halt_reg = 0x33030,
2104	.clkr = {
2105	.enable_reg = 0x33030,
2106	.enable_mask = BIT(0),
2107	.hw.init = &(const struct clk_init_data) {
2108	.name = "gcc_sdcc1_ice_core_clk",
2109	.parent_hws = (const struct clk_hw *[]) {
2110	&sdcc1_ice_core_clk_src.clkr.hw
2111	},
2112	.num_parents = 1,
2113	.flags = CLK_SET_RATE_PARENT,
2114	.ops = &clk_branch2_ops,
2115	},
2116	},
2117	};
2118
2119	static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
2120	F(24000000, P_XO, 1, 0, 0),
2121	F(50000000, P_GPLL0, 16, 0, 0),
2122	F(80000000, P_GPLL0, 10, 0, 0),
2123	F(100000000, P_GPLL0, 8, 0, 0),
2124	{ }
2125	};
2126
2127	static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
2128	.cmd_rcgr = 0x31004,
2129	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
2130	.hid_width = 5,
2131	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2132	.clkr.hw.init = &(const struct clk_init_data) {
2133	.name = "pcnoc_bfdcd_clk_src",
2134	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2135	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2136	.flags = CLK_IS_CRITICAL,
2137	.ops = &clk_rcg2_ops,
2138	},
2139	};
2140
2141	static struct clk_branch gcc_crypto_axi_clk = {
2142	.halt_reg = 0x16010,
2143	.clkr = {
2144	.enable_reg = 0x16010,
2145	.enable_mask = BIT(0),
2146	.hw.init = &(const struct clk_init_data) {
2147	.name = "gcc_crypto_axi_clk",
2148	.parent_hws = (const struct clk_hw *[]) {
2149	&pcnoc_bfdcd_clk_src.clkr.hw },
2150	.num_parents = 1,
2151	.flags = CLK_SET_RATE_PARENT,
2152	.ops = &clk_branch2_ops,
2153	},
2154	},
2155	};
2156
2157	static struct clk_branch gcc_crypto_ahb_clk = {
2158	.halt_reg = 0x16014,
2159	.clkr = {
2160	.enable_reg = 0x16014,
2161	.enable_mask = BIT(0),
2162	.hw.init = &(const struct clk_init_data) {
2163	.name = "gcc_crypto_ahb_clk",
2164	.parent_hws = (const struct clk_hw *[]) {
2165	&pcnoc_bfdcd_clk_src.clkr.hw },
2166	.num_parents = 1,
2167	.flags = CLK_SET_RATE_PARENT,
2168	.ops = &clk_branch2_ops,
2169	},
2170	},
2171	};
2172
2173	static struct clk_branch gcc_nsscfg_clk = {
2174	.halt_reg = 0x1702c,
2175	.clkr = {
2176	.enable_reg = 0x1702c,
2177	.enable_mask = BIT(0),
2178	.hw.init = &(const struct clk_init_data) {
2179	.name = "gcc_nsscfg_clk",
2180	.parent_hws = (const struct clk_hw *[]) {
2181	&pcnoc_bfdcd_clk_src.clkr.hw
2182	},
2183	.num_parents = 1,
2184	.flags = CLK_SET_RATE_PARENT,
2185	.ops = &clk_branch2_ops,
2186	},
2187	},
2188	};
2189
2190	static struct clk_branch gcc_nssnoc_nsscc_clk = {
2191	.halt_reg = 0x17030,
2192	.clkr = {
2193	.enable_reg = 0x17030,
2194	.enable_mask = BIT(0),
2195	.hw.init = &(const struct clk_init_data) {
2196	.name = "gcc_nssnoc_nsscc_clk",
2197	.parent_hws = (const struct clk_hw *[]) {
2198	&pcnoc_bfdcd_clk_src.clkr.hw
2199	},
2200	.num_parents = 1,
2201	.flags = CLK_SET_RATE_PARENT,
2202	.ops = &clk_branch2_ops,
2203	},
2204	},
2205	};
2206
2207	static struct clk_branch gcc_nsscc_clk = {
2208	.halt_reg = 0x17034,
2209	.clkr = {
2210	.enable_reg = 0x17034,
2211	.enable_mask = BIT(0),
2212	.hw.init = &(const struct clk_init_data) {
2213	.name = "gcc_nsscc_clk",
2214	.parent_hws = (const struct clk_hw *[]) {
2215	&pcnoc_bfdcd_clk_src.clkr.hw
2216	},
2217	.num_parents = 1,
2218	.flags = CLK_SET_RATE_PARENT,
2219	.ops = &clk_branch2_ops,
2220	},
2221	},
2222	};
2223
2224	static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
2225	.halt_reg = 0x17080,
2226	.clkr = {
2227	.enable_reg = 0x17080,
2228	.enable_mask = BIT(0),
2229	.hw.init = &(const struct clk_init_data) {
2230	.name = "gcc_nssnoc_pcnoc_1_clk",
2231	.parent_hws = (const struct clk_hw *[]) {
2232	&pcnoc_bfdcd_clk_src.clkr.hw
2233	},
2234	.num_parents = 1,
2235	.flags = CLK_SET_RATE_PARENT,
2236	.ops = &clk_branch2_ops,
2237	},
2238	},
2239	};
2240
2241	static struct clk_branch gcc_qdss_dap_ahb_clk = {
2242	.halt_reg = 0x2d064,
2243	.clkr = {
2244	.enable_reg = 0x2d064,
2245	.enable_mask = BIT(0),
2246	.hw.init = &(const struct clk_init_data) {
2247	.name = "gcc_qdss_dap_ahb_clk",
2248	.parent_hws = (const struct clk_hw *[]) {
2249	&pcnoc_bfdcd_clk_src.clkr.hw
2250	},
2251	.num_parents = 1,
2252	.flags = CLK_SET_RATE_PARENT,
2253	.ops = &clk_branch2_ops,
2254	},
2255	},
2256	};
2257
2258	static struct clk_branch gcc_qdss_cfg_ahb_clk = {
2259	.halt_reg = 0x2d068,
2260	.clkr = {
2261	.enable_reg = 0x2d068,
2262	.enable_mask = BIT(0),
2263	.hw.init = &(const struct clk_init_data) {
2264	.name = "gcc_qdss_cfg_ahb_clk",
2265	.parent_hws = (const struct clk_hw *[]) {
2266	&pcnoc_bfdcd_clk_src.clkr.hw
2267	},
2268	.num_parents = 1,
2269	.flags = CLK_SET_RATE_PARENT,
2270	.ops = &clk_branch2_ops,
2271	},
2272	},
2273	};
2274
2275	static struct clk_branch gcc_qpic_ahb_clk = {
2276	.halt_reg = 0x32010,
2277	.clkr = {
2278	.enable_reg = 0x32010,
2279	.enable_mask = BIT(0),
2280	.hw.init = &(const struct clk_init_data) {
2281	.name = "gcc_qpic_ahb_clk",
2282	.parent_hws = (const struct clk_hw *[]) {
2283	&pcnoc_bfdcd_clk_src.clkr.hw
2284	},
2285	.num_parents = 1,
2286	.flags = CLK_SET_RATE_PARENT,
2287	.ops = &clk_branch2_ops,
2288	},
2289	},
2290	};
2291
2292	static struct clk_branch gcc_qpic_clk = {
2293	.halt_reg = 0x32014,
2294	.clkr = {
2295	.enable_reg = 0x32014,
2296	.enable_mask = BIT(0),
2297	.hw.init = &(const struct clk_init_data) {
2298	.name = "gcc_qpic_clk",
2299	.parent_hws = (const struct clk_hw *[]) {
2300	&pcnoc_bfdcd_clk_src.clkr.hw
2301	},
2302	.num_parents = 1,
2303	.flags = CLK_SET_RATE_PARENT,
2304	.ops = &clk_branch2_ops,
2305	},
2306	},
2307	};
2308
2309	static struct clk_branch gcc_blsp1_ahb_clk = {
2310	.halt_reg = 0x01004,
2311	.halt_check = BRANCH_HALT_VOTED,
2312	.clkr = {
2313	.enable_reg = 0x0b004,
2314	.enable_mask = BIT(4),
2315	.hw.init = &(const struct clk_init_data) {
2316	.name = "gcc_blsp1_ahb_clk",
2317	.parent_hws = (const struct clk_hw *[]) {
2318	&pcnoc_bfdcd_clk_src.clkr.hw
2319	},
2320	.num_parents = 1,
2321	.flags = CLK_SET_RATE_PARENT,
2322	.ops = &clk_branch2_ops,
2323	},
2324	},
2325	};
2326
2327	static struct clk_branch gcc_mdio_ahb_clk = {
2328	.halt_reg = 0x17040,
2329	.clkr = {
2330	.enable_reg = 0x17040,
2331	.enable_mask = BIT(0),
2332	.hw.init = &(const struct clk_init_data) {
2333	.name = "gcc_mdio_ahb_clk",
2334	.parent_hws = (const struct clk_hw *[]) {
2335	&pcnoc_bfdcd_clk_src.clkr.hw
2336	},
2337	.num_parents = 1,
2338	.flags = CLK_SET_RATE_PARENT,
2339	.ops = &clk_branch2_ops,
2340	},
2341	},
2342	};
2343
2344	static struct clk_branch gcc_prng_ahb_clk = {
2345	.halt_reg = 0x13024,
2346	.halt_check = BRANCH_HALT_VOTED,
2347	.clkr = {
2348	.enable_reg = 0x0b004,
2349	.enable_mask = BIT(10),
2350	.hw.init = &(const struct clk_init_data) {
2351	.name = "gcc_prng_ahb_clk",
2352	.parent_hws = (const struct clk_hw *[]) {
2353	&pcnoc_bfdcd_clk_src.clkr.hw
2354	},
2355	.num_parents = 1,
2356	.flags = CLK_SET_RATE_PARENT,
2357	.ops = &clk_branch2_ops,
2358	},
2359	},
2360	};
2361
2362	static struct clk_branch gcc_uniphy0_ahb_clk = {
2363	.halt_reg = 0x1704c,
2364	.clkr = {
2365	.enable_reg = 0x1704c,
2366	.enable_mask = BIT(0),
2367	.hw.init = &(const struct clk_init_data) {
2368	.name = "gcc_uniphy0_ahb_clk",
2369	.parent_hws = (const struct clk_hw *[]) {
2370	&pcnoc_bfdcd_clk_src.clkr.hw
2371	},
2372	.num_parents = 1,
2373	.flags = CLK_SET_RATE_PARENT,
2374	.ops = &clk_branch2_ops,
2375	},
2376	},
2377	};
2378
2379	static struct clk_branch gcc_uniphy1_ahb_clk = {
2380	.halt_reg = 0x1705c,
2381	.clkr = {
2382	.enable_reg = 0x1705c,
2383	.enable_mask = BIT(0),
2384	.hw.init = &(const struct clk_init_data) {
2385	.name = "gcc_uniphy1_ahb_clk",
2386	.parent_hws = (const struct clk_hw *[]) {
2387	&pcnoc_bfdcd_clk_src.clkr.hw
2388	},
2389	.num_parents = 1,
2390	.flags = CLK_SET_RATE_PARENT,
2391	.ops = &clk_branch2_ops,
2392	},
2393	},
2394	};
2395
2396	static struct clk_branch gcc_uniphy2_ahb_clk = {
2397	.halt_reg = 0x1706c,
2398	.clkr = {
2399	.enable_reg = 0x1706c,
2400	.enable_mask = BIT(0),
2401	.hw.init = &(const struct clk_init_data) {
2402	.name = "gcc_uniphy2_ahb_clk",
2403	.parent_hws = (const struct clk_hw *[]) {
2404	&pcnoc_bfdcd_clk_src.clkr.hw
2405	},
2406	.num_parents = 1,
2407	.flags = CLK_SET_RATE_PARENT,
2408	.ops = &clk_branch2_ops,
2409	},
2410	},
2411	};
2412
2413	static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
2414	.halt_reg = 0x3a004,
2415	.clkr = {
2416	.enable_reg = 0x3a004,
2417	.enable_mask = BIT(0),
2418	.hw.init = &(const struct clk_init_data) {
2419	.name = "gcc_cmn_12gpll_ahb_clk",
2420	.parent_hws = (const struct clk_hw *[]) {
2421	&pcnoc_bfdcd_clk_src.clkr.hw
2422	},
2423	.num_parents = 1,
2424	.flags = CLK_SET_RATE_PARENT,
2425	.ops = &clk_branch2_ops,
2426	},
2427	},
2428	};
2429
2430	static struct clk_branch gcc_cmn_12gpll_apu_clk = {
2431	.halt_reg = 0x3a00c,
2432	.clkr = {
2433	.enable_reg = 0x3a00c,
2434	.enable_mask = BIT(0),
2435	.hw.init = &(const struct clk_init_data) {
2436	.name = "gcc_cmn_12gpll_apu_clk",
2437	.parent_hws = (const struct clk_hw *[]) {
2438	&pcnoc_bfdcd_clk_src.clkr.hw
2439	},
2440	.num_parents = 1,
2441	.flags = CLK_SET_RATE_PARENT,
2442	.ops = &clk_branch2_ops,
2443	},
2444	},
2445	};
2446
2447	static struct clk_branch gcc_pcie0_ahb_clk = {
2448	.halt_reg = 0x28030,
2449	.clkr = {
2450	.enable_reg = 0x28030,
2451	.enable_mask = BIT(0),
2452	.hw.init = &(const struct clk_init_data) {
2453	.name = "gcc_pcie0_ahb_clk",
2454	.parent_hws = (const struct clk_hw *[]) {
2455	&pcnoc_bfdcd_clk_src.clkr.hw
2456	},
2457	.num_parents = 1,
2458	.flags = CLK_SET_RATE_PARENT,
2459	.ops = &clk_branch2_ops,
2460	},
2461	},
2462	};
2463
2464	static struct clk_branch gcc_pcie1_ahb_clk = {
2465	.halt_reg = 0x29030,
2466	.clkr = {
2467	.enable_reg = 0x29030,
2468	.enable_mask = BIT(0),
2469	.hw.init = &(const struct clk_init_data) {
2470	.name = "gcc_pcie1_ahb_clk",
2471	.parent_hws = (const struct clk_hw *[]) {
2472	&pcnoc_bfdcd_clk_src.clkr.hw
2473	},
2474	.num_parents = 1,
2475	.flags = CLK_SET_RATE_PARENT,
2476	.ops = &clk_branch2_ops,
2477	},
2478	},
2479	};
2480
2481	static struct clk_branch gcc_pcie2_ahb_clk = {
2482	.halt_reg = 0x2a030,
2483	.clkr = {
2484	.enable_reg = 0x2a030,
2485	.enable_mask = BIT(0),
2486	.hw.init = &(const struct clk_init_data) {
2487	.name = "gcc_pcie2_ahb_clk",
2488	.parent_hws = (const struct clk_hw *[]) {
2489	&pcnoc_bfdcd_clk_src.clkr.hw
2490	},
2491	.num_parents = 1,
2492	.flags = CLK_SET_RATE_PARENT,
2493	.ops = &clk_branch2_ops,
2494	},
2495	},
2496	};
2497
2498	static struct clk_branch gcc_pcie3_ahb_clk = {
2499	.halt_reg = 0x2b030,
2500	.clkr = {
2501	.enable_reg = 0x2b030,
2502	.enable_mask = BIT(0),
2503	.hw.init = &(const struct clk_init_data) {
2504	.name = "gcc_pcie3_ahb_clk",
2505	.parent_hws = (const struct clk_hw *[]) {
2506	&pcnoc_bfdcd_clk_src.clkr.hw
2507	},
2508	.num_parents = 1,
2509	.flags = CLK_SET_RATE_PARENT,
2510	.ops = &clk_branch2_ops,
2511	},
2512	},
2513	};
2514
2515	static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2516	.halt_reg = 0x2c05c,
2517	.clkr = {
2518	.enable_reg = 0x2c05c,
2519	.enable_mask = BIT(0),
2520	.hw.init = &(const struct clk_init_data) {
2521	.name = "gcc_usb0_phy_cfg_ahb_clk",
2522	.parent_hws = (const struct clk_hw *[]) {
2523	&pcnoc_bfdcd_clk_src.clkr.hw
2524	},
2525	.num_parents = 1,
2526	.flags = CLK_SET_RATE_PARENT,
2527	.ops = &clk_branch2_ops,
2528	},
2529	},
2530	};
2531
2532	static struct clk_branch gcc_sdcc1_ahb_clk = {
2533	.halt_reg = 0x33034,
2534	.clkr = {
2535	.enable_reg = 0x33034,
2536	.enable_mask = BIT(0),
2537	.hw.init = &(const struct clk_init_data) {
2538	.name = "gcc_sdcc1_ahb_clk",
2539	.parent_hws = (const struct clk_hw *[]) {
2540	&pcnoc_bfdcd_clk_src.clkr.hw
2541	},
2542	.num_parents = 1,
2543	.flags = CLK_SET_RATE_PARENT,
2544	.ops = &clk_branch2_ops,
2545	},
2546	},
2547	};
2548
2549	static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
2550	F(24000000, P_XO, 1, 0, 0),
2551	F(133333333, P_GPLL0, 6, 0, 0),
2552	F(200000000, P_GPLL0, 4, 0, 0),
2553	F(342850000, P_GPLL4, 3.5, 0, 0),
2554	{ }
2555	};
2556
2557	static struct clk_rcg2 system_noc_bfdcd_clk_src = {
2558	.cmd_rcgr = 0x2e004,
2559	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
2560	.hid_width = 5,
2561	.parent_map = gcc_xo_gpll0_gpll4_map,
2562	.clkr.hw.init = &(const struct clk_init_data) {
2563	.name = "system_noc_bfdcd_clk_src",
2564	.parent_data = gcc_xo_gpll0_gpll4,
2565	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
2566	.flags = CLK_IS_CRITICAL,
2567	.ops = &clk_rcg2_ops,
2568	},
2569	};
2570
2571	static struct clk_branch gcc_q6ss_boot_clk = {
2572	.halt_reg = 0x25080,
2573	.halt_check = BRANCH_HALT_SKIP,
2574	.clkr = {
2575	.enable_reg = 0x25080,
2576	.enable_mask = BIT(0),
2577	.hw.init = &(const struct clk_init_data) {
2578	.name = "gcc_q6ss_boot_clk",
2579	.parent_hws = (const struct clk_hw *[]) {
2580	&system_noc_bfdcd_clk_src.clkr.hw
2581	},
2582	.num_parents = 1,
2583	.flags = CLK_SET_RATE_PARENT,
2584	.ops = &clk_branch2_ops,
2585	},
2586	},
2587	};
2588
2589	static struct clk_branch gcc_nssnoc_snoc_clk = {
2590	.halt_reg = 0x17028,
2591	.clkr = {
2592	.enable_reg = 0x17028,
2593	.enable_mask = BIT(0),
2594	.hw.init = &(const struct clk_init_data) {
2595	.name = "gcc_nssnoc_snoc_clk",
2596	.parent_hws = (const struct clk_hw *[]) {
2597	&system_noc_bfdcd_clk_src.clkr.hw
2598	},
2599	.num_parents = 1,
2600	.flags = CLK_SET_RATE_PARENT,
2601	.ops = &clk_branch2_ops,
2602	},
2603	},
2604	};
2605
2606	static struct clk_branch gcc_nssnoc_snoc_1_clk = {
2607	.halt_reg = 0x1707c,
2608	.clkr = {
2609	.enable_reg = 0x1707c,
2610	.enable_mask = BIT(0),
2611	.hw.init = &(const struct clk_init_data) {
2612	.name = "gcc_nssnoc_snoc_1_clk",
2613	.parent_hws = (const struct clk_hw *[]) {
2614	&system_noc_bfdcd_clk_src.clkr.hw
2615	},
2616	.num_parents = 1,
2617	.flags = CLK_SET_RATE_PARENT,
2618	.ops = &clk_branch2_ops,
2619	},
2620	},
2621	};
2622
2623	static struct clk_branch gcc_qdss_etr_usb_clk = {
2624	.halt_reg = 0x2d060,
2625	.clkr = {
2626	.enable_reg = 0x2d060,
2627	.enable_mask = BIT(0),
2628	.hw.init = &(const struct clk_init_data) {
2629	.name = "gcc_qdss_etr_usb_clk",
2630	.parent_hws = (const struct clk_hw *[]) {
2631	&system_noc_bfdcd_clk_src.clkr.hw
2632	},
2633	.num_parents = 1,
2634	.flags = CLK_SET_RATE_PARENT,
2635	.ops = &clk_branch2_ops,
2636	},
2637	},
2638	};
2639
2640	static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
2641	F(24000000, P_XO, 1, 0, 0),
2642	F(133333333, P_GPLL0, 6, 0, 0),
2643	{ }
2644	};
2645
2646	static struct clk_rcg2 wcss_ahb_clk_src = {
2647	.cmd_rcgr = 0x25030,
2648	.freq_tbl = ftbl_wcss_ahb_clk_src,
2649	.hid_width = 5,
2650	.parent_map = gcc_xo_gpll0_map,
2651	.clkr.hw.init = &(const struct clk_init_data) {
2652	.name = "wcss_ahb_clk_src",
2653	.parent_data = gcc_xo_gpll0,
2654	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2655	.ops = &clk_rcg2_ops,
2656	},
2657	};
2658
2659	static struct clk_branch gcc_q6_ahb_clk = {
2660	.halt_reg = 0x25014,
2661	.clkr = {
2662	.enable_reg = 0x25014,
2663	.enable_mask = BIT(0),
2664	.hw.init = &(const struct clk_init_data) {
2665	.name = "gcc_q6_ahb_clk",
2666	.parent_hws = (const struct clk_hw *[]) {
2667	&wcss_ahb_clk_src.clkr.hw
2668	},
2669	.num_parents = 1,
2670	.flags = CLK_SET_RATE_PARENT,
2671	.ops = &clk_branch2_ops,
2672	},
2673	},
2674	};
2675
2676	static struct clk_branch gcc_q6_ahb_s_clk = {
2677	.halt_reg = 0x25018,
2678	.clkr = {
2679	.enable_reg = 0x25018,
2680	.enable_mask = BIT(0),
2681	.hw.init = &(const struct clk_init_data) {
2682	.name = "gcc_q6_ahb_s_clk",
2683	.parent_hws = (const struct clk_hw *[]) {
2684	&wcss_ahb_clk_src.clkr.hw
2685	},
2686	.num_parents = 1,
2687	.flags = CLK_SET_RATE_PARENT,
2688	.ops = &clk_branch2_ops,
2689	},
2690	},
2691	};
2692
2693	static struct clk_branch gcc_wcss_ecahb_clk = {
2694	.halt_reg = 0x25058,
2695	.clkr = {
2696	.enable_reg = 0x25058,
2697	.enable_mask = BIT(0),
2698	.hw.init = &(const struct clk_init_data) {
2699	.name = "gcc_wcss_ecahb_clk",
2700	.parent_hws = (const struct clk_hw *[]) {
2701	&wcss_ahb_clk_src.clkr.hw
2702	},
2703	.num_parents = 1,
2704	.flags = CLK_SET_RATE_PARENT,
2705	.ops = &clk_branch2_ops,
2706	},
2707	},
2708	};
2709
2710	static struct clk_branch gcc_wcss_acmt_clk = {
2711	.halt_reg = 0x2505c,
2712	.clkr = {
2713	.enable_reg = 0x2505c,
2714	.enable_mask = BIT(0),
2715	.hw.init = &(const struct clk_init_data) {
2716	.name = "gcc_wcss_acmt_clk",
2717	.parent_hws = (const struct clk_hw *[]) {
2718	&wcss_ahb_clk_src.clkr.hw
2719	},
2720	.num_parents = 1,
2721	.flags = CLK_SET_RATE_PARENT,
2722	.ops = &clk_branch2_ops,
2723	},
2724	},
2725	};
2726
2727	static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
2728	.halt_reg = 0x2e030,
2729	.clkr = {
2730	.enable_reg = 0x2e030,
2731	.enable_mask = BIT(0),
2732	.hw.init = &(const struct clk_init_data) {
2733	.name = "gcc_sys_noc_wcss_ahb_clk",
2734	.parent_hws = (const struct clk_hw *[]) {
2735	&wcss_ahb_clk_src.clkr.hw
2736	},
2737	.num_parents = 1,
2738	.flags = CLK_SET_RATE_PARENT,
2739	.ops = &clk_branch2_ops,
2740	},
2741	},
2742	};
2743
2744	static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
2745	F(24000000, P_XO, 1, 0, 0),
2746	F(133333333, P_GPLL0, 6, 0, 0),
2747	F(266666667, P_GPLL0, 3, 0, 0),
2748	{ }
2749	};
2750
2751	static struct clk_rcg2 wcss_axi_m_clk_src = {
2752	.cmd_rcgr = 0x25078,
2753	.freq_tbl = ftbl_wcss_axi_m_clk_src,
2754	.hid_width = 5,
2755	.parent_map = gcc_xo_gpll0_map,
2756	.clkr.hw.init = &(const struct clk_init_data) {
2757	.name = "wcss_axi_m_clk_src",
2758	.parent_data = gcc_xo_gpll0,
2759	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
2760	.ops = &clk_rcg2_ops,
2761	},
2762	};
2763
2764	static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
2765	.halt_reg = 0x2e0a8,
2766	.clkr = {
2767	.enable_reg = 0x2e0a8,
2768	.enable_mask = BIT(0),
2769	.hw.init = &(const struct clk_init_data) {
2770	.name = "gcc_anoc_wcss_axi_m_clk",
2771	.parent_hws = (const struct clk_hw *[]) {
2772	&wcss_axi_m_clk_src.clkr.hw
2773	},
2774	.num_parents = 1,
2775	.flags = CLK_SET_RATE_PARENT,
2776	.ops = &clk_branch2_ops,
2777	},
2778	},
2779	};
2780
2781	static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
2782	F(240000000, P_GPLL4, 5, 0, 0),
2783	{ }
2784	};
2785
2786	static struct clk_rcg2 qdss_at_clk_src = {
2787	.cmd_rcgr = 0x2d004,
2788	.freq_tbl = ftbl_qdss_at_clk_src,
2789	.hid_width = 5,
2790	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
2791	.clkr.hw.init = &(const struct clk_init_data) {
2792	.name = "qdss_at_clk_src",
2793	.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
2794	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
2795	.ops = &clk_rcg2_ops,
2796	},
2797	};
2798
2799	static struct clk_branch gcc_q6ss_atbm_clk = {
2800	.halt_reg = 0x2501c,
2801	.clkr = {
2802	.enable_reg = 0x2501c,
2803	.enable_mask = BIT(0),
2804	.hw.init = &(const struct clk_init_data) {
2805	.name = "gcc_q6ss_atbm_clk",
2806	.parent_hws = (const struct clk_hw *[]) {
2807	&qdss_at_clk_src.clkr.hw
2808	},
2809	.num_parents = 1,
2810	.flags = CLK_SET_RATE_PARENT,
2811	.ops = &clk_branch2_ops,
2812	},
2813	},
2814	};
2815
2816	static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
2817	.halt_reg = 0x2503c,
2818	.clkr = {
2819	.enable_reg = 0x2503c,
2820	.enable_mask = BIT(0),
2821	.hw.init = &(const struct clk_init_data) {
2822	.name = "gcc_wcss_dbg_ifc_atb_clk",
2823	.parent_hws = (const struct clk_hw *[]) {
2824	&qdss_at_clk_src.clkr.hw
2825	},
2826	.num_parents = 1,
2827	.flags = CLK_SET_RATE_PARENT,
2828	.ops = &clk_branch2_ops,
2829	},
2830	},
2831	};
2832
2833	static struct clk_branch gcc_nssnoc_atb_clk = {
2834	.halt_reg = 0x17014,
2835	.clkr = {
2836	.enable_reg = 0x17014,
2837	.enable_mask = BIT(0),
2838	.hw.init = &(const struct clk_init_data) {
2839	.name = "gcc_nssnoc_atb_clk",
2840	.parent_hws = (const struct clk_hw *[]) {
2841	&qdss_at_clk_src.clkr.hw
2842	},
2843	.num_parents = 1,
2844	.flags = CLK_SET_RATE_PARENT,
2845	.ops = &clk_branch2_ops,
2846	},
2847	},
2848	};
2849
2850	static struct clk_branch gcc_qdss_at_clk = {
2851	.halt_reg = 0x2d038,
2852	.clkr = {
2853	.enable_reg = 0x2d038,
2854	.enable_mask = BIT(0),
2855	.hw.init = &(const struct clk_init_data) {
2856	.name = "gcc_qdss_at_clk",
2857	.parent_hws = (const struct clk_hw *[]) {
2858	&qdss_at_clk_src.clkr.hw
2859	},
2860	.num_parents = 1,
2861	.flags = CLK_SET_RATE_PARENT,
2862	.ops = &clk_branch2_ops,
2863	},
2864	},
2865	};
2866
2867	static struct clk_branch gcc_sys_noc_at_clk = {
2868	.halt_reg = 0x2e038,
2869	.clkr = {
2870	.enable_reg = 0x2e038,
2871	.enable_mask = BIT(0),
2872	.hw.init = &(const struct clk_init_data) {
2873	.name = "gcc_sys_noc_at_clk",
2874	.parent_hws = (const struct clk_hw *[]) {
2875	&qdss_at_clk_src.clkr.hw
2876	},
2877	.num_parents = 1,
2878	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2879	.ops = &clk_branch2_ops,
2880	},
2881	},
2882	};
2883
2884	static struct clk_branch gcc_pcnoc_at_clk = {
2885	.halt_reg = 0x31024,
2886	.clkr = {
2887	.enable_reg = 0x31024,
2888	.enable_mask = BIT(0),
2889	.hw.init = &(const struct clk_init_data) {
2890	.name = "gcc_pcnoc_at_clk",
2891	.parent_hws = (const struct clk_hw *[]) {
2892	&qdss_at_clk_src.clkr.hw
2893	},
2894	.num_parents = 1,
2895	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
2896	.ops = &clk_branch2_ops,
2897	},
2898	},
2899	};
2900
2901	static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
2902	.mult = 1,
2903	.div = 6,
2904	.hw.init = &(const struct clk_init_data) {
2905	.name = "gcc_eud_at_div_clk_src",
2906	.parent_hws = (const struct clk_hw *[]) {
2907	&qdss_at_clk_src.clkr.hw
2908	},
2909	.num_parents = 1,
2910	.flags = CLK_SET_RATE_PARENT,
2911	.ops = &clk_fixed_factor_ops,
2912	},
2913	};
2914
2915	static struct clk_branch gcc_usb0_eud_at_clk = {
2916	.halt_reg = 0x30004,
2917	.clkr = {
2918	.enable_reg = 0x30004,
2919	.enable_mask = BIT(0),
2920	.hw.init = &(const struct clk_init_data) {
2921	.name = "gcc_usb0_eud_at_clk",
2922	.parent_hws = (const struct clk_hw *[]) {
2923	&gcc_eud_at_div_clk_src.hw
2924	},
2925	.num_parents = 1,
2926	.flags = CLK_SET_RATE_PARENT,
2927	.ops = &clk_branch2_ops,
2928	},
2929	},
2930	};
2931
2932	static struct clk_branch gcc_qdss_eud_at_clk = {
2933	.halt_reg = 0x2d06c,
2934	.clkr = {
2935	.enable_reg = 0x2d06c,
2936	.enable_mask = BIT(0),
2937	.hw.init = &(const struct clk_init_data) {
2938	.name = "gcc_qdss_eud_at_clk",
2939	.parent_hws = (const struct clk_hw *[]) {
2940	&gcc_eud_at_div_clk_src.hw
2941	},
2942	.num_parents = 1,
2943	.flags = CLK_SET_RATE_PARENT,
2944	.ops = &clk_branch2_ops,
2945	},
2946	},
2947	};
2948
2949	static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
2950	F(24000000, P_XO, 1, 0, 0),
2951	F(200000000, P_GPLL0, 4, 0, 0),
2952	{ }
2953	};
2954
2955	static struct clk_rcg2 qdss_stm_clk_src = {
2956	.cmd_rcgr = 0x2d00c,
2957	.freq_tbl = ftbl_qdss_stm_clk_src,
2958	.hid_width = 5,
2959	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
2960	.clkr.hw.init = &(const struct clk_init_data) {
2961	.name = "qdss_stm_clk_src",
2962	.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
2963	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
2964	.ops = &clk_rcg2_ops,
2965	},
2966	};
2967
2968	static struct clk_branch gcc_qdss_stm_clk = {
2969	.halt_reg = 0x2d03c,
2970	.clkr = {
2971	.enable_reg = 0x2d03c,
2972	.enable_mask = BIT(0),
2973	.hw.init = &(const struct clk_init_data) {
2974	.name = "gcc_qdss_stm_clk",
2975	.parent_hws = (const struct clk_hw *[]) {
2976	&qdss_stm_clk_src.clkr.hw
2977	},
2978	.num_parents = 1,
2979	.flags = CLK_SET_RATE_PARENT,
2980	.ops = &clk_branch2_ops,
2981	},
2982	},
2983	};
2984
2985	static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
2986	.halt_reg = 0x2e034,
2987	.clkr = {
2988	.enable_reg = 0x2e034,
2989	.enable_mask = BIT(0),
2990	.hw.init = &(const struct clk_init_data) {
2991	.name = "gcc_sys_noc_qdss_stm_axi_clk",
2992	.parent_hws = (const struct clk_hw *[]) {
2993	&qdss_stm_clk_src.clkr.hw
2994	},
2995	.num_parents = 1,
2996	.flags = CLK_SET_RATE_PARENT,
2997	.ops = &clk_branch2_ops,
2998	},
2999	},
3000	};
3001
3002	static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
3003	F(300000000, P_GPLL4, 4, 0, 0),
3004	{ }
3005	};
3006
3007	static struct clk_rcg2 qdss_traceclkin_clk_src = {
3008	.cmd_rcgr = 0x2d014,
3009	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
3010	.hid_width = 5,
3011	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3012	.clkr.hw.init = &(const struct clk_init_data) {
3013	.name = "qdss_traceclkin_clk_src",
3014	.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3015	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3016	.ops = &clk_rcg2_ops,
3017	},
3018	};
3019
3020	static struct clk_branch gcc_qdss_traceclkin_clk = {
3021	.halt_reg = 0x2d040,
3022	.clkr = {
3023	.enable_reg = 0x2d040,
3024	.enable_mask = BIT(0),
3025	.hw.init = &(const struct clk_init_data) {
3026	.name = "gcc_qdss_traceclkin_clk",
3027	.parent_hws = (const struct clk_hw *[]) {
3028	&qdss_traceclkin_clk_src.clkr.hw
3029	},
3030	.num_parents = 1,
3031	.flags = CLK_SET_RATE_PARENT,
3032	.ops = &clk_branch2_ops,
3033	},
3034	},
3035	};
3036
3037	static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
3038	F(600000000, P_GPLL4, 2, 0, 0),
3039	{ }
3040	};
3041
3042	static struct clk_rcg2 qdss_tsctr_clk_src = {
3043	.cmd_rcgr = 0x2d01c,
3044	.freq_tbl = ftbl_qdss_tsctr_clk_src,
3045	.hid_width = 5,
3046	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
3047	.clkr.hw.init = &(const struct clk_init_data) {
3048	.name = "qdss_tsctr_clk_src",
3049	.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
3050	.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
3051	.ops = &clk_rcg2_ops,
3052	},
3053	};
3054
3055	static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
3056	.mult = 1,
3057	.div = 2,
3058	.hw.init = &(const struct clk_init_data) {
3059	.name = "qdss_tsctr_div2_clk_src",
3060	.parent_hws = (const struct clk_hw *[]) {
3061	&qdss_tsctr_clk_src.clkr.hw
3062	},
3063	.num_parents = 1,
3064	.flags = CLK_SET_RATE_PARENT,
3065	.ops = &clk_fixed_factor_ops,
3066	},
3067	};
3068
3069	static struct clk_branch gcc_q6_tsctr_1to2_clk = {
3070	.halt_reg = 0x25020,
3071	.clkr = {
3072	.enable_reg = 0x25020,
3073	.enable_mask = BIT(0),
3074	.hw.init = &(const struct clk_init_data) {
3075	.name = "gcc_q6_tsctr_1to2_clk",
3076	.parent_hws = (const struct clk_hw *[]) {
3077	&qdss_tsctr_div2_clk_src.hw
3078	},
3079	.num_parents = 1,
3080	.flags = CLK_SET_RATE_PARENT,
3081	.ops = &clk_branch2_ops,
3082	},
3083	},
3084	};
3085
3086	static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
3087	.halt_reg = 0x25040,
3088	.clkr = {
3089	.enable_reg = 0x25040,
3090	.enable_mask = BIT(0),
3091	.hw.init = &(const struct clk_init_data) {
3092	.name = "gcc_wcss_dbg_ifc_nts_clk",
3093	.parent_hws = (const struct clk_hw *[]) {
3094	&qdss_tsctr_div2_clk_src.hw
3095	},
3096	.num_parents = 1,
3097	.flags = CLK_SET_RATE_PARENT,
3098	.ops = &clk_branch2_ops,
3099	},
3100	},
3101	};
3102
3103	static struct clk_branch gcc_qdss_tsctr_div2_clk = {
3104	.halt_reg = 0x2d044,
3105	.clkr = {
3106	.enable_reg = 0x2d044,
3107	.enable_mask = BIT(0),
3108	.hw.init = &(const struct clk_init_data) {
3109	.name = "gcc_qdss_tsctr_div2_clk",
3110	.parent_hws = (const struct clk_hw *[]) {
3111	&qdss_tsctr_div2_clk_src.hw
3112	},
3113	.num_parents = 1,
3114	.flags = CLK_SET_RATE_PARENT,
3115	.ops = &clk_branch2_ops,
3116	},
3117	},
3118	};
3119
3120	static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
3121	F(24000000, P_XO, 1, 0, 0),
3122	{ }
3123	};
3124
3125	static struct clk_rcg2 uniphy_sys_clk_src = {
3126	.cmd_rcgr = 0x17090,
3127	.freq_tbl = ftbl_uniphy_sys_clk_src,
3128	.mnd_width = 8,
3129	.hid_width = 5,
3130	.parent_map = gcc_xo_map,
3131	.clkr.hw.init = &(const struct clk_init_data) {
3132	.name = "uniphy_sys_clk_src",
3133	.parent_data = gcc_xo_data,
3134	.num_parents = ARRAY_SIZE(gcc_xo_data),
3135	.ops = &clk_rcg2_ops,
3136	},
3137	};
3138
3139	static struct clk_rcg2 nss_ts_clk_src = {
3140	.cmd_rcgr = 0x17088,
3141	.freq_tbl = ftbl_uniphy_sys_clk_src,
3142	.mnd_width = 8,
3143	.hid_width = 5,
3144	.parent_map = gcc_xo_map,
3145	.clkr.hw.init = &(const struct clk_init_data) {
3146	.name = "nss_ts_clk_src",
3147	.parent_data = gcc_xo_data,
3148	.num_parents = ARRAY_SIZE(gcc_xo_data),
3149	.ops = &clk_rcg2_ops,
3150	},
3151	};
3152
3153	static struct clk_branch gcc_qdss_ts_clk = {
3154	.halt_reg = 0x2d078,
3155	.clkr = {
3156	.enable_reg = 0x2d078,
3157	.enable_mask = BIT(0),
3158	.hw.init = &(const struct clk_init_data) {
3159	.name = "gcc_qdss_ts_clk",
3160	.parent_hws = (const struct clk_hw *[]) {
3161	&nss_ts_clk_src.clkr.hw
3162	},
3163	.num_parents = 1,
3164	.flags = CLK_SET_RATE_PARENT,
3165	.ops = &clk_branch2_ops,
3166	},
3167	},
3168	};
3169
3170	static struct clk_fixed_factor qdss_dap_sync_clk_src = {
3171	.mult = 1,
3172	.div = 4,
3173	.hw.init = &(const struct clk_init_data) {
3174	.name = "qdss_dap_sync_clk_src",
3175	.parent_hws = (const struct clk_hw *[]) {
3176	&qdss_tsctr_clk_src.clkr.hw
3177	},
3178	.num_parents = 1,
3179	.ops = &clk_fixed_factor_ops,
3180	},
3181	};
3182
3183	static struct clk_branch gcc_qdss_tsctr_div4_clk = {
3184	.halt_reg = 0x2d04c,
3185	.clkr = {
3186	.enable_reg = 0x2d04c,
3187	.enable_mask = BIT(0),
3188	.hw.init = &(const struct clk_init_data) {
3189	.name = "gcc_qdss_tsctr_div4_clk",
3190	.parent_hws = (const struct clk_hw *[]) {
3191	&qdss_dap_sync_clk_src.hw
3192	},
3193	.num_parents = 1,
3194	.flags = CLK_SET_RATE_PARENT,
3195	.ops = &clk_branch2_ops,
3196	},
3197	},
3198	};
3199
3200	static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
3201	.mult = 1,
3202	.div = 8,
3203	.hw.init = &(const struct clk_init_data) {
3204	.name = "qdss_tsctr_div8_clk_src",
3205	.parent_hws = (const struct clk_hw *[]) {
3206	&qdss_tsctr_clk_src.clkr.hw
3207	},
3208	.num_parents = 1,
3209	.ops = &clk_fixed_factor_ops,
3210	},
3211	};
3212
3213	static struct clk_branch gcc_nss_ts_clk = {
3214	.halt_reg = 0x17018,
3215	.clkr = {
3216	.enable_reg = 0x17018,
3217	.enable_mask = BIT(0),
3218	.hw.init = &(const struct clk_init_data) {
3219	.name = "gcc_nss_ts_clk",
3220	.parent_hws = (const struct clk_hw *[]) {
3221	&nss_ts_clk_src.clkr.hw
3222	},
3223	.num_parents = 1,
3224	.flags = CLK_SET_RATE_PARENT,
3225	.ops = &clk_branch2_ops,
3226	},
3227	},
3228	};
3229
3230	static struct clk_branch gcc_qdss_tsctr_div8_clk = {
3231	.halt_reg = 0x2d050,
3232	.clkr = {
3233	.enable_reg = 0x2d050,
3234	.enable_mask = BIT(0),
3235	.hw.init = &(const struct clk_init_data) {
3236	.name = "gcc_qdss_tsctr_div8_clk",
3237	.parent_hws = (const struct clk_hw *[]) {
3238	&qdss_tsctr_div8_clk_src.hw
3239	},
3240	.num_parents = 1,
3241	.flags = CLK_SET_RATE_PARENT,
3242	.ops = &clk_branch2_ops,
3243	},
3244	},
3245	};
3246
3247	static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
3248	.mult = 1,
3249	.div = 16,
3250	.hw.init = &(const struct clk_init_data) {
3251	.name = "qdss_tsctr_div16_clk_src",
3252	.parent_hws = (const struct clk_hw *[]) {
3253	&qdss_tsctr_clk_src.clkr.hw
3254	},
3255	.num_parents = 1,
3256	.ops = &clk_fixed_factor_ops,
3257	},
3258	};
3259
3260	static struct clk_branch gcc_qdss_tsctr_div16_clk = {
3261	.halt_reg = 0x2d054,
3262	.clkr = {
3263	.enable_reg = 0x2d054,
3264	.enable_mask = BIT(0),
3265	.hw.init = &(const struct clk_init_data) {
3266	.name = "gcc_qdss_tsctr_div16_clk",
3267	.parent_hws = (const struct clk_hw *[]) {
3268	&qdss_tsctr_div16_clk_src.hw
3269	},
3270	.num_parents = 1,
3271	.flags = CLK_SET_RATE_PARENT,
3272	.ops = &clk_branch2_ops,
3273	},
3274	},
3275	};
3276
3277	static struct clk_branch gcc_q6ss_pclkdbg_clk = {
3278	.halt_reg = 0x25024,
3279	.clkr = {
3280	.enable_reg = 0x25024,
3281	.enable_mask = BIT(0),
3282	.hw.init = &(const struct clk_init_data) {
3283	.name = "gcc_q6ss_pclkdbg_clk",
3284	.parent_hws = (const struct clk_hw *[]) {
3285	&qdss_dap_sync_clk_src.hw
3286	},
3287	.num_parents = 1,
3288	.flags = CLK_SET_RATE_PARENT,
3289	.ops = &clk_branch2_ops,
3290	},
3291	},
3292	};
3293
3294	static struct clk_branch gcc_q6ss_trig_clk = {
3295	.halt_reg = 0x25068,
3296	.clkr = {
3297	.enable_reg = 0x25068,
3298	.enable_mask = BIT(0),
3299	.hw.init = &(const struct clk_init_data) {
3300	.name = "gcc_q6ss_trig_clk",
3301	.parent_hws = (const struct clk_hw *[]) {
3302	&qdss_dap_sync_clk_src.hw
3303	},
3304	.num_parents = 1,
3305	.flags = CLK_SET_RATE_PARENT,
3306	.ops = &clk_branch2_ops,
3307	},
3308	},
3309	};
3310
3311	static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
3312	.halt_reg = 0x25038,
3313	.clkr = {
3314	.enable_reg = 0x25038,
3315	.enable_mask = BIT(0),
3316	.hw.init = &(const struct clk_init_data) {
3317	.name = "gcc_wcss_dbg_ifc_apb_clk",
3318	.parent_hws = (const struct clk_hw *[]) {
3319	&qdss_dap_sync_clk_src.hw
3320	},
3321	.num_parents = 1,
3322	.flags = CLK_SET_RATE_PARENT,
3323	.ops = &clk_branch2_ops,
3324	},
3325	},
3326	};
3327
3328	static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
3329	.halt_reg = 0x25044,
3330	.clkr = {
3331	.enable_reg = 0x25044,
3332	.enable_mask = BIT(0),
3333	.hw.init = &(const struct clk_init_data) {
3334	.name = "gcc_wcss_dbg_ifc_dapbus_clk",
3335	.parent_hws = (const struct clk_hw *[]) {
3336	&qdss_dap_sync_clk_src.hw
3337	},
3338	.num_parents = 1,
3339	.flags = CLK_SET_RATE_PARENT,
3340	.ops = &clk_branch2_ops,
3341	},
3342	},
3343	};
3344
3345	static struct clk_branch gcc_qdss_dap_clk = {
3346	.halt_reg = 0x2d058,
3347	.clkr = {
3348	.enable_reg = 0x2d058,
3349	.enable_mask = BIT(0),
3350	.hw.init = &(const struct clk_init_data) {
3351	.name = "gcc_qdss_dap_clk",
3352	.parent_hws = (const struct clk_hw *[]) {
3353	&qdss_dap_sync_clk_src.hw
3354	},
3355	.num_parents = 1,
3356	.flags = CLK_SET_RATE_PARENT,
3357	.ops = &clk_branch2_ops,
3358	},
3359	},
3360	};
3361
3362	static struct clk_branch gcc_qdss_apb2jtag_clk = {
3363	.halt_reg = 0x2d05c,
3364	.clkr = {
3365	.enable_reg = 0x2d05c,
3366	.enable_mask = BIT(0),
3367	.hw.init = &(const struct clk_init_data) {
3368	.name = "gcc_qdss_apb2jtag_clk",
3369	.parent_hws = (const struct clk_hw *[]) {
3370	&qdss_dap_sync_clk_src.hw
3371	},
3372	.num_parents = 1,
3373	.flags = CLK_SET_RATE_PARENT,
3374	.ops = &clk_branch2_ops,
3375	},
3376	},
3377	};
3378
3379	static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
3380	.mult = 1,
3381	.div = 3,
3382	.hw.init = &(const struct clk_init_data) {
3383	.name = "qdss_tsctr_div3_clk_src",
3384	.parent_hws = (const struct clk_hw *[]) {
3385	&qdss_tsctr_clk_src.clkr.hw
3386	},
3387	.num_parents = 1,
3388	.ops = &clk_fixed_factor_ops,
3389	},
3390	};
3391
3392	static struct clk_branch gcc_qdss_tsctr_div3_clk = {
3393	.halt_reg = 0x2d048,
3394	.clkr = {
3395	.enable_reg = 0x2d048,
3396	.enable_mask = BIT(0),
3397	.hw.init = &(const struct clk_init_data) {
3398	.name = "gcc_qdss_tsctr_div3_clk",
3399	.parent_hws = (const struct clk_hw *[]) {
3400	&qdss_tsctr_div3_clk_src.hw
3401	},
3402	.num_parents = 1,
3403	.flags = CLK_SET_RATE_PARENT,
3404	.ops = &clk_branch2_ops,
3405	},
3406	},
3407	};
3408
3409	static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
3410	F(24000000, P_XO, 1, 0, 0),
3411	F(100000000, P_GPLL0, 8, 0, 0),
3412	F(200000000, P_GPLL0, 4, 0, 0),
3413	F(320000000, P_GPLL0, 2.5, 0, 0),
3414	F(400000000, P_GPLL0, 2, 0, 0),
3415	{ }
3416	};
3417
3418	static struct clk_rcg2 qpic_io_macro_clk_src = {
3419	.cmd_rcgr = 0x32004,
3420	.freq_tbl = ftbl_qpic_io_macro_clk_src,
3421	.hid_width = 5,
3422	.parent_map = gcc_xo_gpll0_gpll2_map,
3423	.clkr.hw.init = &(const struct clk_init_data) {
3424	.name = "qpic_io_macro_clk_src",
3425	.parent_data = gcc_xo_gpll0_gpll2,
3426	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
3427	.ops = &clk_rcg2_ops,
3428	},
3429	};
3430
3431	static struct clk_branch gcc_qpic_io_macro_clk = {
3432	.halt_reg = 0x3200c,
3433	.clkr = {
3434	.enable_reg = 0x3200c,
3435	.enable_mask = BIT(0),
3436	.hw.init = &(const struct clk_init_data){
3437	.name = "gcc_qpic_io_macro_clk",
3438	.parent_hws = (const struct clk_hw *[]){
3439	&qpic_io_macro_clk_src.clkr.hw
3440	},
3441	.num_parents = 1,
3442	.flags = CLK_SET_RATE_PARENT,
3443	.ops = &clk_branch2_ops,
3444	},
3445	},
3446	};
3447
3448	static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
3449	F(533333333, P_GPLL0, 1.5, 0, 0),
3450	{ }
3451	};
3452
3453	static struct clk_rcg2 q6_axi_clk_src = {
3454	.cmd_rcgr = 0x25004,
3455	.freq_tbl = ftbl_q6_axi_clk_src,
3456	.hid_width = 5,
3457	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
3458	.clkr.hw.init = &(const struct clk_init_data) {
3459	.name = "q6_axi_clk_src",
3460	.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
3461	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
3462	.ops = &clk_rcg2_ops,
3463	},
3464	};
3465
3466	static struct clk_branch gcc_q6_axim_clk = {
3467	.halt_reg = 0x2500c,
3468	.clkr = {
3469	.enable_reg = 0x2500c,
3470	.enable_mask = BIT(0),
3471	.hw.init = &(const struct clk_init_data) {
3472	.name = "gcc_q6_axim_clk",
3473	.parent_hws = (const struct clk_hw *[]) {
3474	&q6_axi_clk_src.clkr.hw
3475	},
3476	.num_parents = 1,
3477	.flags = CLK_SET_RATE_PARENT,
3478	.ops = &clk_branch2_ops,
3479	},
3480	},
3481	};
3482
3483	static struct clk_branch gcc_wcss_q6_tbu_clk = {
3484	.halt_reg = 0x12050,
3485	.halt_check = BRANCH_HALT_DELAY,
3486	.clkr = {
3487	.enable_reg = 0xb00c,
3488	.enable_mask = BIT(6),
3489	.hw.init = &(const struct clk_init_data) {
3490	.name = "gcc_wcss_q6_tbu_clk",
3491	.parent_hws = (const struct clk_hw *[]) {
3492	&q6_axi_clk_src.clkr.hw
3493	},
3494	.num_parents = 1,
3495	.flags = CLK_SET_RATE_PARENT,
3496	.ops = &clk_branch2_ops,
3497	},
3498	},
3499	};
3500
3501	static struct clk_branch gcc_mem_noc_q6_axi_clk = {
3502	.halt_reg = 0x19010,
3503	.clkr = {
3504	.enable_reg = 0x19010,
3505	.enable_mask = BIT(0),
3506	.hw.init = &(const struct clk_init_data) {
3507	.name = "gcc_mem_noc_q6_axi_clk",
3508	.parent_hws = (const struct clk_hw *[]) {
3509	&q6_axi_clk_src.clkr.hw
3510	},
3511	.num_parents = 1,
3512	.flags = CLK_SET_RATE_PARENT,
3513	.ops = &clk_branch2_ops,
3514	},
3515	},
3516	};
3517
3518	static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
3519	F(342857143, P_GPLL4, 3.5, 0, 0),
3520	{ }
3521	};
3522
3523	static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
3524	{ P_XO, 0 },
3525	{ P_GPLL0, 1 },
3526	{ P_GPLL4, 2 },
3527	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
3528	};
3529
3530	static struct clk_rcg2 q6_axim2_clk_src = {
3531	.cmd_rcgr = 0x25028,
3532	.freq_tbl = ftbl_q6_axim2_clk_src,
3533	.hid_width = 5,
3534	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
3535	.clkr.hw.init = &(const struct clk_init_data) {
3536	.name = "q6_axim2_clk_src",
3537	.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
3538	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
3539	.ops = &clk_rcg2_ops,
3540	},
3541	};
3542
3543	static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
3544	F(533333333, P_GPLL0, 1.5, 0, 0),
3545	{ }
3546	};
3547
3548	static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
3549	.cmd_rcgr = 0x17004,
3550	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
3551	.hid_width = 5,
3552	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
3553	.clkr.hw.init = &(const struct clk_init_data) {
3554	.name = "nssnoc_memnoc_bfdcd_clk_src",
3555	.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
3556	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
3557	.ops = &clk_rcg2_ops,
3558	},
3559	};
3560
3561	static struct clk_branch gcc_nssnoc_memnoc_clk = {
3562	.halt_reg = 0x17024,
3563	.clkr = {
3564	.enable_reg = 0x17024,
3565	.enable_mask = BIT(0),
3566	.hw.init = &(const struct clk_init_data) {
3567	.name = "gcc_nssnoc_memnoc_clk",
3568	.parent_hws = (const struct clk_hw *[]) {
3569	&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3570	},
3571	.num_parents = 1,
3572	.flags = CLK_SET_RATE_PARENT,
3573	.ops = &clk_branch2_ops,
3574	},
3575	},
3576	};
3577
3578	static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
3579	.halt_reg = 0x17084,
3580	.clkr = {
3581	.enable_reg = 0x17084,
3582	.enable_mask = BIT(0),
3583	.hw.init = &(const struct clk_init_data) {
3584	.name = "gcc_nssnoc_mem_noc_1_clk",
3585	.parent_hws = (const struct clk_hw *[]) {
3586	&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3587	},
3588	.num_parents = 1,
3589	.flags = CLK_SET_RATE_PARENT,
3590	.ops = &clk_branch2_ops,
3591	},
3592	},
3593	};
3594
3595	static struct clk_branch gcc_nss_tbu_clk = {
3596	.halt_reg = 0x12040,
3597	.clkr = {
3598	.enable_reg = 0xb00c,
3599	.enable_mask = BIT(4),
3600	.hw.init = &(const struct clk_init_data) {
3601	.name = "gcc_nss_tbu_clk",
3602	.parent_hws = (const struct clk_hw *[]) {
3603	&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3604	},
3605	.num_parents = 1,
3606	.flags = CLK_SET_RATE_PARENT,
3607	.ops = &clk_branch2_ops,
3608	},
3609	},
3610	};
3611
3612	static struct clk_branch gcc_mem_noc_nssnoc_clk = {
3613	.halt_reg = 0x19014,
3614	.clkr = {
3615	.enable_reg = 0x19014,
3616	.enable_mask = BIT(0),
3617	.hw.init = &(const struct clk_init_data) {
3618	.name = "gcc_mem_noc_nssnoc_clk",
3619	.parent_hws = (const struct clk_hw *[]) {
3620	&nssnoc_memnoc_bfdcd_clk_src.clkr.hw
3621	},
3622	.num_parents = 1,
3623	.flags = CLK_SET_RATE_PARENT,
3624	.ops = &clk_branch2_ops,
3625	},
3626	},
3627	};
3628
3629	static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
3630	F(133333333, P_GPLL0, 6, 0, 0),
3631	{ }
3632	};
3633
3634	static struct clk_rcg2 lpass_axim_clk_src = {
3635	.cmd_rcgr = 0x2700c,
3636	.freq_tbl = ftbl_lpass_axim_clk_src,
3637	.hid_width = 5,
3638	.parent_map = gcc_xo_gpll0_map,
3639	.clkr.hw.init = &(const struct clk_init_data) {
3640	.name = "lpass_axim_clk_src",
3641	.parent_data = gcc_xo_gpll0,
3642	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3643	.ops = &clk_rcg2_ops,
3644	},
3645	};
3646
3647	static struct clk_rcg2 lpass_sway_clk_src = {
3648	.cmd_rcgr = 0x27004,
3649	.freq_tbl = ftbl_lpass_axim_clk_src,
3650	.hid_width = 5,
3651	.parent_map = gcc_xo_gpll0_map,
3652	.clkr.hw.init = &(const struct clk_init_data) {
3653	.name = "lpass_sway_clk_src",
3654	.parent_data = gcc_xo_gpll0,
3655	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3656	.ops = &clk_rcg2_ops,
3657	},
3658	};
3659
3660	static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
3661	F(24000000, P_XO, 1, 0, 0),
3662	F(100000000, P_GPLL0, 8, 0, 0),
3663	{ }
3664	};
3665
3666	static struct clk_rcg2 adss_pwm_clk_src = {
3667	.cmd_rcgr = 0x1c004,
3668	.freq_tbl = ftbl_adss_pwm_clk_src,
3669	.hid_width = 5,
3670	.parent_map = gcc_xo_gpll0_map,
3671	.clkr.hw.init = &(const struct clk_init_data) {
3672	.name = "adss_pwm_clk_src",
3673	.parent_data = gcc_xo_gpll0,
3674	.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
3675	.ops = &clk_rcg2_ops,
3676	},
3677	};
3678
3679	static struct clk_branch gcc_adss_pwm_clk = {
3680	.halt_reg = 0x1c00c,
3681	.clkr = {
3682	.enable_reg = 0x1c00c,
3683	.enable_mask = BIT(0),
3684	.hw.init = &(const struct clk_init_data) {
3685	.name = "gcc_adss_pwm_clk",
3686	.parent_hws = (const struct clk_hw *[]) {
3687	&adss_pwm_clk_src.clkr.hw
3688	},
3689	.num_parents = 1,
3690	.flags = CLK_SET_RATE_PARENT,
3691	.ops = &clk_branch2_ops,
3692	},
3693	},
3694	};
3695
3696	static const struct freq_tbl ftbl_gp1_clk_src[] = {
3697	F(24000000, P_XO, 1, 0, 0),
3698	F(200000000, P_GPLL0, 4, 0, 0),
3699	{ }
3700	};
3701
3702	static struct clk_rcg2 gp1_clk_src = {
3703	.cmd_rcgr = 0x8004,
3704	.freq_tbl = ftbl_gp1_clk_src,
3705	.hid_width = 5,
3706	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3707	.clkr.hw.init = &(const struct clk_init_data) {
3708	.name = "gp1_clk_src",
3709	.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3710	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3711	.ops = &clk_rcg2_ops,
3712	},
3713	};
3714
3715	static struct clk_rcg2 gp2_clk_src = {
3716	.cmd_rcgr = 0x9004,
3717	.freq_tbl = ftbl_gp1_clk_src,
3718	.hid_width = 5,
3719	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3720	.clkr.hw.init = &(const struct clk_init_data) {
3721	.name = "gp2_clk_src",
3722	.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3723	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3724	.ops = &clk_rcg2_ops,
3725	},
3726	};
3727
3728	static struct clk_rcg2 gp3_clk_src = {
3729	.cmd_rcgr = 0xa004,
3730	.freq_tbl = ftbl_gp1_clk_src,
3731	.hid_width = 5,
3732	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
3733	.clkr.hw.init = &(const struct clk_init_data) {
3734	.name = "gp3_clk_src",
3735	.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
3736	.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
3737	.ops = &clk_rcg2_ops,
3738	},
3739	};
3740
3741	static struct clk_branch gcc_xo_clk_src = {
3742	.halt_reg = 0x34004,
3743	.clkr = {
3744	.enable_reg = 0x34004,
3745	.enable_mask = BIT(1),
3746	.hw.init = &(const struct clk_init_data) {
3747	.name = "gcc_xo_clk_src",
3748	.parent_data = gcc_xo_data,
3749	.num_parents = ARRAY_SIZE(gcc_xo_data),
3750	.flags = CLK_SET_RATE_PARENT,
3751	.ops = &clk_branch2_ops,
3752	},
3753	},
3754	};
3755
3756	static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
3757	.halt_reg = 0x17074,
3758	.clkr = {
3759	.enable_reg = 0x17074,
3760	.enable_mask = BIT(0),
3761	.hw.init = &(const struct clk_init_data) {
3762	.name = "gcc_nssnoc_xo_dcd_clk",
3763	.parent_hws = (const struct clk_hw *[]) {
3764	&gcc_xo_clk_src.clkr.hw
3765	},
3766	.num_parents = 1,
3767	.flags = CLK_SET_RATE_PARENT,
3768	.ops = &clk_branch2_ops,
3769	},
3770	},
3771	};
3772
3773	static struct clk_branch gcc_xo_clk = {
3774	.halt_reg = 0x34018,
3775	.clkr = {
3776	.enable_reg = 0x34018,
3777	.enable_mask = BIT(0),
3778	.hw.init = &(const struct clk_init_data) {
3779	.name = "gcc_xo_clk",
3780	.parent_hws = (const struct clk_hw *[]) {
3781	&gcc_xo_clk_src.clkr.hw
3782	},
3783	.num_parents = 1,
3784	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3785	.ops = &clk_branch2_ops,
3786	},
3787	},
3788	};
3789
3790	static struct clk_branch gcc_uniphy0_sys_clk = {
3791	.halt_reg = 0x17048,
3792	.clkr = {
3793	.enable_reg = 0x17048,
3794	.enable_mask = BIT(0),
3795	.hw.init = &(const struct clk_init_data) {
3796	.name = "gcc_uniphy0_sys_clk",
3797	.parent_hws = (const struct clk_hw *[]) {
3798	&uniphy_sys_clk_src.clkr.hw
3799	},
3800	.num_parents = 1,
3801	.flags = CLK_SET_RATE_PARENT,
3802	.ops = &clk_branch2_ops,
3803	},
3804	},
3805	};
3806
3807	static struct clk_branch gcc_uniphy1_sys_clk = {
3808	.halt_reg = 0x17058,
3809	.clkr = {
3810	.enable_reg = 0x17058,
3811	.enable_mask = BIT(0),
3812	.hw.init = &(const struct clk_init_data) {
3813	.name = "gcc_uniphy1_sys_clk",
3814	.parent_hws = (const struct clk_hw *[]) {
3815	&uniphy_sys_clk_src.clkr.hw
3816	},
3817	.num_parents = 1,
3818	.flags = CLK_SET_RATE_PARENT,
3819	.ops = &clk_branch2_ops,
3820	},
3821	},
3822	};
3823
3824	static struct clk_branch gcc_uniphy2_sys_clk = {
3825	.halt_reg = 0x17068,
3826	.clkr = {
3827	.enable_reg = 0x17068,
3828	.enable_mask = BIT(0),
3829	.hw.init = &(const struct clk_init_data) {
3830	.name = "gcc_uniphy2_sys_clk",
3831	.parent_hws = (const struct clk_hw *[]) {
3832	&uniphy_sys_clk_src.clkr.hw
3833	},
3834	.num_parents = 1,
3835	.flags = CLK_SET_RATE_PARENT,
3836	.ops = &clk_branch2_ops,
3837	},
3838	},
3839	};
3840
3841	static struct clk_branch gcc_cmn_12gpll_sys_clk = {
3842	.halt_reg = 0x3a008,
3843	.clkr = {
3844	.enable_reg = 0x3a008,
3845	.enable_mask = BIT(0),
3846	.hw.init = &(const struct clk_init_data) {
3847	.name = "gcc_cmn_12gpll_sys_clk",
3848	.parent_hws = (const struct clk_hw *[]) {
3849	&uniphy_sys_clk_src.clkr.hw
3850	},
3851	.num_parents = 1,
3852	.flags = CLK_SET_RATE_PARENT,
3853	.ops = &clk_branch2_ops,
3854	},
3855	},
3856	};
3857
3858	static struct clk_fixed_factor gcc_xo_div4_clk_src = {
3859	.mult = 1,
3860	.div = 4,
3861	.hw.init = &(const struct clk_init_data) {
3862	.name = "gcc_xo_div4_clk_src",
3863	.parent_hws = (const struct clk_hw *[]) {
3864	&gcc_xo_clk_src.clkr.hw
3865	},
3866	.num_parents = 1,
3867	.flags = CLK_SET_RATE_PARENT,
3868	.ops = &clk_fixed_factor_ops,
3869	},
3870	};
3871
3872	static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
3873	.halt_reg = 0x1701c,
3874	.clkr = {
3875	.enable_reg = 0x1701c,
3876	.enable_mask = BIT(0),
3877	.hw.init = &(const struct clk_init_data) {
3878	.name = "gcc_nssnoc_qosgen_ref_clk",
3879	.parent_hws = (const struct clk_hw *[]) {
3880	&gcc_xo_div4_clk_src.hw
3881	},
3882	.num_parents = 1,
3883	.flags = CLK_SET_RATE_PARENT,
3884	.ops = &clk_branch2_ops,
3885	},
3886	},
3887	};
3888
3889	static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
3890	.halt_reg = 0x17020,
3891	.clkr = {
3892	.enable_reg = 0x17020,
3893	.enable_mask = BIT(0),
3894	.hw.init = &(const struct clk_init_data) {
3895	.name = "gcc_nssnoc_timeout_ref_clk",
3896	.parent_hws = (const struct clk_hw *[]) {
3897	&gcc_xo_div4_clk_src.hw
3898	},
3899	.num_parents = 1,
3900	.flags = CLK_SET_RATE_PARENT,
3901	.ops = &clk_branch2_ops,
3902	},
3903	},
3904	};
3905
3906	static struct clk_branch gcc_xo_div4_clk = {
3907	.halt_reg = 0x3401c,
3908	.clkr = {
3909	.enable_reg = 0x3401c,
3910	.enable_mask = BIT(0),
3911	.hw.init = &(const struct clk_init_data) {
3912	.name = "gcc_xo_div4_clk",
3913	.parent_hws = (const struct clk_hw *[]) {
3914	&gcc_xo_div4_clk_src.hw
3915	},
3916	.num_parents = 1,
3917	.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
3918	.ops = &clk_branch2_ops,
3919	},
3920	},
3921	};
3922
3923	static struct clk_hw *gcc_ipq9574_hws[] = {
3924	&gpll0_out_main_div2.hw,
3925	&gcc_xo_div4_clk_src.hw,
3926	&qdss_dap_sync_clk_src.hw,
3927	&qdss_tsctr_div2_clk_src.hw,
3928	&qdss_tsctr_div8_clk_src.hw,
3929	&qdss_tsctr_div16_clk_src.hw,
3930	&qdss_tsctr_div3_clk_src.hw,
3931	&gcc_eud_at_div_clk_src.hw,
3932	};
3933
3934	static struct clk_regmap *gcc_ipq9574_clks[] = {
3935	[GPLL0_MAIN] = &gpll0_main.clkr,
3936	[GPLL0] = &gpll0.clkr,
3937	[GPLL4_MAIN] = &gpll4_main.clkr,
3938	[GPLL4] = &gpll4.clkr,
3939	[GPLL2_MAIN] = &gpll2_main.clkr,
3940	[GPLL2] = &gpll2.clkr,
3941	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
3942	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3943	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
3944	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
3945	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
3946	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
3947	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
3948	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
3949	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
3950	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
3951	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
3952	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
3953	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
3954	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
3955	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
3956	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
3957	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
3958	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
3959	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
3960	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
3961	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
3962	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
3963	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
3964	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
3965	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
3966	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
3967	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
3968	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
3969	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
3970	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
3971	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
3972	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
3973	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3974	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3975	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3976	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3977	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3978	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3979	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3980	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3981	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3982	[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
3983	[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
3984	[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
3985	[GCC_CRYPTO_CLK_SRC] = &gcc_crypto_clk_src.clkr,
3986	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
3987	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3988	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
3989	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3990	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
3991	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
3992	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
3993	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
3994	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
3995	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
3996	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3997	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
3998	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
3999	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4000	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
4001	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
4002	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
4003	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
4004	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
4005	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
4006	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4007	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4008	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
4009	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
4010	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
4011	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4012	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4013	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
4014	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
4015	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4016	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4017	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
4018	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
4019	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
4020	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
4021	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
4022	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
4023	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4024	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4025	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
4026	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
4027	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4028	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4029	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4030	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4031	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
4032	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
4033	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4034	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
4035	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4036	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4037	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4038	[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4039	[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4040	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4041	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4042	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4043	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4044	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4045	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4046	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
4047	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
4048	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
4049	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
4050	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
4051	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
4052	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4053	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4054	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4055	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4056	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4057	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4058	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4059	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4060	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4061	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
4062	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4063	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4064	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
4065	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
4066	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
4067	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
4068	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
4069	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
4070	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
4071	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
4072	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
4073	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
4074	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
4075	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
4076	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
4077	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
4078	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
4079	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
4080	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
4081	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
4082	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
4083	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
4084	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
4085	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
4086	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
4087	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
4088	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
4089	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
4090	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
4091	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
4092	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
4093	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
4094	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
4095	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
4096	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
4097	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
4098	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
4099	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
4100	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
4101	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
4102	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
4103	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
4104	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
4105	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
4106	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
4107	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
4108	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
4109	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
4110	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
4111	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
4112	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
4113	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
4114	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
4115	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
4116	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
4117	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
4118	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
4119	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
4120	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
4121	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
4122	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
4123	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4124	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
4125	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
4126	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4127	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4128	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
4129	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4130	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4131	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4132	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4133	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
4134	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
4135	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
4136	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
4137	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
4138	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
4139	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
4140	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
4141	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
4142	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
4143	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
4144	};
4145
4146	static const struct qcom_reset_map gcc_ipq9574_resets[] = {
4147	[GCC_ADSS_BCR] = { 0x1c000, 0 },
4148	[GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },
4149	[GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },
4150	[GCC_ANOC_BCR] = { 0x2e074, 0 },
4151	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
4152	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
4153	[GCC_BLSP1_BCR] = { 0x01000, 0 },
4154	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
4155	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
4156	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
4157	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
4158	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
4159	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
4160	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
4161	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
4162	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
4163	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
4164	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
4165	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
4166	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
4167	[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },
4168	[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },
4169	[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },
4170	[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },
4171	[GCC_CRYPTO_BCR] = { 0x16000, 0 },
4172	[GCC_DCC_BCR] = { 0x35000, 0 },
4173	[GCC_DDRSS_BCR] = { 0x11000, 0 },
4174	[GCC_IMEM_BCR] = { 0x0e000, 0 },
4175	[GCC_LPASS_BCR] = { 0x27000, 0 },
4176	[GCC_MDIO_BCR] = { 0x1703c, 0 },
4177	[GCC_MPM_BCR] = { 0x37000, 0 },
4178	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
4179	[GCC_NSS_BCR] = { 0x17000, 0 },
4180	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
4181	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
4182	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
4183	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038, 11 },
4184	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038, 10 },
4185	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
4186	[GCC_NSSCC_ARES] = { 0x17038, 8 },
4187	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
4188	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
4189	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
4190	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
4191	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
4192	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
4193	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
4194	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
4195	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
4196	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
4197	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
4198	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
4199	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
4200	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
4201	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
4202	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
4203	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
4204	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
4205	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
4206	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
4207	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
4208	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
4209	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
4210	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
4211	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
4212	[GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },
4213	[GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },
4214	[GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },
4215	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },
4216	[GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },
4217	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
4218	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },
4219	[GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },
4220	[GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },
4221	[GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },
4222	[GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },
4223	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },
4224	[GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },
4225	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },
4226	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },
4227	[GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },
4228	[GCC_PCIE0_BCR] = { 0x28000, 0 },
4229	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
4230	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
4231	[GCC_PCIE1_BCR] = { 0x29000, 0 },
4232	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
4233	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
4234	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
4235	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
4236	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
4237	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
4238	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
4239	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
4240	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
4241	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
4242	[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },
4243	[GCC_PCNOC_BCR] = { 0x31000, 0 },
4244	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
4245	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
4246	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
4247	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
4248	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
4249	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
4250	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
4251	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
4252	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
4253	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
4254	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
4255	[GCC_PRNG_BCR] = { 0x13020, 0 },
4256	[GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },
4257	[GCC_Q6_AHB_ARES] = { 0x2506c, 3 },
4258	[GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },
4259	[GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },
4260	[GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },
4261	[GCC_QDSS_BCR] = { 0x2d000, 0 },
4262	[GCC_QPIC_BCR] = { 0x32000, 0 },
4263	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
4264	[GCC_QPIC_ARES] = { 0x3201c, 0 },
4265	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
4266	[GCC_RBCPR_BCR] = { 0x39000, 0 },
4267	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
4268	[GCC_SDCC_BCR] = { 0x33000, 0 },
4269	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
4270	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
4271	[GCC_SNOC_BCR] = { 0x2e000, 0 },
4272	[GCC_SPDM_BCR] = { 0x36000, 0 },
4273	[GCC_TCSR_BCR] = { 0x3d000, 0 },
4274	[GCC_TLMM_BCR] = { 0x3e000, 0 },
4275	[GCC_TME_BCR] = { 0x10000, 0 },
4276	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
4277	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
4278	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
4279	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
4280	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
4281	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
4282	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
4283	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
4284	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
4285	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
4286	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
4287	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
4288	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
4289	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
4290	[GCC_USB_BCR] = { 0x2c000, 0 },
4291	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
4292	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
4293	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
4294	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
4295	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
4296	[GCC_WCSS_BCR] = { 0x18004, 0 },
4297	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
4298	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
4299	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
4300	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
4301	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
4302	};
4303
4304	static const struct of_device_id gcc_ipq9574_match_table[] = {
4305	{ .compatible = "qcom,ipq9574-gcc" },
4306	{ }
4307	};
4308	MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
4309
4310	static const struct regmap_config gcc_ipq9574_regmap_config = {
4311	.reg_bits = 32,
4312	.reg_stride = 4,
4313	.val_bits = 32,
4314	.max_register = 0x7fffc,
4315	.fast_io = true,
4316	};
4317
4318	static const struct qcom_cc_desc gcc_ipq9574_desc = {
4319	.config = &gcc_ipq9574_regmap_config,
4320	.clks = gcc_ipq9574_clks,
4321	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
4322	.resets = gcc_ipq9574_resets,
4323	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
4324	.clk_hws = gcc_ipq9574_hws,
4325	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
4326	};
4327
4328	static int gcc_ipq9574_probe(struct platform_device *pdev)
4329	{
4330	return qcom_cc_probe(pdev, desc: &gcc_ipq9574_desc);
4331	}
4332
4333	static struct platform_driver gcc_ipq9574_driver = {
4334	.probe = gcc_ipq9574_probe,
4335	.driver = {
4336	.name = "qcom,gcc-ipq9574",
4337	.of_match_table = gcc_ipq9574_match_table,
4338	},
4339	};
4340
4341	static int __init gcc_ipq9574_init(void)
4342	{
4343	return platform_driver_register(&gcc_ipq9574_driver);
4344	}
4345	core_initcall(gcc_ipq9574_init);
4346
4347	static void __exit gcc_ipq9574_exit(void)
4348	{
4349	platform_driver_unregister(&gcc_ipq9574_driver);
4350	}
4351	module_exit(gcc_ipq9574_exit);
4352
4353	MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
4354	MODULE_LICENSE("GPL");
4355